* [Intel-gfx] [PATCH] drm/i915/selftests: Confirm RING_TIMESTAMP / CTX_TIMESTAMP share a clock
@ 2020-08-10 15:38 Chris Wilson
2020-08-10 15:53 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Chris Wilson @ 2020-08-10 15:38 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
We assume that both timestamps are driven off the same clock [reported
to userspace as I915_PARAM_CS_TIMESTAMP_FREQUENCY]. Verify that this is
so by reading the timestamp registers around a busywait (on an otherwise
engine so there should be no preemptions).
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 145 +++++++++++++++++++
1 file changed, 145 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
index b08fc5390e8a..f44e29ea523a 100644
--- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
@@ -5,12 +5,156 @@
*/
#include "i915_selftest.h"
+#include "intel_gt_clock_utils.h"
#include "selftest_engine.h"
#include "selftest_engine_heartbeat.h"
#include "selftests/igt_atomic.h"
#include "selftests/igt_flush_test.h"
#include "selftests/igt_spinner.h"
+static u32 *emit_wait(u32 *cs, u32 offset, int op, u32 value)
+{
+ *cs++ = MI_SEMAPHORE_WAIT |
+ MI_SEMAPHORE_GLOBAL_GTT |
+ MI_SEMAPHORE_POLL |
+ op;
+ *cs++ = value;
+ *cs++ = offset;
+ *cs++ = 0;
+
+ return cs;
+}
+
+static u32 *emit_store(u32 *cs, u32 offset, u32 value)
+{
+ *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
+ *cs++ = offset;
+ *cs++ = 0;
+ *cs++ = value;
+
+ return cs;
+}
+
+static u32 *emit_srm(u32 *cs, i915_reg_t reg, u32 offset)
+{
+ *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;
+ *cs++ = i915_mmio_reg_offset(reg);
+ *cs++ = offset;
+ *cs++ = 0;
+
+ return cs;
+}
+
+static void write_semaphore(u32 *x, u32 value)
+{
+ WRITE_ONCE(*x, value);
+ wmb();
+}
+
+static int __live_engine_timestamps(struct intel_engine_cs *engine)
+{
+ u32 *sema = memset32(engine->status_page.addr + 1000, 0, 5);
+ u32 offset = i915_ggtt_offset(engine->status_page.vma);
+ struct intel_context *ce;
+ struct i915_request *rq;
+ u32 d_ring, d_ctx;
+ u64 start, end;
+ u32 *cs;
+
+ ce = intel_context_create(engine);
+ if (IS_ERR(ce))
+ return PTR_ERR(ce);
+
+ rq = intel_context_create_request(ce);
+ intel_context_put(ce);
+ if (IS_ERR(rq))
+ return PTR_ERR(rq);
+
+ cs = intel_ring_begin(rq, 28);
+ if (IS_ERR(cs)) {
+ i915_request_add(rq);
+ return PTR_ERR(cs);
+ }
+
+ /* Signal & wait for start */
+ cs = emit_store(cs, offset + 4008, 1);
+ cs = emit_wait(cs, offset + 4008, MI_SEMAPHORE_SAD_NEQ_SDD, 1);
+
+ cs = emit_srm(cs, RING_TIMESTAMP(engine->mmio_base), offset + 4000);
+ cs = emit_srm(cs, RING_CTX_TIMESTAMP(engine->mmio_base), offset + 4004);
+
+ /* Busy wait */
+ cs = emit_wait(cs, offset + 4008, MI_SEMAPHORE_SAD_EQ_SDD, 1);
+
+ cs = emit_srm(cs, RING_TIMESTAMP(engine->mmio_base), offset + 4016);
+ cs = emit_srm(cs, RING_CTX_TIMESTAMP(engine->mmio_base), offset + 4012);
+
+ intel_ring_advance(rq, cs);
+ i915_request_get(rq);
+ i915_request_add(rq);
+ intel_engine_flush_submission(engine);
+
+ while (READ_ONCE(sema[2]) == 0)
+ cpu_relax();
+
+ preempt_disable();
+ start = ktime_get_mono_fast_ns();
+ write_semaphore(&sema[2], 0);
+ udelay(100);
+ write_semaphore(&sema[2], 1);
+ end = ktime_get_mono_fast_ns();
+ preempt_enable();
+
+ if (i915_request_wait(rq, 0, HZ / 2) < 0) {
+ i915_request_put(rq);
+ return -ETIME;
+ }
+ i915_request_put(rq);
+
+ pr_debug("%s CTX_TIMESTAMP: [%x, %x]\n",
+ engine->name, sema[1], sema[3]);
+ pr_debug("%s RING_TIMESTAMP: [%x, %x]\n",
+ engine->name, sema[0], sema[4]);
+
+ d_ctx = sema[3] - sema[1];
+ d_ring = sema[4] - sema[0];
+
+ pr_info("%s elapsed:%lldns, CTX_TIMESTAMP:%dns, RING_TIMESTAMP:%dns\n",
+ engine->name, end - start,
+ intel_gt_clock_interval_to_ns(engine->gt, d_ctx),
+ intel_gt_clock_interval_to_ns(engine->gt, d_ring));
+
+ if (4 * d_ctx > 5 * d_ring || 5 * d_ctx < 4 * d_ring) {
+ pr_err("%s Mismatch between ring and context timestamps!\n",
+ engine->name);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int live_engine_timestamps(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+
+ if (INTEL_GEN(gt->i915) < 8)
+ return 0;
+
+ for_each_engine(engine, gt, id) {
+ int err;
+
+ st_engine_heartbeat_disable(engine);
+ err = __live_engine_timestamps(engine);
+ st_engine_heartbeat_enable(engine);
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
static int live_engine_busy_stats(void *arg)
{
struct intel_gt *gt = arg;
@@ -177,6 +321,7 @@ static int live_engine_pm(void *arg)
int live_engine_pm_selftests(struct intel_gt *gt)
{
static const struct i915_subtest tests[] = {
+ SUBTEST(live_engine_timestamps),
SUBTEST(live_engine_busy_stats),
SUBTEST(live_engine_pm),
};
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Confirm RING_TIMESTAMP / CTX_TIMESTAMP share a clock
2020-08-10 15:38 [Intel-gfx] [PATCH] drm/i915/selftests: Confirm RING_TIMESTAMP / CTX_TIMESTAMP share a clock Chris Wilson
@ 2020-08-10 15:53 ` Patchwork
2020-08-10 15:54 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-08-10 16:17 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2020-08-10 15:53 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/selftests: Confirm RING_TIMESTAMP / CTX_TIMESTAMP share a clock
URL : https://patchwork.freedesktop.org/series/80475/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
89b5186bbf39 drm/i915/selftests: Confirm RING_TIMESTAMP / CTX_TIMESTAMP share a clock
-:65: WARNING:MEMORY_BARRIER: memory barrier without comment
#65: FILE: drivers/gpu/drm/i915/gt/selftest_engine_pm.c:51:
+ wmb();
-:117: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst
#117: FILE: drivers/gpu/drm/i915/gt/selftest_engine_pm.c:103:
+ udelay(100);
total: 0 errors, 1 warnings, 1 checks, 163 lines checked
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/selftests: Confirm RING_TIMESTAMP / CTX_TIMESTAMP share a clock
2020-08-10 15:38 [Intel-gfx] [PATCH] drm/i915/selftests: Confirm RING_TIMESTAMP / CTX_TIMESTAMP share a clock Chris Wilson
2020-08-10 15:53 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
@ 2020-08-10 15:54 ` Patchwork
2020-08-10 16:17 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2020-08-10 15:54 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/selftests: Confirm RING_TIMESTAMP / CTX_TIMESTAMP share a clock
URL : https://patchwork.freedesktop.org/series/80475/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.0
Fast mode used, each commit won't be checked separately.
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftests: Confirm RING_TIMESTAMP / CTX_TIMESTAMP share a clock
2020-08-10 15:38 [Intel-gfx] [PATCH] drm/i915/selftests: Confirm RING_TIMESTAMP / CTX_TIMESTAMP share a clock Chris Wilson
2020-08-10 15:53 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2020-08-10 15:54 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2020-08-10 16:17 ` Patchwork
2 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2020-08-10 16:17 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 6036 bytes --]
== Series Details ==
Series: drm/i915/selftests: Confirm RING_TIMESTAMP / CTX_TIMESTAMP share a clock
URL : https://patchwork.freedesktop.org/series/80475/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8864 -> Patchwork_18333
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_18333 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18333, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18333/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_18333:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live@gt_engines:
- fi-icl-y: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8864/fi-icl-y/igt@i915_selftest@live@gt_engines.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18333/fi-icl-y/igt@i915_selftest@live@gt_engines.html
- fi-icl-u2: [PASS][3] -> [FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8864/fi-icl-u2/igt@i915_selftest@live@gt_engines.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18333/fi-icl-u2/igt@i915_selftest@live@gt_engines.html
Known issues
------------
Here are the changes found in Patchwork_18333 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8864/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18333/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
- fi-icl-u2: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8864/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18333/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
* igt@kms_flip@basic-flip-vs-wf_vblank@c-hdmi-a2:
- fi-skl-guc: [PASS][9] -> [DMESG-WARN][10] ([i915#2203])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8864/fi-skl-guc/igt@kms_flip@basic-flip-vs-wf_vblank@c-hdmi-a2.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18333/fi-skl-guc/igt@kms_flip@basic-flip-vs-wf_vblank@c-hdmi-a2.html
#### Possible fixes ####
* igt@i915_selftest@live@execlists:
- fi-icl-y: [INCOMPLETE][11] ([i915#2276]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8864/fi-icl-y/igt@i915_selftest@live@execlists.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18333/fi-icl-y/igt@i915_selftest@live@execlists.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7500u: [DMESG-WARN][13] ([i915#2203]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8864/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18333/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-kbl-r: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8864/fi-kbl-r/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18333/fi-kbl-r/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
#### Warnings ####
* igt@kms_force_connector_basic@force-edid:
- fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][18] ([i915#62] / [i915#92]) +3 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8864/fi-kbl-x1275/igt@kms_force_connector_basic@force-edid.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18333/fi-kbl-x1275/igt@kms_force_connector_basic@force-edid.html
* igt@kms_force_connector_basic@prune-stale-modes:
- fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92]) -> [DMESG-WARN][20] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8864/fi-kbl-x1275/igt@kms_force_connector_basic@prune-stale-modes.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18333/fi-kbl-x1275/igt@kms_force_connector_basic@prune-stale-modes.html
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
[i915#2276]: https://gitlab.freedesktop.org/drm/intel/issues/2276
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (44 -> 37)
------------------------------
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_8864 -> Patchwork_18333
CI-20190529: 20190529
CI_DRM_8864: 1eb4b065044226eb99cc089abf87d5b91eda2dc8 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5765: 9f0977284d54ed37496260988dfcd6d2ad72dd1e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18333: 89b5186bbf39e367c91c9dfb42cdd1122c61f49f @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
89b5186bbf39 drm/i915/selftests: Confirm RING_TIMESTAMP / CTX_TIMESTAMP share a clock
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18333/index.html
[-- Attachment #1.2: Type: text/html, Size: 7554 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/selftests: Confirm RING_TIMESTAMP / CTX_TIMESTAMP share a clock
2020-08-11 15:37 ` Lionel Landwerlin
@ 2020-08-11 15:47 ` Chris Wilson
0 siblings, 0 replies; 7+ messages in thread
From: Chris Wilson @ 2020-08-11 15:47 UTC (permalink / raw)
To: Lionel Landwerlin, intel-gfx
Quoting Lionel Landwerlin (2020-08-11 16:37:10)
> On 11/08/2020 12:17, Chris Wilson wrote:
> > We assume that both timestamps are driven off the same clock [reported
> > to userspace as I915_PARAM_CS_TIMESTAMP_FREQUENCY]. Verify that this is
> > so by reading the timestamp registers around a busywait (on an otherwise
> > idle engine so there should be no preemptions).
> >
> > v2: Icelake (not ehl, nor tgl) seems to be using a fixed 80ns interval
> > for, and only for, CTX_TIMESTAMP. As far as I can tell, this behaviour
> > is undocumented.
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>
>
> I really thought the CTX_TIMESTAMP was running 8 times slower :
>
>
> For the 2015 - 2016 Intel CoreTM Processors, CeleronTM Processors,
> and PentiumTM Processors based on the "Skylake" Platform
>
> Volume 2c: Command Reference: Registers
> Part 1 – Registers A through L
>
> May 2016, Revision 1.0
>
> CTX_TIMESTAMP - Context Timestamp Count:
>
> The granularity of this toggle is at the rate of the bit 3 in the
> "Reported Timestamp Count"
> register(0x2358).. The toggle will be 8 times slower that "Reported
> Timestamp Count". The
> granularity of the time stamp base unit for "Reported Timestamp Count"
> is defined in the
> “Timestamp Bases” subsection in Power Management chapter.
I read that paragraph in the same way, that the CTX_TIMESTAMP is only
being advanced [by 1 tick] on every 8th tick of CS_TIMESTAMP.
That turns out to be not what happens... So I guess they mean that
CTX_TIMESTAMP increments by 8 every 8th tick. I haven't bothered to
check to see if there's anything in the low 2 bits of CTX_TIMESTAMP.
Still nothing mentions that Icelake has a completely different
behaviour afaict.
-Chris
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/selftests: Confirm RING_TIMESTAMP / CTX_TIMESTAMP share a clock
2020-08-11 9:17 [Intel-gfx] [PATCH] " Chris Wilson
@ 2020-08-11 15:37 ` Lionel Landwerlin
2020-08-11 15:47 ` Chris Wilson
0 siblings, 1 reply; 7+ messages in thread
From: Lionel Landwerlin @ 2020-08-11 15:37 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On 11/08/2020 12:17, Chris Wilson wrote:
> We assume that both timestamps are driven off the same clock [reported
> to userspace as I915_PARAM_CS_TIMESTAMP_FREQUENCY]. Verify that this is
> so by reading the timestamp registers around a busywait (on an otherwise
> idle engine so there should be no preemptions).
>
> v2: Icelake (not ehl, nor tgl) seems to be using a fixed 80ns interval
> for, and only for, CTX_TIMESTAMP. As far as I can tell, this behaviour
> is undocumented.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
I really thought the CTX_TIMESTAMP was running 8 times slower :
For the 2015 - 2016 Intel CoreTM Processors, CeleronTM Processors,
and PentiumTM Processors based on the "Skylake" Platform
Volume 2c: Command Reference: Registers
Part 1 – Registers A through L
May 2016, Revision 1.0
CTX_TIMESTAMP - Context Timestamp Count:
The granularity of this toggle is at the rate of the bit 3 in the
"Reported Timestamp Count"
register(0x2358).. The toggle will be 8 times slower that "Reported
Timestamp Count". The
granularity of the time stamp base unit for "Reported Timestamp Count"
is defined in the
“Timestamp Bases” subsection in Power Management chapter.
> ---
> drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 157 +++++++++++++++++++
> 1 file changed, 157 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
> index b08fc5390e8a..9d5778238015 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
> @@ -5,12 +5,168 @@
> */
>
> #include "i915_selftest.h"
> +#include "intel_gt_clock_utils.h"
> #include "selftest_engine.h"
> #include "selftest_engine_heartbeat.h"
> #include "selftests/igt_atomic.h"
> #include "selftests/igt_flush_test.h"
> #include "selftests/igt_spinner.h"
>
> +static u32 *emit_wait(u32 *cs, u32 offset, int op, u32 value)
> +{
> + *cs++ = MI_SEMAPHORE_WAIT |
> + MI_SEMAPHORE_GLOBAL_GTT |
> + MI_SEMAPHORE_POLL |
> + op;
> + *cs++ = value;
> + *cs++ = offset;
> + *cs++ = 0;
> +
> + return cs;
> +}
> +
> +static u32 *emit_store(u32 *cs, u32 offset, u32 value)
> +{
> + *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
> + *cs++ = offset;
> + *cs++ = 0;
> + *cs++ = value;
> +
> + return cs;
> +}
> +
> +static u32 *emit_srm(u32 *cs, i915_reg_t reg, u32 offset)
> +{
> + *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;
> + *cs++ = i915_mmio_reg_offset(reg);
> + *cs++ = offset;
> + *cs++ = 0;
> +
> + return cs;
> +}
> +
> +static void write_semaphore(u32 *x, u32 value)
> +{
> + WRITE_ONCE(*x, value);
> + wmb();
> +}
> +
> +static int __live_engine_timestamps(struct intel_engine_cs *engine)
> +{
> + u32 *sema = memset32(engine->status_page.addr + 1000, 0, 5);
> + u32 offset = i915_ggtt_offset(engine->status_page.vma);
> + struct intel_context *ce;
> + struct i915_request *rq;
> + u64 d_ring, d_ctx, dt;
> + u32 *cs;
> +
> + ce = intel_context_create(engine);
> + if (IS_ERR(ce))
> + return PTR_ERR(ce);
> +
> + rq = intel_context_create_request(ce);
> + intel_context_put(ce);
> + if (IS_ERR(rq))
> + return PTR_ERR(rq);
> +
> + cs = intel_ring_begin(rq, 28);
> + if (IS_ERR(cs)) {
> + i915_request_add(rq);
> + return PTR_ERR(cs);
> + }
> +
> + /* Signal & wait for start */
> + cs = emit_store(cs, offset + 4008, 1);
> + cs = emit_wait(cs, offset + 4008, MI_SEMAPHORE_SAD_NEQ_SDD, 1);
> +
> + cs = emit_srm(cs, RING_TIMESTAMP(engine->mmio_base), offset + 4000);
> + cs = emit_srm(cs, RING_CTX_TIMESTAMP(engine->mmio_base), offset + 4004);
> +
> + /* Busy wait */
> + cs = emit_wait(cs, offset + 4008, MI_SEMAPHORE_SAD_EQ_SDD, 1);
> +
> + cs = emit_srm(cs, RING_TIMESTAMP(engine->mmio_base), offset + 4016);
> + cs = emit_srm(cs, RING_CTX_TIMESTAMP(engine->mmio_base), offset + 4012);
> +
> + intel_ring_advance(rq, cs);
> + i915_request_get(rq);
> + i915_request_add(rq);
> + intel_engine_flush_submission(engine);
> +
> + /* Wait for the request to start executing, that then waits for us */
> + while (READ_ONCE(sema[2]) == 0)
> + cpu_relax();
> +
> + /* Run the request for a 100us, sampling timestamps before/after */
> + preempt_disable();
> + dt = ktime_get_mono_fast_ns();
> + write_semaphore(&sema[2], 0);
> + udelay(100);
> + write_semaphore(&sema[2], 1);
> + dt = ktime_get_mono_fast_ns() - dt;
> + preempt_enable();
> +
> + if (i915_request_wait(rq, 0, HZ / 2) < 0) {
> + i915_request_put(rq);
> + return -ETIME;
> + }
> + i915_request_put(rq);
> +
> + pr_debug("%s CTX_TIMESTAMP: [%x, %x]\n",
> + engine->name, sema[1], sema[3]);
> + pr_debug("%s RING_TIMESTAMP: [%x, %x]\n",
> + engine->name, sema[0], sema[4]);
> +
> + d_ctx = sema[3] - sema[1];
> + d_ring = sema[4] - sema[0];
> +
> + pr_info("%s elapsed:%lldns, CTX_TIMESTAMP:%dns, RING_TIMESTAMP:%dns\n",
> + engine->name, dt,
> + intel_gt_clock_interval_to_ns(engine->gt, d_ctx),
> + intel_gt_clock_interval_to_ns(engine->gt, d_ring));
> +
> + d_ctx *= RUNTIME_INFO(engine->i915)->cs_timestamp_frequency_hz;
> + if (IS_ICELAKE(engine->i915))
> + d_ring *= 12500000; /* Fixed 80ns for icl ctx timestamp? */
> + else
> + d_ring *= RUNTIME_INFO(engine->i915)->cs_timestamp_frequency_hz;
> +
> + if (4 * d_ctx > 5 * d_ring || 5 * d_ctx < 4 * d_ring) {
> + pr_err("%s Mismatch between ring and context timestamps!\n",
> + engine->name);
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static int live_engine_timestamps(void *arg)
> +{
> + struct intel_gt *gt = arg;
> + struct intel_engine_cs *engine;
> + enum intel_engine_id id;
> +
> + /*
> + * Check that CS_TIMESTAMP / CTX_TIMESTAMP are in sync, i.e. share
> + * the same CS clock.
> + */
> +
> + if (INTEL_GEN(gt->i915) < 8)
> + return 0;
> +
> + for_each_engine(engine, gt, id) {
> + int err;
> +
> + st_engine_heartbeat_disable(engine);
> + err = __live_engine_timestamps(engine);
> + st_engine_heartbeat_enable(engine);
> + if (err)
> + return err;
> + }
> +
> + return 0;
> +}
> +
> static int live_engine_busy_stats(void *arg)
> {
> struct intel_gt *gt = arg;
> @@ -177,6 +333,7 @@ static int live_engine_pm(void *arg)
> int live_engine_pm_selftests(struct intel_gt *gt)
> {
> static const struct i915_subtest tests[] = {
> + SUBTEST(live_engine_timestamps),
> SUBTEST(live_engine_busy_stats),
> SUBTEST(live_engine_pm),
> };
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/selftests: Confirm RING_TIMESTAMP / CTX_TIMESTAMP share a clock
@ 2020-08-11 9:17 Chris Wilson
2020-08-11 15:37 ` Lionel Landwerlin
0 siblings, 1 reply; 7+ messages in thread
From: Chris Wilson @ 2020-08-11 9:17 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
We assume that both timestamps are driven off the same clock [reported
to userspace as I915_PARAM_CS_TIMESTAMP_FREQUENCY]. Verify that this is
so by reading the timestamp registers around a busywait (on an otherwise
idle engine so there should be no preemptions).
v2: Icelake (not ehl, nor tgl) seems to be using a fixed 80ns interval
for, and only for, CTX_TIMESTAMP. As far as I can tell, this behaviour
is undocumented.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 157 +++++++++++++++++++
1 file changed, 157 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
index b08fc5390e8a..9d5778238015 100644
--- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
@@ -5,12 +5,168 @@
*/
#include "i915_selftest.h"
+#include "intel_gt_clock_utils.h"
#include "selftest_engine.h"
#include "selftest_engine_heartbeat.h"
#include "selftests/igt_atomic.h"
#include "selftests/igt_flush_test.h"
#include "selftests/igt_spinner.h"
+static u32 *emit_wait(u32 *cs, u32 offset, int op, u32 value)
+{
+ *cs++ = MI_SEMAPHORE_WAIT |
+ MI_SEMAPHORE_GLOBAL_GTT |
+ MI_SEMAPHORE_POLL |
+ op;
+ *cs++ = value;
+ *cs++ = offset;
+ *cs++ = 0;
+
+ return cs;
+}
+
+static u32 *emit_store(u32 *cs, u32 offset, u32 value)
+{
+ *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
+ *cs++ = offset;
+ *cs++ = 0;
+ *cs++ = value;
+
+ return cs;
+}
+
+static u32 *emit_srm(u32 *cs, i915_reg_t reg, u32 offset)
+{
+ *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;
+ *cs++ = i915_mmio_reg_offset(reg);
+ *cs++ = offset;
+ *cs++ = 0;
+
+ return cs;
+}
+
+static void write_semaphore(u32 *x, u32 value)
+{
+ WRITE_ONCE(*x, value);
+ wmb();
+}
+
+static int __live_engine_timestamps(struct intel_engine_cs *engine)
+{
+ u32 *sema = memset32(engine->status_page.addr + 1000, 0, 5);
+ u32 offset = i915_ggtt_offset(engine->status_page.vma);
+ struct intel_context *ce;
+ struct i915_request *rq;
+ u64 d_ring, d_ctx, dt;
+ u32 *cs;
+
+ ce = intel_context_create(engine);
+ if (IS_ERR(ce))
+ return PTR_ERR(ce);
+
+ rq = intel_context_create_request(ce);
+ intel_context_put(ce);
+ if (IS_ERR(rq))
+ return PTR_ERR(rq);
+
+ cs = intel_ring_begin(rq, 28);
+ if (IS_ERR(cs)) {
+ i915_request_add(rq);
+ return PTR_ERR(cs);
+ }
+
+ /* Signal & wait for start */
+ cs = emit_store(cs, offset + 4008, 1);
+ cs = emit_wait(cs, offset + 4008, MI_SEMAPHORE_SAD_NEQ_SDD, 1);
+
+ cs = emit_srm(cs, RING_TIMESTAMP(engine->mmio_base), offset + 4000);
+ cs = emit_srm(cs, RING_CTX_TIMESTAMP(engine->mmio_base), offset + 4004);
+
+ /* Busy wait */
+ cs = emit_wait(cs, offset + 4008, MI_SEMAPHORE_SAD_EQ_SDD, 1);
+
+ cs = emit_srm(cs, RING_TIMESTAMP(engine->mmio_base), offset + 4016);
+ cs = emit_srm(cs, RING_CTX_TIMESTAMP(engine->mmio_base), offset + 4012);
+
+ intel_ring_advance(rq, cs);
+ i915_request_get(rq);
+ i915_request_add(rq);
+ intel_engine_flush_submission(engine);
+
+ /* Wait for the request to start executing, that then waits for us */
+ while (READ_ONCE(sema[2]) == 0)
+ cpu_relax();
+
+ /* Run the request for a 100us, sampling timestamps before/after */
+ preempt_disable();
+ dt = ktime_get_mono_fast_ns();
+ write_semaphore(&sema[2], 0);
+ udelay(100);
+ write_semaphore(&sema[2], 1);
+ dt = ktime_get_mono_fast_ns() - dt;
+ preempt_enable();
+
+ if (i915_request_wait(rq, 0, HZ / 2) < 0) {
+ i915_request_put(rq);
+ return -ETIME;
+ }
+ i915_request_put(rq);
+
+ pr_debug("%s CTX_TIMESTAMP: [%x, %x]\n",
+ engine->name, sema[1], sema[3]);
+ pr_debug("%s RING_TIMESTAMP: [%x, %x]\n",
+ engine->name, sema[0], sema[4]);
+
+ d_ctx = sema[3] - sema[1];
+ d_ring = sema[4] - sema[0];
+
+ pr_info("%s elapsed:%lldns, CTX_TIMESTAMP:%dns, RING_TIMESTAMP:%dns\n",
+ engine->name, dt,
+ intel_gt_clock_interval_to_ns(engine->gt, d_ctx),
+ intel_gt_clock_interval_to_ns(engine->gt, d_ring));
+
+ d_ctx *= RUNTIME_INFO(engine->i915)->cs_timestamp_frequency_hz;
+ if (IS_ICELAKE(engine->i915))
+ d_ring *= 12500000; /* Fixed 80ns for icl ctx timestamp? */
+ else
+ d_ring *= RUNTIME_INFO(engine->i915)->cs_timestamp_frequency_hz;
+
+ if (4 * d_ctx > 5 * d_ring || 5 * d_ctx < 4 * d_ring) {
+ pr_err("%s Mismatch between ring and context timestamps!\n",
+ engine->name);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int live_engine_timestamps(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+
+ /*
+ * Check that CS_TIMESTAMP / CTX_TIMESTAMP are in sync, i.e. share
+ * the same CS clock.
+ */
+
+ if (INTEL_GEN(gt->i915) < 8)
+ return 0;
+
+ for_each_engine(engine, gt, id) {
+ int err;
+
+ st_engine_heartbeat_disable(engine);
+ err = __live_engine_timestamps(engine);
+ st_engine_heartbeat_enable(engine);
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
static int live_engine_busy_stats(void *arg)
{
struct intel_gt *gt = arg;
@@ -177,6 +333,7 @@ static int live_engine_pm(void *arg)
int live_engine_pm_selftests(struct intel_gt *gt)
{
static const struct i915_subtest tests[] = {
+ SUBTEST(live_engine_timestamps),
SUBTEST(live_engine_busy_stats),
SUBTEST(live_engine_pm),
};
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 7+ messages in thread
end of thread, other threads:[~2020-08-11 15:47 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-08-10 15:38 [Intel-gfx] [PATCH] drm/i915/selftests: Confirm RING_TIMESTAMP / CTX_TIMESTAMP share a clock Chris Wilson
2020-08-10 15:53 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2020-08-10 15:54 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-08-10 16:17 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2020-08-11 9:17 [Intel-gfx] [PATCH] " Chris Wilson
2020-08-11 15:37 ` Lionel Landwerlin
2020-08-11 15:47 ` Chris Wilson
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