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* [PATCH] arm64: perf: Add general hardware LLC events for PMUv3
@ 2020-08-11  5:35 ` Leo Yan
  0 siblings, 0 replies; 4+ messages in thread
From: Leo Yan @ 2020-08-11  5:35 UTC (permalink / raw)
  To: Will Deacon, Mark Rutland, Catalin Marinas, Peter Zijlstra,
	Ingo Molnar, Arnaldo Carvalho de Melo, Alexander Shishkin,
	Jiri Olsa, Namhyung Kim, John Garry, linux-kernel,
	linux-arm-kernel
  Cc: Leo Yan

This patch is to add the general hardware last level cache (LLC) events
for PMUv3: one event is for LLC access and another is for LLC miss.

With this change, perf tool can support last level cache profiling,
below is an example to demonstrate the usage on Arm64:

  $ perf stat -e LLC-load-misses -e LLC-loads -- \
	  perf bench mem memcpy -s 1024MB -l 100 -f default

  [...]

    Performance counter stats for 'perf bench mem memcpy -s 1024MB -l 100 -f default':

        35,534,262      LLC-load-misses           #    2.16% of all LL-cache hits
     1,643,946,443      LLC-loads

  [...]

Signed-off-by: Leo Yan <leo.yan@linaro.org>
---
 arch/arm64/kernel/perf_event.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index 462f9a9cc44b..86e2328b0c2e 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -69,6 +69,9 @@ static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 	[C(ITLB)][C(OP_READ)][C(RESULT_MISS)]	= ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
 	[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)]	= ARMV8_PMUV3_PERFCTR_L1I_TLB,
 
+	[C(LL)][C(OP_READ)][C(RESULT_MISS)]	= ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD,
+	[C(LL)][C(OP_READ)][C(RESULT_ACCESS)]	= ARMV8_PMUV3_PERFCTR_LL_CACHE_RD,
+
 	[C(BPU)][C(OP_READ)][C(RESULT_ACCESS)]	= ARMV8_PMUV3_PERFCTR_BR_PRED,
 	[C(BPU)][C(OP_READ)][C(RESULT_MISS)]	= ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 };
-- 
2.17.1


^ permalink raw reply related	[flat|nested] 4+ messages in thread
* [PATCH] arm64: perf: Add general hardware LLC events for PMUv3
@ 2020-08-11  5:35 ` Leo Yan
  0 siblings, 0 replies; 4+ messages in thread
From: Leo Yan @ 2020-08-11  5:35 UTC (permalink / raw)
  To: Will Deacon, Mark Rutland, Catalin Marinas, Peter Zijlstra,
	Ingo Molnar, Arnaldo Carvalho de Melo, Alexander Shishkin,
	Jiri Olsa, Namhyung Kim, John Garry, linux-kernel,
	linux-arm-kernel
  Cc: Leo Yan

This patch is to add the general hardware last level cache (LLC) events
for PMUv3: one event is for LLC access and another is for LLC miss.

With this change, perf tool can support last level cache profiling,
below is an example to demonstrate the usage on Arm64:

  $ perf stat -e LLC-load-misses -e LLC-loads -- \
	  perf bench mem memcpy -s 1024MB -l 100 -f default

  [...]

    Performance counter stats for 'perf bench mem memcpy -s 1024MB -l 100 -f default':

        35,534,262      LLC-load-misses           #    2.16% of all LL-cache hits
     1,643,946,443      LLC-loads

  [...]

Signed-off-by: Leo Yan <leo.yan@linaro.org>
---
 arch/arm64/kernel/perf_event.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index 462f9a9cc44b..86e2328b0c2e 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -69,6 +69,9 @@ static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 	[C(ITLB)][C(OP_READ)][C(RESULT_MISS)]	= ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
 	[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)]	= ARMV8_PMUV3_PERFCTR_L1I_TLB,
 
+	[C(LL)][C(OP_READ)][C(RESULT_MISS)]	= ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD,
+	[C(LL)][C(OP_READ)][C(RESULT_ACCESS)]	= ARMV8_PMUV3_PERFCTR_LL_CACHE_RD,
+
 	[C(BPU)][C(OP_READ)][C(RESULT_ACCESS)]	= ARMV8_PMUV3_PERFCTR_BR_PRED,
 	[C(BPU)][C(OP_READ)][C(RESULT_MISS)]	= ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 };
-- 
2.17.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 4+ messages in thread
* Re: [PATCH] arm64: perf: Add general hardware LLC events for PMUv3
  2020-08-11  5:35 ` Leo Yan
@ 2020-09-07 16:05   ` Will Deacon
  -1 siblings, 0 replies; 4+ messages in thread
From: Will Deacon @ 2020-09-07 16:05 UTC (permalink / raw)
  To: Catalin Marinas, Namhyung Kim, Alexander Shishkin, Mark Rutland,
	John Garry, linux-kernel, Arnaldo Carvalho de Melo, Ingo Molnar,
	Leo Yan, Peter Zijlstra, Jiri Olsa, linux-arm-kernel
  Cc: kernel-team, Will Deacon

On Tue, 11 Aug 2020 13:35:05 +0800, Leo Yan wrote:
> This patch is to add the general hardware last level cache (LLC) events
> for PMUv3: one event is for LLC access and another is for LLC miss.
> 
> With this change, perf tool can support last level cache profiling,
> below is an example to demonstrate the usage on Arm64:
> 
>   $ perf stat -e LLC-load-misses -e LLC-loads -- \
> 	  perf bench mem memcpy -s 1024MB -l 100 -f default
> 
> [...]

Applied to will (for-next/perf), thanks!

[1/1] arm64: perf: Add general hardware LLC events for PMUv3
      https://git.kernel.org/will/c/ffdbd3d83553

Cheers,
-- 
Will

https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev

^ permalink raw reply	[flat|nested] 4+ messages in thread
* Re: [PATCH] arm64: perf: Add general hardware LLC events for PMUv3
@ 2020-09-07 16:05   ` Will Deacon
  0 siblings, 0 replies; 4+ messages in thread
From: Will Deacon @ 2020-09-07 16:05 UTC (permalink / raw)
  To: Catalin Marinas, Namhyung Kim, Alexander Shishkin, Mark Rutland,
	John Garry, linux-kernel, Arnaldo Carvalho de Melo, Ingo Molnar,
	Leo Yan, Peter Zijlstra, Jiri Olsa, linux-arm-kernel
  Cc: Will Deacon, kernel-team

On Tue, 11 Aug 2020 13:35:05 +0800, Leo Yan wrote:
> This patch is to add the general hardware last level cache (LLC) events
> for PMUv3: one event is for LLC access and another is for LLC miss.
> 
> With this change, perf tool can support last level cache profiling,
> below is an example to demonstrate the usage on Arm64:
> 
>   $ perf stat -e LLC-load-misses -e LLC-loads -- \
> 	  perf bench mem memcpy -s 1024MB -l 100 -f default
> 
> [...]

Applied to will (for-next/perf), thanks!

[1/1] arm64: perf: Add general hardware LLC events for PMUv3
      https://git.kernel.org/will/c/ffdbd3d83553

Cheers,
-- 
Will

https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 4+ messages in thread
end of thread, other threads:[~2020-09-07 16:07 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2020-08-11  5:35 [PATCH] arm64: perf: Add general hardware LLC events for PMUv3 Leo Yan
2020-08-11  5:35 ` Leo Yan
2020-09-07 16:05 ` Will Deacon
2020-09-07 16:05   ` Will Deacon

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