[PATCH 0/5] J7200: Add HyperFlash boot support

[PATCH 0/5] J7200: Add HyperFlash boot support

[Vignesh Raghavendra]

Add support to boot from HyperFlash on J7200 SoC

Vignesh Raghavendra (5):
  arm: mach-k3: Add HyperFlash boot mode support
  board: ti: j721e: Add support for HyperFlash detection
  ARM: dts: k3-j7200-r5-common-proc-board: Enable HyperFlash
  configs: j7200_evm_*_defconfig: Enable HyperFlash boot related configs
  configs: j721e_evm.h: Add U-Boot image address for HyperFlash boot

 .../k3-j7200-common-proc-board-u-boot.dtsi    | 28 +++++++++++++
 .../arm/dts/k3-j7200-r5-common-proc-board.dts | 40 +++++++++++++++++++
 arch/arm/mach-k3/include/mach/j721e_spl.h     |  1 +
 board/ti/j721e/evm.c                          |  7 ++++
 configs/j7200_evm_a72_defconfig               |  3 ++
 configs/j7200_evm_r5_defconfig                | 13 ++++++
 include/configs/j721e_evm.h                   |  2 +
 7 files changed, 94 insertions(+)

-- 
2.28.0

[PATCH 1/5] arm: mach-k3: Add HyperFlash boot mode support

[Vignesh Raghavendra]

HBMC controller on TI K3 SoC provides MMIO access to HyperFlash similar
to legacy Parallel CFI NOR flashes. Therefore alias HyperFlash bootmode
to NOR boot to enable SPL to load next stage using NOR boot flow.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
 arch/arm/mach-k3/include/mach/j721e_spl.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-k3/include/mach/j721e_spl.h b/arch/arm/mach-k3/include/mach/j721e_spl.h
index 3fa85ca3b6..e8947917a6 100644
--- a/arch/arm/mach-k3/include/mach/j721e_spl.h
+++ b/arch/arm/mach-k3/include/mach/j721e_spl.h
@@ -15,6 +15,7 @@
 #define BOOT_DEVICE_ETHERNET		0x04
 #define BOOT_DEVICE_I2C			0x06
 #define BOOT_DEVICE_UART		0x07
+#define BOOT_DEVICE_NOR			BOOT_DEVICE_HYPERFLASH
 
 /* With BootMode B = 1 */
 #define BOOT_DEVICE_MMC2		0x10
-- 
2.28.0

[PATCH 2/5] board: ti: j721e: Add support for HyperFlash detection

[Vignesh Raghavendra]

On J7200 SoC OSPI and HypeFlash are muxed at HW level and only one of
them can be used at any time. J7200 EVM has both HyperFlash and OSPI
flash on board. There is a user switch (SW3.1) that can be toggled to
select OSPI flash vs HyperFlash.
Read the state of this switch via wkup_gpio0_6 line and fixup the DT
nodes to select OSPI vs HyperFlash

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
 board/ti/j721e/evm.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
index ebaa6faa93..7925b76ab7 100644
--- a/board/ti/j721e/evm.c
+++ b/board/ti/j721e/evm.c
@@ -117,6 +117,13 @@ static void __maybe_unused detect_enable_hyperflash(void *blob)
 }
 #endif
 
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_TARGET_J7200_A72_EVM)
+void spl_perform_fixups(struct spl_image_info *spl_image)
+{
+	detect_enable_hyperflash(spl_image->fdt_addr);
+}
+#endif
+
 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 int ft_board_setup(void *blob, struct bd_info *bd)
 {
-- 
2.28.0

[PATCH 3/5] ARM: dts: k3-j7200-r5-common-proc-board: Enable HyperFlash

[Vignesh Raghavendra]

Enable HyperBus and HyperFlash to support HyperFlash boot.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
 .../k3-j7200-common-proc-board-u-boot.dtsi    | 28 +++++++++++++
 .../arm/dts/k3-j7200-r5-common-proc-board.dts | 40 +++++++++++++++++++
 2 files changed, 68 insertions(+)

diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
index 4972a7559f..0a5faa2134 100644
--- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
@@ -131,3 +131,31 @@
 	dr_mode = "peripheral";
 	u-boot,dm-spl;
 };
+
+&wkup_gpio_pins_default {
+	u-boot,dm-spl;
+};
+
+&wkup_gpio0 {
+	u-boot,dm-spl;
+};
+
+&mcu_fss0_hpb0_pins_default {
+	u-boot,dm-spl;
+};
+
+&fss {
+	u-boot,dm-spl;
+};
+
+&hbmc {
+	u-boot,dm-spl;
+
+	flash at 0,0 {
+		u-boot,dm-spl;
+	};
+};
+
+&hbmc_mux {
+	u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
index f5e4166926..bd30284755 100644
--- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
@@ -107,6 +107,31 @@
 			J721E_WKUP_IOPAD(0x104, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */
 		>;
 	};
+
+	mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {
+		pinctrl-single,pins = <
+			J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (E20) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
+			J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C21) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
+			J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (F19) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
+			J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* (E22) MCU_OSPI1_CSn1.MCU_HYPERBUS0_CSn1 */
+			J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (E19) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
+			J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (D21) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
+			J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D20) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
+			J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (G19) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */
+			J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (G20) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */
+			J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (F20) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */
+			J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (F21) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */
+			J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (E21) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
+			J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (B22) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
+			J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (G21) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
+		>;
+	};
+
+	wkup_gpio_pins_default: wkup-gpio-pins-default {
+		pinctrl-single,pins = <
+			J721E_WKUP_IOPAD(0xd8, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */
+		>;
+	};
 };
 
 &main_pmx0 {
@@ -214,4 +239,19 @@
 	maximum-speed = "high-speed";
 };
 
+&hbmc {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
+	reg = <0x0 0x47040000 0x0 0x100>,
+	      <0x0 0x50000000 0x0 0x8000000>;
+	ranges = <0x0 0x0 0x0 0x50000000 0x4000000>, /* 64MB Flash on CS0 */
+		 <0x1 0x0 0x0 0x54000000 0x800000>; /* 8MB flash on CS1 */
+
+	flash at 0,0 {
+		compatible = "cypress,hyperflash", "cfi-flash";
+		reg = <0x0 0x0 0x4000000>;
+	};
+};
+
 #include "k3-j7200-common-proc-board-u-boot.dtsi"
-- 
2.28.0

[PATCH 4/5] configs: j7200_evm_*_defconfig: Enable HyperFlash boot related configs

[Vignesh Raghavendra]

Enable configs required to support HyperFlash boot and detection of
onboard mux switch for HyperFlash selection

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
 configs/j7200_evm_a72_defconfig |  3 +++
 configs/j7200_evm_r5_defconfig  | 13 +++++++++++++
 2 files changed, 16 insertions(+)

diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig
index 6e854648eb..a0046c32e1 100644
--- a/configs/j7200_evm_a72_defconfig
+++ b/configs/j7200_evm_a72_defconfig
@@ -41,7 +41,9 @@ CONFIG_SPL_DMA=y
 CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_MTD_SUPPORT=y
 CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_NOR_SUPPORT=y
 CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_POWER_SUPPORT=y
 CONFIG_SPL_POWER_DOMAIN=y
@@ -87,6 +89,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
 CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig
index 2908bc30c4..bd1268e9cf 100644
--- a/configs/j7200_evm_r5_defconfig
+++ b/configs/j7200_evm_r5_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_K3=y
+CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x70000
@@ -37,7 +38,9 @@ CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_FS_EXT4=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_MTD_SUPPORT=y
 CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_NOR_SUPPORT=y
 CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_POWER_SUPPORT=y
 CONFIG_SPL_POWER_DOMAIN=y
@@ -67,6 +70,8 @@ CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
@@ -87,6 +92,14 @@ CONFIG_MMC_SDHCI=y
 CONFIG_SPL_MMC_SDHCI_ADMA=y
 CONFIG_MMC_SDHCI_AM654=y
 CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_FLASH_CFI_MTD=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_HBMC_AM654=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPI_FLASH_STMICRO=y
-- 
2.28.0

[PATCH 5/5] configs: j721e_evm.h: Add U-Boot image address for HyperFlash boot

[Vignesh Raghavendra]

Add memory mapped address location of U-Boot images in HyperFlash boot
mode.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
 include/configs/j721e_evm.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h
index c8a76037ff..a570893378 100644
--- a/include/configs/j721e_evm.h
+++ b/include/configs/j721e_evm.h
@@ -23,8 +23,10 @@
 #if defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM)
 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SPL_TEXT_BASE +	\
 					 CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE)
+#define CONFIG_SYS_UBOOT_BASE		0x50280000
 /* Image load address in RAM for DFU boot*/
 #else
+#define CONFIG_SYS_UBOOT_BASE		0x50080000
 /*
  * Maximum size in memory allocated to the SPL BSS. Keep it as tight as
  * possible (to allow the build to go through), as this directly affects
-- 
2.28.0

[PATCH 0/5] J7200: Add HyperFlash boot support

[Lokesh Vutla]

On 13/08/20 2:56 pm, Vignesh Raghavendra wrote:
> Add support to boot from HyperFlash on J7200 SoC

Applied to u-boot-ti.

Thanks and regards,
Lokesh