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From: Dmitry Osipenko <digetx@gmail.com>
To: Thierry Reding <thierry.reding@gmail.com>,
	Jonathan Hunter <jonathanh@nvidia.com>,
	Georgi Djakov <georgi.djakov@linaro.org>,
	Rob Herring <robh+dt@kernel.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Peter De Schrijver <pdeschrijver@nvidia.com>,
	MyungJoo Ham <myungjoo.ham@samsung.com>,
	Kyungmin Park <kyungmin.park@samsung.com>,
	Chanwoo Choi <cw00.choi@samsung.com>,
	Mikko Perttunen <cyndis@kapsi.fi>
Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org,
	linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
	devicetree@vger.kernel.org
Subject: [PATCH v5 30/36] memory: tegra20-emc: Register as interconnect provider
Date: Fri, 14 Aug 2020 03:06:15 +0300	[thread overview]
Message-ID: <20200814000621.8415-31-digetx@gmail.com> (raw)
In-Reply-To: <20200814000621.8415-1-digetx@gmail.com>

Now memory controller is a memory interconnection provider. This allows us
to use interconnect API in order to change memory configuration.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
 drivers/memory/tegra/tegra20-emc.c | 110 +++++++++++++++++++++++++++++
 1 file changed, 110 insertions(+)

diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c
index 89e077d797e7..437d9d789941 100644
--- a/drivers/memory/tegra/tegra20-emc.c
+++ b/drivers/memory/tegra/tegra20-emc.c
@@ -9,6 +9,7 @@
 #include <linux/clk/tegra.h>
 #include <linux/debugfs.h>
 #include <linux/err.h>
+#include <linux/interconnect-provider.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
 #include <linux/iopoll.h>
@@ -148,6 +149,7 @@ struct emc_timing {
 struct tegra_emc {
 	struct device *dev;
 	struct notifier_block clk_nb;
+	struct icc_provider provider;
 	struct clk *clk;
 	void __iomem *regs;
 
@@ -661,6 +663,113 @@ static void tegra_emc_debugfs_init(struct tegra_emc *emc)
 			    emc, &tegra_emc_debug_max_rate_fops);
 }
 
+static inline struct tegra_emc *
+to_tegra_emc_provider(struct icc_provider *provider)
+{
+	return container_of(provider, struct tegra_emc, provider);
+}
+
+static struct icc_node *
+emc_of_icc_xlate(struct of_phandle_args *spec, void *data)
+{
+	struct icc_provider *provider = data;
+	struct icc_node *node;
+
+	/* External Memory is the only possible ICC route */
+	list_for_each_entry(node, &provider->nodes, node_list) {
+		if (node->id == TEGRA_ICC_EMEM)
+			return node;
+	}
+
+	return ERR_PTR(-EINVAL);
+}
+
+static int emc_icc_set(struct icc_node *src, struct icc_node *dst)
+{
+	struct tegra_emc *emc = to_tegra_emc_provider(dst->provider);
+	unsigned long long rate = icc_units_to_bps(dst->avg_bw);
+	unsigned int dram_data_bus_width_bytes = 4;
+	unsigned int ddr = 2;
+	int err;
+
+	do_div(rate, ddr * dram_data_bus_width_bytes);
+	rate = min_t(u64, rate, U32_MAX);
+
+	err = clk_set_min_rate(emc->clk, rate);
+	if (err)
+		return err;
+
+	err = clk_set_rate(emc->clk, rate);
+	if (err)
+		return err;
+
+	return 0;
+}
+
+static int emc_icc_aggregate(struct icc_node *node,
+			     u32 tag, u32 avg_bw, u32 peak_bw,
+			     u32 *agg_avg, u32 *agg_peak)
+{
+	*agg_avg = min((u64)avg_bw + (*agg_avg), (u64)U32_MAX);
+	*agg_peak = max(*agg_peak, peak_bw);
+
+	return 0;
+}
+
+static int tegra_emc_interconnect_init(struct tegra_emc *emc)
+{
+	struct icc_node *node;
+	int err;
+
+	/* older device-trees don't have interconnect properties */
+	if (!of_find_property(emc->dev->of_node, "#interconnect-cells", NULL))
+		return 0;
+
+	emc->provider.dev = emc->dev;
+	emc->provider.set = emc_icc_set;
+	emc->provider.data = &emc->provider;
+	emc->provider.xlate = emc_of_icc_xlate;
+	emc->provider.aggregate = emc_icc_aggregate;
+
+	err = icc_provider_add(&emc->provider);
+	if (err)
+		goto err_msg;
+
+	/* create External Memory Controller node */
+	node = icc_node_create(TEGRA_ICC_EMC);
+	err = PTR_ERR_OR_ZERO(node);
+	if (err)
+		goto del_provider;
+
+	node->name = "External Memory Controller";
+	icc_node_add(node, &emc->provider);
+
+	/* link External Memory Controller to External Memory (DRAM) */
+	err = icc_link_create(node, TEGRA_ICC_EMEM);
+	if (err)
+		goto remove_nodes;
+
+	/* create External Memory node */
+	node = icc_node_create(TEGRA_ICC_EMEM);
+	err = PTR_ERR_OR_ZERO(node);
+	if (err)
+		goto remove_nodes;
+
+	node->name = "External Memory (DRAM)";
+	icc_node_add(node, &emc->provider);
+
+	return 0;
+
+remove_nodes:
+	icc_nodes_remove(&emc->provider);
+del_provider:
+	icc_provider_del(&emc->provider);
+err_msg:
+	dev_err(emc->dev, "failed to initialize ICC: %d\n", err);
+
+	return err;
+}
+
 static int tegra_emc_init_mc_timings(struct tegra_emc *emc)
 {
 	struct tegra_mc_timing *timing;
@@ -773,6 +882,7 @@ static int tegra_emc_probe(struct platform_device *pdev)
 
 	platform_set_drvdata(pdev, emc);
 	tegra_emc_debugfs_init(emc);
+	tegra_emc_interconnect_init(emc);
 
 	/*
 	 * Don't allow the kernel module to be unloaded. Unloading adds some
-- 
2.27.0


WARNING: multiple messages have this Message-ID (diff)
From: Dmitry Osipenko <digetx@gmail.com>
To: Thierry Reding <thierry.reding@gmail.com>,
	Jonathan Hunter <jonathanh@nvidia.com>,
	Georgi Djakov <georgi.djakov@linaro.org>,
	Rob Herring <robh+dt@kernel.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Peter De Schrijver <pdeschrijver@nvidia.com>,
	MyungJoo Ham <myungjoo.ham@samsung.com>,
	Kyungmin Park <kyungmin.park@samsung.com>,
	Chanwoo Choi <cw00.choi@samsung.com>,
	Mikko Perttunen <cyndis@kapsi.fi>
Cc: linux-tegra@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
	linux-pm@vger.kernel.org
Subject: [PATCH v5 30/36] memory: tegra20-emc: Register as interconnect provider
Date: Fri, 14 Aug 2020 03:06:15 +0300	[thread overview]
Message-ID: <20200814000621.8415-31-digetx@gmail.com> (raw)
In-Reply-To: <20200814000621.8415-1-digetx@gmail.com>

Now memory controller is a memory interconnection provider. This allows us
to use interconnect API in order to change memory configuration.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
 drivers/memory/tegra/tegra20-emc.c | 110 +++++++++++++++++++++++++++++
 1 file changed, 110 insertions(+)

diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c
index 89e077d797e7..437d9d789941 100644
--- a/drivers/memory/tegra/tegra20-emc.c
+++ b/drivers/memory/tegra/tegra20-emc.c
@@ -9,6 +9,7 @@
 #include <linux/clk/tegra.h>
 #include <linux/debugfs.h>
 #include <linux/err.h>
+#include <linux/interconnect-provider.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
 #include <linux/iopoll.h>
@@ -148,6 +149,7 @@ struct emc_timing {
 struct tegra_emc {
 	struct device *dev;
 	struct notifier_block clk_nb;
+	struct icc_provider provider;
 	struct clk *clk;
 	void __iomem *regs;
 
@@ -661,6 +663,113 @@ static void tegra_emc_debugfs_init(struct tegra_emc *emc)
 			    emc, &tegra_emc_debug_max_rate_fops);
 }
 
+static inline struct tegra_emc *
+to_tegra_emc_provider(struct icc_provider *provider)
+{
+	return container_of(provider, struct tegra_emc, provider);
+}
+
+static struct icc_node *
+emc_of_icc_xlate(struct of_phandle_args *spec, void *data)
+{
+	struct icc_provider *provider = data;
+	struct icc_node *node;
+
+	/* External Memory is the only possible ICC route */
+	list_for_each_entry(node, &provider->nodes, node_list) {
+		if (node->id == TEGRA_ICC_EMEM)
+			return node;
+	}
+
+	return ERR_PTR(-EINVAL);
+}
+
+static int emc_icc_set(struct icc_node *src, struct icc_node *dst)
+{
+	struct tegra_emc *emc = to_tegra_emc_provider(dst->provider);
+	unsigned long long rate = icc_units_to_bps(dst->avg_bw);
+	unsigned int dram_data_bus_width_bytes = 4;
+	unsigned int ddr = 2;
+	int err;
+
+	do_div(rate, ddr * dram_data_bus_width_bytes);
+	rate = min_t(u64, rate, U32_MAX);
+
+	err = clk_set_min_rate(emc->clk, rate);
+	if (err)
+		return err;
+
+	err = clk_set_rate(emc->clk, rate);
+	if (err)
+		return err;
+
+	return 0;
+}
+
+static int emc_icc_aggregate(struct icc_node *node,
+			     u32 tag, u32 avg_bw, u32 peak_bw,
+			     u32 *agg_avg, u32 *agg_peak)
+{
+	*agg_avg = min((u64)avg_bw + (*agg_avg), (u64)U32_MAX);
+	*agg_peak = max(*agg_peak, peak_bw);
+
+	return 0;
+}
+
+static int tegra_emc_interconnect_init(struct tegra_emc *emc)
+{
+	struct icc_node *node;
+	int err;
+
+	/* older device-trees don't have interconnect properties */
+	if (!of_find_property(emc->dev->of_node, "#interconnect-cells", NULL))
+		return 0;
+
+	emc->provider.dev = emc->dev;
+	emc->provider.set = emc_icc_set;
+	emc->provider.data = &emc->provider;
+	emc->provider.xlate = emc_of_icc_xlate;
+	emc->provider.aggregate = emc_icc_aggregate;
+
+	err = icc_provider_add(&emc->provider);
+	if (err)
+		goto err_msg;
+
+	/* create External Memory Controller node */
+	node = icc_node_create(TEGRA_ICC_EMC);
+	err = PTR_ERR_OR_ZERO(node);
+	if (err)
+		goto del_provider;
+
+	node->name = "External Memory Controller";
+	icc_node_add(node, &emc->provider);
+
+	/* link External Memory Controller to External Memory (DRAM) */
+	err = icc_link_create(node, TEGRA_ICC_EMEM);
+	if (err)
+		goto remove_nodes;
+
+	/* create External Memory node */
+	node = icc_node_create(TEGRA_ICC_EMEM);
+	err = PTR_ERR_OR_ZERO(node);
+	if (err)
+		goto remove_nodes;
+
+	node->name = "External Memory (DRAM)";
+	icc_node_add(node, &emc->provider);
+
+	return 0;
+
+remove_nodes:
+	icc_nodes_remove(&emc->provider);
+del_provider:
+	icc_provider_del(&emc->provider);
+err_msg:
+	dev_err(emc->dev, "failed to initialize ICC: %d\n", err);
+
+	return err;
+}
+
 static int tegra_emc_init_mc_timings(struct tegra_emc *emc)
 {
 	struct tegra_mc_timing *timing;
@@ -773,6 +882,7 @@ static int tegra_emc_probe(struct platform_device *pdev)
 
 	platform_set_drvdata(pdev, emc);
 	tegra_emc_debugfs_init(emc);
+	tegra_emc_interconnect_init(emc);
 
 	/*
 	 * Don't allow the kernel module to be unloaded. Unloading adds some
-- 
2.27.0

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  parent reply	other threads:[~2020-08-14  0:07 UTC|newest]

Thread overview: 94+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-08-14  0:05 [PATCH v5 00/36] Introduce memory interconnect for NVIDIA Tegra SoCs Dmitry Osipenko
2020-08-14  0:05 ` Dmitry Osipenko
2020-08-14  0:05 ` [PATCH v5 01/36] clk: Export clk_hw_reparent() Dmitry Osipenko
2020-08-14  0:05   ` Dmitry Osipenko
2020-08-14  0:05 ` [PATCH v5 02/36] clk: tegra: Remove Memory Controller lock Dmitry Osipenko
2020-08-14  0:05   ` Dmitry Osipenko
2020-08-14  0:05 ` [PATCH v5 03/36] clk: tegra: Export Tegra20 EMC kernel symbols Dmitry Osipenko
2020-08-14  0:05   ` Dmitry Osipenko
2020-08-14  0:05 ` [PATCH v5 04/36] memory: tegra20-emc: Make driver modular Dmitry Osipenko
2020-08-14  0:05   ` Dmitry Osipenko
2020-08-14  0:05 ` [PATCH v5 05/36] memory: tegra30-emc: " Dmitry Osipenko
2020-08-14  0:05   ` Dmitry Osipenko
2020-08-14  0:05 ` [PATCH v5 06/36] memory: tegra124-emc: " Dmitry Osipenko
2020-08-14  0:05   ` Dmitry Osipenko
2020-08-14  0:05 ` [PATCH v5 07/36] memory: tegra124-emc: Use devm_platform_ioremap_resource Dmitry Osipenko
2020-08-14  0:05   ` Dmitry Osipenko
2020-08-14  0:05 ` [PATCH v5 08/36] soc/tegra: fuse: Export tegra_read_ram_code() Dmitry Osipenko
2020-08-14  0:05   ` Dmitry Osipenko
2020-08-14  0:05 ` [PATCH v5 09/36] memory: tegra20-emc: Initialize MC timings Dmitry Osipenko
2020-08-14  0:05   ` Dmitry Osipenko
2020-08-14  0:05 ` [PATCH v5 10/36] PM / devfreq: tegra20: Silence deferred probe error Dmitry Osipenko
2020-08-14  0:05   ` Dmitry Osipenko
2020-08-14  0:05 ` [PATCH v5 11/36] PM / devfreq: tegra30: " Dmitry Osipenko
2020-08-14  0:05   ` Dmitry Osipenko
2020-08-14  0:05 ` [PATCH v5 12/36] PM / devfreq: tegra20: Use MC timings for building OPP table Dmitry Osipenko
2020-08-14  0:05   ` Dmitry Osipenko
2020-08-14  1:00   ` Chanwoo Choi
2020-08-14  1:00     ` Chanwoo Choi
2020-08-14  0:05 ` [PATCH v5 13/36] PM / devfreq: tegra30: " Dmitry Osipenko
2020-08-14  0:05   ` Dmitry Osipenko
2020-08-14  2:02   ` Chanwoo Choi
2020-08-14  2:02     ` Chanwoo Choi
2020-08-14 16:47     ` Dmitry Osipenko
2020-08-14 16:47       ` Dmitry Osipenko
2020-08-28  1:47       ` Chanwoo Choi
2020-08-28  1:47         ` Chanwoo Choi
2020-08-28  8:30         ` Dmitry Osipenko
2020-08-28  8:30           ` Dmitry Osipenko
2020-08-14  0:05 ` [PATCH v5 14/36] PM / devfreq: tegra20: Add error messages to tegra_devfreq_target() Dmitry Osipenko
2020-08-14  0:05   ` Dmitry Osipenko
2020-08-14  0:06 ` [PATCH v5 15/36] PM / devfreq: tegra30: " Dmitry Osipenko
2020-08-14  0:06   ` Dmitry Osipenko
2020-08-14  0:06 ` [PATCH v5 16/36] PM / devfreq: tegra20: Adjust clocks conversion ratio and polling interval Dmitry Osipenko
2020-08-14  0:06   ` Dmitry Osipenko
2020-08-14  0:06 ` [PATCH v5 17/36] PM / devfreq: tegra20: Relax Kconfig dependency Dmitry Osipenko
2020-08-14  0:06   ` Dmitry Osipenko
2020-08-14  0:06 ` [PATCH v5 18/36] dt-bindings: memory: tegra20: mc: Document new interconnect property Dmitry Osipenko
2020-08-14  0:06   ` Dmitry Osipenko
2020-08-14  0:06 ` [PATCH v5 19/36] dt-bindings: memory: tegra20: emc: " Dmitry Osipenko
2020-08-14  0:06   ` Dmitry Osipenko
2020-08-14  0:06 ` [PATCH v5 20/36] dt-bindings: memory: tegra30: mc: " Dmitry Osipenko
2020-08-14  0:06   ` Dmitry Osipenko
2020-08-14  0:06 ` [PATCH v5 21/36] dt-bindings: memory: tegra30: emc: " Dmitry Osipenko
2020-08-14  0:06   ` Dmitry Osipenko
2020-08-14  0:06 ` [PATCH v5 22/36] dt-bindings: host1x: Document new interconnect properties Dmitry Osipenko
2020-08-14  0:06   ` Dmitry Osipenko
2020-08-25  2:09   ` Rob Herring
2020-08-25  2:09     ` Rob Herring
2020-08-14  0:06 ` [PATCH v5 23/36] dt-bindings: memory: tegra20: Add memory client IDs Dmitry Osipenko
2020-08-14  0:06   ` Dmitry Osipenko
2020-08-14  0:06 ` [PATCH v5 24/36] dt-bindings: memory: tegra30: " Dmitry Osipenko
2020-08-14  0:06   ` Dmitry Osipenko
2020-08-14  0:06 ` [PATCH v5 25/36] ARM: tegra: Add interconnect properties to Tegra20 device-tree Dmitry Osipenko
2020-08-14  0:06   ` Dmitry Osipenko
2020-08-14  0:06 ` [PATCH v5 26/36] ARM: tegra: Add interconnect properties to Tegra30 device-tree Dmitry Osipenko
2020-08-14  0:06   ` Dmitry Osipenko
2020-08-14  0:06 ` [PATCH v5 27/36] memory: tegra-mc: Register as interconnect provider Dmitry Osipenko
2020-08-14  0:06   ` Dmitry Osipenko
2020-09-09  8:31   ` Georgi Djakov
2020-09-09  8:31     ` Georgi Djakov
2020-09-09 21:15     ` Dmitry Osipenko
2020-09-09 21:15       ` Dmitry Osipenko
2020-08-14  0:06 ` [PATCH v5 28/36] memory: tegra20-emc: Use devm_platform_ioremap_resource Dmitry Osipenko
2020-08-14  0:06   ` Dmitry Osipenko
2020-08-14  0:06 ` [PATCH v5 29/36] memory: tegra20-emc: Continue probing if timings are missing in device-tree Dmitry Osipenko
2020-08-14  0:06   ` Dmitry Osipenko
2020-08-14  0:06 ` Dmitry Osipenko [this message]
2020-08-14  0:06   ` [PATCH v5 30/36] memory: tegra20-emc: Register as interconnect provider Dmitry Osipenko
2020-09-09  8:32   ` Georgi Djakov
2020-09-09  8:32     ` Georgi Djakov
2020-08-14  0:06 ` [PATCH v5 31/36] memory: tegra20-emc: Create tegra20-devfreq device Dmitry Osipenko
2020-08-14  0:06   ` Dmitry Osipenko
2020-08-14  0:06 ` [PATCH v5 32/36] memory: tegra30-emc: Continue probing if timings are missing in device-tree Dmitry Osipenko
2020-08-14  0:06   ` Dmitry Osipenko
2020-08-14  0:06 ` [PATCH v5 33/36] memory: tegra30-emc: Register as interconnect provider Dmitry Osipenko
2020-08-14  0:06   ` Dmitry Osipenko
2020-09-09  8:32   ` Georgi Djakov
2020-09-09  8:32     ` Georgi Djakov
2020-08-14  0:06 ` [PATCH v5 34/36] drm/tegra: dc: Support memory bandwidth management Dmitry Osipenko
2020-08-14  0:06   ` Dmitry Osipenko
2020-08-14  0:06 ` [PATCH v5 35/36] drm/tegra: dc: Tune up high priority request controls for Tegra20 Dmitry Osipenko
2020-08-14  0:06   ` Dmitry Osipenko
2020-08-14  0:06 ` [PATCH v5 36/36] drm/tegra: dc: Extend debug stats with total number of events Dmitry Osipenko
2020-08-14  0:06   ` Dmitry Osipenko

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