* [PATCH] dmaengine: dw-edma: Fix linked list physical address calculation on non-64 bits architectures
@ 2020-08-13 14:13 Gustavo Pimentel
2020-08-13 17:07 ` kernel test robot
2020-08-25 11:09 ` Vinod Koul
0 siblings, 2 replies; 6+ messages in thread
From: Gustavo Pimentel @ 2020-08-13 14:13 UTC (permalink / raw)
To: vkoul, dmaengine; +Cc: Gustavo Pimentel, Joao Pinto, stable
Fix linked list physical address calculation on non-64 bits architectures.
The paddr variable is phys_addr_t type, which can assume a different
type (u64 or u32) depending on the conditional compilation flag
CONFIG_PHYS_ADDR_T_64BIT.
Since this variable is used in with upper_32 bits() macro to get the
value from 32 to 63 bits, on a non-64 bits architecture this variable
will assume a u32 type, it can cause a compilation warning.
This issue was reported by a Coverity analysis.
Fixes: 7e4b8a4fbe2c ("dmaengine: Add Synopsys eDMA IP version 0 support")
Cc: Joao Pinto <jpinto@synopsys.com>
Cc: stable@vger.kernel.org
Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
---
drivers/dma/dw-edma/dw-edma-v0-core.c | 23 +++++++++++++++++------
1 file changed, 17 insertions(+), 6 deletions(-)
diff --git a/drivers/dma/dw-edma/dw-edma-v0-core.c b/drivers/dma/dw-edma/dw-edma-v0-core.c
index 692de47..cfabbf5 100644
--- a/drivers/dma/dw-edma/dw-edma-v0-core.c
+++ b/drivers/dma/dw-edma/dw-edma-v0-core.c
@@ -229,8 +229,13 @@ static void dw_edma_v0_core_write_chunk(struct dw_edma_chunk *chunk)
/* Channel control */
SET_LL(&llp->control, control);
/* Linked list - low, high */
- SET_LL(&llp->llp_low, lower_32_bits(chunk->ll_region.paddr));
- SET_LL(&llp->llp_high, upper_32_bits(chunk->ll_region.paddr));
+ #ifdef CONFIG_PHYS_ADDR_T_64BIT
+ SET_LL(&llp->llp_low, lower_32_bits(chunk->ll_region.paddr));
+ SET_LL(&llp->llp_high, upper_32_bits(chunk->ll_region.paddr));
+ #else /* CONFIG_PHYS_ADDR_T_64BIT */
+ SET_LL(&llp->llp_low, chunk->ll_region.paddr);
+ SET_LL(&llp->llp_high, 0x0);
+ #endif /* CONFIG_PHYS_ADDR_T_64BIT */
}
void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first)
@@ -257,10 +262,16 @@ void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first)
SET_CH(dw, chan->dir, chan->id, ch_control1,
(DW_EDMA_V0_CCS | DW_EDMA_V0_LLE));
/* Linked list - low, high */
- SET_CH(dw, chan->dir, chan->id, llp_low,
- lower_32_bits(chunk->ll_region.paddr));
- SET_CH(dw, chan->dir, chan->id, llp_high,
- upper_32_bits(chunk->ll_region.paddr));
+ #ifdef CONFIG_PHYS_ADDR_T_64BIT
+ SET_CH(dw, chan->dir, chan->id, llp_low,
+ lower_32_bits(chunk->ll_region.paddr));
+ SET_CH(dw, chan->dir, chan->id, llp_high,
+ upper_32_bits(chunk->ll_region.paddr));
+ #else /* CONFIG_PHYS_ADDR_T_64BIT */
+ SET_CH(dw, chan->dir, chan->id, llp_low,
+ chunk->ll_region.paddr);
+ SET_CH(dw, chan->dir, chan->id, llp_high, 0x0);
+ #endif /* CONFIG_PHYS_ADDR_T_64BIT*/
}
/* Doorbell */
SET_RW(dw, chan->dir, doorbell,
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] dmaengine: dw-edma: Fix linked list physical address calculation on non-64 bits architectures
2020-08-13 14:13 [PATCH] dmaengine: dw-edma: Fix linked list physical address calculation on non-64 bits architectures Gustavo Pimentel
@ 2020-08-13 17:07 ` kernel test robot
2020-08-25 11:09 ` Vinod Koul
1 sibling, 0 replies; 6+ messages in thread
From: kernel test robot @ 2020-08-13 17:07 UTC (permalink / raw)
To: Gustavo Pimentel, vkoul, dmaengine
Cc: kbuild-all, Gustavo Pimentel, Joao Pinto, stable
[-- Attachment #1: Type: text/plain, Size: 8377 bytes --]
Hi Gustavo,
I love your patch! Perhaps something to improve:
[auto build test WARNING on vkoul-dmaengine/next]
[also build test WARNING on v5.8 next-20200813]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Gustavo-Pimentel/dmaengine-dw-edma-Fix-linked-list-physical-address-calculation-on-non-64-bits-architectures/20200813-221607
base: https://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine.git next
config: x86_64-randconfig-m001-20200811 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
smatch warnings:
drivers/dma/dw-edma/dw-edma-v0-core.c:233 dw_edma_v0_core_write_chunk() warn: inconsistent indenting
drivers/dma/dw-edma/dw-edma-v0-core.c:266 dw_edma_v0_core_start() warn: inconsistent indenting
vim +233 drivers/dma/dw-edma/dw-edma-v0-core.c
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 191
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 192 static void dw_edma_v0_core_write_chunk(struct dw_edma_chunk *chunk)
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 193 {
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 194 struct dw_edma_burst *child;
756c3ef93492af Arnd Bergmann 2019-07-22 195 struct dw_edma_v0_lli __iomem *lli;
756c3ef93492af Arnd Bergmann 2019-07-22 196 struct dw_edma_v0_llp __iomem *llp;
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 197 u32 control = 0, i = 0;
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 198 int j;
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 199
756c3ef93492af Arnd Bergmann 2019-07-22 200 lli = chunk->ll_region.vaddr;
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 201
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 202 if (chunk->cb)
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 203 control = DW_EDMA_V0_CB;
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 204
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 205 j = chunk->bursts_alloc;
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 206 list_for_each_entry(child, &chunk->burst->list, list) {
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 207 j--;
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 208 if (!j)
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 209 control |= (DW_EDMA_V0_LIE | DW_EDMA_V0_RIE);
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 210
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 211 /* Channel control */
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 212 SET_LL(&lli[i].control, control);
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 213 /* Transfer size */
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 214 SET_LL(&lli[i].transfer_size, child->sz);
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 215 /* SAR - low, high */
6f4722b1d1ebf2 Arnd Bergmann 2019-07-22 216 SET_LL(&lli[i].sar_low, lower_32_bits(child->sar));
6f4722b1d1ebf2 Arnd Bergmann 2019-07-22 217 SET_LL(&lli[i].sar_high, upper_32_bits(child->sar));
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 218 /* DAR - low, high */
6f4722b1d1ebf2 Arnd Bergmann 2019-07-22 219 SET_LL(&lli[i].dar_low, lower_32_bits(child->dar));
6f4722b1d1ebf2 Arnd Bergmann 2019-07-22 220 SET_LL(&lli[i].dar_high, upper_32_bits(child->dar));
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 221 i++;
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 222 }
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 223
756c3ef93492af Arnd Bergmann 2019-07-22 224 llp = (void __iomem *)&lli[i];
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 225 control = DW_EDMA_V0_LLP | DW_EDMA_V0_TCB;
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 226 if (!chunk->cb)
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 227 control |= DW_EDMA_V0_CB;
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 228
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 229 /* Channel control */
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 230 SET_LL(&llp->control, control);
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 231 /* Linked list - low, high */
c6442f1a5db52e Gustavo Pimentel 2020-08-13 232 #ifdef CONFIG_PHYS_ADDR_T_64BIT
6f4722b1d1ebf2 Arnd Bergmann 2019-07-22 @233 SET_LL(&llp->llp_low, lower_32_bits(chunk->ll_region.paddr));
6f4722b1d1ebf2 Arnd Bergmann 2019-07-22 234 SET_LL(&llp->llp_high, upper_32_bits(chunk->ll_region.paddr));
c6442f1a5db52e Gustavo Pimentel 2020-08-13 235 #else /* CONFIG_PHYS_ADDR_T_64BIT */
c6442f1a5db52e Gustavo Pimentel 2020-08-13 236 SET_LL(&llp->llp_low, chunk->ll_region.paddr);
c6442f1a5db52e Gustavo Pimentel 2020-08-13 237 SET_LL(&llp->llp_high, 0x0);
c6442f1a5db52e Gustavo Pimentel 2020-08-13 238 #endif /* CONFIG_PHYS_ADDR_T_64BIT */
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 239 }
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 240
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 241 void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first)
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 242 {
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 243 struct dw_edma_chan *chan = chunk->chan;
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 244 struct dw_edma *dw = chan->chip->dw;
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 245 u32 tmp;
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 246
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 247 dw_edma_v0_core_write_chunk(chunk);
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 248
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 249 if (first) {
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 250 /* Enable engine */
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 251 SET_RW(dw, chan->dir, engine_en, BIT(0));
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 252 /* Interrupt unmask - done, abort */
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 253 tmp = GET_RW(dw, chan->dir, int_mask);
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 254 tmp &= ~FIELD_PREP(EDMA_V0_DONE_INT_MASK, BIT(chan->id));
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 255 tmp &= ~FIELD_PREP(EDMA_V0_ABORT_INT_MASK, BIT(chan->id));
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 256 SET_RW(dw, chan->dir, int_mask, tmp);
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 257 /* Linked list error */
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 258 tmp = GET_RW(dw, chan->dir, linked_list_err_en);
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 259 tmp |= FIELD_PREP(EDMA_V0_LINKED_LIST_ERR_MASK, BIT(chan->id));
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 260 SET_RW(dw, chan->dir, linked_list_err_en, tmp);
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 261 /* Channel control */
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 262 SET_CH(dw, chan->dir, chan->id, ch_control1,
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 263 (DW_EDMA_V0_CCS | DW_EDMA_V0_LLE));
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 264 /* Linked list - low, high */
c6442f1a5db52e Gustavo Pimentel 2020-08-13 265 #ifdef CONFIG_PHYS_ADDR_T_64BIT
6f4722b1d1ebf2 Arnd Bergmann 2019-07-22 @266 SET_CH(dw, chan->dir, chan->id, llp_low,
6f4722b1d1ebf2 Arnd Bergmann 2019-07-22 267 lower_32_bits(chunk->ll_region.paddr));
6f4722b1d1ebf2 Arnd Bergmann 2019-07-22 268 SET_CH(dw, chan->dir, chan->id, llp_high,
6f4722b1d1ebf2 Arnd Bergmann 2019-07-22 269 upper_32_bits(chunk->ll_region.paddr));
c6442f1a5db52e Gustavo Pimentel 2020-08-13 270 #else /* CONFIG_PHYS_ADDR_T_64BIT */
c6442f1a5db52e Gustavo Pimentel 2020-08-13 271 SET_CH(dw, chan->dir, chan->id, llp_low,
c6442f1a5db52e Gustavo Pimentel 2020-08-13 272 chunk->ll_region.paddr);
c6442f1a5db52e Gustavo Pimentel 2020-08-13 273 SET_CH(dw, chan->dir, chan->id, llp_high, 0x0);
c6442f1a5db52e Gustavo Pimentel 2020-08-13 274 #endif /* CONFIG_PHYS_ADDR_T_64BIT*/
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 275 }
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 276 /* Doorbell */
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 277 SET_RW(dw, chan->dir, doorbell,
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 278 FIELD_PREP(EDMA_V0_DOORBELL_CH_MASK, chan->id));
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 279 }
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 280
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 39302 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] dmaengine: dw-edma: Fix linked list physical address calculation on non-64 bits architectures
@ 2020-08-13 17:07 ` kernel test robot
0 siblings, 0 replies; 6+ messages in thread
From: kernel test robot @ 2020-08-13 17:07 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 8497 bytes --]
Hi Gustavo,
I love your patch! Perhaps something to improve:
[auto build test WARNING on vkoul-dmaengine/next]
[also build test WARNING on v5.8 next-20200813]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Gustavo-Pimentel/dmaengine-dw-edma-Fix-linked-list-physical-address-calculation-on-non-64-bits-architectures/20200813-221607
base: https://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine.git next
config: x86_64-randconfig-m001-20200811 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
smatch warnings:
drivers/dma/dw-edma/dw-edma-v0-core.c:233 dw_edma_v0_core_write_chunk() warn: inconsistent indenting
drivers/dma/dw-edma/dw-edma-v0-core.c:266 dw_edma_v0_core_start() warn: inconsistent indenting
vim +233 drivers/dma/dw-edma/dw-edma-v0-core.c
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 191
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 192 static void dw_edma_v0_core_write_chunk(struct dw_edma_chunk *chunk)
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 193 {
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 194 struct dw_edma_burst *child;
756c3ef93492af Arnd Bergmann 2019-07-22 195 struct dw_edma_v0_lli __iomem *lli;
756c3ef93492af Arnd Bergmann 2019-07-22 196 struct dw_edma_v0_llp __iomem *llp;
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 197 u32 control = 0, i = 0;
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 198 int j;
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 199
756c3ef93492af Arnd Bergmann 2019-07-22 200 lli = chunk->ll_region.vaddr;
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 201
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 202 if (chunk->cb)
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 203 control = DW_EDMA_V0_CB;
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 204
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 205 j = chunk->bursts_alloc;
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 206 list_for_each_entry(child, &chunk->burst->list, list) {
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 207 j--;
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 208 if (!j)
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 209 control |= (DW_EDMA_V0_LIE | DW_EDMA_V0_RIE);
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 210
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 211 /* Channel control */
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 212 SET_LL(&lli[i].control, control);
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 213 /* Transfer size */
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 214 SET_LL(&lli[i].transfer_size, child->sz);
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 215 /* SAR - low, high */
6f4722b1d1ebf2 Arnd Bergmann 2019-07-22 216 SET_LL(&lli[i].sar_low, lower_32_bits(child->sar));
6f4722b1d1ebf2 Arnd Bergmann 2019-07-22 217 SET_LL(&lli[i].sar_high, upper_32_bits(child->sar));
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 218 /* DAR - low, high */
6f4722b1d1ebf2 Arnd Bergmann 2019-07-22 219 SET_LL(&lli[i].dar_low, lower_32_bits(child->dar));
6f4722b1d1ebf2 Arnd Bergmann 2019-07-22 220 SET_LL(&lli[i].dar_high, upper_32_bits(child->dar));
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 221 i++;
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 222 }
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 223
756c3ef93492af Arnd Bergmann 2019-07-22 224 llp = (void __iomem *)&lli[i];
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 225 control = DW_EDMA_V0_LLP | DW_EDMA_V0_TCB;
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 226 if (!chunk->cb)
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 227 control |= DW_EDMA_V0_CB;
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 228
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 229 /* Channel control */
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 230 SET_LL(&llp->control, control);
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 231 /* Linked list - low, high */
c6442f1a5db52e Gustavo Pimentel 2020-08-13 232 #ifdef CONFIG_PHYS_ADDR_T_64BIT
6f4722b1d1ebf2 Arnd Bergmann 2019-07-22 @233 SET_LL(&llp->llp_low, lower_32_bits(chunk->ll_region.paddr));
6f4722b1d1ebf2 Arnd Bergmann 2019-07-22 234 SET_LL(&llp->llp_high, upper_32_bits(chunk->ll_region.paddr));
c6442f1a5db52e Gustavo Pimentel 2020-08-13 235 #else /* CONFIG_PHYS_ADDR_T_64BIT */
c6442f1a5db52e Gustavo Pimentel 2020-08-13 236 SET_LL(&llp->llp_low, chunk->ll_region.paddr);
c6442f1a5db52e Gustavo Pimentel 2020-08-13 237 SET_LL(&llp->llp_high, 0x0);
c6442f1a5db52e Gustavo Pimentel 2020-08-13 238 #endif /* CONFIG_PHYS_ADDR_T_64BIT */
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 239 }
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 240
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 241 void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first)
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 242 {
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 243 struct dw_edma_chan *chan = chunk->chan;
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 244 struct dw_edma *dw = chan->chip->dw;
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 245 u32 tmp;
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 246
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 247 dw_edma_v0_core_write_chunk(chunk);
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 248
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 249 if (first) {
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 250 /* Enable engine */
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 251 SET_RW(dw, chan->dir, engine_en, BIT(0));
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 252 /* Interrupt unmask - done, abort */
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 253 tmp = GET_RW(dw, chan->dir, int_mask);
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 254 tmp &= ~FIELD_PREP(EDMA_V0_DONE_INT_MASK, BIT(chan->id));
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 255 tmp &= ~FIELD_PREP(EDMA_V0_ABORT_INT_MASK, BIT(chan->id));
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 256 SET_RW(dw, chan->dir, int_mask, tmp);
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 257 /* Linked list error */
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 258 tmp = GET_RW(dw, chan->dir, linked_list_err_en);
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 259 tmp |= FIELD_PREP(EDMA_V0_LINKED_LIST_ERR_MASK, BIT(chan->id));
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 260 SET_RW(dw, chan->dir, linked_list_err_en, tmp);
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 261 /* Channel control */
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 262 SET_CH(dw, chan->dir, chan->id, ch_control1,
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 263 (DW_EDMA_V0_CCS | DW_EDMA_V0_LLE));
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 264 /* Linked list - low, high */
c6442f1a5db52e Gustavo Pimentel 2020-08-13 265 #ifdef CONFIG_PHYS_ADDR_T_64BIT
6f4722b1d1ebf2 Arnd Bergmann 2019-07-22 @266 SET_CH(dw, chan->dir, chan->id, llp_low,
6f4722b1d1ebf2 Arnd Bergmann 2019-07-22 267 lower_32_bits(chunk->ll_region.paddr));
6f4722b1d1ebf2 Arnd Bergmann 2019-07-22 268 SET_CH(dw, chan->dir, chan->id, llp_high,
6f4722b1d1ebf2 Arnd Bergmann 2019-07-22 269 upper_32_bits(chunk->ll_region.paddr));
c6442f1a5db52e Gustavo Pimentel 2020-08-13 270 #else /* CONFIG_PHYS_ADDR_T_64BIT */
c6442f1a5db52e Gustavo Pimentel 2020-08-13 271 SET_CH(dw, chan->dir, chan->id, llp_low,
c6442f1a5db52e Gustavo Pimentel 2020-08-13 272 chunk->ll_region.paddr);
c6442f1a5db52e Gustavo Pimentel 2020-08-13 273 SET_CH(dw, chan->dir, chan->id, llp_high, 0x0);
c6442f1a5db52e Gustavo Pimentel 2020-08-13 274 #endif /* CONFIG_PHYS_ADDR_T_64BIT*/
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 275 }
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 276 /* Doorbell */
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 277 SET_RW(dw, chan->dir, doorbell,
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 278 FIELD_PREP(EDMA_V0_DOORBELL_CH_MASK, chan->id));
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 279 }
7e4b8a4fbe2cec Gustavo Pimentel 2019-06-04 280
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 39302 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] dmaengine: dw-edma: Fix linked list physical address calculation on non-64 bits architectures
2020-08-13 14:13 [PATCH] dmaengine: dw-edma: Fix linked list physical address calculation on non-64 bits architectures Gustavo Pimentel
2020-08-13 17:07 ` kernel test robot
@ 2020-08-25 11:09 ` Vinod Koul
2020-08-26 12:31 ` Gustavo Pimentel
1 sibling, 1 reply; 6+ messages in thread
From: Vinod Koul @ 2020-08-25 11:09 UTC (permalink / raw)
To: Gustavo Pimentel; +Cc: dmaengine, Joao Pinto, stable
On 13-08-20, 16:13, Gustavo Pimentel wrote:
> Fix linked list physical address calculation on non-64 bits architectures.
>
> The paddr variable is phys_addr_t type, which can assume a different
> type (u64 or u32) depending on the conditional compilation flag
> CONFIG_PHYS_ADDR_T_64BIT.
>
> Since this variable is used in with upper_32 bits() macro to get the
> value from 32 to 63 bits, on a non-64 bits architecture this variable
> will assume a u32 type, it can cause a compilation warning.
>
> This issue was reported by a Coverity analysis.
>
> Fixes: 7e4b8a4fbe2c ("dmaengine: Add Synopsys eDMA IP version 0 support")
>
> Cc: Joao Pinto <jpinto@synopsys.com>
> Cc: stable@vger.kernel.org
> Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
> ---
> drivers/dma/dw-edma/dw-edma-v0-core.c | 23 +++++++++++++++++------
> 1 file changed, 17 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/dma/dw-edma/dw-edma-v0-core.c b/drivers/dma/dw-edma/dw-edma-v0-core.c
> index 692de47..cfabbf5 100644
> --- a/drivers/dma/dw-edma/dw-edma-v0-core.c
> +++ b/drivers/dma/dw-edma/dw-edma-v0-core.c
> @@ -229,8 +229,13 @@ static void dw_edma_v0_core_write_chunk(struct dw_edma_chunk *chunk)
> /* Channel control */
> SET_LL(&llp->control, control);
> /* Linked list - low, high */
> - SET_LL(&llp->llp_low, lower_32_bits(chunk->ll_region.paddr));
> - SET_LL(&llp->llp_high, upper_32_bits(chunk->ll_region.paddr));
> + #ifdef CONFIG_PHYS_ADDR_T_64BIT
> + SET_LL(&llp->llp_low, lower_32_bits(chunk->ll_region.paddr));
> + SET_LL(&llp->llp_high, upper_32_bits(chunk->ll_region.paddr));
> + #else /* CONFIG_PHYS_ADDR_T_64BIT */
> + SET_LL(&llp->llp_low, chunk->ll_region.paddr);
> + SET_LL(&llp->llp_high, 0x0);
Shouldn't upper_32_bits(chunk->ll_region.paddr) return zero for non
64bit archs?
> + #endif /* CONFIG_PHYS_ADDR_T_64BIT */
> }
>
> void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first)
> @@ -257,10 +262,16 @@ void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first)
> SET_CH(dw, chan->dir, chan->id, ch_control1,
> (DW_EDMA_V0_CCS | DW_EDMA_V0_LLE));
> /* Linked list - low, high */
> - SET_CH(dw, chan->dir, chan->id, llp_low,
> - lower_32_bits(chunk->ll_region.paddr));
> - SET_CH(dw, chan->dir, chan->id, llp_high,
> - upper_32_bits(chunk->ll_region.paddr));
> + #ifdef CONFIG_PHYS_ADDR_T_64BIT
> + SET_CH(dw, chan->dir, chan->id, llp_low,
> + lower_32_bits(chunk->ll_region.paddr));
> + SET_CH(dw, chan->dir, chan->id, llp_high,
> + upper_32_bits(chunk->ll_region.paddr));
> + #else /* CONFIG_PHYS_ADDR_T_64BIT */
> + SET_CH(dw, chan->dir, chan->id, llp_low,
> + chunk->ll_region.paddr);
> + SET_CH(dw, chan->dir, chan->id, llp_high, 0x0);
> + #endif /* CONFIG_PHYS_ADDR_T_64BIT*/
> }
> /* Doorbell */
> SET_RW(dw, chan->dir, doorbell,
> --
> 2.7.4
--
~Vinod
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH] dmaengine: dw-edma: Fix linked list physical address calculation on non-64 bits architectures
2020-08-25 11:09 ` Vinod Koul
@ 2020-08-26 12:31 ` Gustavo Pimentel
2020-08-27 5:10 ` Vinod Koul
0 siblings, 1 reply; 6+ messages in thread
From: Gustavo Pimentel @ 2020-08-26 12:31 UTC (permalink / raw)
To: Vinod Koul; +Cc: dmaengine, Joao Pinto, stable
On Tue, Aug 25, 2020 at 12:9:37, Vinod Koul <vkoul@kernel.org> wrote:
> On 13-08-20, 16:13, Gustavo Pimentel wrote:
> > Fix linked list physical address calculation on non-64 bits architectures.
> >
> > The paddr variable is phys_addr_t type, which can assume a different
> > type (u64 or u32) depending on the conditional compilation flag
> > CONFIG_PHYS_ADDR_T_64BIT.
> >
> > Since this variable is used in with upper_32 bits() macro to get the
> > value from 32 to 63 bits, on a non-64 bits architecture this variable
> > will assume a u32 type, it can cause a compilation warning.
> >
> > This issue was reported by a Coverity analysis.
> >
> > Fixes: 7e4b8a4fbe2c ("dmaengine: Add Synopsys eDMA IP version 0 support")
> >
> > Cc: Joao Pinto <jpinto@synopsys.com>
> > Cc: stable@vger.kernel.org
> > Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
> > ---
> > drivers/dma/dw-edma/dw-edma-v0-core.c | 23 +++++++++++++++++------
> > 1 file changed, 17 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/dma/dw-edma/dw-edma-v0-core.c b/drivers/dma/dw-edma/dw-edma-v0-core.c
> > index 692de47..cfabbf5 100644
> > --- a/drivers/dma/dw-edma/dw-edma-v0-core.c
> > +++ b/drivers/dma/dw-edma/dw-edma-v0-core.c
> > @@ -229,8 +229,13 @@ static void dw_edma_v0_core_write_chunk(struct dw_edma_chunk *chunk)
> > /* Channel control */
> > SET_LL(&llp->control, control);
> > /* Linked list - low, high */
> > - SET_LL(&llp->llp_low, lower_32_bits(chunk->ll_region.paddr));
> > - SET_LL(&llp->llp_high, upper_32_bits(chunk->ll_region.paddr));
> > + #ifdef CONFIG_PHYS_ADDR_T_64BIT
> > + SET_LL(&llp->llp_low, lower_32_bits(chunk->ll_region.paddr));
> > + SET_LL(&llp->llp_high, upper_32_bits(chunk->ll_region.paddr));
> > + #else /* CONFIG_PHYS_ADDR_T_64BIT */
> > + SET_LL(&llp->llp_low, chunk->ll_region.paddr);
> > + SET_LL(&llp->llp_high, 0x0);
>
> Shouldn't upper_32_bits(chunk->ll_region.paddr) return zero for non
> 64bit archs?
At the time when I made this patch, I got a compiler warning about the
u32 vs u64 type mixing (phys_addr_t) and the macro usage upper_32 bits()
on non-64 bits architectures. That's why I made this patch, but now I
don't see this warning anymore.
Vinod, please disregard this patch.
-Gustavo
>
> > + #endif /* CONFIG_PHYS_ADDR_T_64BIT */
> > }
> >
> > void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first)
> > @@ -257,10 +262,16 @@ void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first)
> > SET_CH(dw, chan->dir, chan->id, ch_control1,
> > (DW_EDMA_V0_CCS | DW_EDMA_V0_LLE));
> > /* Linked list - low, high */
> > - SET_CH(dw, chan->dir, chan->id, llp_low,
> > - lower_32_bits(chunk->ll_region.paddr));
> > - SET_CH(dw, chan->dir, chan->id, llp_high,
> > - upper_32_bits(chunk->ll_region.paddr));
> > + #ifdef CONFIG_PHYS_ADDR_T_64BIT
> > + SET_CH(dw, chan->dir, chan->id, llp_low,
> > + lower_32_bits(chunk->ll_region.paddr));
> > + SET_CH(dw, chan->dir, chan->id, llp_high,
> > + upper_32_bits(chunk->ll_region.paddr));
> > + #else /* CONFIG_PHYS_ADDR_T_64BIT */
> > + SET_CH(dw, chan->dir, chan->id, llp_low,
> > + chunk->ll_region.paddr);
> > + SET_CH(dw, chan->dir, chan->id, llp_high, 0x0);
> > + #endif /* CONFIG_PHYS_ADDR_T_64BIT*/
> > }
> > /* Doorbell */
> > SET_RW(dw, chan->dir, doorbell,
> > --
> > 2.7.4
>
> --
> ~Vinod
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] dmaengine: dw-edma: Fix linked list physical address calculation on non-64 bits architectures
2020-08-26 12:31 ` Gustavo Pimentel
@ 2020-08-27 5:10 ` Vinod Koul
0 siblings, 0 replies; 6+ messages in thread
From: Vinod Koul @ 2020-08-27 5:10 UTC (permalink / raw)
To: Gustavo Pimentel; +Cc: dmaengine, Joao Pinto, stable
On 26-08-20, 12:31, Gustavo Pimentel wrote:
> On Tue, Aug 25, 2020 at 12:9:37, Vinod Koul <vkoul@kernel.org> wrote:
>
> > On 13-08-20, 16:13, Gustavo Pimentel wrote:
> > > Fix linked list physical address calculation on non-64 bits architectures.
> > >
> > > The paddr variable is phys_addr_t type, which can assume a different
> > > type (u64 or u32) depending on the conditional compilation flag
> > > CONFIG_PHYS_ADDR_T_64BIT.
> > >
> > > Since this variable is used in with upper_32 bits() macro to get the
> > > value from 32 to 63 bits, on a non-64 bits architecture this variable
> > > will assume a u32 type, it can cause a compilation warning.
> > >
> > > This issue was reported by a Coverity analysis.
> > >
> > > Fixes: 7e4b8a4fbe2c ("dmaengine: Add Synopsys eDMA IP version 0 support")
> > >
> > > Cc: Joao Pinto <jpinto@synopsys.com>
> > > Cc: stable@vger.kernel.org
> > > Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
> > > ---
> > > drivers/dma/dw-edma/dw-edma-v0-core.c | 23 +++++++++++++++++------
> > > 1 file changed, 17 insertions(+), 6 deletions(-)
> > >
> > > diff --git a/drivers/dma/dw-edma/dw-edma-v0-core.c b/drivers/dma/dw-edma/dw-edma-v0-core.c
> > > index 692de47..cfabbf5 100644
> > > --- a/drivers/dma/dw-edma/dw-edma-v0-core.c
> > > +++ b/drivers/dma/dw-edma/dw-edma-v0-core.c
> > > @@ -229,8 +229,13 @@ static void dw_edma_v0_core_write_chunk(struct dw_edma_chunk *chunk)
> > > /* Channel control */
> > > SET_LL(&llp->control, control);
> > > /* Linked list - low, high */
> > > - SET_LL(&llp->llp_low, lower_32_bits(chunk->ll_region.paddr));
> > > - SET_LL(&llp->llp_high, upper_32_bits(chunk->ll_region.paddr));
> > > + #ifdef CONFIG_PHYS_ADDR_T_64BIT
> > > + SET_LL(&llp->llp_low, lower_32_bits(chunk->ll_region.paddr));
> > > + SET_LL(&llp->llp_high, upper_32_bits(chunk->ll_region.paddr));
> > > + #else /* CONFIG_PHYS_ADDR_T_64BIT */
> > > + SET_LL(&llp->llp_low, chunk->ll_region.paddr);
> > > + SET_LL(&llp->llp_high, 0x0);
> >
> > Shouldn't upper_32_bits(chunk->ll_region.paddr) return zero for non
> > 64bit archs?
>
> At the time when I made this patch, I got a compiler warning about the
> u32 vs u64 type mixing (phys_addr_t) and the macro usage upper_32 bits()
> on non-64 bits architectures. That's why I made this patch, but now I
> don't see this warning anymore.
>
> Vinod, please disregard this patch.
Ok dropped
--
~Vinod
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-08-27 5:10 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-08-13 14:13 [PATCH] dmaengine: dw-edma: Fix linked list physical address calculation on non-64 bits architectures Gustavo Pimentel
2020-08-13 17:07 ` kernel test robot
2020-08-13 17:07 ` kernel test robot
2020-08-25 11:09 ` Vinod Koul
2020-08-26 12:31 ` Gustavo Pimentel
2020-08-27 5:10 ` Vinod Koul
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