[PATCH 0/5] Add PCIe EP nodes on RZ/G2[EMN]

[PATCH 0/5] Add PCIe EP nodes on RZ/G2[EMN]

[Lad Prabhakar]

Hi All,

This patch series adds support for PCIe EP nodes to Renesas r8a774a1,
r8a774b1 and r8a774c0 SoC's.

Patches are based on top of [1].

[1] https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/
    pci.git/log/?h=next

Cheers,
Prabhakar

Lad Prabhakar (5):
  dt-bindings: pci: rcar-pci-ep: Document r8a774a1 and r8a774b1
  misc: pci_endpoint_test: Add Device ID for RZ/G2M and RZ/G2N PCIe
    controllers
  arm64: dts: renesas: r8a774a1: Add PCIe EP nodes
  arm64: dts: renesas: r8a774b1: Add PCIe EP nodes
  arm64: dts: renesas: r8a774c0: Add PCIe EP node

 .../devicetree/bindings/pci/rcar-pci-ep.yaml  |  7 +++-
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi     | 38 +++++++++++++++++++
 arch/arm64/boot/dts/renesas/r8a774b1.dtsi     | 38 +++++++++++++++++++
 arch/arm64/boot/dts/renesas/r8a774c0.dtsi     | 19 ++++++++++
 drivers/misc/pci_endpoint_test.c              |  7 +++-
 5 files changed, 105 insertions(+), 4 deletions(-)

-- 
2.17.1

[PATCH 1/5] dt-bindings: pci: rcar-pci-ep: Document r8a774a1 and r8a774b1

[Lad Prabhakar]

Document the support for R-Car PCIe EP on R8A774A1 and R8A774B1 SoC
devices.

Also constify "renesas,rcar-gen3-pcie-ep" so that it can be used as
fallback compatible string for R-Car Gen3 and RZ/G2 devices as the
PCIe module is identical.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml b/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml
index aa483c7f27fd..70c45f72ab20 100644
--- a/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml
@@ -14,8 +14,11 @@ maintainers:
 properties:
   compatible:
     items:
-      - const: renesas,r8a774c0-pcie-ep
-      - const: renesas,rcar-gen3-pcie-ep
+      - enum:
+          - renesas,r8a774a1-pcie-ep     # RZ/G2M
+          - renesas,r8a774b1-pcie-ep     # RZ/G2N
+          - renesas,r8a774c0-pcie-ep     # RZ/G2E
+      - const: renesas,rcar-gen3-pcie-ep # R-Car Gen3 and RZ/G2
 
   reg:
     maxItems: 5
-- 
2.17.1

[PATCH 2/5] misc: pci_endpoint_test: Add Device ID for RZ/G2M and RZ/G2N PCIe controllers

[Lad Prabhakar]

Add Renesas R8A774A1 and R8A774B1 in pci_device_id table so that
pci-epf-test can be used for testing PCIe EP on RZ/G2M and RZ/G2N.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/misc/pci_endpoint_test.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
index e060796f9caa..ba654f42dc10 100644
--- a/drivers/misc/pci_endpoint_test.c
+++ b/drivers/misc/pci_endpoint_test.c
@@ -74,6 +74,8 @@
 #define is_am654_pci_dev(pdev)		\
 		((pdev)->device == PCI_DEVICE_ID_TI_AM654)
 
+#define PCI_DEVICE_ID_RENESAS_R8A774A1		0x0028
+#define PCI_DEVICE_ID_RENESAS_R8A774B1		0x002b
 #define PCI_DEVICE_ID_RENESAS_R8A774C0		0x002d
 
 static DEFINE_IDA(pci_endpoint_test_ida);
@@ -950,8 +952,9 @@ static const struct pci_device_id pci_endpoint_test_tbl[] = {
 	{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654),
 	  .driver_data = (kernel_ulong_t)&am654_data
 	},
-	{ PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774C0),
-	},
+	{ PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774A1),},
+	{ PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774B1),},
+	{ PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774C0),},
 	{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_J721E),
 	  .driver_data = (kernel_ulong_t)&j721e_data,
 	},
-- 
2.17.1

[PATCH 3/5] arm64: dts: renesas: r8a774a1: Add PCIe EP nodes

[Lad Prabhakar]

Add PCIe EP nodes to R8A774A1 (RZ/G2M) SoC dtsi.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 38 +++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index a603d947970e..50e9ed16a36d 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -2369,6 +2369,44 @@
 			status = "disabled";
 		};
 
+		pciec0_ep: pcie_ep@fe000000 {
+			compatible = "renesas,r8a774a1-pcie-ep",
+				     "renesas,rcar-gen3-pcie-ep";
+			reg = <0x0 0xfe000000 0 0x80000>,
+			      <0x0 0xfe100000 0 0x100000>,
+			      <0x0 0xfe200000 0 0x200000>,
+			      <0x0 0x30000000 0 0x8000000>,
+			      <0x0 0x38000000 0 0x8000000>;
+			reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
+			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 319>;
+			clock-names = "pcie";
+			resets = <&cpg 319>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
+			status = "disabled";
+		};
+
+		pciec1_ep: pcie_ep@ee800000 {
+			compatible = "renesas,r8a774a1-pcie-ep",
+				     "renesas,rcar-gen3-pcie-ep";
+			reg = <0x0 0xee800000 0 0x80000>,
+			      <0x0 0xee900000 0 0x100000>,
+			      <0x0 0xeea00000 0 0x200000>,
+			      <0x0 0xc0000000 0 0x8000000>,
+			      <0x0 0xc8000000 0 0x8000000>;
+			reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
+			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 318>;
+			clock-names = "pcie";
+			resets = <&cpg 318>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
+			status = "disabled";
+		};
+
 		fdp1@fe940000 {
 			compatible = "renesas,fdp1";
 			reg = <0 0xfe940000 0 0x2400>;
-- 
2.17.1

[PATCH 4/5] arm64: dts: renesas: r8a774b1: Add PCIe EP nodes

[Lad Prabhakar]

Add PCIe EP nodes to R8A774B1 (RZ/G2N) SoC dtsi.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 38 +++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
index 1e51855c7cd3..e45ac177eb58 100644
--- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
@@ -2238,6 +2238,44 @@
 			status = "disabled";
 		};
 
+		pciec0_ep: pcie_ep@fe000000 {
+			compatible = "renesas,r8a774b1-pcie-ep",
+				     "renesas,rcar-gen3-pcie-ep";
+			reg = <0x0 0xfe000000 0 0x80000>,
+			      <0x0 0xfe100000 0 0x100000>,
+			      <0x0 0xfe200000 0 0x200000>,
+			      <0x0 0x30000000 0 0x8000000>,
+			      <0x0 0x38000000 0 0x8000000>;
+			reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
+			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 319>;
+			clock-names = "pcie";
+			resets = <&cpg 319>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			status = "disabled";
+		};
+
+		pciec1_ep: pcie_ep@ee800000 {
+			compatible = "renesas,r8a774b1-pcie-ep",
+				     "renesas,rcar-gen3-pcie-ep";
+			reg = <0x0 0xee800000 0 0x80000>,
+			      <0x0 0xee900000 0 0x100000>,
+			      <0x0 0xeea00000 0 0x200000>,
+			      <0x0 0xc0000000 0 0x8000000>,
+			      <0x0 0xc8000000 0 0x8000000>;
+			reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
+			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 318>;
+			clock-names = "pcie";
+			resets = <&cpg 318>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			status = "disabled";
+		};
+
 		fdp1@fe940000 {
 			compatible = "renesas,fdp1";
 			reg = <0 0xfe940000 0 0x2400>;
-- 
2.17.1

[PATCH 5/5] arm64: dts: renesas: r8a774c0: Add PCIe EP node

[Lad Prabhakar]

Add PCIe EP node to R8A774C0 (RZ/G2E) SoC dtsi.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index 5c72a7efbb03..81f218539688 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -1698,6 +1698,25 @@
 			status = "disabled";
 		};
 
+		pciec0_ep: pcie_ep@fe000000 {
+			compatible = "renesas,r8a774c0-pcie-ep",
+				     "renesas,rcar-gen3-pcie-ep";
+			reg = <0x0 0xfe000000 0 0x80000>,
+			      <0x0 0xfe100000 0 0x100000>,
+			      <0x0 0xfe200000 0 0x200000>,
+			      <0x0 0x30000000 0 0x8000000>,
+			      <0x0 0x38000000 0 0x8000000>;
+			reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
+			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 319>;
+			clock-names = "pcie";
+			resets = <&cpg 319>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			status = "disabled";
+		};
+
 		vspb0: vsp@fe960000 {
 			compatible = "renesas,vsp2";
 			reg = <0 0xfe960000 0 0x8000>;
-- 
2.17.1

Re: [PATCH 3/5] arm64: dts: renesas: r8a774a1: Add PCIe EP nodes

[Sergei Shtylyov]

Hello!

On 14.08.2020 20:30, Lad Prabhakar wrote:

> Add PCIe EP nodes to R8A774A1 (RZ/G2M) SoC dtsi.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
>   arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 38 +++++++++++++++++++++++
>   1 file changed, 38 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
> index a603d947970e..50e9ed16a36d 100644
> --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
> @@ -2369,6 +2369,44 @@
>   			status = "disabled";
>   		};
>   
> +		pciec0_ep: pcie_ep@fe000000 {

    Hyphens are preferred over underscores in the node/prop names.

[...]> +		pciec1_ep: pcie_ep@ee800000 {

    Ditto, should be "pci-ep@ee800000".

[...]

MBR, Sergei

Re: [PATCH 3/5] arm64: dts: renesas: r8a774a1: Add PCIe EP nodes

[Lad, Prabhakar]

Hi Sergei,

Thank you for the review.

On Sat, Aug 15, 2020 at 9:45 AM Sergei Shtylyov
<sergei.shtylyov@gmail.com> wrote:
>
> Hello!
>
> On 14.08.2020 20:30, Lad Prabhakar wrote:
>
> > Add PCIe EP nodes to R8A774A1 (RZ/G2M) SoC dtsi.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> >   arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 38 +++++++++++++++++++++++
> >   1 file changed, 38 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
> > index a603d947970e..50e9ed16a36d 100644
> > --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
> > @@ -2369,6 +2369,44 @@
> >                       status = "disabled";
> >               };
> >
> > +             pciec0_ep: pcie_ep@fe000000 {
>
>     Hyphens are preferred over underscores in the node/prop names.
>
> [...]> +                pciec1_ep: pcie_ep@ee800000 {
>
>     Ditto, should be "pci-ep@ee800000".
>
My bad will fix that in v2.

Cheers,
Prabhakar

> [...]
>
> MBR, Sergei

Re: [PATCH 3/5] arm64: dts: renesas: r8a774a1: Add PCIe EP nodes

[Sergei Shtylyov]

On 18.08.2020 10:23, Lad, Prabhakar wrote:

[...]
>>> Add PCIe EP nodes to R8A774A1 (RZ/G2M) SoC dtsi.
>>>
>>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>>> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
>>> ---
>>>    arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 38 +++++++++++++++++++++++
>>>    1 file changed, 38 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
>>> index a603d947970e..50e9ed16a36d 100644
>>> --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
>>> +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
>>> @@ -2369,6 +2369,44 @@
>>>                        status = "disabled";
>>>                };
>>>
>>> +             pciec0_ep: pcie_ep@fe000000 {
>>
>>      Hyphens are preferred over underscores in the node/prop names.
>>
>> [...]
>> +                pciec1_ep: pcie_ep@ee800000 {
>>
>>      Ditto, should be "pci-ep@ee800000".
>>
> My bad will fix that in v2.

    Sorry, I meant to type "pcie-ep@ee800000".

> Cheers,
> Prabhakar

MBR, Sergei

Re: [PATCH 1/5] dt-bindings: pci: rcar-pci-ep: Document r8a774a1 and r8a774b1

[Geert Uytterhoeven]

On Fri, Aug 14, 2020 at 7:32 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> Document the support for R-Car PCIe EP on R8A774A1 and R8A774B1 SoC
> devices.
>
> Also constify "renesas,rcar-gen3-pcie-ep" so that it can be used as
> fallback compatible string for R-Car Gen3 and RZ/G2 devices as the
> PCIe module is identical.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 2/5] misc: pci_endpoint_test: Add Device ID for RZ/G2M and RZ/G2N PCIe controllers

[Geert Uytterhoeven]

On Fri, Aug 14, 2020 at 7:33 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> Add Renesas R8A774A1 and R8A774B1 in pci_device_id table so that
> pci-epf-test can be used for testing PCIe EP on RZ/G2M and RZ/G2N.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 3/5] arm64: dts: renesas: r8a774a1: Add PCIe EP nodes

[Geert Uytterhoeven]

On Fri, Aug 14, 2020 at 7:33 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> Add PCIe EP nodes to R8A774A1 (RZ/G2M) SoC dtsi.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.10, with s/pcie_ep@/pcie-ep@/.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 4/5] arm64: dts: renesas: r8a774b1: Add PCIe EP nodes

[Geert Uytterhoeven]

On Fri, Aug 14, 2020 at 7:33 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> Add PCIe EP nodes to R8A774B1 (RZ/G2N) SoC dtsi.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.10, with s/pcie_ep@/pcie-ep@/.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 5/5] arm64: dts: renesas: r8a774c0: Add PCIe EP node

[Geert Uytterhoeven]

On Fri, Aug 14, 2020 at 7:34 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> Add PCIe EP node to R8A774C0 (RZ/G2E) SoC dtsi.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.10, with s/pcie_ep@/pcie-ep@/.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH 1/5] dt-bindings: pci: rcar-pci-ep: Document r8a774a1 and r8a774b1

[Yoshihiro Shimoda]

Hi Lad-san,

> From: Lad Prabhakar, Sent: Saturday, August 15, 2020 2:31 AM
> 
> Document the support for R-Car PCIe EP on R8A774A1 and R8A774B1 SoC
> devices.
> 
> Also constify "renesas,rcar-gen3-pcie-ep" so that it can be used as
> fallback compatible string for R-Car Gen3 and RZ/G2 devices as the
> PCIe module is identical.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>

Thank you for the patch!

Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Best regards,
Yoshihiro Shimoda

Re: [PATCH 1/5] dt-bindings: pci: rcar-pci-ep: Document r8a774a1 and r8a774b1

[Rob Herring]

On Fri, 14 Aug 2020 18:30:33 +0100, Lad Prabhakar wrote:
> Document the support for R-Car PCIe EP on R8A774A1 and R8A774B1 SoC
> devices.
> 
> Also constify "renesas,rcar-gen3-pcie-ep" so that it can be used as
> fallback compatible string for R-Car Gen3 and RZ/G2 devices as the
> PCIe module is identical.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
>  Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

Re: [PATCH 0/5] Add PCIe EP nodes on RZ/G2[EMN]

[Lorenzo Pieralisi]

On Fri, Aug 14, 2020 at 06:30:32PM +0100, Lad Prabhakar wrote:
> Hi All,
> 
> This patch series adds support for PCIe EP nodes to Renesas r8a774a1,
> r8a774b1 and r8a774c0 SoC's.
> 
> Patches are based on top of [1].
> 
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/
>     pci.git/log/?h=next
> 
> Cheers,
> Prabhakar
> 
> Lad Prabhakar (5):
>   dt-bindings: pci: rcar-pci-ep: Document r8a774a1 and r8a774b1
>   misc: pci_endpoint_test: Add Device ID for RZ/G2M and RZ/G2N PCIe
>     controllers
>   arm64: dts: renesas: r8a774a1: Add PCIe EP nodes
>   arm64: dts: renesas: r8a774b1: Add PCIe EP nodes
>   arm64: dts: renesas: r8a774c0: Add PCIe EP node
> 
>  .../devicetree/bindings/pci/rcar-pci-ep.yaml  |  7 +++-
>  arch/arm64/boot/dts/renesas/r8a774a1.dtsi     | 38 +++++++++++++++++++
>  arch/arm64/boot/dts/renesas/r8a774b1.dtsi     | 38 +++++++++++++++++++
>  arch/arm64/boot/dts/renesas/r8a774c0.dtsi     | 19 ++++++++++
>  drivers/misc/pci_endpoint_test.c              |  7 +++-
>  5 files changed, 105 insertions(+), 4 deletions(-)

I can take the first two patches but the dts changes should be routed
and posted to arm-soc.

Lorenzo

Re: [PATCH 0/5] Add PCIe EP nodes on RZ/G2[EMN]

[Lad, Prabhakar]

Hi Lorenzo,

On Mon, Sep 7, 2020 at 11:09 AM Lorenzo Pieralisi
<lorenzo.pieralisi@arm.com> wrote:
>
> On Fri, Aug 14, 2020 at 06:30:32PM +0100, Lad Prabhakar wrote:
> > Hi All,
> >
> > This patch series adds support for PCIe EP nodes to Renesas r8a774a1,
> > r8a774b1 and r8a774c0 SoC's.
> >
> > Patches are based on top of [1].
> >
> > [1] https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/
> >     pci.git/log/?h=next
> >
> > Cheers,
> > Prabhakar
> >
> > Lad Prabhakar (5):
> >   dt-bindings: pci: rcar-pci-ep: Document r8a774a1 and r8a774b1
> >   misc: pci_endpoint_test: Add Device ID for RZ/G2M and RZ/G2N PCIe
> >     controllers
> >   arm64: dts: renesas: r8a774a1: Add PCIe EP nodes
> >   arm64: dts: renesas: r8a774b1: Add PCIe EP nodes
> >   arm64: dts: renesas: r8a774c0: Add PCIe EP node
> >
> >  .../devicetree/bindings/pci/rcar-pci-ep.yaml  |  7 +++-
> >  arch/arm64/boot/dts/renesas/r8a774a1.dtsi     | 38 +++++++++++++++++++
> >  arch/arm64/boot/dts/renesas/r8a774b1.dtsi     | 38 +++++++++++++++++++
> >  arch/arm64/boot/dts/renesas/r8a774c0.dtsi     | 19 ++++++++++
> >  drivers/misc/pci_endpoint_test.c              |  7 +++-
> >  5 files changed, 105 insertions(+), 4 deletions(-)
>
> I can take the first two patches but the dts changes should be routed
> and posted to arm-soc.
>
Thanks, the DTS changes have been picked up by Geert.

Cheers,
Prabhakar

Re: [PATCH 0/5] Add PCIe EP nodes on RZ/G2[EMN]

[Lorenzo Pieralisi]

On Fri, Aug 14, 2020 at 06:30:32PM +0100, Lad Prabhakar wrote:
> Hi All,
> 
> This patch series adds support for PCIe EP nodes to Renesas r8a774a1,
> r8a774b1 and r8a774c0 SoC's.
> 
> Patches are based on top of [1].
> 
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/
>     pci.git/log/?h=next
> 
> Cheers,
> Prabhakar
> 
> Lad Prabhakar (5):
>   dt-bindings: pci: rcar-pci-ep: Document r8a774a1 and r8a774b1
>   misc: pci_endpoint_test: Add Device ID for RZ/G2M and RZ/G2N PCIe
>     controllers
>   arm64: dts: renesas: r8a774a1: Add PCIe EP nodes
>   arm64: dts: renesas: r8a774b1: Add PCIe EP nodes
>   arm64: dts: renesas: r8a774c0: Add PCIe EP node
> 
>  .../devicetree/bindings/pci/rcar-pci-ep.yaml  |  7 +++-
>  arch/arm64/boot/dts/renesas/r8a774a1.dtsi     | 38 +++++++++++++++++++
>  arch/arm64/boot/dts/renesas/r8a774b1.dtsi     | 38 +++++++++++++++++++
>  arch/arm64/boot/dts/renesas/r8a774c0.dtsi     | 19 ++++++++++
>  drivers/misc/pci_endpoint_test.c              |  7 +++-
>  5 files changed, 105 insertions(+), 4 deletions(-)

I took the first two patches in pci/rcar, thanks.

Lorenzo