* [PATCH 1/5] drm/amd/pm: disable/enable gfx ulv on UMD pstate enter/exit
@ 2020-08-17 7:49 Evan Quan
2020-08-17 7:49 ` [PATCH 2/5] drm/amd/pm: add Navi1x gfx ulv control interface Evan Quan
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: Evan Quan @ 2020-08-17 7:49 UTC (permalink / raw)
To: amd-gfx; +Cc: alexander.deucher, Evan Quan
Add gfx ulv disablement/enablement on UMD pstate entering/exiting.
Change-Id: Ieb38fdb5975b563f24c0b172fedd01acf99afb10
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 1 +
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 ++
drivers/gpu/drm/amd/pm/swsmu/smu_internal.h | 1 +
3 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index bbe4a343e9f1..7cc707ec21c3 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -596,6 +596,7 @@ struct pptable_funcs {
int (*set_pp_feature_mask)(struct smu_context *smu, uint64_t new_mask);
ssize_t (*get_gpu_metrics)(struct smu_context *smu, void **table);
int (*enable_mgpu_fan_boost)(struct smu_context *smu);
+ int (*gfx_ulv_control)(struct smu_context *smu, bool enablement);
};
typedef enum {
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 7d17c4f1b489..221b5c923ce1 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1440,6 +1440,7 @@ static int smu_enable_umd_pstate(void *handle,
amdgpu_device_ip_set_clockgating_state(smu->adev,
AMD_IP_BLOCK_TYPE_GFX,
AMD_CG_STATE_UNGATE);
+ smu_gfx_ulv_control(smu, false);
}
} else {
/* exit umd pstate, restore level, enable gfx cg*/
@@ -1447,6 +1448,7 @@ static int smu_enable_umd_pstate(void *handle,
if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
*level = smu_dpm_ctx->saved_dpm_level;
smu_dpm_ctx->enable_umd_pstate = false;
+ smu_gfx_ulv_control(smu, true);
amdgpu_device_ip_set_clockgating_state(smu->adev,
AMD_IP_BLOCK_TYPE_GFX,
AMD_CG_STATE_GATE);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h b/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h
index 264073d4e263..2fe29c6a00ce 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h
@@ -92,6 +92,7 @@
#define smu_get_asic_power_limits(smu) smu_ppt_funcs(get_power_limit, 0, smu)
#define smu_get_pp_feature_mask(smu, buf) smu_ppt_funcs(get_pp_feature_mask, 0, smu, buf)
#define smu_set_pp_feature_mask(smu, new_mask) smu_ppt_funcs(set_pp_feature_mask, 0, smu, new_mask)
+#define smu_gfx_ulv_control(smu, enablement) smu_ppt_funcs(gfx_ulv_control, 0, smu, enablement)
#endif
#endif
--
2.28.0
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^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/5] drm/amd/pm: add Navi1x gfx ulv control interface
2020-08-17 7:49 [PATCH 1/5] drm/amd/pm: disable/enable gfx ulv on UMD pstate enter/exit Evan Quan
@ 2020-08-17 7:49 ` Evan Quan
2020-08-17 7:49 ` [PATCH 3/5] drm/amd/pm: add Arcturus " Evan Quan
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Evan Quan @ 2020-08-17 7:49 UTC (permalink / raw)
To: amd-gfx; +Cc: alexander.deucher, Evan Quan
This is needed for UMD pstate switch.
Change-Id: Id14399d3a5e4b24bb8a72a298ec4e96717444741
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index 4b4d461899df..c10119f29904 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -2578,6 +2578,17 @@ static int navi10_enable_mgpu_fan_boost(struct smu_context *smu)
NULL);
}
+static int navi10_gfx_ulv_control(struct smu_context *smu,
+ bool enablement)
+{
+ int ret = 0;
+
+ if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
+ ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
+
+ return ret;
+}
+
static const struct pptable_funcs navi10_ppt_funcs = {
.get_allowed_feature_mask = navi10_get_allowed_feature_mask,
.set_default_dpm_table = navi10_set_default_dpm_table,
@@ -2660,6 +2671,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
.set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
.get_gpu_metrics = navi10_get_gpu_metrics,
.enable_mgpu_fan_boost = navi10_enable_mgpu_fan_boost,
+ .gfx_ulv_control = navi10_gfx_ulv_control,
};
void navi10_set_ppt_funcs(struct smu_context *smu)
--
2.28.0
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 3/5] drm/amd/pm: add Arcturus gfx ulv control interface
2020-08-17 7:49 [PATCH 1/5] drm/amd/pm: disable/enable gfx ulv on UMD pstate enter/exit Evan Quan
2020-08-17 7:49 ` [PATCH 2/5] drm/amd/pm: add Navi1x gfx ulv control interface Evan Quan
@ 2020-08-17 7:49 ` Evan Quan
2020-08-17 7:49 ` [PATCH 4/5] drm/amd/pm: add Sienna Cichlid " Evan Quan
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Evan Quan @ 2020-08-17 7:49 UTC (permalink / raw)
To: amd-gfx; +Cc: alexander.deucher, Evan Quan
This is needed for UMD pstate switch.
Change-Id: I40e235add95d6abbf99186112673a411edf2bb39
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
index 81f43fea4d52..c82ef2872a50 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
@@ -2313,6 +2313,17 @@ static ssize_t arcturus_get_gpu_metrics(struct smu_context *smu,
return sizeof(struct gpu_metrics_v1_0);
}
+static int arcturus_gfx_ulv_control(struct smu_context *smu,
+ bool enablement)
+{
+ int ret = 0;
+
+ if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
+ ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
+
+ return ret;
+}
+
static const struct pptable_funcs arcturus_ppt_funcs = {
/* init dpm */
.get_allowed_feature_mask = arcturus_get_allowed_feature_mask,
@@ -2391,6 +2402,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
.set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
.get_gpu_metrics = arcturus_get_gpu_metrics,
+ .gfx_ulv_control = arcturus_gfx_ulv_control,
};
void arcturus_set_ppt_funcs(struct smu_context *smu)
--
2.28.0
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 4/5] drm/amd/pm: add Sienna Cichlid gfx ulv control interface
2020-08-17 7:49 [PATCH 1/5] drm/amd/pm: disable/enable gfx ulv on UMD pstate enter/exit Evan Quan
2020-08-17 7:49 ` [PATCH 2/5] drm/amd/pm: add Navi1x gfx ulv control interface Evan Quan
2020-08-17 7:49 ` [PATCH 3/5] drm/amd/pm: add Arcturus " Evan Quan
@ 2020-08-17 7:49 ` Evan Quan
2020-08-17 7:49 ` [PATCH 5/5] drm/amd/pm: widely share the logic for gfx ulv control Evan Quan
2020-08-17 14:18 ` [PATCH 1/5] drm/amd/pm: disable/enable gfx ulv on UMD pstate enter/exit Deucher, Alexander
4 siblings, 0 replies; 6+ messages in thread
From: Evan Quan @ 2020-08-17 7:49 UTC (permalink / raw)
To: amd-gfx; +Cc: alexander.deucher, Evan Quan
This is needed for UMD pstate switch.
Change-Id: I23d68bc291960118c799366cbb3fc89ccb42f98c
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
.../gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 407a11c2826b..3559b33da0c4 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -2718,6 +2718,17 @@ static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
NULL);
}
+static int sienna_cichlid_gfx_ulv_control(struct smu_context *smu,
+ bool enablement)
+{
+ int ret = 0;
+
+ if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
+ ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
+
+ return ret;
+}
+
static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
.get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
.set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
@@ -2796,6 +2807,7 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
.set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
.get_gpu_metrics = sienna_cichlid_get_gpu_metrics,
.enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost,
+ .gfx_ulv_control = sienna_cichlid_gfx_ulv_control,
};
void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
--
2.28.0
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 5/5] drm/amd/pm: widely share the logic for gfx ulv control
2020-08-17 7:49 [PATCH 1/5] drm/amd/pm: disable/enable gfx ulv on UMD pstate enter/exit Evan Quan
` (2 preceding siblings ...)
2020-08-17 7:49 ` [PATCH 4/5] drm/amd/pm: add Sienna Cichlid " Evan Quan
@ 2020-08-17 7:49 ` Evan Quan
2020-08-17 14:18 ` [PATCH 1/5] drm/amd/pm: disable/enable gfx ulv on UMD pstate enter/exit Deucher, Alexander
4 siblings, 0 replies; 6+ messages in thread
From: Evan Quan @ 2020-08-17 7:49 UTC (permalink / raw)
To: amd-gfx; +Cc: alexander.deucher, Evan Quan
Considering the same logic can be applied to Arcturus, Navi1X
and Sienna Cichlid.
Change-Id: I16958d114afbb2433789ca350019fea9b50e1218
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/pm/inc/smu_v11_0.h | 3 +++
drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 13 +------------
drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 13 +------------
.../gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 13 +------------
drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 11 +++++++++++
5 files changed, 17 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
index 65363d56e3cc..89d70165ac44 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
@@ -274,5 +274,8 @@ int smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu);
void smu_v11_0_init_gpu_metrics_v1_0(struct gpu_metrics_v1_0 *gpu_metrics);
+int smu_v11_0_gfx_ulv_control(struct smu_context *smu,
+ bool enablement);
+
#endif
#endif
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
index c82ef2872a50..aab83b957246 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
@@ -2313,17 +2313,6 @@ static ssize_t arcturus_get_gpu_metrics(struct smu_context *smu,
return sizeof(struct gpu_metrics_v1_0);
}
-static int arcturus_gfx_ulv_control(struct smu_context *smu,
- bool enablement)
-{
- int ret = 0;
-
- if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
- ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
-
- return ret;
-}
-
static const struct pptable_funcs arcturus_ppt_funcs = {
/* init dpm */
.get_allowed_feature_mask = arcturus_get_allowed_feature_mask,
@@ -2402,7 +2391,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
.set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
.get_gpu_metrics = arcturus_get_gpu_metrics,
- .gfx_ulv_control = arcturus_gfx_ulv_control,
+ .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
};
void arcturus_set_ppt_funcs(struct smu_context *smu)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index c10119f29904..c968f05533d9 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -2578,17 +2578,6 @@ static int navi10_enable_mgpu_fan_boost(struct smu_context *smu)
NULL);
}
-static int navi10_gfx_ulv_control(struct smu_context *smu,
- bool enablement)
-{
- int ret = 0;
-
- if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
- ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
-
- return ret;
-}
-
static const struct pptable_funcs navi10_ppt_funcs = {
.get_allowed_feature_mask = navi10_get_allowed_feature_mask,
.set_default_dpm_table = navi10_set_default_dpm_table,
@@ -2671,7 +2660,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
.set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
.get_gpu_metrics = navi10_get_gpu_metrics,
.enable_mgpu_fan_boost = navi10_enable_mgpu_fan_boost,
- .gfx_ulv_control = navi10_gfx_ulv_control,
+ .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
};
void navi10_set_ppt_funcs(struct smu_context *smu)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 3559b33da0c4..45b9defebd07 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -2718,17 +2718,6 @@ static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
NULL);
}
-static int sienna_cichlid_gfx_ulv_control(struct smu_context *smu,
- bool enablement)
-{
- int ret = 0;
-
- if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
- ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
-
- return ret;
-}
-
static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
.get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
.set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
@@ -2807,7 +2796,7 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
.set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
.get_gpu_metrics = sienna_cichlid_get_gpu_metrics,
.enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost,
- .gfx_ulv_control = sienna_cichlid_gfx_ulv_control,
+ .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
};
void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index 580889a02a94..f1130a288f1d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -1985,3 +1985,14 @@ void smu_v11_0_init_gpu_metrics_v1_0(struct gpu_metrics_v1_0 *gpu_metrics)
gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
}
+
+int smu_v11_0_gfx_ulv_control(struct smu_context *smu,
+ bool enablement)
+{
+ int ret = 0;
+
+ if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
+ ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
+
+ return ret;
+}
--
2.28.0
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^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 1/5] drm/amd/pm: disable/enable gfx ulv on UMD pstate enter/exit
2020-08-17 7:49 [PATCH 1/5] drm/amd/pm: disable/enable gfx ulv on UMD pstate enter/exit Evan Quan
` (3 preceding siblings ...)
2020-08-17 7:49 ` [PATCH 5/5] drm/amd/pm: widely share the logic for gfx ulv control Evan Quan
@ 2020-08-17 14:18 ` Deucher, Alexander
4 siblings, 0 replies; 6+ messages in thread
From: Deucher, Alexander @ 2020-08-17 14:18 UTC (permalink / raw)
To: Quan, Evan, amd-gfx
[-- Attachment #1.1: Type: text/plain, Size: 3610 bytes --]
[AMD Official Use Only - Internal Distribution Only]
You can probably just squash patches 2-5 into one patch. Either way, series is:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
________________________________
From: Quan, Evan <Evan.Quan@amd.com>
Sent: Monday, August 17, 2020 3:49 AM
To: amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Quan, Evan <Evan.Quan@amd.com>
Subject: [PATCH 1/5] drm/amd/pm: disable/enable gfx ulv on UMD pstate enter/exit
Add gfx ulv disablement/enablement on UMD pstate entering/exiting.
Change-Id: Ieb38fdb5975b563f24c0b172fedd01acf99afb10
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 1 +
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 ++
drivers/gpu/drm/amd/pm/swsmu/smu_internal.h | 1 +
3 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index bbe4a343e9f1..7cc707ec21c3 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -596,6 +596,7 @@ struct pptable_funcs {
int (*set_pp_feature_mask)(struct smu_context *smu, uint64_t new_mask);
ssize_t (*get_gpu_metrics)(struct smu_context *smu, void **table);
int (*enable_mgpu_fan_boost)(struct smu_context *smu);
+ int (*gfx_ulv_control)(struct smu_context *smu, bool enablement);
};
typedef enum {
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 7d17c4f1b489..221b5c923ce1 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1440,6 +1440,7 @@ static int smu_enable_umd_pstate(void *handle,
amdgpu_device_ip_set_clockgating_state(smu->adev,
AMD_IP_BLOCK_TYPE_GFX,
AMD_CG_STATE_UNGATE);
+ smu_gfx_ulv_control(smu, false);
}
} else {
/* exit umd pstate, restore level, enable gfx cg*/
@@ -1447,6 +1448,7 @@ static int smu_enable_umd_pstate(void *handle,
if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
*level = smu_dpm_ctx->saved_dpm_level;
smu_dpm_ctx->enable_umd_pstate = false;
+ smu_gfx_ulv_control(smu, true);
amdgpu_device_ip_set_clockgating_state(smu->adev,
AMD_IP_BLOCK_TYPE_GFX,
AMD_CG_STATE_GATE);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h b/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h
index 264073d4e263..2fe29c6a00ce 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h
@@ -92,6 +92,7 @@
#define smu_get_asic_power_limits(smu) smu_ppt_funcs(get_power_limit, 0, smu)
#define smu_get_pp_feature_mask(smu, buf) smu_ppt_funcs(get_pp_feature_mask, 0, smu, buf)
#define smu_set_pp_feature_mask(smu, new_mask) smu_ppt_funcs(set_pp_feature_mask, 0, smu, new_mask)
+#define smu_gfx_ulv_control(smu, enablement) smu_ppt_funcs(gfx_ulv_control, 0, smu, enablement)
#endif
#endif
--
2.28.0
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^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-08-17 14:18 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-08-17 7:49 [PATCH 1/5] drm/amd/pm: disable/enable gfx ulv on UMD pstate enter/exit Evan Quan
2020-08-17 7:49 ` [PATCH 2/5] drm/amd/pm: add Navi1x gfx ulv control interface Evan Quan
2020-08-17 7:49 ` [PATCH 3/5] drm/amd/pm: add Arcturus " Evan Quan
2020-08-17 7:49 ` [PATCH 4/5] drm/amd/pm: add Sienna Cichlid " Evan Quan
2020-08-17 7:49 ` [PATCH 5/5] drm/amd/pm: widely share the logic for gfx ulv control Evan Quan
2020-08-17 14:18 ` [PATCH 1/5] drm/amd/pm: disable/enable gfx ulv on UMD pstate enter/exit Deucher, Alexander
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