From: frank.chang@sifive.com
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Frank Chang <frank.chang@sifive.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Subject: [RFC v4 62/70] target/riscv: introduce floating-point rounding mode enum
Date: Mon, 17 Aug 2020 16:49:47 +0800 [thread overview]
Message-ID: <20200817084955.28793-63-frank.chang@sifive.com> (raw)
In-Reply-To: <20200817084955.28793-1-frank.chang@sifive.com>
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/fpu_helper.c | 12 ++++++------
target/riscv/insn_trans/trans_rvv.inc.c | 18 +++++++++---------
target/riscv/internals.h | 9 +++++++++
3 files changed, 24 insertions(+), 15 deletions(-)
diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
index bb346a82499..92e076c6ed8 100644
--- a/target/riscv/fpu_helper.c
+++ b/target/riscv/fpu_helper.c
@@ -55,23 +55,23 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm)
{
int softrm;
- if (rm == 7) {
+ if (rm == FRM_DYN) {
rm = env->frm;
}
switch (rm) {
- case 0:
+ case FRM_RNE:
softrm = float_round_nearest_even;
break;
- case 1:
+ case FRM_RTZ:
softrm = float_round_to_zero;
break;
- case 2:
+ case FRM_RDN:
softrm = float_round_down;
break;
- case 3:
+ case FRM_RUP:
softrm = float_round_up;
break;
- case 4:
+ case FRM_RMM:
softrm = float_round_ties_away;
break;
default:
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 4f33c42990e..c148ed40c9f 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2430,7 +2430,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_helper_##NAME##_d, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, FRM_DYN); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -2510,7 +2510,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_helper_##NAME##_w, \
gen_helper_##NAME##_d, \
}; \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, FRM_DYN); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
@@ -2542,7 +2542,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, FRM_DYN); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -2578,7 +2578,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
static gen_helper_opfvf *const fns[2] = { \
gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
}; \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, FRM_DYN); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
@@ -2608,7 +2608,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, FRM_DYN); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -2644,7 +2644,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
static gen_helper_opfvf *const fns[2] = { \
gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
}; \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, FRM_DYN); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
@@ -2721,7 +2721,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
gen_helper_##NAME##_d, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, FRM_DYN); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -2862,7 +2862,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
gen_helper_##NAME##_w, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, FRM_DYN); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -2908,7 +2908,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
gen_helper_##NAME##_w, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, FRM_DYN); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index bca48297dab..d9ea6a32188 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -37,6 +37,15 @@ target_ulong fclass_d(uint64_t frs1);
#define SEW32 2
#define SEW64 3
+enum {
+ FRM_RNE = 0, /* Round to Nearest, ties to Even */
+ FRM_RTZ = 1, /* Round towards Zero */
+ FRM_RDN = 2, /* Round Down */
+ FRM_RUP = 3, /* Round Up */
+ FRM_RMM = 4, /* Round to Nearest, ties to Max Magnitude */
+ FRM_DYN = 7, /* Dynamic rounding mode */
+};
+
static inline uint64_t nanbox_s(float32 f)
{
return f | MAKE_64BIT_MASK(32, 32);
--
2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: frank.chang@sifive.com
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Frank Chang <frank.chang@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Subject: [RFC v4 62/70] target/riscv: introduce floating-point rounding mode enum
Date: Mon, 17 Aug 2020 16:49:47 +0800 [thread overview]
Message-ID: <20200817084955.28793-63-frank.chang@sifive.com> (raw)
In-Reply-To: <20200817084955.28793-1-frank.chang@sifive.com>
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/fpu_helper.c | 12 ++++++------
target/riscv/insn_trans/trans_rvv.inc.c | 18 +++++++++---------
target/riscv/internals.h | 9 +++++++++
3 files changed, 24 insertions(+), 15 deletions(-)
diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
index bb346a82499..92e076c6ed8 100644
--- a/target/riscv/fpu_helper.c
+++ b/target/riscv/fpu_helper.c
@@ -55,23 +55,23 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm)
{
int softrm;
- if (rm == 7) {
+ if (rm == FRM_DYN) {
rm = env->frm;
}
switch (rm) {
- case 0:
+ case FRM_RNE:
softrm = float_round_nearest_even;
break;
- case 1:
+ case FRM_RTZ:
softrm = float_round_to_zero;
break;
- case 2:
+ case FRM_RDN:
softrm = float_round_down;
break;
- case 3:
+ case FRM_RUP:
softrm = float_round_up;
break;
- case 4:
+ case FRM_RMM:
softrm = float_round_ties_away;
break;
default:
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 4f33c42990e..c148ed40c9f 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2430,7 +2430,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_helper_##NAME##_d, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, FRM_DYN); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -2510,7 +2510,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_helper_##NAME##_w, \
gen_helper_##NAME##_d, \
}; \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, FRM_DYN); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
@@ -2542,7 +2542,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, FRM_DYN); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -2578,7 +2578,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
static gen_helper_opfvf *const fns[2] = { \
gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
}; \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, FRM_DYN); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
@@ -2608,7 +2608,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, FRM_DYN); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -2644,7 +2644,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
static gen_helper_opfvf *const fns[2] = { \
gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
}; \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, FRM_DYN); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
@@ -2721,7 +2721,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
gen_helper_##NAME##_d, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, FRM_DYN); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -2862,7 +2862,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
gen_helper_##NAME##_w, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, FRM_DYN); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -2908,7 +2908,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
gen_helper_##NAME##_w, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, FRM_DYN); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index bca48297dab..d9ea6a32188 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -37,6 +37,15 @@ target_ulong fclass_d(uint64_t frs1);
#define SEW32 2
#define SEW64 3
+enum {
+ FRM_RNE = 0, /* Round to Nearest, ties to Even */
+ FRM_RTZ = 1, /* Round towards Zero */
+ FRM_RDN = 2, /* Round Down */
+ FRM_RUP = 3, /* Round Up */
+ FRM_RMM = 4, /* Round to Nearest, ties to Max Magnitude */
+ FRM_DYN = 7, /* Dynamic rounding mode */
+};
+
static inline uint64_t nanbox_s(float32 f)
{
return f | MAKE_64BIT_MASK(32, 32);
--
2.17.1
next prev parent reply other threads:[~2020-08-17 9:18 UTC|newest]
Thread overview: 249+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-17 8:48 [RFC v4 00/70] support vector extension v1.0 frank.chang
2020-08-17 8:48 ` [RFC v4 01/70] target/riscv: drop vector 0.7.1 and add 1.0 support frank.chang
2020-08-17 8:48 ` frank.chang
2020-08-17 8:48 ` [RFC v4 02/70] target/riscv: Use FIELD_EX32() to extract wd field frank.chang
2020-08-17 8:48 ` frank.chang
2020-08-17 8:48 ` [RFC v4 03/70] target/riscv: rvv-1.0: add mstatus VS field frank.chang
2020-08-17 8:48 ` frank.chang
2020-08-17 8:48 ` [RFC v4 04/70] target/riscv: rvv-1.0: add sstatus " frank.chang
2020-08-17 8:48 ` frank.chang
2020-08-17 8:48 ` [RFC v4 05/70] target/riscv: rvv-1.0: introduce writable misa.v field frank.chang
2020-08-17 8:48 ` frank.chang
2020-08-17 8:48 ` [RFC v4 06/70] target/riscv: rvv-1.0: add translation-time vector context status frank.chang
2020-08-17 8:48 ` frank.chang
2020-08-17 8:48 ` [RFC v4 07/70] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers frank.chang
2020-08-17 8:48 ` frank.chang
2020-08-29 15:49 ` Richard Henderson
2020-08-29 15:49 ` Richard Henderson
2020-08-17 8:48 ` [RFC v4 08/70] target/riscv: rvv-1.0: add vcsr register frank.chang
2020-08-17 8:48 ` frank.chang
2020-08-17 8:48 ` [RFC v4 09/70] target/riscv: rvv-1.0: add vlenb register frank.chang
2020-08-17 8:48 ` frank.chang
2020-08-17 8:48 ` [RFC v4 10/70] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers frank.chang
2020-08-17 8:48 ` frank.chang
2020-08-17 8:48 ` [RFC v4 11/70] target/riscv: rvv-1.0: remove MLEN calculations frank.chang
2020-08-17 8:48 ` frank.chang
2020-08-17 8:48 ` [RFC v4 12/70] target/riscv: rvv-1.0: add fractional LMUL frank.chang
2020-08-17 8:48 ` frank.chang
2020-08-29 15:51 ` Richard Henderson
2020-08-29 15:51 ` Richard Henderson
2020-08-17 8:48 ` [RFC v4 13/70] target/riscv: rvv-1.0: add VMA and VTA frank.chang
2020-08-17 8:48 ` frank.chang
2020-08-17 8:48 ` [RFC v4 14/70] target/riscv: rvv-1.0: update check functions frank.chang
2020-08-17 8:48 ` frank.chang
2020-08-29 17:50 ` Richard Henderson
2020-08-29 17:50 ` Richard Henderson
2020-08-17 8:49 ` [RFC v4 15/70] target/riscv: introduce more imm value modes in translator functions frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-29 17:51 ` Richard Henderson
2020-08-29 17:51 ` Richard Henderson
2020-08-17 8:49 ` [RFC v4 16/70] target/riscv: rvv:1.0: add translation-time nan-box helper function frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-29 17:53 ` Richard Henderson
2020-08-29 17:53 ` Richard Henderson
2020-08-17 8:49 ` [RFC v4 17/70] target/riscv: rvv-1.0: configure instructions frank.chang
2020-08-17 8:49 ` frank.chang
2020-09-25 8:51 ` Frank Chang
2020-09-25 8:51 ` Frank Chang
2020-09-25 18:28 ` Richard Henderson
2020-09-25 18:28 ` Richard Henderson
2020-09-26 5:05 ` Frank Chang
2020-09-26 5:05 ` Frank Chang
2020-08-17 8:49 ` [RFC v4 18/70] target/riscv: rvv-1.0: stride load and store instructions frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-29 18:10 ` Richard Henderson
2020-08-29 18:10 ` Richard Henderson
2020-08-17 8:49 ` [RFC v4 19/70] target/riscv: rvv-1.0: index " frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-29 18:33 ` Richard Henderson
2020-08-29 18:33 ` Richard Henderson
2020-08-17 8:49 ` [RFC v4 20/70] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-29 18:34 ` Richard Henderson
2020-08-29 18:34 ` Richard Henderson
2020-08-17 8:49 ` [RFC v4 21/70] target/riscv: rvv-1.0: fault-only-first unit stride load frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-29 18:36 ` Richard Henderson
2020-08-29 18:36 ` Richard Henderson
2020-08-17 8:49 ` [RFC v4 22/70] target/riscv: rvv-1.0: amo operations frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-29 18:50 ` Richard Henderson
2020-08-29 18:50 ` Richard Henderson
2020-08-17 8:49 ` [RFC v4 23/70] target/riscv: rvv-1.0: load/store whole register instructions frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-29 19:13 ` Richard Henderson
2020-08-29 19:13 ` Richard Henderson
2020-08-17 8:49 ` [RFC v4 24/70] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-29 19:30 ` Richard Henderson
2020-08-29 19:30 ` Richard Henderson
2020-08-17 8:49 ` [RFC v4 25/70] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-29 19:36 ` Richard Henderson
2020-08-29 19:36 ` Richard Henderson
2020-08-17 8:49 ` [RFC v4 26/70] target/riscv: rvv-1.0: floating-point square-root instruction frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-17 8:49 ` [RFC v4 27/70] target/riscv: rvv-1.0: floating-point classify instructions frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-17 8:49 ` [RFC v4 28/70] target/riscv: rvv-1.0: mask population count instruction frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-17 8:49 ` [RFC v4 29/70] target/riscv: rvv-1.0: find-first-set mask bit instruction frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-17 8:49 ` [RFC v4 30/70] target/riscv: rvv-1.0: set-X-first mask bit instructions frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-17 8:49 ` [RFC v4 31/70] target/riscv: rvv-1.0: iota instruction frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-17 8:49 ` [RFC v4 32/70] target/riscv: rvv-1.0: element index instruction frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-17 8:49 ` [RFC v4 33/70] target/riscv: rvv-1.0: allow load element with sign-extended frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-17 8:49 ` [RFC v4 34/70] target/riscv: rvv-1.0: register gather instructions frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-29 19:52 ` Richard Henderson
2020-08-29 19:52 ` Richard Henderson
2020-08-17 8:49 ` [RFC v4 35/70] target/riscv: rvv-1.0: integer scalar move instructions frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-17 8:49 ` [RFC v4 36/70] target/riscv: rvv-1.0: floating-point move instruction frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-29 20:00 ` Richard Henderson
2020-08-29 20:00 ` Richard Henderson
2020-08-29 20:03 ` Richard Henderson
2020-08-29 20:03 ` Richard Henderson
2020-08-17 8:49 ` [RFC v4 37/70] target/riscv: rvv-1.0: floating-point scalar move instructions frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-29 20:07 ` Richard Henderson
2020-08-29 20:07 ` Richard Henderson
2020-08-17 8:49 ` [RFC v4 38/70] target/riscv: rvv-1.0: whole register " frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-29 20:08 ` Richard Henderson
2020-08-29 20:08 ` Richard Henderson
2020-08-17 8:49 ` [RFC v4 39/70] target/riscv: rvv-1.0: integer extension instructions frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-17 8:49 ` [RFC v4 40/70] target/riscv: rvv-1.0: single-width averaging add and subtract instructions frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-29 20:11 ` Richard Henderson
2020-08-29 20:11 ` Richard Henderson
2020-08-17 8:49 ` [RFC v4 41/70] target/riscv: rvv-1.0: single-width bit shift instructions frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-17 8:49 ` [RFC v4 42/70] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-29 20:16 ` Richard Henderson
2020-08-29 20:16 ` Richard Henderson
2020-08-17 8:49 ` [RFC v4 43/70] target/riscv: rvv-1.0: narrowing integer right shift instructions frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-17 8:49 ` [RFC v4 44/70] target/riscv: rvv-1.0: widening integer multiply-add instructions frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-17 8:49 ` [RFC v4 45/70] target/riscv: rvv-1.0: add Zvqmac extension frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-29 20:17 ` Richard Henderson
2020-08-29 20:17 ` Richard Henderson
2020-08-29 20:21 ` Richard Henderson
2020-08-29 20:21 ` Richard Henderson
2020-08-17 8:49 ` [RFC v4 46/70] target/riscv: rvv-1.0: quad-widening integer multiply-add instructions frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-29 20:22 ` Richard Henderson
2020-08-29 20:22 ` Richard Henderson
2020-08-17 8:49 ` [RFC v4 47/70] target/riscv: rvv-1.0: single-width saturating add and subtract instructions frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-29 20:23 ` Richard Henderson
2020-08-29 20:23 ` Richard Henderson
2020-08-17 8:49 ` [RFC v4 48/70] target/riscv: rvv-1.0: integer comparison instructions frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-29 20:23 ` Richard Henderson
2020-08-29 20:23 ` Richard Henderson
2020-08-17 8:49 ` [RFC v4 49/70] target/riscv: use softfloat lib float16 comparison functions frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-17 8:49 ` [RFC v4 50/70] target/riscv: rvv-1.0: floating-point compare instructions frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-29 20:25 ` Richard Henderson
2020-08-29 20:25 ` Richard Henderson
2020-08-17 8:49 ` [RFC v4 51/70] target/riscv: rvv-1.0: mask-register logical instructions frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-29 20:25 ` Richard Henderson
2020-08-29 20:25 ` Richard Henderson
2020-08-17 8:49 ` [RFC v4 52/70] target/riscv: rvv-1.0: slide instructions frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-29 20:28 ` Richard Henderson
2020-08-29 20:28 ` Richard Henderson
2020-08-17 8:49 ` [RFC v4 53/70] target/riscv: rvv-1.0: floating-point " frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-29 20:33 ` Richard Henderson
2020-08-29 20:33 ` Richard Henderson
2020-09-25 8:21 ` Frank Chang
2020-09-25 8:21 ` Frank Chang
2020-09-25 18:31 ` Richard Henderson
2020-09-25 18:31 ` Richard Henderson
2020-08-17 8:49 ` [RFC v4 54/70] target/riscv: rvv-1.0: narrowing fixed-point clip instructions frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-17 8:49 ` [RFC v4 55/70] target/riscv: rvv-1.0: single-width floating-point reduction frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-29 23:50 ` Richard Henderson
2020-08-29 23:50 ` Richard Henderson
2020-08-29 23:58 ` Richard Henderson
2020-08-29 23:58 ` Richard Henderson
2020-08-31 18:50 ` Chih-Min Chao
2020-08-31 18:50 ` Chih-Min Chao
2020-08-17 8:49 ` [RFC v4 56/70] target/riscv: rvv-1.0: widening floating-point reduction instructions frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-29 23:50 ` Richard Henderson
2020-08-29 23:50 ` Richard Henderson
2020-08-17 8:49 ` [RFC v4 57/70] target/riscv: rvv-1.0: single-width scaling shift instructions frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-29 23:54 ` Richard Henderson
2020-08-29 23:54 ` Richard Henderson
2020-08-17 8:49 ` [RFC v4 58/70] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-17 8:49 ` [RFC v4 59/70] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-17 8:49 ` [RFC v4 60/70] target/riscv: rvv-1.0: remove integer extract instruction frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-17 8:49 ` [RFC v4 61/70] target/riscv: rvv-1.0: floating-point min/max instructions frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-29 23:58 ` Richard Henderson
2020-08-29 23:58 ` Richard Henderson
2020-08-17 8:49 ` frank.chang [this message]
2020-08-17 8:49 ` [RFC v4 62/70] target/riscv: introduce floating-point rounding mode enum frank.chang
2020-08-30 0:02 ` Richard Henderson
2020-08-30 0:02 ` Richard Henderson
2020-08-17 8:49 ` [RFC v4 63/70] target/riscv: rvv-1.0: floating-point/integer type-convert instructions frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-30 0:06 ` Richard Henderson
2020-08-30 0:06 ` Richard Henderson
2020-08-17 8:49 ` [RFC v4 64/70] target/riscv: rvv-1.0: widening floating-point/integer type-convert frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-30 0:14 ` Richard Henderson
2020-08-30 0:14 ` Richard Henderson
2020-08-17 8:49 ` [RFC v4 65/70] target/riscv: add "set round to odd" rounding mode helper function frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-30 0:18 ` Richard Henderson
2020-08-30 0:18 ` Richard Henderson
2020-08-17 8:49 ` [RFC v4 66/70] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-30 0:21 ` Richard Henderson
2020-08-30 0:21 ` Richard Henderson
2020-08-17 8:49 ` [RFC v4 67/70] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 512-bits frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-30 1:39 ` Richard Henderson
2020-08-30 1:39 ` Richard Henderson
2020-08-17 8:49 ` [RFC v4 68/70] target/riscv: gdb: modify gdb csr xml file to align with csr register map frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-30 2:16 ` Richard Henderson
2020-08-30 2:16 ` Richard Henderson
2020-08-17 8:49 ` [RFC v4 69/70] target/riscv: gdb: support vector registers for rv64 frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-30 1:57 ` Richard Henderson
2020-08-30 1:57 ` Richard Henderson
2020-08-17 8:49 ` [RFC v4 70/70] target/riscv: gdb: support vector registers for rv32 frank.chang
2020-08-17 8:49 ` frank.chang
2020-08-30 1:57 ` Richard Henderson
2020-08-25 8:28 ` [RFC v4 00/70] support vector extension v1.0 Frank Chang
2020-08-26 16:45 ` Alistair Francis
2020-08-26 16:45 ` Alistair Francis
2020-08-26 17:39 ` Frank Chang
2020-08-26 17:39 ` Frank Chang
2020-08-26 17:52 ` Alistair Francis
2020-08-26 17:52 ` Alistair Francis
2020-08-26 18:12 ` Frank Chang
2020-08-26 18:12 ` Frank Chang
2020-08-26 21:17 ` Alistair Francis
2020-08-26 21:17 ` Alistair Francis
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