[PATCH 0/8] Early-boot support of R5FSS from A72 U-Boot for J7200 SoCs

[PATCH 0/8] Early-boot support of R5FSS from A72 U-Boot for J7200 SoCs

[Suman Anna]

Hi Lokesh,

The following series adds the early-boot support of the revised R5FSS IP
on J7200 SoCS from A72 U-Boot. The J7200 SoCs has two R5FSS clusters, one
in MCU domain and another in MAIN domain. Patches are on top of the latest
master + "Configure J721E Main R5FSS1 to Split-mode & env" series [1].

The current series enables the default variables only for the MAIN R5FSS
cores. The config file used is common between J721E and J7200 SoCs, so is
adjusted accordingly.

The MCU R5FSS is shutdown at the end of R5 SPL, and can be booted by
modifying env variables. Early-boot is supported only through the MMC
rootfs just like on J721E SoCs.

Following are the default modes and firmware image names supported with
this series:
1. Modes
  MCU R5FSS0: LockStep mode
  MAIN R5FSS0: Split mode
2. Firmware images
    MCU R5FSS0 Core0  : j7200-mcu-r5f0_0-fw
    MCU R5FSS0 Core1  : j7200-mcu-r5f0_1-fw
    MAIN R5FSS0 Core0 : j7200-main-r5f0_0-fw
    MAIN R5FSS0 Core0 : j7200-main-r5f0_1-fw

Following is the patch summary:
 - Patches #1 and #2 update the binding and the K3 R5F remoteproc driver
   for J7200 SoCs
 - Patch #3 sets up a separate MMU map for J7200 SoCs using the appropriate
   CONFIG_TARGET_<SOC>_A72_EVM symbols
 - Patches #4 and #5 add the dts nodes with LockStep for MCU R5FSS0 and
   Split-mode for MAIN R5FSS0
 - Patch #6 leverages the CONFIG_TARGET_<SOC>_A72_EVM symbols to set the
   SoC-specific default remoteproc boot list
 - Patch #7 enables the R5F remoteproc driver and needed options for
   A72 U-Boot
 - Patch #8 enhances the bootcmd variable to include the booting of the
   rprocs based on couple of control variables

regards
Suman

[1] https://patchwork.ozlabs.org/project/uboot/list/?series=196091

Suman Anna (8):
  dt-bindings: remoteproc: k3-r5f: Update bindings for J7200 SoCs
  remoteproc: k3-r5: Add support for J7200 R5Fs
  armv8: K3: j7200: Add custom MMU support
  arm: dts: k3-j7200-mcu: Add MCU domain R5F cluster node
  arm: dts: k3-j7200-main: Add MAIN domain R5F cluster nodes
  env: ti: j721e-evm: Update rproc_fw_binaries env variable for J7200
  configs: j7200_evm_a72: Enable R5F remoteproc driver
  configs: j7200_evm_a72: Enhance bootcmd to start remoteprocs

 arch/arm/dts/k3-j7200-common-proc-board.dts   |  7 ++
 arch/arm/dts/k3-j7200-main.dtsi               | 40 ++++++++
 arch/arm/dts/k3-j7200-mcu-wakeup.dtsi         | 40 ++++++++
 arch/arm/mach-k3/arm64-mmu.c                  | 59 ++++++++++-
 configs/j7200_evm_a72_defconfig               |  6 +-
 .../remoteproc/ti,k3-r5f-rproc.txt            |  5 +-
 drivers/remoteproc/ti_k3_r5f_rproc.c          | 99 +++++++++++++++++--
 include/configs/j721e_evm.h                   | 14 ++-
 8 files changed, 255 insertions(+), 15 deletions(-)

-- 
2.28.0

[PATCH 1/8] dt-bindings: remoteproc: k3-r5f: Update bindings for J7200 SoCs

[Suman Anna]

The K3 J7200 SoCs have two dual-core Arm R5F clusters/subsystems, with
2 R5F cores each, one in each of the MCU and MAIN voltage domains.

These clusters are a revised version compared to those present on
J721E SoCs. Update the K3 R5F remoteproc bindings with the compatible
info relevant to these R5F clusters/subsystems on K3 J7200 SoCs.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 doc/device-tree-bindings/remoteproc/ti,k3-r5f-rproc.txt | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/doc/device-tree-bindings/remoteproc/ti,k3-r5f-rproc.txt b/doc/device-tree-bindings/remoteproc/ti,k3-r5f-rproc.txt
index c2fa6e834406..5708c230175c 100644
--- a/doc/device-tree-bindings/remoteproc/ti,k3-r5f-rproc.txt
+++ b/doc/device-tree-bindings/remoteproc/ti,k3-r5f-rproc.txt
@@ -25,6 +25,8 @@ The following are the mandatory properties:
 			                       K3 AM65x SoCs
 			    "ti,j721e-r5fss" for R5F clusters/subsystems on
 			                       K3 J721E SoCs
+			    "ti,j7200-r5fss" for R5F clusters/subsystems on
+			                       K3 J7200 SoCs
 - power-domains:	Should contain a phandle to a PM domain provider node
 			and an args specifier containing the R5FSS device id
 			value. This property is as per the binding,
@@ -56,6 +58,7 @@ The following are the mandatory properties:
 - compatible:		Should be one of the following,
 			    "ti,am654-r5f" for the R5F cores in K3 AM65x SoCs
 			    "ti,j721e-r5f" for the R5F cores in K3 J721E SOCs
+			    "ti,j7200-r5f" for the R5F cores in K3 J7200 SOCs
 - reg:			Should contain an entry for each value in 'reg-names'.
 			Each entry should have the memory region's start address
 			and the size of the region, the representation matching
@@ -79,7 +82,7 @@ The following are the mandatory properties:
 			specifier. Please refer to the following reset bindings
 			for the reset argument specifier,
 			Documentation/devicetree/bindings/reset/ti,sci-reset.txt
-			    for AM65x and J721E SoCs
+			    for AM65x, J721E and J7200 SoCs
 
 Optional properties:
 --------------------
-- 
2.28.0

[PATCH 2/8] remoteproc: k3-r5: Add support for J7200 R5Fs

[Suman Anna]

The K3 J7200 SoC family has a revised R5F sub-system and contains a
subset of the R5F clusters present on J721E SoCs. The integration of
these clusters is very much similar to J721E SoCs otherwise.

The revised IP has the following two new features:
 1. TCMs are auto-initialized during module power-up, and the behavior
    is programmable through a MMR bit controlled by System Firmware.
 2. The LockStep-mode allows the Core1 TCMs to be combined with the
    Core0 TCMs effectively doubling the amount of TCMs available.
    The LockStep-mode on previous SoCs could only use the Core0 TCMs.
    This combined TCMs appear contiguous at the respective Core0 TCM
    addresses.

Add the support to these clusters in the K3 R5F remoteproc driver
using J7200 specific compatibles and revised logic accounting for
the above IP features/differences.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 drivers/remoteproc/ti_k3_r5f_rproc.c | 99 +++++++++++++++++++++++++---
 1 file changed, 89 insertions(+), 10 deletions(-)

diff --git a/drivers/remoteproc/ti_k3_r5f_rproc.c b/drivers/remoteproc/ti_k3_r5f_rproc.c
index 1a7f1f8a005f..8e21a38be7f1 100644
--- a/drivers/remoteproc/ti_k3_r5f_rproc.c
+++ b/drivers/remoteproc/ti_k3_r5f_rproc.c
@@ -2,8 +2,9 @@
 /*
  * Texas Instruments' K3 R5 Remoteproc driver
  *
- * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018-2020 Texas Instruments Incorporated - https://www.ti.com/
  *	Lokesh Vutla <lokeshvutla@ti.com>
+ *	Suman Anna <s-anna@ti.com>
  */
 
 #include <common.h>
@@ -37,6 +38,8 @@
 #define PROC_BOOT_CFG_FLAG_R5_BTCM_EN			0x00001000
 #define PROC_BOOT_CFG_FLAG_R5_ATCM_EN			0x00002000
 #define PROC_BOOT_CFG_FLAG_GEN_IGN_BOOTVECTOR		0x10000000
+/* Available from J7200 SoCs onwards */
+#define PROC_BOOT_CFG_FLAG_R5_MEM_INIT_DIS		0x00004000
 
 /* R5 TI-SCI Processor Control Flags */
 #define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT		0x00000001
@@ -54,6 +57,16 @@ enum cluster_mode {
 	CLUSTER_MODE_LOCKSTEP,
 };
 
+/**
+ * struct k3_r5f_ip_data - internal data structure used for IP variations
+ * @tcm_is_double: flag to denote the larger unified TCMs in certain modes
+ * @tcm_ecc_autoinit: flag to denote the auto-initialization of TCMs for ECC
+ */
+struct k3_r5f_ip_data {
+	bool tcm_is_double;
+	bool tcm_ecc_autoinit;
+};
+
 /**
  * struct k3_r5_mem - internal memory structure
  * @cpu_addr: MPU virtual address of the memory region
@@ -74,6 +87,7 @@ struct k3_r5f_mem {
  * @cluster: pointer to the parent cluster.
  * @reset: reset control handle
  * @tsp: TI-SCI processor control handle
+ * @ipdata: cached pointer to R5F IP specific feature data
  * @mem: Array of available internal memories
  * @num_mem: Number of available memories
  * @atcm_enable: flag to control ATCM enablement
@@ -86,6 +100,7 @@ struct k3_r5f_core {
 	struct k3_r5f_cluster *cluster;
 	struct reset_ctl reset;
 	struct ti_sci_proc tsp;
+	struct k3_r5f_ip_data *ipdata;
 	struct k3_r5f_mem *mem;
 	int num_mems;
 	u32 atcm_enable;
@@ -257,6 +272,18 @@ static int k3_r5f_core_sanity_check(struct k3_r5f_core *core)
 	return 0;
 }
 
+/* Zero out TCMs so that ECC can be effective on all TCM addresses */
+void k3_r5f_init_tcm_memories(struct k3_r5f_core *core, bool auto_inited)
+{
+	if (core->ipdata->tcm_ecc_autoinit && auto_inited)
+		return;
+
+	if (core->atcm_enable)
+		memset(core->mem[0].cpu_addr, 0x00, core->mem[0].size);
+	if (core->btcm_enable)
+		memset(core->mem[1].cpu_addr, 0x00, core->mem[1].size);
+}
+
 /**
  * k3_r5f_load() - Load up the Remote processor image
  * @dev:	rproc device pointer
@@ -268,7 +295,9 @@ static int k3_r5f_core_sanity_check(struct k3_r5f_core *core)
 static int k3_r5f_load(struct udevice *dev, ulong addr, ulong size)
 {
 	struct k3_r5f_core *core = dev_get_priv(dev);
-	u32 boot_vector;
+	u64 boot_vector;
+	u32 ctrl, sts, cfg = 0;
+	bool mem_auto_init;
 	int ret;
 
 	dev_dbg(dev, "%s addr = 0x%lx, size = 0x%lx\n", __func__, addr, size);
@@ -281,6 +310,12 @@ static int k3_r5f_load(struct udevice *dev, ulong addr, ulong size)
 	if (ret)
 		return ret;
 
+	ret = ti_sci_proc_get_status(&core->tsp, &boot_vector, &cfg, &ctrl,
+				     &sts);
+	if (ret)
+		return ret;
+	mem_auto_init = !(cfg & PROC_BOOT_CFG_FLAG_R5_MEM_INIT_DIS);
+
 	ret = k3_r5f_prepare(dev);
 	if (ret) {
 		dev_err(dev, "R5f prepare failed for core %d\n",
@@ -288,11 +323,7 @@ static int k3_r5f_load(struct udevice *dev, ulong addr, ulong size)
 		goto proc_release;
 	}
 
-	/* Zero out TCMs so that ECC can be effective on all TCM addresses */
-	if (core->atcm_enable)
-		memset(core->mem[0].cpu_addr, 0x00, core->mem[0].size);
-	if (core->btcm_enable)
-		memset(core->mem[1].cpu_addr, 0x00, core->mem[1].size);
+	k3_r5f_init_tcm_memories(core, mem_auto_init);
 
 	ret = rproc_elf_load_image(dev, addr, size);
 	if (ret < 0) {
@@ -302,7 +333,7 @@ static int k3_r5f_load(struct udevice *dev, ulong addr, ulong size)
 
 	boot_vector = rproc_elf_get_boot_addr(dev, addr);
 
-	dev_dbg(dev, "%s: Boot vector = 0x%x\n", __func__, boot_vector);
+	dev_dbg(dev, "%s: Boot vector = 0x%llx\n", __func__, boot_vector);
 
 	ret = ti_sci_proc_set_config(&core->tsp, boot_vector, 0, 0);
 
@@ -657,6 +688,8 @@ static int k3_r5f_of_to_priv(struct k3_r5f_core *core)
 		return ret;
 	}
 
+	core->ipdata = (struct k3_r5f_ip_data *)dev_get_driver_data(core->dev);
+
 	return 0;
 }
 
@@ -702,6 +735,38 @@ static int k3_r5f_core_of_get_memories(struct k3_r5f_core *core)
 	return 0;
 }
 
+/*
+ * Each R5F core within a typical R5FSS instance has a total of 64 KB of TCMs,
+ * split equally into two 32 KB banks between ATCM and BTCM. The TCMs from both
+ * cores are usable in Split-mode, but only the Core0 TCMs can be used in
+ * LockStep-mode. The newer revisions of the R5FSS IP maximizes these TCMs by
+ * leveraging the Core1 TCMs as well in certain modes where they would have
+ * otherwise been unusable (Eg: LockStep-mode on J7200 SoCs). This is done by
+ * making a Core1 TCM visible immediately after the corresponding Core0 TCM.
+ * The SoC memory map uses the larger 64 KB sizes for the Core0 TCMs, and the
+ * dts representation reflects this increased size on supported SoCs. The Core0
+ * TCM sizes therefore have to be adjusted to only half the original size in
+ * Split mode.
+ */
+static void k3_r5f_core_adjust_tcm_sizes(struct k3_r5f_core *core)
+{
+	struct k3_r5f_cluster *cluster = core->cluster;
+
+	if (cluster->mode == CLUSTER_MODE_LOCKSTEP)
+		return;
+
+	if (!core->ipdata->tcm_is_double)
+		return;
+
+	if (core == cluster->cores[0]) {
+		core->mem[0].size /= 2;
+		core->mem[1].size /= 2;
+
+		dev_dbg(core->dev, "adjusted TCM sizes, ATCM = 0x%zx BTCM = 0x%zx\n",
+			core->mem[0].size, core->mem[1].size);
+	}
+}
+
 /**
  * k3_r5f_probe() - Basic probe
  * @dev:	corresponding k3 remote processor device
@@ -755,6 +820,8 @@ static int k3_r5f_probe(struct udevice *dev)
 		return ret;
 	}
 
+	k3_r5f_core_adjust_tcm_sizes(core);
+
 	dev_dbg(dev, "Remoteproc successfully probed\n");
 
 	return 0;
@@ -771,9 +838,20 @@ static int k3_r5f_remove(struct udevice *dev)
 	return 0;
 }
 
+static const struct k3_r5f_ip_data k3_data = {
+	.tcm_is_double = false,
+	.tcm_ecc_autoinit = false,
+};
+
+static const struct k3_r5f_ip_data j7200_data = {
+	.tcm_is_double = true,
+	.tcm_ecc_autoinit = true,
+};
+
 static const struct udevice_id k3_r5f_rproc_ids[] = {
-	{ .compatible = "ti,am654-r5f"},
-	{ .compatible = "ti,j721e-r5f"},
+	{ .compatible = "ti,am654-r5f", .data = (ulong)&k3_data, },
+	{ .compatible = "ti,j721e-r5f", .data = (ulong)&k3_data, },
+	{ .compatible = "ti,j7200-r5f", .data = (ulong)&j7200_data, },
 	{}
 };
 
@@ -810,6 +888,7 @@ static int k3_r5f_cluster_probe(struct udevice *dev)
 static const struct udevice_id k3_r5fss_ids[] = {
 	{ .compatible = "ti,am654-r5fss"},
 	{ .compatible = "ti,j721e-r5fss"},
+	{ .compatible = "ti,j7200-r5fss"},
 	{}
 };
 
-- 
2.28.0

[PATCH 3/8] armv8: K3: j7200: Add custom MMU support

[Suman Anna]

The A72 U-Boot code can load and boot a number of the available
R5FSS Cores on the J7200 SoC. Change the memory attributes for the
DDR regions used by the remote processors so that the cores can see
and execute the proper code.

The J7200 SoC has less number of remote processors compared to J721E,
so use less memory for the remote processors. So, a separate table
based on the current J721E table is added for J7200 SoCs, and selected
using the appropriate Kconfig CONFIG_TARGET_J7200_A72_EVM symbol.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm/mach-k3/arm64-mmu.c | 59 +++++++++++++++++++++++++++++++++++-
 1 file changed, 58 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c
index 95f830b7ffe4..a0da3df59388 100644
--- a/arch/arm/mach-k3/arm64-mmu.c
+++ b/arch/arm/mach-k3/arm64-mmu.c
@@ -2,8 +2,9 @@
 /*
  * K3: ARM64 MMU setup
  *
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018-2020 Texas Instruments Incorporated - https://www.ti.com/
  *	Lokesh Vutla <lokeshvutla@ti.com>
+ *	Suman Anna <s-anna@ti.com>
  * (This file is derived from arch/arm/mach-zynqmp/cpu.c)
  *
  */
@@ -66,6 +67,8 @@ struct mm_region *mem_map = am654_mem_map;
 #endif /* CONFIG_SOC_K3_AM6 */
 
 #ifdef CONFIG_SOC_K3_J721E
+
+#ifdef CONFIG_TARGET_J721E_A72_EVM
 /* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
 #define NR_MMU_REGIONS	(CONFIG_NR_DRAM_BANKS + 6)
 
@@ -122,4 +125,58 @@ struct mm_region j721e_mem_map[NR_MMU_REGIONS] = {
 };
 
 struct mm_region *mem_map = j721e_mem_map;
+#endif /* CONFIG_TARGET_J721E_A72_EVM */
+
+#ifdef CONFIG_TARGET_J7200_A72_EVM
+#define NR_MMU_REGIONS	(CONFIG_NR_DRAM_BANKS + 5)
+
+/* ToDo: Add 64bit IO */
+struct mm_region j7200_mem_map[NR_MMU_REGIONS] = {
+	{
+		.virt = 0x0UL,
+		.phys = 0x0UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		.virt = 0x80000000UL,
+		.phys = 0x80000000UL,
+		.size = 0x20000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.virt = 0xa0000000UL,
+		.phys = 0xa0000000UL,
+		.size = 0x04800000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
+			 PTE_BLOCK_NON_SHARE
+	}, {
+		.virt = 0xa4800000UL,
+		.phys = 0xa4800000UL,
+		.size = 0x5b800000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.virt = 0x880000000UL,
+		.phys = 0x880000000UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.virt = 0x500000000UL,
+		.phys = 0x500000000UL,
+		.size = 0x400000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = j7200_mem_map;
+#endif /* CONFIG_TARGET_J7200_A72_EVM */
+
 #endif /* CONFIG_SOC_K3_J721E */
-- 
2.28.0

[PATCH 4/8] arm: dts: k3-j7200-mcu: Add MCU domain R5F cluster node

[Suman Anna]

The J7200 SoCs have 2 dual-core Arm Cortex-R5F processor (R5FSS)
subsystems/clusters. One R5F cluster is present within the MCU
domain (MCU_R5FSS0), and the other one is present within the MAIN
domain (MAIN_R5FSS0). Each of these can be configured at boot time
to be either run in a LockStep mode or in an Asymmetric Multi
Processing (AMP) fashion in Split-mode. These subsystems have 64 KB
each Tightly-Coupled Memory (TCM) internal memories for each core
split between two banks - ATCM and BTCM (further interleaved into
two banks). The TCMs of both Cores are combined in LockStep-mode
to provide a larger 128 KB of memory.

Add the DT node for the MCU domain R5F cluster/subsystem, the two
R5F cores are added as child nodes to the main cluster/subsystem node.
The cluster is configured to run in LockStep mode by default, with
the ATCMs enabled to allow the R5 cores to execute code from DDR with
boot-strapping code from ATCM. The inter-processor communication
between the main A72 cores and these processors is achieved through
shared memory and Mailboxes.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm/dts/k3-j7200-common-proc-board.dts |  5 +++
 arch/arm/dts/k3-j7200-mcu-wakeup.dtsi       | 40 +++++++++++++++++++++
 2 files changed, 45 insertions(+)

diff --git a/arch/arm/dts/k3-j7200-common-proc-board.dts b/arch/arm/dts/k3-j7200-common-proc-board.dts
index 3f1d03c96037..b48588952513 100644
--- a/arch/arm/dts/k3-j7200-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-common-proc-board.dts
@@ -13,6 +13,11 @@
 		stdout-path = "serial2:115200n8";
 		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
 	};
+
+	aliases {
+		remoteproc0 = &mcu_r5fss0_core0;
+		remoteproc1 = &mcu_r5fss0_core1;
+	};
 };
 
 &wkup_pmx0 {
diff --git a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi b/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
index 4c899c8aca5d..75c0c8597dc9 100644
--- a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
+++ b/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
@@ -269,4 +269,44 @@
 			ti,cpts-periodic-outputs = <2>;
 		};
 	};
+
+	mcu_r5fss0: r5fss at 41000000 {
+		compatible = "ti,j7200-r5fss";
+		lockstep-mode = <1>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x41000000 0x00 0x41000000 0x20000>,
+			 <0x41400000 0x00 0x41400000 0x20000>;
+		power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
+
+		mcu_r5fss0_core0: r5f at 41000000 {
+			compatible = "ti,j7200-r5f";
+			reg = <0x41000000 0x00010000>,
+			      <0x41010000 0x00010000>;
+			reg-names = "atcm", "btcm";
+			ti,sci = <&dmsc>;
+			ti,sci-dev-id = <250>;
+			ti,sci-proc-ids = <0x01 0xff>;
+			resets = <&k3_reset 250 1>;
+			firmware-name = "j7200-mcu-r5f0_0-fw";
+			atcm-enable = <1>;
+			btcm-enable = <1>;
+			loczrama = <1>;
+		};
+
+		mcu_r5fss0_core1: r5f at 41400000 {
+			compatible = "ti,j7200-r5f";
+			reg = <0x41400000 0x00008000>,
+			      <0x41410000 0x00008000>;
+			reg-names = "atcm", "btcm";
+			ti,sci = <&dmsc>;
+			ti,sci-dev-id = <251>;
+			ti,sci-proc-ids = <0x02 0xff>;
+			resets = <&k3_reset 251 1>;
+			firmware-name = "j7200-mcu-r5f0_1-fw";
+			atcm-enable = <1>;
+			btcm-enable = <1>;
+			loczrama = <1>;
+		};
+	};
 };
-- 
2.28.0

[PATCH 5/8] arm: dts: k3-j7200-main: Add MAIN domain R5F cluster nodes

[Suman Anna]

The J7200 SoCs have 2 dual-core Arm Cortex-R5F processor (R5FSS)
subsystems/clusters. One R5F cluster is present within the MCU
domain (MCU_R5FSS0), and the other one is present within the MAIN
domain (MAIN_R5FSS0). Each of these can be configured at boot time
to be either run in a LockStep mode or in an Asymmetric Multi
Processing (AMP) fashion in Split-mode. These subsystems have 64 KB
each Tightly-Coupled Memory (TCM) internal memories for each core
split between two banks - ATCM and BTCM (further interleaved into
two banks). The TCMs of both Cores are combined in LockStep-mode
to provide a larger 128 KB of memory.

Add the DT node for the MAIN domain R5F cluster/subsystem, the two
R5F cores are added as child nodes to the main cluster/subsystem node.
The cluster is configured to run in Split-mode by default, with the
ATCMs enabled to allow the R5 cores to execute code from DDR with
boot-strapping code from ATCM. The inter-processor communication
between the main A72 cores and these processors is achieved through
shared memory and Mailboxes.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm/dts/k3-j7200-common-proc-board.dts |  2 ++
 arch/arm/dts/k3-j7200-main.dtsi             | 40 +++++++++++++++++++++
 2 files changed, 42 insertions(+)

diff --git a/arch/arm/dts/k3-j7200-common-proc-board.dts b/arch/arm/dts/k3-j7200-common-proc-board.dts
index b48588952513..cc3d933cbb51 100644
--- a/arch/arm/dts/k3-j7200-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-common-proc-board.dts
@@ -17,6 +17,8 @@
 	aliases {
 		remoteproc0 = &mcu_r5fss0_core0;
 		remoteproc1 = &mcu_r5fss0_core1;
+		remoteproc2 = &main_r5fss0_core0;
+		remoteproc3 = &main_r5fss0_core1;
 	};
 };
 
diff --git a/arch/arm/dts/k3-j7200-main.dtsi b/arch/arm/dts/k3-j7200-main.dtsi
index aaa1fdd5a3ce..c25f03cf23d9 100644
--- a/arch/arm/dts/k3-j7200-main.dtsi
+++ b/arch/arm/dts/k3-j7200-main.dtsi
@@ -340,4 +340,44 @@
 			dr_mode = "otg";
 		};
 	};
+
+	main_r5fss0: r5fss at 5c00000 {
+		compatible = "ti,j7200-r5fss";
+		lockstep-mode = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
+			 <0x5d00000 0x00 0x5d00000 0x20000>;
+		power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
+
+		main_r5fss0_core0: r5f at 5c00000 {
+			compatible = "ti,j7200-r5f";
+			reg = <0x5c00000 0x00010000>,
+			      <0x5c10000 0x00010000>;
+			reg-names = "atcm", "btcm";
+			ti,sci = <&dmsc>;
+			ti,sci-dev-id = <245>;
+			ti,sci-proc-ids = <0x06 0xFF>;
+			resets = <&k3_reset 245 1>;
+			firmware-name = "j7200-main-r5f0_0-fw";
+			atcm-enable = <1>;
+			btcm-enable = <1>;
+			loczrama = <1>;
+		};
+
+		main_r5fss0_core1: r5f at 5d00000 {
+			compatible = "ti,j7200-r5f";
+			reg = <0x5d00000 0x00008000>,
+			      <0x5d10000 0x00008000>;
+			reg-names = "atcm", "btcm";
+			ti,sci = <&dmsc>;
+			ti,sci-dev-id = <246>;
+			ti,sci-proc-ids = <0x07 0xFF>;
+			resets = <&k3_reset 246 1>;
+			firmware-name = "j7200-main-r5f0_1-fw";
+			atcm-enable = <1>;
+			btcm-enable = <1>;
+			loczrama = <1>;
+		};
+	};
 };
-- 
2.28.0

[PATCH 6/8] env: ti: j721e-evm: Update rproc_fw_binaries env variable for J7200

[Suman Anna]

The J7200 SoCs have different number of remote processors, but reuse
the same environment settings as the J721E SoCs. The current env
variable rproc_fw_binaries is geared towards J721E SoCs and is
incorrect for J7200 SoCs. Please see the logic originally added in
commit 0b4ab9c9a754 ("env: ti: j721e-evm: Add support to boot rprocs
including R5Fs and DSPs").

Fix this by defining the DEFAULT_RPROCS macro appropriately using
the corresponding TARGET_EVM Kconfig symbol. This macro is used by
the 'rproc_fw_binaries' env variable in the common remoteproc env
header file k3_rproc.h.

The list of R5F cores to be started before loading and booting the
Linux kernel are as follows, and mainly comprises of the Main R5FSS0
cores in this order:
   Main R5FSS0 (Split) Core0 : 2 /lib/firmware/j7200-main-r5f0_0-fw
   Main R5FSS0 (Split) Core1 : 3 /lib/firmware/j7200-main-r5f0_1-fw

The MCU R5FSS0 is in LockStep mode and is expected to be booted by
R5 SPL, so it is not included in the list. The order of rprocs to
boot cannot be really modified as only the Main R5FSS0 cores are
involved and Core0 has to be booted first always before the
corresponding Core1.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 include/configs/j721e_evm.h | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h
index cddcd7a00d37..dc06de234154 100644
--- a/include/configs/j721e_evm.h
+++ b/include/configs/j721e_evm.h
@@ -2,7 +2,7 @@
 /*
  * Configuration header file for K3 J721E EVM
  *
- * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018-2020 Texas Instruments Incorporated - https://www.ti.com/
  *	Lokesh Vutla <lokeshvutla@ti.com>
  */
 
@@ -116,9 +116,14 @@
 		"${bootdir}/${name_fit}\0"				\
 	"partitions=" PARTS_DEFAULT
 
+/* Set the default list of remote processors to boot */
+#if defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM)
 #ifdef DEFAULT_RPROCS
 #undef DEFAULT_RPROCS
 #endif
+#endif
+
+#ifdef CONFIG_TARGET_J721E_A72_EVM
 #define DEFAULT_RPROCS	""						\
 		"3 /lib/firmware/j7-main-r5f0_1-fw "			\
 		"4 /lib/firmware/j7-main-r5f1_0-fw "			\
@@ -126,6 +131,13 @@
 		"6 /lib/firmware/j7-c66_0-fw "				\
 		"7 /lib/firmware/j7-c66_1-fw "				\
 		"8 /lib/firmware/j7-c71_0-fw "
+#endif /* CONFIG_TARGET_J721E_A72_EVM */
+
+#ifdef CONFIG_TARGET_J7200_A72_EVM
+#define DEFAULT_RPROCS ""						\
+		"2 /lib/firmware/j7200-main-r5f0_0-fw "			\
+		"3 /lib/firmware/j7200-main-r5f0_1-fw "
+#endif /* CONFIG_TARGET_J7200_A72_EVM */
 
 /* set default dfu_bufsiz to 128KB (sector size of OSPI) */
 #define EXTRA_ENV_DFUARGS \
-- 
2.28.0

[PATCH 7/8] configs: j7200_evm_a72: Enable R5F remoteproc driver

[Suman Anna]

The J7200 SoCs has two R5F sub-systems. Enable the TI K3
R5F remoteproc driver and the remoteproc command options
to allow these R5F processors to be booted from A72 U-Boot.

The Kconfigs are added using savedefconfig.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 configs/j7200_evm_a72_defconfig | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig
index 6e854648eb45..52440a09a647 100644
--- a/configs/j7200_evm_a72_defconfig
+++ b/configs/j7200_evm_a72_defconfig
@@ -4,6 +4,7 @@ CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_NR_DRAM_BANKS=2
 CONFIG_SOC_K3_J721E=y
 CONFIG_TARGET_J7200_A72_EVM=y
 CONFIG_ENV_SIZE=0x20000
@@ -16,7 +17,6 @@ CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_OFFSET_REDUND=0x6A0000
 CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
@@ -61,6 +61,7 @@ CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_MTD=y
+CONFIG_CMD_REMOTEPROC=y
 CONFIG_CMD_UFS=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
@@ -140,6 +141,7 @@ CONFIG_POWER_DOMAIN=y
 CONFIG_TI_SCI_POWER_DOMAIN=y
 CONFIG_RAM=y
 CONFIG_SPL_RAM=y
+CONFIG_REMOTEPROC_TI_K3_R5F=y
 CONFIG_DM_RESET=y
 CONFIG_RESET_TI_SCI=y
 CONFIG_SCSI=y
-- 
2.28.0

[PATCH 8/8] configs: j7200_evm_a72: Enhance bootcmd to start remoteprocs

[Suman Anna]

The A72 U-boot can support early booting of any of the Main or MCU R5F
remote processors from U-boot prompt to achieve various system usecases
before booting the Linux kernel. Update the default BOOTCOMMAND to provide
an automatic and easier way to start various remote processors through
added environment variables.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 configs/j7200_evm_a72_defconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig
index 52440a09a647..3572d7ba9414 100644
--- a/configs/j7200_evm_a72_defconfig
+++ b/configs/j7200_evm_a72_defconfig
@@ -30,7 +30,7 @@ CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
 # CONFIG_USE_SPL_FIT_GENERATOR is not set
 CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
+CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
-- 
2.28.0

[PATCH 0/8] Early-boot support of R5FSS from A72 U-Boot for J7200 SoCs

[Lokesh Vutla]

On 18/08/20 4:45 am, Suman Anna wrote:
> Hi Lokesh,
> 
> The following series adds the early-boot support of the revised R5FSS IP
> on J7200 SoCS from A72 U-Boot. The J7200 SoCs has two R5FSS clusters, one
> in MCU domain and another in MAIN domain. Patches are on top of the latest
> master + "Configure J721E Main R5FSS1 to Split-mode & env" series [1].
> 
> The current series enables the default variables only for the MAIN R5FSS
> cores. The config file used is common between J721E and J7200 SoCs, so is
> adjusted accordingly.
> 
> The MCU R5FSS is shutdown at the end of R5 SPL, and can be booted by
> modifying env variables. Early-boot is supported only through the MMC
> rootfs just like on J721E SoCs.
> 
> Following are the default modes and firmware image names supported with
> this series:
> 1. Modes
>   MCU R5FSS0: LockStep mode
>   MAIN R5FSS0: Split mode
> 2. Firmware images
>     MCU R5FSS0 Core0  : j7200-mcu-r5f0_0-fw
>     MCU R5FSS0 Core1  : j7200-mcu-r5f0_1-fw
>     MAIN R5FSS0 Core0 : j7200-main-r5f0_0-fw
>     MAIN R5FSS0 Core0 : j7200-main-r5f0_1-fw
> 
> Following is the patch summary:
>  - Patches #1 and #2 update the binding and the K3 R5F remoteproc driver
>    for J7200 SoCs
>  - Patch #3 sets up a separate MMU map for J7200 SoCs using the appropriate
>    CONFIG_TARGET_<SOC>_A72_EVM symbols
>  - Patches #4 and #5 add the dts nodes with LockStep for MCU R5FSS0 and
>    Split-mode for MAIN R5FSS0
>  - Patch #6 leverages the CONFIG_TARGET_<SOC>_A72_EVM symbols to set the
>    SoC-specific default remoteproc boot list
>  - Patch #7 enables the R5F remoteproc driver and needed options for
>    A72 U-Boot
>  - Patch #8 enhances the bootcmd variable to include the booting of the
>    rprocs based on couple of control variables


Applied to u-boot-ti next branch.

Thanks and regards,
Lokesh