[PATCH 1/4] drm/amd/pm: correct gfx and pcie settings on umd pstate switching

[PATCH 1/4] drm/amd/pm: correct gfx and pcie settings on umd pstate switching

[Evan Quan]

For entering UMD stable Pstate, the operations to enter rlc_safe
mode, disable mgcg_perfmon and disable PCIE aspm are needed. And
the opposite operations should be performed on UMD stable Pstate
exiting.

Change-Id: Iff4aa465fd16f55a4f4de8ee0503997b204f8f9d
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h       | 3 +++
 drivers/gpu/drm/amd/amdgpu/nv.c           | 7 +++++++
 drivers/gpu/drm/amd/amdgpu/soc15.c        | 7 +++++++
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 ++
 4 files changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 8ba389780001..6ff4ddb09d1f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -617,6 +617,8 @@ struct amdgpu_asic_funcs {
 	uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);
 	/* device supports BACO */
 	bool (*supports_baco)(struct amdgpu_device *adev);
+	/* enter/exit umd stable pstate */
+	int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter);
 };
 
 /*
@@ -1132,6 +1134,7 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev))
+#define amdgpu_asic_update_umd_stable_pstate(adev, enter) (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter))
 
 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter));
 
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 54e941e0db60..d07c84a7543d 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -691,6 +691,12 @@ static void nv_init_doorbell_index(struct amdgpu_device *adev)
 	adev->doorbell_index.sdma_doorbell_range = 20;
 }
 
+static int nv_update_umd_stable_pstate(struct amdgpu_device *adev,
+				       bool enter)
+{
+	return 0;
+}
+
 static const struct amdgpu_asic_funcs nv_asic_funcs =
 {
 	.read_disabled_bios = &nv_read_disabled_bios,
@@ -710,6 +716,7 @@ static const struct amdgpu_asic_funcs nv_asic_funcs =
 	.need_reset_on_init = &nv_need_reset_on_init,
 	.get_pcie_replay_count = &nv_get_pcie_replay_count,
 	.supports_baco = &nv_asic_supports_baco,
+	.update_umd_stable_pstate = &nv_update_umd_stable_pstate,
 };
 
 static int nv_common_early_init(void *handle)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 3cd98c144bc6..d9671db3b98d 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -1029,6 +1029,12 @@ static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev)
 	return (nak_r + nak_g);
 }
 
+static int soc15_update_umd_stable_pstate(struct amdgpu_device *adev,
+					  bool enter)
+{
+	return 0;
+}
+
 static const struct amdgpu_asic_funcs soc15_asic_funcs =
 {
 	.read_disabled_bios = &soc15_read_disabled_bios,
@@ -1049,6 +1055,7 @@ static const struct amdgpu_asic_funcs soc15_asic_funcs =
 	.need_reset_on_init = &soc15_need_reset_on_init,
 	.get_pcie_replay_count = &soc15_get_pcie_replay_count,
 	.supports_baco = &soc15_supports_baco,
+	.update_umd_stable_pstate = &soc15_update_umd_stable_pstate,
 };
 
 static const struct amdgpu_asic_funcs vega20_asic_funcs =
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 8eb5b92903cd..db0f1718087d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1442,6 +1442,7 @@ static int smu_enable_umd_pstate(void *handle,
 							       AMD_CG_STATE_UNGATE);
 			smu_gfx_ulv_control(smu, false);
 			smu_deep_sleep_control(smu, false);
+			amdgpu_asic_update_umd_stable_pstate(smu->adev, true);
 		}
 	} else {
 		/* exit umd pstate, restore level, enable gfx cg*/
@@ -1449,6 +1450,7 @@ static int smu_enable_umd_pstate(void *handle,
 			if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
 				*level = smu_dpm_ctx->saved_dpm_level;
 			smu_dpm_ctx->enable_umd_pstate = false;
+			amdgpu_asic_update_umd_stable_pstate(smu->adev, false);
 			smu_deep_sleep_control(smu, true);
 			smu_gfx_ulv_control(smu, true);
 			amdgpu_device_ip_set_clockgating_state(smu->adev,
-- 
2.28.0

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[PATCH 2/4] drm/amdgpu: add interface for setting ASPM

[Evan Quan]

Support NAVI10 ASPM setting.

Change-Id: I0c9410951e23b1d4a30bf8e373431dcb16a4573b
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h |  2 ++
 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c   | 39 ++++++++++++++++++++++++
 2 files changed, 41 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
index edaac242ff85..344faf39b7dd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
@@ -85,6 +85,8 @@ struct amdgpu_nbio_funcs {
 	void (*query_ras_error_count)(struct amdgpu_device *adev,
 					void *ras_error_status);
 	int (*ras_late_init)(struct amdgpu_device *adev);
+	void (*enable_aspm)(struct amdgpu_device *adev,
+			    bool enable);
 };
 
 struct amdgpu_nbio {
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
index 7429f30398b9..e0048806afaa 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
@@ -28,10 +28,12 @@
 #include "nbio/nbio_2_3_offset.h"
 #include "nbio/nbio_2_3_sh_mask.h"
 #include <uapi/linux/kfd_ioctl.h>
+#include <linux/pci.h>
 
 #define smnPCIE_CONFIG_CNTL	0x11180044
 #define smnCPM_CONTROL		0x11180460
 #define smnPCIE_CNTL2		0x11180070
+#define smnPCIE_LC_CNTL		0x11140280
 
 #define mmBIF_SDMA2_DOORBELL_RANGE		0x01d6
 #define mmBIF_SDMA2_DOORBELL_RANGE_BASE_IDX	2
@@ -312,6 +314,42 @@ static void nbio_v2_3_init_registers(struct amdgpu_device *adev)
 		WREG32_PCIE(smnPCIE_CONFIG_CNTL, data);
 }
 
+#define NAVI10_PCIE__LC_L0S_INACTIVITY_DEFAULT		0x00000000 // off by default, no gains over L1
+#define NAVI10_PCIE__LC_L1_INACTIVITY_DEFAULT		0x00000009 // 1=1us, 9=1ms
+#define NAVI10_PCIE__LC_L1_INACTIVITY_TBT_DEFAULT	0x0000000E // 4ms
+
+static void nbio_v2_3_enable_aspm(struct amdgpu_device *adev,
+				  bool enable)
+{
+	uint32_t def, data;
+
+	def = data = RREG32_PCIE(smnPCIE_LC_CNTL);
+
+	if (enable) {
+		/* Disable ASPM L0s/L1 first */
+		data &= ~(PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK | PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK);
+
+		data |= NAVI10_PCIE__LC_L0S_INACTIVITY_DEFAULT << PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT;
+
+		if (pci_is_thunderbolt_attached(adev->pdev))
+			data |= NAVI10_PCIE__LC_L1_INACTIVITY_TBT_DEFAULT  << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT;
+		else
+			data |= NAVI10_PCIE__LC_L1_INACTIVITY_DEFAULT << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT;
+
+		data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
+	} else {
+		/* Disbale ASPM L1 */
+		data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK;
+		/* Disable ASPM TxL0s */
+		data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;
+		/* Disable ACPI L1 */
+		data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
+	}
+
+	if (def != data)
+		WREG32_PCIE(smnPCIE_LC_CNTL, data);
+}
+
 const struct amdgpu_nbio_funcs nbio_v2_3_funcs = {
 	.get_hdp_flush_req_offset = nbio_v2_3_get_hdp_flush_req_offset,
 	.get_hdp_flush_done_offset = nbio_v2_3_get_hdp_flush_done_offset,
@@ -332,4 +370,5 @@ const struct amdgpu_nbio_funcs nbio_v2_3_funcs = {
 	.ih_control = nbio_v2_3_ih_control,
 	.init_registers = nbio_v2_3_init_registers,
 	.remap_hdp_registers = nbio_v2_3_remap_hdp_registers,
+	.enable_aspm = nbio_v2_3_enable_aspm,
 };
-- 
2.28.0

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[PATCH 3/4] drm/amdgpu: add interface for setting MGCG perfmon

[Evan Quan]

Enable Navi1X MGCG perfmon setting.

Change-Id: Ifc860a798becbe372f974f7eb537a4a57ac4943f
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h |  1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c  | 16 ++++++++++++++++
 2 files changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index a611e78dd4ba..ab71f7327e50 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -217,6 +217,7 @@ struct amdgpu_gfx_funcs {
 	int (*query_ras_error_count) (struct amdgpu_device *adev, void *ras_error_status);
 	void (*reset_ras_error_count) (struct amdgpu_device *adev);
 	void (*init_spm_golden)(struct amdgpu_device *adev);
+	void (*update_perfmon_mgcg)(struct amdgpu_device *adev, bool enable);
 };
 
 struct sq_work {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index e527be22a3d5..7e3ae68f4ad8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4156,6 +4156,21 @@ static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
        nv_grbm_select(adev, me, pipe, q, vm);
  }
 
+static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev,
+					  bool enable)
+{
+	uint32_t data, def;
+
+	data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL);
+
+	if (enable)
+		data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
+	else
+		data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
+
+	if (data != def)
+		WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data);
+}
 
 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
 	.get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
@@ -4165,6 +4180,7 @@ static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
 	.read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
 	.select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
 	.init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
+	.update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg,
 };
 
 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
-- 
2.28.0

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[PATCH 4/4] drm/amdgpu: fulfill Navi gfx and pcie settings on umd pstate switching(V2)

[Evan Quan]

Fulfill Navi gfx and pcie settings on umd pstate switching.

V2: temporarily skip the pcie ASPM setting considering the ASPM function
    is not fully enabled yet

Change-Id: I8d746d4c25f890665feeffddf64164ed2b1f5ccc
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/nv.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index d07c84a7543d..36e59c735a05 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -694,6 +694,23 @@ static void nv_init_doorbell_index(struct amdgpu_device *adev)
 static int nv_update_umd_stable_pstate(struct amdgpu_device *adev,
 				       bool enter)
 {
+	if (enter)
+		amdgpu_gfx_rlc_enter_safe_mode(adev);
+	else
+		amdgpu_gfx_rlc_exit_safe_mode(adev);
+
+	if (adev->gfx.funcs->update_perfmon_mgcg)
+		adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);
+
+	/*
+	 * The ASPM function is not fully enabled and verified on
+	 * Navi yet. Temporarily skip this until ASPM enabled.
+	 */
+#if 0
+	if (adev->nbio.funcs->enable_aspm)
+		adev->nbio.funcs->enable_aspm(adev, !enter);
+#endif
+
 	return 0;
 }
 
-- 
2.28.0

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Re: [PATCH 4/4] drm/amdgpu: fulfill Navi gfx and pcie settings on umd pstate switching(V2)

[Nirmoy]

Series is Acked-by: Nirmoy Das <nirmoy.das@amd.com>

On 8/19/20 11:58 AM, Evan Quan wrote:
> Fulfill Navi gfx and pcie settings on umd pstate switching.
>
> V2: temporarily skip the pcie ASPM setting considering the ASPM function
>      is not fully enabled yet
>
> Change-Id: I8d746d4c25f890665feeffddf64164ed2b1f5ccc
> Signed-off-by: Evan Quan <evan.quan@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/nv.c | 17 +++++++++++++++++
>   1 file changed, 17 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
> index d07c84a7543d..36e59c735a05 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
> @@ -694,6 +694,23 @@ static void nv_init_doorbell_index(struct amdgpu_device *adev)
>   static int nv_update_umd_stable_pstate(struct amdgpu_device *adev,
>   				       bool enter)
>   {
> +	if (enter)
> +		amdgpu_gfx_rlc_enter_safe_mode(adev);
> +	else
> +		amdgpu_gfx_rlc_exit_safe_mode(adev);
> +
> +	if (adev->gfx.funcs->update_perfmon_mgcg)
> +		adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);
> +
> +	/*
> +	 * The ASPM function is not fully enabled and verified on
> +	 * Navi yet. Temporarily skip this until ASPM enabled.
> +	 */
> +#if 0
> +	if (adev->nbio.funcs->enable_aspm)
> +		adev->nbio.funcs->enable_aspm(adev, !enter);
> +#endif
> +
>   	return 0;
>   }
>   
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Re: [PATCH 1/4] drm/amd/pm: correct gfx and pcie settings on umd pstate switching

[Alex Deucher]

On Wed, Aug 19, 2020 at 5:58 AM Evan Quan <evan.quan@amd.com> wrote:
>
> For entering UMD stable Pstate, the operations to enter rlc_safe
> mode, disable mgcg_perfmon and disable PCIE aspm are needed. And
> the opposite operations should be performed on UMD stable Pstate
> exiting.
>
> Change-Id: Iff4aa465fd16f55a4f4de8ee0503997b204f8f9d
> Signed-off-by: Evan Quan <evan.quan@amd.com>

Might want to add stub callbacks for si.c, cik.c, vi.c as well to
avoid unwanted crashes if this ends up getting used elsewhere.

Alex

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h       | 3 +++
>  drivers/gpu/drm/amd/amdgpu/nv.c           | 7 +++++++
>  drivers/gpu/drm/amd/amdgpu/soc15.c        | 7 +++++++
>  drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 ++
>  4 files changed, 19 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 8ba389780001..6ff4ddb09d1f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -617,6 +617,8 @@ struct amdgpu_asic_funcs {
>         uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);
>         /* device supports BACO */
>         bool (*supports_baco)(struct amdgpu_device *adev);
> +       /* enter/exit umd stable pstate */
> +       int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter);
>  };
>
>  /*
> @@ -1132,6 +1134,7 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
>  #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
>  #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
>  #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev))
> +#define amdgpu_asic_update_umd_stable_pstate(adev, enter) (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter))
>
>  #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter));
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
> index 54e941e0db60..d07c84a7543d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
> @@ -691,6 +691,12 @@ static void nv_init_doorbell_index(struct amdgpu_device *adev)
>         adev->doorbell_index.sdma_doorbell_range = 20;
>  }
>
> +static int nv_update_umd_stable_pstate(struct amdgpu_device *adev,
> +                                      bool enter)
> +{
> +       return 0;
> +}
> +
>  static const struct amdgpu_asic_funcs nv_asic_funcs =
>  {
>         .read_disabled_bios = &nv_read_disabled_bios,
> @@ -710,6 +716,7 @@ static const struct amdgpu_asic_funcs nv_asic_funcs =
>         .need_reset_on_init = &nv_need_reset_on_init,
>         .get_pcie_replay_count = &nv_get_pcie_replay_count,
>         .supports_baco = &nv_asic_supports_baco,
> +       .update_umd_stable_pstate = &nv_update_umd_stable_pstate,
>  };
>
>  static int nv_common_early_init(void *handle)
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 3cd98c144bc6..d9671db3b98d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -1029,6 +1029,12 @@ static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev)
>         return (nak_r + nak_g);
>  }
>
> +static int soc15_update_umd_stable_pstate(struct amdgpu_device *adev,
> +                                         bool enter)
> +{
> +       return 0;
> +}
> +
>  static const struct amdgpu_asic_funcs soc15_asic_funcs =
>  {
>         .read_disabled_bios = &soc15_read_disabled_bios,
> @@ -1049,6 +1055,7 @@ static const struct amdgpu_asic_funcs soc15_asic_funcs =
>         .need_reset_on_init = &soc15_need_reset_on_init,
>         .get_pcie_replay_count = &soc15_get_pcie_replay_count,
>         .supports_baco = &soc15_supports_baco,
> +       .update_umd_stable_pstate = &soc15_update_umd_stable_pstate,
>  };
>
>  static const struct amdgpu_asic_funcs vega20_asic_funcs =
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index 8eb5b92903cd..db0f1718087d 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -1442,6 +1442,7 @@ static int smu_enable_umd_pstate(void *handle,
>                                                                AMD_CG_STATE_UNGATE);
>                         smu_gfx_ulv_control(smu, false);
>                         smu_deep_sleep_control(smu, false);
> +                       amdgpu_asic_update_umd_stable_pstate(smu->adev, true);
>                 }
>         } else {
>                 /* exit umd pstate, restore level, enable gfx cg*/
> @@ -1449,6 +1450,7 @@ static int smu_enable_umd_pstate(void *handle,
>                         if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
>                                 *level = smu_dpm_ctx->saved_dpm_level;
>                         smu_dpm_ctx->enable_umd_pstate = false;
> +                       amdgpu_asic_update_umd_stable_pstate(smu->adev, false);
>                         smu_deep_sleep_control(smu, true);
>                         smu_gfx_ulv_control(smu, true);
>                         amdgpu_device_ip_set_clockgating_state(smu->adev,
> --
> 2.28.0
>
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