* [PATCH v2 0/3] mtd: spinand: gigadevice: quadIO fixes and add GD5F4GQ4xC
@ 2020-08-20 16:51 Hauke Mehrtens
2020-08-20 16:51 ` [PATCH v2 1/3] mtd: spinand: gigadevice: Only one dummy byte in QUADIO Hauke Mehrtens
` (2 more replies)
0 siblings, 3 replies; 10+ messages in thread
From: Hauke Mehrtens @ 2020-08-20 16:51 UTC (permalink / raw)
To: miquel.raynal, richard
Cc: linux-mtd, gch981213, vigneshr, wigyori, Hauke Mehrtens
This series fixes some problems I found in the code when adding support
for GD5F4GQ4xC and in the end it adds support for GD5F4GQ4xC.
Quad IO did not work for me even with all these changes, single IO works
fine. I assume that quadIO is broken in the SPI controller driver of the
Imagination Technologies pistachio chip found on the Creator Ci40
(Marduk).
Hauke Mehrtens (3):
mtd: spinand: gigadevice: Only one dummy byte in QUADIO
mtd: spinand: gigadevice: Add QE Bit
mtd: spinand: gigadevice: Add support for GD5F4GQ4xC
drivers/mtd/nand/spi/gigadevice.c | 63 +++++++++++++++++++++++++++----
1 file changed, 56 insertions(+), 7 deletions(-)
--
2.20.1
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^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 1/3] mtd: spinand: gigadevice: Only one dummy byte in QUADIO
2020-08-20 16:51 [PATCH v2 0/3] mtd: spinand: gigadevice: quadIO fixes and add GD5F4GQ4xC Hauke Mehrtens
@ 2020-08-20 16:51 ` Hauke Mehrtens
2020-09-01 5:22 ` Chuanhong Guo
2020-09-11 16:56 ` Miquel Raynal
2020-08-20 16:51 ` [PATCH v2 2/3] mtd: spinand: gigadevice: Add QE Bit Hauke Mehrtens
2020-08-20 16:51 ` [PATCH v2 3/3] mtd: spinand: gigadevice: Add support for GD5F4GQ4xC Hauke Mehrtens
2 siblings, 2 replies; 10+ messages in thread
From: Hauke Mehrtens @ 2020-08-20 16:51 UTC (permalink / raw)
To: miquel.raynal, richard
Cc: linux-mtd, gch981213, vigneshr, wigyori, Hauke Mehrtens
The datasheet only lists one dummy byte in the 0xEH operation for the
following chips:
* GD5F1GQ4xExxG
* GD5F1GQ4xFxxG
* GD5F1GQ4UAYIG
* GD5F4GQ4UAYIG
Fixes: c93c613214ac ("mtd: spinand: add support for GigaDevice GD5FxGQ4xA")
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
drivers/mtd/nand/spi/gigadevice.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/spi/gigadevice.c b/drivers/mtd/nand/spi/gigadevice.c
index d219c970042a..679d3c43e15a 100644
--- a/drivers/mtd/nand/spi/gigadevice.c
+++ b/drivers/mtd/nand/spi/gigadevice.c
@@ -21,7 +21,7 @@
#define GD5FXGQ4UXFXXG_STATUS_ECC_UNCOR_ERROR (7 << 4)
static SPINAND_OP_VARIANTS(read_cache_variants,
- SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
@@ -29,7 +29,7 @@ static SPINAND_OP_VARIANTS(read_cache_variants,
SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
static SPINAND_OP_VARIANTS(read_cache_variants_f,
- SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_X4_OP_3A(0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_X2_OP_3A(0, 1, NULL, 0),
--
2.20.1
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^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 2/3] mtd: spinand: gigadevice: Add QE Bit
2020-08-20 16:51 [PATCH v2 0/3] mtd: spinand: gigadevice: quadIO fixes and add GD5F4GQ4xC Hauke Mehrtens
2020-08-20 16:51 ` [PATCH v2 1/3] mtd: spinand: gigadevice: Only one dummy byte in QUADIO Hauke Mehrtens
@ 2020-08-20 16:51 ` Hauke Mehrtens
2020-09-01 5:23 ` Chuanhong Guo
2020-09-11 16:56 ` Miquel Raynal
2020-08-20 16:51 ` [PATCH v2 3/3] mtd: spinand: gigadevice: Add support for GD5F4GQ4xC Hauke Mehrtens
2 siblings, 2 replies; 10+ messages in thread
From: Hauke Mehrtens @ 2020-08-20 16:51 UTC (permalink / raw)
To: miquel.raynal, richard
Cc: linux-mtd, gch981213, vigneshr, wigyori, Hauke Mehrtens
The following GigaDevice chips have the QE BIT in the feature flags, I
checked the datasheets, but did not try this.
* GD5F1GQ4xExxG
* GD5F1GQ4xFxxG
* GD5F1GQ4UAYIG
* GD5F4GQ4UAYIG
The Quad operations like 0xEB mention that the QE bit has to be set.
Fixes: c93c613214ac ("mtd: spinand: add support for GigaDevice GD5FxGQ4xA")
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
drivers/mtd/nand/spi/gigadevice.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/mtd/nand/spi/gigadevice.c b/drivers/mtd/nand/spi/gigadevice.c
index 679d3c43e15a..0b7667e60780 100644
--- a/drivers/mtd/nand/spi/gigadevice.c
+++ b/drivers/mtd/nand/spi/gigadevice.c
@@ -202,7 +202,7 @@ static const struct spinand_info gigadevice_spinand_table[] = {
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
- 0,
+ SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
gd5fxgq4xa_ecc_get_status)),
SPINAND_INFO("GD5F2GQ4xA",
@@ -212,7 +212,7 @@ static const struct spinand_info gigadevice_spinand_table[] = {
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
- 0,
+ SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
gd5fxgq4xa_ecc_get_status)),
SPINAND_INFO("GD5F4GQ4xA",
@@ -222,7 +222,7 @@ static const struct spinand_info gigadevice_spinand_table[] = {
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
- 0,
+ SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
gd5fxgq4xa_ecc_get_status)),
SPINAND_INFO("GD5F1GQ4UExxG",
@@ -232,7 +232,7 @@ static const struct spinand_info gigadevice_spinand_table[] = {
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
- 0,
+ SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout,
gd5fxgq4uexxg_ecc_get_status)),
SPINAND_INFO("GD5F1GQ4UFxxG",
@@ -242,7 +242,7 @@ static const struct spinand_info gigadevice_spinand_table[] = {
SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f,
&write_cache_variants,
&update_cache_variants),
- 0,
+ SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout,
gd5fxgq4ufxxg_ecc_get_status)),
};
--
2.20.1
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http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 3/3] mtd: spinand: gigadevice: Add support for GD5F4GQ4xC
2020-08-20 16:51 [PATCH v2 0/3] mtd: spinand: gigadevice: quadIO fixes and add GD5F4GQ4xC Hauke Mehrtens
2020-08-20 16:51 ` [PATCH v2 1/3] mtd: spinand: gigadevice: Only one dummy byte in QUADIO Hauke Mehrtens
2020-08-20 16:51 ` [PATCH v2 2/3] mtd: spinand: gigadevice: Add QE Bit Hauke Mehrtens
@ 2020-08-20 16:51 ` Hauke Mehrtens
2020-09-11 16:56 ` Miquel Raynal
2 siblings, 1 reply; 10+ messages in thread
From: Hauke Mehrtens @ 2020-08-20 16:51 UTC (permalink / raw)
To: miquel.raynal, richard
Cc: linux-mtd, gch981213, vigneshr, wigyori, Hauke Mehrtens
This adds support for the following 4GiB chips:
GD5F4GQ4RCYIG 1.8V
GD5F4GQ4UCYIG 3.3V
The datasheet can be found here:
https://www.novitronic.ch/sixcms/media.php/2/DS-00173-GD5F4GQ4xCxIG-Rev1.574695.pdf
The GD5F4GQ4UCYIGT (3.3V) version is used on the Imagination
Technologies Creator Ci40 (Marduk), the 1.8V version was not tested.
This device only works in single SPI mode and not in dual or quad mode
for me on this board.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
drivers/mtd/nand/spi/gigadevice.c | 49 +++++++++++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/drivers/mtd/nand/spi/gigadevice.c b/drivers/mtd/nand/spi/gigadevice.c
index 0b7667e60780..33c67403c4aa 100644
--- a/drivers/mtd/nand/spi/gigadevice.c
+++ b/drivers/mtd/nand/spi/gigadevice.c
@@ -132,6 +132,35 @@ static const struct mtd_ooblayout_ops gd5fxgq4_variant2_ooblayout = {
.free = gd5fxgq4_variant2_ooblayout_free,
};
+static int gd5fxgq4xc_ooblayout_256_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobregion)
+{
+ if (section)
+ return -ERANGE;
+
+ oobregion->offset = 128;
+ oobregion->length = 128;
+
+ return 0;
+}
+
+static int gd5fxgq4xc_ooblayout_256_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobregion)
+{
+ if (section)
+ return -ERANGE;
+
+ oobregion->offset = 1;
+ oobregion->length = 127;
+
+ return 0;
+}
+
+static const struct mtd_ooblayout_ops gd5fxgq4xc_oob_256_ops = {
+ .ecc = gd5fxgq4xc_ooblayout_256_ecc,
+ .free = gd5fxgq4xc_ooblayout_256_free,
+};
+
static int gd5fxgq4uexxg_ecc_get_status(struct spinand_device *spinand,
u8 status)
{
@@ -225,6 +254,26 @@ static const struct spinand_info gigadevice_spinand_table[] = {
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
gd5fxgq4xa_ecc_get_status)),
+ SPINAND_INFO("GD5F4GQ4RC",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xa4, 0x68),
+ NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgq4xc_oob_256_ops,
+ gd5fxgq4ufxxg_ecc_get_status)),
+ SPINAND_INFO("GD5F4GQ4UC",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xb4, 0x68),
+ NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgq4xc_oob_256_ops,
+ gd5fxgq4ufxxg_ecc_get_status)),
SPINAND_INFO("GD5F1GQ4UExxG",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xd1),
NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
--
2.20.1
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http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v2 1/3] mtd: spinand: gigadevice: Only one dummy byte in QUADIO
2020-08-20 16:51 ` [PATCH v2 1/3] mtd: spinand: gigadevice: Only one dummy byte in QUADIO Hauke Mehrtens
@ 2020-09-01 5:22 ` Chuanhong Guo
2020-09-01 17:34 ` Hauke Mehrtens
2020-09-11 16:56 ` Miquel Raynal
1 sibling, 1 reply; 10+ messages in thread
From: Chuanhong Guo @ 2020-09-01 5:22 UTC (permalink / raw)
To: Hauke Mehrtens
Cc: Richard Weinberger, linux-mtd, Vignesh Raghavendra, wigyori,
Miquel Raynal
Hi!
On Fri, Aug 21, 2020 at 12:53 AM Hauke Mehrtens <hauke@hauke-m.de> wrote:
>
> The datasheet only lists one dummy byte in the 0xEH operation for the
> following chips:
> * GD5F1GQ4xExxG
> * GD5F1GQ4xFxxG
> * GD5F1GQ4UAYIG
> * GD5F4GQ4UAYIG
>
> Fixes: c93c613214ac ("mtd: spinand: add support for GigaDevice GD5FxGQ4xA")
> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
I made myself a QSPI-capable device and verified that QSPI works on
GD5F1GQ4UAYIG
after this and the QE bit patch.
Thanks for the fixes!
Tested-by: Chuanhong Guo <gch981213@gmail.com>
--
Regards,
Chuanhong Guo
______________________________________________________
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 2/3] mtd: spinand: gigadevice: Add QE Bit
2020-08-20 16:51 ` [PATCH v2 2/3] mtd: spinand: gigadevice: Add QE Bit Hauke Mehrtens
@ 2020-09-01 5:23 ` Chuanhong Guo
2020-09-11 16:56 ` Miquel Raynal
1 sibling, 0 replies; 10+ messages in thread
From: Chuanhong Guo @ 2020-09-01 5:23 UTC (permalink / raw)
To: Hauke Mehrtens
Cc: Richard Weinberger, linux-mtd, Vignesh Raghavendra, wigyori,
Miquel Raynal
On Fri, Aug 21, 2020 at 12:53 AM Hauke Mehrtens <hauke@hauke-m.de> wrote:
>
> The following GigaDevice chips have the QE BIT in the feature flags, I
> checked the datasheets, but did not try this.
> * GD5F1GQ4xExxG
> * GD5F1GQ4xFxxG
> * GD5F1GQ4UAYIG
> * GD5F4GQ4UAYIG
>
> The Quad operations like 0xEB mention that the QE bit has to be set.
>
> Fixes: c93c613214ac ("mtd: spinand: add support for GigaDevice GD5FxGQ4xA")
> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Tested-by: Chuanhong Guo <gch981213@gmail.com>
--
Regards,
Chuanhong Guo
______________________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 1/3] mtd: spinand: gigadevice: Only one dummy byte in QUADIO
2020-09-01 5:22 ` Chuanhong Guo
@ 2020-09-01 17:34 ` Hauke Mehrtens
0 siblings, 0 replies; 10+ messages in thread
From: Hauke Mehrtens @ 2020-09-01 17:34 UTC (permalink / raw)
To: Chuanhong Guo
Cc: Richard Weinberger, linux-mtd, Vignesh Raghavendra, wigyori,
Miquel Raynal
[-- Attachment #1.1.1: Type: text/plain, Size: 840 bytes --]
On 9/1/20 7:22 AM, Chuanhong Guo wrote:
> Hi!
>
> On Fri, Aug 21, 2020 at 12:53 AM Hauke Mehrtens <hauke@hauke-m.de> wrote:
>>
>> The datasheet only lists one dummy byte in the 0xEH operation for the
>> following chips:
>> * GD5F1GQ4xExxG
>> * GD5F1GQ4xFxxG
>> * GD5F1GQ4UAYIG
>> * GD5F4GQ4UAYIG
>>
>> Fixes: c93c613214ac ("mtd: spinand: add support for GigaDevice GD5FxGQ4xA")
>> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
>
> I made myself a QSPI-capable device and verified that QSPI works on
> GD5F1GQ4UAYIG
> after this and the QE bit patch.
> Thanks for the fixes!
>
> Tested-by: Chuanhong Guo <gch981213@gmail.com>
>
Thank you for testing this.
Then I am sure the QSPI mode of my SPI controller driver is broken. The
QSPI support for this controller is anyway not in Linux mainline.
Hauke
[-- Attachment #1.2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
[-- Attachment #2: Type: text/plain, Size: 144 bytes --]
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 3/3] mtd: spinand: gigadevice: Add support for GD5F4GQ4xC
2020-08-20 16:51 ` [PATCH v2 3/3] mtd: spinand: gigadevice: Add support for GD5F4GQ4xC Hauke Mehrtens
@ 2020-09-11 16:56 ` Miquel Raynal
0 siblings, 0 replies; 10+ messages in thread
From: Miquel Raynal @ 2020-09-11 16:56 UTC (permalink / raw)
To: Hauke Mehrtens, miquel.raynal, richard
Cc: gch981213, linux-mtd, vigneshr, wigyori
On Thu, 2020-08-20 at 16:51:21 UTC, Hauke Mehrtens wrote:
> This adds support for the following 4GiB chips:
> GD5F4GQ4RCYIG 1.8V
> GD5F4GQ4UCYIG 3.3V
>
> The datasheet can be found here:
> https://www.novitronic.ch/sixcms/media.php/2/DS-00173-GD5F4GQ4xCxIG-Rev1.574695.pdf
>
> The GD5F4GQ4UCYIGT (3.3V) version is used on the Imagination
> Technologies Creator Ci40 (Marduk), the 1.8V version was not tested.
>
> This device only works in single SPI mode and not in dual or quad mode
> for me on this board.
>
> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/next, thanks.
Miquel
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 2/3] mtd: spinand: gigadevice: Add QE Bit
2020-08-20 16:51 ` [PATCH v2 2/3] mtd: spinand: gigadevice: Add QE Bit Hauke Mehrtens
2020-09-01 5:23 ` Chuanhong Guo
@ 2020-09-11 16:56 ` Miquel Raynal
1 sibling, 0 replies; 10+ messages in thread
From: Miquel Raynal @ 2020-09-11 16:56 UTC (permalink / raw)
To: Hauke Mehrtens, miquel.raynal, richard
Cc: gch981213, linux-mtd, vigneshr, wigyori
On Thu, 2020-08-20 at 16:51:20 UTC, Hauke Mehrtens wrote:
> The following GigaDevice chips have the QE BIT in the feature flags, I
> checked the datasheets, but did not try this.
> * GD5F1GQ4xExxG
> * GD5F1GQ4xFxxG
> * GD5F1GQ4UAYIG
> * GD5F4GQ4UAYIG
>
> The Quad operations like 0xEB mention that the QE bit has to be set.
>
> Fixes: c93c613214ac ("mtd: spinand: add support for GigaDevice GD5FxGQ4xA")
> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
> Tested-by: Chuanhong Guo <gch981213@gmail.com>
Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/next, thanks.
Miquel
______________________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 1/3] mtd: spinand: gigadevice: Only one dummy byte in QUADIO
2020-08-20 16:51 ` [PATCH v2 1/3] mtd: spinand: gigadevice: Only one dummy byte in QUADIO Hauke Mehrtens
2020-09-01 5:22 ` Chuanhong Guo
@ 2020-09-11 16:56 ` Miquel Raynal
1 sibling, 0 replies; 10+ messages in thread
From: Miquel Raynal @ 2020-09-11 16:56 UTC (permalink / raw)
To: Hauke Mehrtens, miquel.raynal, richard
Cc: gch981213, linux-mtd, vigneshr, wigyori
On Thu, 2020-08-20 at 16:51:19 UTC, Hauke Mehrtens wrote:
> The datasheet only lists one dummy byte in the 0xEH operation for the
> following chips:
> * GD5F1GQ4xExxG
> * GD5F1GQ4xFxxG
> * GD5F1GQ4UAYIG
> * GD5F4GQ4UAYIG
>
> Fixes: c93c613214ac ("mtd: spinand: add support for GigaDevice GD5FxGQ4xA")
> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
> Tested-by: Chuanhong Guo <gch981213@gmail.com>
Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/next, thanks.
Miquel
______________________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2020-09-11 16:59 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-08-20 16:51 [PATCH v2 0/3] mtd: spinand: gigadevice: quadIO fixes and add GD5F4GQ4xC Hauke Mehrtens
2020-08-20 16:51 ` [PATCH v2 1/3] mtd: spinand: gigadevice: Only one dummy byte in QUADIO Hauke Mehrtens
2020-09-01 5:22 ` Chuanhong Guo
2020-09-01 17:34 ` Hauke Mehrtens
2020-09-11 16:56 ` Miquel Raynal
2020-08-20 16:51 ` [PATCH v2 2/3] mtd: spinand: gigadevice: Add QE Bit Hauke Mehrtens
2020-09-01 5:23 ` Chuanhong Guo
2020-09-11 16:56 ` Miquel Raynal
2020-08-20 16:51 ` [PATCH v2 3/3] mtd: spinand: gigadevice: Add support for GD5F4GQ4xC Hauke Mehrtens
2020-09-11 16:56 ` Miquel Raynal
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