[PATCH v2 0/8] Add C66x & C71x DSP nodes on J721E SoCs

[PATCH v2 0/8] Add C66x & C71x DSP nodes on J721E SoCs

[Suman Anna]

Hi Nishanth,

The following is a revised version of the series [1] that adds the base
dt nodes for the 2 C66x and 1 C71x DSP remote processors present in MAIN
domain on J721E SoCs, and the required nodes to boot these successfully
on J721E EVM board. It addresses the cleanup comments from you.

The patches are based on top of the pending ABI 3.0 pull-request [2] and
I have used your temporary staging branch [3] as the baseline.

Main changes in v2:
- Patch 1 is new, and moves all the mailbox dts nodes from the common
  board dts file to the k3-j721e-som-p0.dtsi file
- Patches 3 & 6 are reworked to add the mboxes properties directly
  in the k3-j721e-som-p0.dtsi file
- Patches 4 & 8 are rebased versions to sit on top of the modified
  mailbox addition patches
- Patches 2, 5 and 8 are unchanged

regards
Suman

[1] https://patchwork.kernel.org/cover/11725347/
[2] https://lore.kernel.org/patchwork/patch/1295019/
[3] https://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux.git/log/?h=ti-k3-dts-stage

Suman Anna (8):
  arm64: dts: ti: k3-j721e-som-p0: Move mailbox nodes from board dts
    file
  arm64: dts: ti: k3-j721e-main: Add C66x DSP nodes
  arm64: dts: ti: k3-j721e-som-p0: Add mailboxes to C66x DSPs
  arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for C66
    DSPs
  arm64: dts: ti: k3-j721e-main: Add C71x DSP node
  arm64: dts: ti: k3-j721e-som-p0: Add mailboxes to C71x DSP
  arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for
    C71x DSP
  arm64: dts: ti: k3-j721e-som-p0: Reserve memory for IPC between RTOS
    cores

 .../dts/ti/k3-j721e-common-proc-board.dts     |  93 -----------
 arch/arm64/boot/dts/ti/k3-j721e-main.dtsi     |  38 +++++
 arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi   | 153 ++++++++++++++++++
 3 files changed, 191 insertions(+), 93 deletions(-)

-- 
2.28.0

[PATCH v2 0/8] Add C66x & C71x DSP nodes on J721E SoCs

[Suman Anna]

Hi Nishanth,

The following is a revised version of the series [1] that adds the base
dt nodes for the 2 C66x and 1 C71x DSP remote processors present in MAIN
domain on J721E SoCs, and the required nodes to boot these successfully
on J721E EVM board. It addresses the cleanup comments from you.

The patches are based on top of the pending ABI 3.0 pull-request [2] and
I have used your temporary staging branch [3] as the baseline.

Main changes in v2:
- Patch 1 is new, and moves all the mailbox dts nodes from the common
  board dts file to the k3-j721e-som-p0.dtsi file
- Patches 3 & 6 are reworked to add the mboxes properties directly
  in the k3-j721e-som-p0.dtsi file
- Patches 4 & 8 are rebased versions to sit on top of the modified
  mailbox addition patches
- Patches 2, 5 and 8 are unchanged

regards
Suman

[1] https://patchwork.kernel.org/cover/11725347/
[2] https://lore.kernel.org/patchwork/patch/1295019/
[3] https://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux.git/log/?h=ti-k3-dts-stage

Suman Anna (8):
  arm64: dts: ti: k3-j721e-som-p0: Move mailbox nodes from board dts
    file
  arm64: dts: ti: k3-j721e-main: Add C66x DSP nodes
  arm64: dts: ti: k3-j721e-som-p0: Add mailboxes to C66x DSPs
  arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for C66
    DSPs
  arm64: dts: ti: k3-j721e-main: Add C71x DSP node
  arm64: dts: ti: k3-j721e-som-p0: Add mailboxes to C71x DSP
  arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for
    C71x DSP
  arm64: dts: ti: k3-j721e-som-p0: Reserve memory for IPC between RTOS
    cores

 .../dts/ti/k3-j721e-common-proc-board.dts     |  93 -----------
 arch/arm64/boot/dts/ti/k3-j721e-main.dtsi     |  38 +++++
 arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi   | 153 ++++++++++++++++++
 3 files changed, 191 insertions(+), 93 deletions(-)

-- 
2.28.0


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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v2 1/8] arm64: dts: ti: k3-j721e-som-p0: Move mailbox nodes from board dts file

[Suman Anna]

The commit eb9f9173d01f ("arm64: dts: ti: k3-j721e-common-proc-board:
Add IPC sub-mailbox nodes") has added the sub-mailbox nodes used by
various remote processors and disabled the unused mailbox clusters
directly in the k3-j721e-common-proc-board dts file. Move all of these
nodes into the k3-j721e-som-p0.dtsi file instead to co-locate all the
mailboxes and the soon to be added DDR reserved-memory carveout nodes
used by remoteprocs within the same dtsi file.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
v2: new cleanup patch relocating the existing mailbox nodes

 .../dts/ti/k3-j721e-common-proc-board.dts     | 93 -------------------
 arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi   | 93 +++++++++++++++++++
 2 files changed, 93 insertions(+), 93 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index e8fc01d97ada..c355692796a9 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -286,99 +286,6 @@ &wkup_gpio1 {
 	status = "disabled";
 };
 
-&mailbox0_cluster0 {
-	interrupts = <436>;
-
-	mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
-		ti,mbox-rx = <0 0 0>;
-		ti,mbox-tx = <1 0 0>;
-	};
-
-	mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
-		ti,mbox-rx = <2 0 0>;
-		ti,mbox-tx = <3 0 0>;
-	};
-};
-
-&mailbox0_cluster1 {
-	interrupts = <432>;
-
-	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
-		ti,mbox-rx = <0 0 0>;
-		ti,mbox-tx = <1 0 0>;
-	};
-
-	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
-		ti,mbox-rx = <2 0 0>;
-		ti,mbox-tx = <3 0 0>;
-	};
-};
-
-&mailbox0_cluster2 {
-	interrupts = <428>;
-
-	mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
-		ti,mbox-rx = <0 0 0>;
-		ti,mbox-tx = <1 0 0>;
-	};
-
-	mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
-		ti,mbox-rx = <2 0 0>;
-		ti,mbox-tx = <3 0 0>;
-	};
-};
-
-&mailbox0_cluster3 {
-	interrupts = <424>;
-
-	mbox_c66_0: mbox-c66-0 {
-		ti,mbox-rx = <0 0 0>;
-		ti,mbox-tx = <1 0 0>;
-	};
-
-	mbox_c66_1: mbox-c66-1 {
-		ti,mbox-rx = <2 0 0>;
-		ti,mbox-tx = <3 0 0>;
-	};
-};
-
-&mailbox0_cluster4 {
-	interrupts = <420>;
-
-	mbox_c71_0: mbox-c71-0 {
-		ti,mbox-rx = <0 0 0>;
-		ti,mbox-tx = <1 0 0>;
-	};
-};
-
-&mailbox0_cluster5 {
-	status = "disabled";
-};
-
-&mailbox0_cluster6 {
-	status = "disabled";
-};
-
-&mailbox0_cluster7 {
-	status = "disabled";
-};
-
-&mailbox0_cluster8 {
-	status = "disabled";
-};
-
-&mailbox0_cluster9 {
-	status = "disabled";
-};
-
-&mailbox0_cluster10 {
-	status = "disabled";
-};
-
-&mailbox0_cluster11 {
-	status = "disabled";
-};
-
 &main_sdhci0 {
 	/* eMMC */
 	non-removable;
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
index 8fa3361e5e45..44a7e03b60d8 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
@@ -72,3 +72,96 @@ flash@0{
 		#size-cells = <1>;
 	};
 };
+
+&mailbox0_cluster0 {
+	interrupts = <436>;
+
+	mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
+		ti,mbox-rx = <0 0 0>;
+		ti,mbox-tx = <1 0 0>;
+	};
+
+	mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
+		ti,mbox-rx = <2 0 0>;
+		ti,mbox-tx = <3 0 0>;
+	};
+};
+
+&mailbox0_cluster1 {
+	interrupts = <432>;
+
+	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
+		ti,mbox-rx = <0 0 0>;
+		ti,mbox-tx = <1 0 0>;
+	};
+
+	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
+		ti,mbox-rx = <2 0 0>;
+		ti,mbox-tx = <3 0 0>;
+	};
+};
+
+&mailbox0_cluster2 {
+	interrupts = <428>;
+
+	mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
+		ti,mbox-rx = <0 0 0>;
+		ti,mbox-tx = <1 0 0>;
+	};
+
+	mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
+		ti,mbox-rx = <2 0 0>;
+		ti,mbox-tx = <3 0 0>;
+	};
+};
+
+&mailbox0_cluster3 {
+	interrupts = <424>;
+
+	mbox_c66_0: mbox-c66-0 {
+		ti,mbox-rx = <0 0 0>;
+		ti,mbox-tx = <1 0 0>;
+	};
+
+	mbox_c66_1: mbox-c66-1 {
+		ti,mbox-rx = <2 0 0>;
+		ti,mbox-tx = <3 0 0>;
+	};
+};
+
+&mailbox0_cluster4 {
+	interrupts = <420>;
+
+	mbox_c71_0: mbox-c71-0 {
+		ti,mbox-rx = <0 0 0>;
+		ti,mbox-tx = <1 0 0>;
+	};
+};
+
+&mailbox0_cluster5 {
+	status = "disabled";
+};
+
+&mailbox0_cluster6 {
+	status = "disabled";
+};
+
+&mailbox0_cluster7 {
+	status = "disabled";
+};
+
+&mailbox0_cluster8 {
+	status = "disabled";
+};
+
+&mailbox0_cluster9 {
+	status = "disabled";
+};
+
+&mailbox0_cluster10 {
+	status = "disabled";
+};
+
+&mailbox0_cluster11 {
+	status = "disabled";
+};
-- 
2.28.0

[PATCH v2 1/8] arm64: dts: ti: k3-j721e-som-p0: Move mailbox nodes from board dts file

[Suman Anna]

The commit eb9f9173d01f ("arm64: dts: ti: k3-j721e-common-proc-board:
Add IPC sub-mailbox nodes") has added the sub-mailbox nodes used by
various remote processors and disabled the unused mailbox clusters
directly in the k3-j721e-common-proc-board dts file. Move all of these
nodes into the k3-j721e-som-p0.dtsi file instead to co-locate all the
mailboxes and the soon to be added DDR reserved-memory carveout nodes
used by remoteprocs within the same dtsi file.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
v2: new cleanup patch relocating the existing mailbox nodes

 .../dts/ti/k3-j721e-common-proc-board.dts     | 93 -------------------
 arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi   | 93 +++++++++++++++++++
 2 files changed, 93 insertions(+), 93 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index e8fc01d97ada..c355692796a9 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -286,99 +286,6 @@ &wkup_gpio1 {
 	status = "disabled";
 };
 
-&mailbox0_cluster0 {
-	interrupts = <436>;
-
-	mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
-		ti,mbox-rx = <0 0 0>;
-		ti,mbox-tx = <1 0 0>;
-	};
-
-	mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
-		ti,mbox-rx = <2 0 0>;
-		ti,mbox-tx = <3 0 0>;
-	};
-};
-
-&mailbox0_cluster1 {
-	interrupts = <432>;
-
-	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
-		ti,mbox-rx = <0 0 0>;
-		ti,mbox-tx = <1 0 0>;
-	};
-
-	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
-		ti,mbox-rx = <2 0 0>;
-		ti,mbox-tx = <3 0 0>;
-	};
-};
-
-&mailbox0_cluster2 {
-	interrupts = <428>;
-
-	mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
-		ti,mbox-rx = <0 0 0>;
-		ti,mbox-tx = <1 0 0>;
-	};
-
-	mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
-		ti,mbox-rx = <2 0 0>;
-		ti,mbox-tx = <3 0 0>;
-	};
-};
-
-&mailbox0_cluster3 {
-	interrupts = <424>;
-
-	mbox_c66_0: mbox-c66-0 {
-		ti,mbox-rx = <0 0 0>;
-		ti,mbox-tx = <1 0 0>;
-	};
-
-	mbox_c66_1: mbox-c66-1 {
-		ti,mbox-rx = <2 0 0>;
-		ti,mbox-tx = <3 0 0>;
-	};
-};
-
-&mailbox0_cluster4 {
-	interrupts = <420>;
-
-	mbox_c71_0: mbox-c71-0 {
-		ti,mbox-rx = <0 0 0>;
-		ti,mbox-tx = <1 0 0>;
-	};
-};
-
-&mailbox0_cluster5 {
-	status = "disabled";
-};
-
-&mailbox0_cluster6 {
-	status = "disabled";
-};
-
-&mailbox0_cluster7 {
-	status = "disabled";
-};
-
-&mailbox0_cluster8 {
-	status = "disabled";
-};
-
-&mailbox0_cluster9 {
-	status = "disabled";
-};
-
-&mailbox0_cluster10 {
-	status = "disabled";
-};
-
-&mailbox0_cluster11 {
-	status = "disabled";
-};
-
 &main_sdhci0 {
 	/* eMMC */
 	non-removable;
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
index 8fa3361e5e45..44a7e03b60d8 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
@@ -72,3 +72,96 @@ flash@0{
 		#size-cells = <1>;
 	};
 };
+
+&mailbox0_cluster0 {
+	interrupts = <436>;
+
+	mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
+		ti,mbox-rx = <0 0 0>;
+		ti,mbox-tx = <1 0 0>;
+	};
+
+	mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
+		ti,mbox-rx = <2 0 0>;
+		ti,mbox-tx = <3 0 0>;
+	};
+};
+
+&mailbox0_cluster1 {
+	interrupts = <432>;
+
+	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
+		ti,mbox-rx = <0 0 0>;
+		ti,mbox-tx = <1 0 0>;
+	};
+
+	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
+		ti,mbox-rx = <2 0 0>;
+		ti,mbox-tx = <3 0 0>;
+	};
+};
+
+&mailbox0_cluster2 {
+	interrupts = <428>;
+
+	mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
+		ti,mbox-rx = <0 0 0>;
+		ti,mbox-tx = <1 0 0>;
+	};
+
+	mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
+		ti,mbox-rx = <2 0 0>;
+		ti,mbox-tx = <3 0 0>;
+	};
+};
+
+&mailbox0_cluster3 {
+	interrupts = <424>;
+
+	mbox_c66_0: mbox-c66-0 {
+		ti,mbox-rx = <0 0 0>;
+		ti,mbox-tx = <1 0 0>;
+	};
+
+	mbox_c66_1: mbox-c66-1 {
+		ti,mbox-rx = <2 0 0>;
+		ti,mbox-tx = <3 0 0>;
+	};
+};
+
+&mailbox0_cluster4 {
+	interrupts = <420>;
+
+	mbox_c71_0: mbox-c71-0 {
+		ti,mbox-rx = <0 0 0>;
+		ti,mbox-tx = <1 0 0>;
+	};
+};
+
+&mailbox0_cluster5 {
+	status = "disabled";
+};
+
+&mailbox0_cluster6 {
+	status = "disabled";
+};
+
+&mailbox0_cluster7 {
+	status = "disabled";
+};
+
+&mailbox0_cluster8 {
+	status = "disabled";
+};
+
+&mailbox0_cluster9 {
+	status = "disabled";
+};
+
+&mailbox0_cluster10 {
+	status = "disabled";
+};
+
+&mailbox0_cluster11 {
+	status = "disabled";
+};
-- 
2.28.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v2 2/8] arm64: dts: ti: k3-j721e-main: Add C66x DSP nodes

[Suman Anna]

The J721E SoCs have two TMS320C66x DSP Core Subsystems (C66x CorePacs)
in the MAIN voltage domain, each with a C66x Fixed/Floating-Point DSP
Core, and 32 KB of L1P & L1D configurable SRAMs/Cache and an additional
288 KB of L2 configurable SRAM/Cache. These subsystems do not have
an MMU but contain a Region Address Translator (RAT) sub-module for
translating 32-bit processor addresses into larger bus addresses.
The inter-processor communication between the main A72 cores and
these processors is achieved through shared memory and Mailboxes.
Add the DT nodes for these DSP processor sub-systems in the common
k3-j721e-main.dtsi file.

The following firmware names are used by default for these cores, and
can be overridden in a board dts file if desired:
    C66x_0 DSP: j7-c66_0-fw
    C66x_1 DSP: j7-c66_1-fw

Signed-off-by: Suman Anna <s-anna@ti.com>
---
v2: No changes
v1: https://patchwork.kernel.org/patch/11725349/

 arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 26 +++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index 12ceea9b3c9a..46cde2677e17 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -1326,4 +1326,30 @@ watchdog1: watchdog@2210000 {
 		assigned-clocks = <&k3_clks 253 1>;
 		assigned-clock-parents = <&k3_clks 253 5>;
 	};
+
+	c66_0: dsp@4d80800000 {
+		compatible = "ti,j721e-c66-dsp";
+		reg = <0x4d 0x80800000 0x00 0x00048000>,
+		      <0x4d 0x80e00000 0x00 0x00008000>,
+		      <0x4d 0x80f00000 0x00 0x00008000>;
+		reg-names = "l2sram", "l1pram", "l1dram";
+		ti,sci = <&dmsc>;
+		ti,sci-dev-id = <142>;
+		ti,sci-proc-ids = <0x03 0xff>;
+		resets = <&k3_reset 142 1>;
+		firmware-name = "j7-c66_0-fw";
+	};
+
+	c66_1: dsp@4d81800000 {
+		compatible = "ti,j721e-c66-dsp";
+		reg = <0x4d 0x81800000 0x00 0x00048000>,
+		      <0x4d 0x81e00000 0x00 0x00008000>,
+		      <0x4d 0x81f00000 0x00 0x00008000>;
+		reg-names = "l2sram", "l1pram", "l1dram";
+		ti,sci = <&dmsc>;
+		ti,sci-dev-id = <143>;
+		ti,sci-proc-ids = <0x04 0xff>;
+		resets = <&k3_reset 143 1>;
+		firmware-name = "j7-c66_1-fw";
+	};
 };
-- 
2.28.0

[PATCH v2 2/8] arm64: dts: ti: k3-j721e-main: Add C66x DSP nodes

[Suman Anna]

The J721E SoCs have two TMS320C66x DSP Core Subsystems (C66x CorePacs)
in the MAIN voltage domain, each with a C66x Fixed/Floating-Point DSP
Core, and 32 KB of L1P & L1D configurable SRAMs/Cache and an additional
288 KB of L2 configurable SRAM/Cache. These subsystems do not have
an MMU but contain a Region Address Translator (RAT) sub-module for
translating 32-bit processor addresses into larger bus addresses.
The inter-processor communication between the main A72 cores and
these processors is achieved through shared memory and Mailboxes.
Add the DT nodes for these DSP processor sub-systems in the common
k3-j721e-main.dtsi file.

The following firmware names are used by default for these cores, and
can be overridden in a board dts file if desired:
    C66x_0 DSP: j7-c66_0-fw
    C66x_1 DSP: j7-c66_1-fw

Signed-off-by: Suman Anna <s-anna@ti.com>
---
v2: No changes
v1: https://patchwork.kernel.org/patch/11725349/

 arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 26 +++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index 12ceea9b3c9a..46cde2677e17 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -1326,4 +1326,30 @@ watchdog1: watchdog@2210000 {
 		assigned-clocks = <&k3_clks 253 1>;
 		assigned-clock-parents = <&k3_clks 253 5>;
 	};
+
+	c66_0: dsp@4d80800000 {
+		compatible = "ti,j721e-c66-dsp";
+		reg = <0x4d 0x80800000 0x00 0x00048000>,
+		      <0x4d 0x80e00000 0x00 0x00008000>,
+		      <0x4d 0x80f00000 0x00 0x00008000>;
+		reg-names = "l2sram", "l1pram", "l1dram";
+		ti,sci = <&dmsc>;
+		ti,sci-dev-id = <142>;
+		ti,sci-proc-ids = <0x03 0xff>;
+		resets = <&k3_reset 142 1>;
+		firmware-name = "j7-c66_0-fw";
+	};
+
+	c66_1: dsp@4d81800000 {
+		compatible = "ti,j721e-c66-dsp";
+		reg = <0x4d 0x81800000 0x00 0x00048000>,
+		      <0x4d 0x81e00000 0x00 0x00008000>,
+		      <0x4d 0x81f00000 0x00 0x00008000>;
+		reg-names = "l2sram", "l1pram", "l1dram";
+		ti,sci = <&dmsc>;
+		ti,sci-dev-id = <143>;
+		ti,sci-proc-ids = <0x04 0xff>;
+		resets = <&k3_reset 143 1>;
+		firmware-name = "j7-c66_1-fw";
+	};
 };
-- 
2.28.0


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[PATCH v2 3/8] arm64: dts: ti: k3-j721e-som-p0: Add mailboxes to C66x DSPs

[Suman Anna]

Add the required 'mboxes' property to both the C66x DSP processors for the
TI J721E common processor board. The mailboxes and some shared memory are
required for running the Remote Processor Messaging (RPMsg) stack between
the host processor and each of the DSPs. The nodes are therefore added
in the common k3-j721e-som-p0.dtsi file so that all of these can be
co-located.

The chosen sub-mailboxes match the values used in the current firmware
images. This can be changed, if needed, as per the system integration
needs after making appropriate changes on the firmware side as well.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
v2:
 - Moved the additions from board dts file to k3-j721e-som-p0.dtsi
 - Revised patch title and description
v1: https://patchwork.kernel.org/patch/11725343/

 arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
index 44a7e03b60d8..20defa0530e5 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
@@ -165,3 +165,11 @@ &mailbox0_cluster10 {
 &mailbox0_cluster11 {
 	status = "disabled";
 };
+
+&c66_0 {
+	mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
+};
+
+&c66_1 {
+	mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
+};
-- 
2.28.0

[PATCH v2 3/8] arm64: dts: ti: k3-j721e-som-p0: Add mailboxes to C66x DSPs

[Suman Anna]

Add the required 'mboxes' property to both the C66x DSP processors for the
TI J721E common processor board. The mailboxes and some shared memory are
required for running the Remote Processor Messaging (RPMsg) stack between
the host processor and each of the DSPs. The nodes are therefore added
in the common k3-j721e-som-p0.dtsi file so that all of these can be
co-located.

The chosen sub-mailboxes match the values used in the current firmware
images. This can be changed, if needed, as per the system integration
needs after making appropriate changes on the firmware side as well.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
v2:
 - Moved the additions from board dts file to k3-j721e-som-p0.dtsi
 - Revised patch title and description
v1: https://patchwork.kernel.org/patch/11725343/

 arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
index 44a7e03b60d8..20defa0530e5 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
@@ -165,3 +165,11 @@ &mailbox0_cluster10 {
 &mailbox0_cluster11 {
 	status = "disabled";
 };
+
+&c66_0 {
+	mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
+};
+
+&c66_1 {
+	mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
+};
-- 
2.28.0


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[PATCH v2 4/8] arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for C66 DSPs

[Suman Anna]

Two carveout reserved memory nodes each have been added for each of the
C66x DSP remote processor devices present within the MAIN voltage domain
for the TI J721E EVM boards. These nodes are assigned to the respective
rproc device nodes as well. The first region will be used as the DMA pool
for the rproc devices, and the second region will furnish the static
carveout regions for the firmware memory.

The minimum granularity on the Cache settings on C66x DSP cores is 16 MB,
so the DMA memory regions are chosen such that they are in separate 16 MB
regions for each DSP, while reserving a total of 16 MB for each DSP and
not changing the overall DSP remoteproc carveouts.

The current carveout addresses and sizes are defined statically for each
device. The C66x DSP processors do not have an MMU, and as such require the
exact memory used by the firmwares to be set-aside. The firmware images
do not require any RSC_CARVEOUT entries in their resource tables to
allocate the memory for firmware memory segments.

The reserved memory nodes can be disabled later on if there is no use-case
defined to use the corresponding remote processor.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
v2: Rebased version, memory-region property added to existing nodes
v1: https://patchwork.kernel.org/patch/11725339/

 arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 28 +++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
index 20defa0530e5..eeffaf9bf471 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
@@ -25,6 +25,30 @@ secure_ddr: optee@9e800000 {
 			alignment = <0x1000>;
 			no-map;
 		};
+
+		c66_1_dma_memory_region: c66-dma-memory@a6000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa6000000 0x00 0x100000>;
+			no-map;
+		};
+
+		c66_0_memory_region: c66-memory@a6100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa6100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		c66_0_dma_memory_region: c66-dma-memory@a7000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa7000000 0x00 0x100000>;
+			no-map;
+		};
+
+		c66_1_memory_region: c66-memory@a7100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa7100000 0x00 0xf00000>;
+			no-map;
+		};
 	};
 };
 
@@ -168,8 +192,12 @@ &mailbox0_cluster11 {
 
 &c66_0 {
 	mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
+	memory-region = <&c66_0_dma_memory_region>,
+			<&c66_0_memory_region>;
 };
 
 &c66_1 {
 	mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
+	memory-region = <&c66_1_dma_memory_region>,
+			<&c66_1_memory_region>;
 };
-- 
2.28.0

[PATCH v2 4/8] arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for C66 DSPs

[Suman Anna]

Two carveout reserved memory nodes each have been added for each of the
C66x DSP remote processor devices present within the MAIN voltage domain
for the TI J721E EVM boards. These nodes are assigned to the respective
rproc device nodes as well. The first region will be used as the DMA pool
for the rproc devices, and the second region will furnish the static
carveout regions for the firmware memory.

The minimum granularity on the Cache settings on C66x DSP cores is 16 MB,
so the DMA memory regions are chosen such that they are in separate 16 MB
regions for each DSP, while reserving a total of 16 MB for each DSP and
not changing the overall DSP remoteproc carveouts.

The current carveout addresses and sizes are defined statically for each
device. The C66x DSP processors do not have an MMU, and as such require the
exact memory used by the firmwares to be set-aside. The firmware images
do not require any RSC_CARVEOUT entries in their resource tables to
allocate the memory for firmware memory segments.

The reserved memory nodes can be disabled later on if there is no use-case
defined to use the corresponding remote processor.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
v2: Rebased version, memory-region property added to existing nodes
v1: https://patchwork.kernel.org/patch/11725339/

 arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 28 +++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
index 20defa0530e5..eeffaf9bf471 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
@@ -25,6 +25,30 @@ secure_ddr: optee@9e800000 {
 			alignment = <0x1000>;
 			no-map;
 		};
+
+		c66_1_dma_memory_region: c66-dma-memory@a6000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa6000000 0x00 0x100000>;
+			no-map;
+		};
+
+		c66_0_memory_region: c66-memory@a6100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa6100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		c66_0_dma_memory_region: c66-dma-memory@a7000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa7000000 0x00 0x100000>;
+			no-map;
+		};
+
+		c66_1_memory_region: c66-memory@a7100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa7100000 0x00 0xf00000>;
+			no-map;
+		};
 	};
 };
 
@@ -168,8 +192,12 @@ &mailbox0_cluster11 {
 
 &c66_0 {
 	mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
+	memory-region = <&c66_0_dma_memory_region>,
+			<&c66_0_memory_region>;
 };
 
 &c66_1 {
 	mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
+	memory-region = <&c66_1_dma_memory_region>,
+			<&c66_1_memory_region>;
 };
-- 
2.28.0


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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v2 5/8] arm64: dts: ti: k3-j721e-main: Add C71x DSP node

[Suman Anna]

The J721E SoCs have a single TMS320C71x DSP Subsystem in the MAIN
voltage domain containing the next-generation C711 CPU core. The
subsystem has 32 KB of L1D configurable SRAM/Cache and 512 KB of
L2 configurable SRAM/Cache. This subsystem has a CMMU but is not
used currently. The inter-processor communication between the main
A72 cores and the C711 processor is achieved through shared memory
and a Mailbox. Add the DT node for this DSP processor sub-system
in the common k3-j721e-main.dtsi file.

The following firmware name is used by default for the C71x core,
and can be overridden in a board dts file if desired:
    C71x_0 DSP: j7-c71_0-fw

Signed-off-by: Suman Anna <s-anna@ti.com>
---
v2: No changes
v1: https://patchwork.kernel.org/patch/11725335/

 arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index 46cde2677e17..4ba5d356655a 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -1352,4 +1352,16 @@ c66_1: dsp@4d81800000 {
 		resets = <&k3_reset 143 1>;
 		firmware-name = "j7-c66_1-fw";
 	};
+
+	c71_0: dsp@64800000 {
+		compatible = "ti,j721e-c71-dsp";
+		reg = <0x00 0x64800000 0x00 0x00080000>,
+		      <0x00 0x64e00000 0x00 0x0000c000>;
+		reg-names = "l2sram", "l1dram";
+		ti,sci = <&dmsc>;
+		ti,sci-dev-id = <15>;
+		ti,sci-proc-ids = <0x30 0xff>;
+		resets = <&k3_reset 15 1>;
+		firmware-name = "j7-c71_0-fw";
+	};
 };
-- 
2.28.0

[PATCH v2 5/8] arm64: dts: ti: k3-j721e-main: Add C71x DSP node

[Suman Anna]

The J721E SoCs have a single TMS320C71x DSP Subsystem in the MAIN
voltage domain containing the next-generation C711 CPU core. The
subsystem has 32 KB of L1D configurable SRAM/Cache and 512 KB of
L2 configurable SRAM/Cache. This subsystem has a CMMU but is not
used currently. The inter-processor communication between the main
A72 cores and the C711 processor is achieved through shared memory
and a Mailbox. Add the DT node for this DSP processor sub-system
in the common k3-j721e-main.dtsi file.

The following firmware name is used by default for the C71x core,
and can be overridden in a board dts file if desired:
    C71x_0 DSP: j7-c71_0-fw

Signed-off-by: Suman Anna <s-anna@ti.com>
---
v2: No changes
v1: https://patchwork.kernel.org/patch/11725335/

 arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index 46cde2677e17..4ba5d356655a 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -1352,4 +1352,16 @@ c66_1: dsp@4d81800000 {
 		resets = <&k3_reset 143 1>;
 		firmware-name = "j7-c66_1-fw";
 	};
+
+	c71_0: dsp@64800000 {
+		compatible = "ti,j721e-c71-dsp";
+		reg = <0x00 0x64800000 0x00 0x00080000>,
+		      <0x00 0x64e00000 0x00 0x0000c000>;
+		reg-names = "l2sram", "l1dram";
+		ti,sci = <&dmsc>;
+		ti,sci-dev-id = <15>;
+		ti,sci-proc-ids = <0x30 0xff>;
+		resets = <&k3_reset 15 1>;
+		firmware-name = "j7-c71_0-fw";
+	};
 };
-- 
2.28.0


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[PATCH v2 6/8] arm64: dts: ti: k3-j721e-som-p0: Add mailboxes to C71x DSP

[Suman Anna]

Add the required 'mboxes' property to the C71x DSP processor for the TI
J721E common processor board. The mailboxes and some shared memory are
required for running the Remote Processor Messaging (RPMsg) stack between
the host processor and each of the DSPs. The nodes are therefore added
in the common k3-j721e-som-p0.dtsi file so that all of these can be
co-located.

The chosen sub-mailboxes match the values used in the current firmware
images. This can be changed, if needed, as per the system integration
needs after making appropriate changes on the firmware side as well.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
v2:
 - Moved the addition from board dts file to k3-j721e-som-p0.dtsi
 - Revised patch title and description
v1: https://patchwork.kernel.org/patch/11725345/

 arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
index eeffaf9bf471..bb37651a0014 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
@@ -201,3 +201,7 @@ &c66_1 {
 	memory-region = <&c66_1_dma_memory_region>,
 			<&c66_1_memory_region>;
 };
+
+&c71_0 {
+	mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
+};
-- 
2.28.0

[PATCH v2 6/8] arm64: dts: ti: k3-j721e-som-p0: Add mailboxes to C71x DSP

[Suman Anna]

Add the required 'mboxes' property to the C71x DSP processor for the TI
J721E common processor board. The mailboxes and some shared memory are
required for running the Remote Processor Messaging (RPMsg) stack between
the host processor and each of the DSPs. The nodes are therefore added
in the common k3-j721e-som-p0.dtsi file so that all of these can be
co-located.

The chosen sub-mailboxes match the values used in the current firmware
images. This can be changed, if needed, as per the system integration
needs after making appropriate changes on the firmware side as well.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
v2:
 - Moved the addition from board dts file to k3-j721e-som-p0.dtsi
 - Revised patch title and description
v1: https://patchwork.kernel.org/patch/11725345/

 arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
index eeffaf9bf471..bb37651a0014 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
@@ -201,3 +201,7 @@ &c66_1 {
 	memory-region = <&c66_1_dma_memory_region>,
 			<&c66_1_memory_region>;
 };
+
+&c71_0 {
+	mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
+};
-- 
2.28.0


_______________________________________________
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[PATCH v2 7/8] arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for C71x DSP

[Suman Anna]

Two carveout reserved memory nodes have been added for the lone C71x DSP
remote processor device present within the MAIN voltage domain for the TI
J721E EVM boards. These nodes are assigned to the respective rproc device
node as well. The first region will be used as the DMA pool for the rproc
device, and the second region will furnish the static carveout regions for
the firmware memory.

The current carveout addresses and sizes are defined statically for each
device. The C71x DSP processor does support a MMU called CMMU, but is not
currently supported and as such requires the exact memory used by the
firmware to be set-aside. The firmware images currently do not need any
RSC_CARVEOUT entries either in their resource tables to allocate the
memory for firmware memory segments.

The reserved memory nodes can be disabled later on if there is no use-case
defined to use the C71x DSP remoteproc processor.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
v2: Rebased version, memory-region property added to existing nodes
v1: https://patchwork.kernel.org/patch/11725337/

 arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
index bb37651a0014..0e28be492ac2 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
@@ -49,6 +49,18 @@ c66_1_memory_region: c66-memory@a7100000 {
 			reg = <0x00 0xa7100000 0x00 0xf00000>;
 			no-map;
 		};
+
+		c71_0_dma_memory_region: c71-dma-memory@a8000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa8000000 0x00 0x100000>;
+			no-map;
+		};
+
+		c71_0_memory_region: c71-memory@a8100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa8100000 0x00 0xf00000>;
+			no-map;
+		};
 	};
 };
 
@@ -204,4 +216,6 @@ &c66_1 {
 
 &c71_0 {
 	mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
+	memory-region = <&c71_0_dma_memory_region>,
+			<&c71_0_memory_region>;
 };
-- 
2.28.0

[PATCH v2 7/8] arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for C71x DSP

[Suman Anna]

Two carveout reserved memory nodes have been added for the lone C71x DSP
remote processor device present within the MAIN voltage domain for the TI
J721E EVM boards. These nodes are assigned to the respective rproc device
node as well. The first region will be used as the DMA pool for the rproc
device, and the second region will furnish the static carveout regions for
the firmware memory.

The current carveout addresses and sizes are defined statically for each
device. The C71x DSP processor does support a MMU called CMMU, but is not
currently supported and as such requires the exact memory used by the
firmware to be set-aside. The firmware images currently do not need any
RSC_CARVEOUT entries either in their resource tables to allocate the
memory for firmware memory segments.

The reserved memory nodes can be disabled later on if there is no use-case
defined to use the C71x DSP remoteproc processor.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
v2: Rebased version, memory-region property added to existing nodes
v1: https://patchwork.kernel.org/patch/11725337/

 arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
index bb37651a0014..0e28be492ac2 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
@@ -49,6 +49,18 @@ c66_1_memory_region: c66-memory@a7100000 {
 			reg = <0x00 0xa7100000 0x00 0xf00000>;
 			no-map;
 		};
+
+		c71_0_dma_memory_region: c71-dma-memory@a8000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa8000000 0x00 0x100000>;
+			no-map;
+		};
+
+		c71_0_memory_region: c71-memory@a8100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa8100000 0x00 0xf00000>;
+			no-map;
+		};
 	};
 };
 
@@ -204,4 +216,6 @@ &c66_1 {
 
 &c71_0 {
 	mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
+	memory-region = <&c71_0_dma_memory_region>,
+			<&c71_0_memory_region>;
 };
-- 
2.28.0


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[PATCH v2 8/8] arm64: dts: ti: k3-j721e-som-p0: Reserve memory for IPC between RTOS cores

[Suman Anna]

Add a reserved memory node to reserve a portion of the DDR memory to be
used for performing inter-processor communication between all the remote
processors running RTOS on the TI J721E EVM boards. 28 MB of memory is
reserved for this purpose, and this accounts for all the vrings and vring
buffers between all the possible pairs of remote processors.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
v2: No changes
v1: https://patchwork.kernel.org/patch/11725341/

 arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
index 0e28be492ac2..d69d90c8b5e3 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
@@ -61,6 +61,12 @@ c71_0_memory_region: c71-memory@a8100000 {
 			reg = <0x00 0xa8100000 0x00 0xf00000>;
 			no-map;
 		};
+
+		rtos_ipc_memory_region: ipc-memories@aa000000 {
+			reg = <0x00 0xaa000000 0x00 0x01c00000>;
+			alignment = <0x1000>;
+			no-map;
+		};
 	};
 };
 
-- 
2.28.0

[PATCH v2 8/8] arm64: dts: ti: k3-j721e-som-p0: Reserve memory for IPC between RTOS cores

[Suman Anna]

Add a reserved memory node to reserve a portion of the DDR memory to be
used for performing inter-processor communication between all the remote
processors running RTOS on the TI J721E EVM boards. 28 MB of memory is
reserved for this purpose, and this accounts for all the vrings and vring
buffers between all the possible pairs of remote processors.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
v2: No changes
v1: https://patchwork.kernel.org/patch/11725341/

 arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
index 0e28be492ac2..d69d90c8b5e3 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
@@ -61,6 +61,12 @@ c71_0_memory_region: c71-memory@a8100000 {
 			reg = <0x00 0xa8100000 0x00 0xf00000>;
 			no-map;
 		};
+
+		rtos_ipc_memory_region: ipc-memories@aa000000 {
+			reg = <0x00 0xaa000000 0x00 0x01c00000>;
+			alignment = <0x1000>;
+			no-map;
+		};
 	};
 };
 
-- 
2.28.0


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Re: [PATCH v2 0/8] Add C66x & C71x DSP nodes on J721E SoCs

[Lokesh Vutla]

On 25/08/20 10:51 pm, Suman Anna wrote:
> Hi Nishanth,
> 
> The following is a revised version of the series [1] that adds the base
> dt nodes for the 2 C66x and 1 C71x DSP remote processors present in MAIN
> domain on J721E SoCs, and the required nodes to boot these successfully
> on J721E EVM board. It addresses the cleanup comments from you.
> 
> The patches are based on top of the pending ABI 3.0 pull-request [2] and
> I have used your temporary staging branch [3] as the baseline.
> 
> Main changes in v2:
> - Patch 1 is new, and moves all the mailbox dts nodes from the common
>   board dts file to the k3-j721e-som-p0.dtsi file
> - Patches 3 & 6 are reworked to add the mboxes properties directly
>   in the k3-j721e-som-p0.dtsi file
> - Patches 4 & 8 are rebased versions to sit on top of the modified
>   mailbox addition patches
> - Patches 2, 5 and 8 are unchanged


FWIW, Series
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>

Thanks and regards,
Lokesh

Re: [PATCH v2 0/8] Add C66x & C71x DSP nodes on J721E SoCs

[Lokesh Vutla]

On 25/08/20 10:51 pm, Suman Anna wrote:
> Hi Nishanth,
> 
> The following is a revised version of the series [1] that adds the base
> dt nodes for the 2 C66x and 1 C71x DSP remote processors present in MAIN
> domain on J721E SoCs, and the required nodes to boot these successfully
> on J721E EVM board. It addresses the cleanup comments from you.
> 
> The patches are based on top of the pending ABI 3.0 pull-request [2] and
> I have used your temporary staging branch [3] as the baseline.
> 
> Main changes in v2:
> - Patch 1 is new, and moves all the mailbox dts nodes from the common
>   board dts file to the k3-j721e-som-p0.dtsi file
> - Patches 3 & 6 are reworked to add the mboxes properties directly
>   in the k3-j721e-som-p0.dtsi file
> - Patches 4 & 8 are rebased versions to sit on top of the modified
>   mailbox addition patches
> - Patches 2, 5 and 8 are unchanged


FWIW, Series
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>

Thanks and regards,
Lokesh


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Re: [PATCH v2 0/8] Add C66x & C71x DSP nodes on J721E SoCs

[Nishanth Menon]

On 10:28-20200827, Lokesh Vutla wrote:
> 
> 
> On 25/08/20 10:51 pm, Suman Anna wrote:
> > Hi Nishanth,
> > 
> > The following is a revised version of the series [1] that adds the base
> > dt nodes for the 2 C66x and 1 C71x DSP remote processors present in MAIN
> > domain on J721E SoCs, and the required nodes to boot these successfully
> > on J721E EVM board. It addresses the cleanup comments from you.
> > 
[..]
> 
> FWIW, Series
> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>

Thanks. I have applied this series to my staging branch for now. Once
rc3 makes in with the irq chip changes, I will rebase and push to
next.

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

Re: [PATCH v2 0/8] Add C66x & C71x DSP nodes on J721E SoCs

[Nishanth Menon]

On 10:28-20200827, Lokesh Vutla wrote:
> 
> 
> On 25/08/20 10:51 pm, Suman Anna wrote:
> > Hi Nishanth,
> > 
> > The following is a revised version of the series [1] that adds the base
> > dt nodes for the 2 C66x and 1 C71x DSP remote processors present in MAIN
> > domain on J721E SoCs, and the required nodes to boot these successfully
> > on J721E EVM board. It addresses the cleanup comments from you.
> > 
[..]
> 
> FWIW, Series
> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>

Thanks. I have applied this series to my staging branch for now. Once
rc3 makes in with the irq chip changes, I will rebase and push to
next.

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

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Re: [PATCH v2 0/8] Add C66x & C71x DSP nodes on J721E SoCs

[Nishanth Menon]

On Tue, 25 Aug 2020 12:21:37 -0500, Suman Anna wrote:
> The following is a revised version of the series [1] that adds the base
> dt nodes for the 2 C66x and 1 C71x DSP remote processors present in MAIN
> domain on J721E SoCs, and the required nodes to boot these successfully
> on J721E EVM board. It addresses the cleanup comments from you.
> 
> The patches are based on top of the pending ABI 3.0 pull-request [2] and
> I have used your temporary staging branch [3] as the baseline.
> 
> [...]

Hi Suman Anna,

I have applied the following to branch ti-k3-dts-next on [1].
Thank you!

[1/8] arm64: dts: ti: k3-j721e-som-p0: Move mailbox nodes from board dts file
      commit: 74b5742b59b19f4ae9c53ae719161928d9768879
[2/8] arm64: dts: ti: k3-j721e-main: Add C66x DSP nodes
      commit: eb9a2a637ae5b23d7881f28fb83d11c88a371229
[3/8] arm64: dts: ti: k3-j721e-som-p0: Add mailboxes to C66x DSPs
      commit: a55babbf00d71f285bbd52433a859862cc3223fb
[4/8] arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for C66 DSPs
      commit: e379ba840a7e2c8fb275722226154339077b8f37
[5/8] arm64: dts: ti: k3-j721e-main: Add C71x DSP node
      commit: 804a4cc7fe3cc7207b25c63f21ea82f1b77d19ae
[6/8] arm64: dts: ti: k3-j721e-som-p0: Add mailboxes to C71x DSP
      commit: cf53928fa0d9120d9c5336504e1c836e453f446a
[7/8] arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for C71x DSP
      commit: 1939d37f94937cf5082ee2612b76106cb3d90978
[8/8] arm64: dts: ti: k3-j721e-som-p0: Reserve memory for IPC between RTOS cores
      commit: 67cfbb62132e4210b4c4785b0ca1fbe4cafb7c4d

[1] git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux.git
-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

Re: [PATCH v2 0/8] Add C66x & C71x DSP nodes on J721E SoCs

[Nishanth Menon]

On Tue, 25 Aug 2020 12:21:37 -0500, Suman Anna wrote:
> The following is a revised version of the series [1] that adds the base
> dt nodes for the 2 C66x and 1 C71x DSP remote processors present in MAIN
> domain on J721E SoCs, and the required nodes to boot these successfully
> on J721E EVM board. It addresses the cleanup comments from you.
> 
> The patches are based on top of the pending ABI 3.0 pull-request [2] and
> I have used your temporary staging branch [3] as the baseline.
> 
> [...]

Hi Suman Anna,

I have applied the following to branch ti-k3-dts-next on [1].
Thank you!

[1/8] arm64: dts: ti: k3-j721e-som-p0: Move mailbox nodes from board dts file
      commit: 74b5742b59b19f4ae9c53ae719161928d9768879
[2/8] arm64: dts: ti: k3-j721e-main: Add C66x DSP nodes
      commit: eb9a2a637ae5b23d7881f28fb83d11c88a371229
[3/8] arm64: dts: ti: k3-j721e-som-p0: Add mailboxes to C66x DSPs
      commit: a55babbf00d71f285bbd52433a859862cc3223fb
[4/8] arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for C66 DSPs
      commit: e379ba840a7e2c8fb275722226154339077b8f37
[5/8] arm64: dts: ti: k3-j721e-main: Add C71x DSP node
      commit: 804a4cc7fe3cc7207b25c63f21ea82f1b77d19ae
[6/8] arm64: dts: ti: k3-j721e-som-p0: Add mailboxes to C71x DSP
      commit: cf53928fa0d9120d9c5336504e1c836e453f446a
[7/8] arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for C71x DSP
      commit: 1939d37f94937cf5082ee2612b76106cb3d90978
[8/8] arm64: dts: ti: k3-j721e-som-p0: Reserve memory for IPC between RTOS cores
      commit: 67cfbb62132e4210b4c4785b0ca1fbe4cafb7c4d

[1] git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux.git
-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D


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