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* [PATCH 0/3] Rename ASPEED SoC clock name
@ 2020-08-28  7:32 Ryan Chen
  2020-08-28  7:32 ` [PATCH 1/3] cosmetic: aspeed: ast2500: Rename clock header Ryan Chen
                   ` (5 more replies)
  0 siblings, 6 replies; 20+ messages in thread
From: Ryan Chen @ 2020-08-28  7:32 UTC (permalink / raw)
  To: u-boot

This patch series refactor the exiting ASPEED clock name define sync
with Linux kernel. And also add SPDX-License

Ryan Chen (3):
  cosmetic: aspeed: ast2500: Rename clock header
  aspeed:clock: Sync with Linux kernel clock header define
  cosmetic: aspeed: Modify for SPDX-License

 arch/arm/dts/ast2500-u-boot.dtsi             | 23 ++++++-----
 arch/arm/mach-aspeed/ast2500/sdram_ast2500.c |  2 +-
 drivers/clk/aspeed/clk_ast2500.c             | 40 +++++++++----------
 include/dt-bindings/clock/aspeed-clock.h     | 42 ++++++++++++++++++++
 include/dt-bindings/clock/ast2500-scu.h      | 30 --------------
 5 files changed, 74 insertions(+), 63 deletions(-)
 create mode 100644 include/dt-bindings/clock/aspeed-clock.h
 delete mode 100644 include/dt-bindings/clock/ast2500-scu.h

-- 
2.17.1

^ permalink raw reply	[flat|nested] 20+ messages in thread
* [PATCH 1/3] cosmetic: aspeed: ast2500: Rename clock header
  2020-08-28  7:32 [PATCH 0/3] Rename ASPEED SoC clock name Ryan Chen
@ 2020-08-28  7:32 ` Ryan Chen
  2020-08-28  7:32 ` [PATCH 1/1] Remove not used export function header Ryan Chen
                   ` (4 subsequent siblings)
  5 siblings, 0 replies; 20+ messages in thread
From: Ryan Chen @ 2020-08-28  7:32 UTC (permalink / raw)
  To: u-boot

Rename the ast2500-scu.h to aspeed-clock.h.

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
---
 arch/arm/dts/ast2500-u-boot.dtsi                            | 2 +-
 arch/arm/mach-aspeed/ast2500/sdram_ast2500.c                | 2 +-
 drivers/clk/aspeed/clk_ast2500.c                            | 2 +-
 include/dt-bindings/clock/{ast2500-scu.h => aspeed-clock.h} | 0
 4 files changed, 3 insertions(+), 3 deletions(-)
 rename include/dt-bindings/clock/{ast2500-scu.h => aspeed-clock.h} (100%)

diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi
index 8ac4215745..3b119e4ace 100644
--- a/arch/arm/dts/ast2500-u-boot.dtsi
+++ b/arch/arm/dts/ast2500-u-boot.dtsi
@@ -1,4 +1,4 @@
-#include <dt-bindings/clock/ast2500-scu.h>
+#include <dt-bindings/clock/aspeed-clock.h>
 #include <dt-bindings/reset/ast2500-reset.h>
 
 #include "ast2500.dtsi"
diff --git a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
index a3adaa8a99..8536a70a19 100644
--- a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
+++ b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
@@ -19,7 +19,7 @@
 #include <asm/arch/wdt.h>
 #include <linux/err.h>
 #include <linux/kernel.h>
-#include <dt-bindings/clock/ast2500-scu.h>
+#include <dt-bindings/clock/aspeed-clock.h>
 
 /* These configuration parameters are taken from Aspeed SDK */
 #define DDR4_MR46_MODE		0x08000000
diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index d1940f1884..392fe76b27 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c
@@ -10,7 +10,7 @@
 #include <asm/io.h>
 #include <asm/arch/scu_ast2500.h>
 #include <dm/lists.h>
-#include <dt-bindings/clock/ast2500-scu.h>
+#include <dt-bindings/clock/aspeed-clock.h>
 #include <linux/delay.h>
 #include <linux/err.h>
 
diff --git a/include/dt-bindings/clock/ast2500-scu.h b/include/dt-bindings/clock/aspeed-clock.h
similarity index 100%
rename from include/dt-bindings/clock/ast2500-scu.h
rename to include/dt-bindings/clock/aspeed-clock.h
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 20+ messages in thread
* [PATCH 1/1] Remove not used export function header.
  2020-08-28  7:32 [PATCH 0/3] Rename ASPEED SoC clock name Ryan Chen
  2020-08-28  7:32 ` [PATCH 1/3] cosmetic: aspeed: ast2500: Rename clock header Ryan Chen
@ 2020-08-28  7:32 ` Ryan Chen
  2020-08-28  7:33 ` [PATCH 2/3] aspeed:clock: Sync with Linux kernel clock header define Ryan Chen
                   ` (3 subsequent siblings)
  5 siblings, 0 replies; 20+ messages in thread
From: Ryan Chen @ 2020-08-28  7:32 UTC (permalink / raw)
  To: u-boot

All driver is use clk dm model, will not use this function call.

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
---
 arch/arm/dts/ast2500-u-boot.dtsi                            | 2 +-
 arch/arm/mach-aspeed/ast2500/sdram_ast2500.c                | 2 +-
 drivers/clk/aspeed/clk_ast2500.c                            | 2 +-
 include/dt-bindings/clock/{ast2500-scu.h => aspeed-clock.h} | 0
 4 files changed, 3 insertions(+), 3 deletions(-)
 rename include/dt-bindings/clock/{ast2500-scu.h => aspeed-clock.h} (100%)

diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi
index 8ac4215745..3b119e4ace 100644
--- a/arch/arm/dts/ast2500-u-boot.dtsi
+++ b/arch/arm/dts/ast2500-u-boot.dtsi
@@ -1,4 +1,4 @@
-#include <dt-bindings/clock/ast2500-scu.h>
+#include <dt-bindings/clock/aspeed-clock.h>
 #include <dt-bindings/reset/ast2500-reset.h>
 
 #include "ast2500.dtsi"
diff --git a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
index a3adaa8a99..8536a70a19 100644
--- a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
+++ b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
@@ -19,7 +19,7 @@
 #include <asm/arch/wdt.h>
 #include <linux/err.h>
 #include <linux/kernel.h>
-#include <dt-bindings/clock/ast2500-scu.h>
+#include <dt-bindings/clock/aspeed-clock.h>
 
 /* These configuration parameters are taken from Aspeed SDK */
 #define DDR4_MR46_MODE		0x08000000
diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index d1940f1884..392fe76b27 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c
@@ -10,7 +10,7 @@
 #include <asm/io.h>
 #include <asm/arch/scu_ast2500.h>
 #include <dm/lists.h>
-#include <dt-bindings/clock/ast2500-scu.h>
+#include <dt-bindings/clock/aspeed-clock.h>
 #include <linux/delay.h>
 #include <linux/err.h>
 
diff --git a/include/dt-bindings/clock/ast2500-scu.h b/include/dt-bindings/clock/aspeed-clock.h
similarity index 100%
rename from include/dt-bindings/clock/ast2500-scu.h
rename to include/dt-bindings/clock/aspeed-clock.h
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 20+ messages in thread
* [PATCH 2/3] aspeed:clock: Sync with Linux kernel clock header define
  2020-08-28  7:32 [PATCH 0/3] Rename ASPEED SoC clock name Ryan Chen
  2020-08-28  7:32 ` [PATCH 1/3] cosmetic: aspeed: ast2500: Rename clock header Ryan Chen
  2020-08-28  7:32 ` [PATCH 1/1] Remove not used export function header Ryan Chen
@ 2020-08-28  7:33 ` Ryan Chen
  2020-08-28  7:33 ` [PATCH 3/3] cosmetic: aspeed: Modify for SPDX-License Ryan Chen
                   ` (2 subsequent siblings)
  5 siblings, 0 replies; 20+ messages in thread
From: Ryan Chen @ 2020-08-28  7:33 UTC (permalink / raw)
  To: u-boot

Use kernel include/dt-bindings/clock/aspeed-clock.h define
for clock driver.

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
---
 arch/arm/dts/ast2500-u-boot.dtsi         | 20 +++----
 drivers/clk/aspeed/clk_ast2500.c         | 38 +++++++------
 include/dt-bindings/clock/aspeed-clock.h | 68 ++++++++++++++----------
 3 files changed, 68 insertions(+), 58 deletions(-)

diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi
index 3b119e4ace..29b08f16ac 100644
--- a/arch/arm/dts/ast2500-u-boot.dtsi
+++ b/arch/arm/dts/ast2500-u-boot.dtsi
@@ -25,7 +25,7 @@
 		reg = <0x1e6e0000 0x174
 			0x1e6e0200 0x1d4 >;
 		#reset-cells = <1>;
-		clocks = <&scu PLL_MPLL>;
+		clocks = <&scu ASPEED_CLK_MPLL>;
 		resets = <&rst AST_RESET_SDRAM>;
 	};
 
@@ -39,7 +39,7 @@
 				compatible = "aspeed,ast2500-sdhci";
 				reg = <0x1e740100>;
 				#reset-cells = <1>;
-				clocks = <&scu BCLK_SDCLK>;
+				clocks = <&scu ASPEED_CLK_SDIO>;
 				resets = <&rst AST_RESET_SDIO>;
 			};
 
@@ -47,7 +47,7 @@
 				compatible = "aspeed,ast2500-sdhci";
 				reg = <0x1e740200>;
 				#reset-cells = <1>;
-				clocks = <&scu BCLK_SDCLK>;
+				clocks = <&scu ASPEED_CLK_SDIO>;
 				resets = <&rst AST_RESET_SDIO>;
 			};
 		};
@@ -56,23 +56,23 @@
 };
 
 &uart1 {
-	clocks = <&scu PCLK_UART1>;
+	clocks = <&scu ASPEED_CLK_GATE_UART1CLK>;
 };
 
 &uart2 {
-	clocks = <&scu PCLK_UART2>;
+	clocks = <&scu ASPEED_CLK_GATE_UART2CLK>;
 };
 
 &uart3 {
-	clocks = <&scu PCLK_UART3>;
+	clocks = <&scu ASPEED_CLK_GATE_UART3CLK>;
 };
 
 &uart4 {
-	clocks = <&scu PCLK_UART4>;
+	clocks = <&scu ASPEED_CLK_GATE_UART4CLK>;
 };
 
 &uart5 {
-	clocks = <&scu PCLK_UART5>;
+	clocks = <&scu ASPEED_CLK_GATE_UART5CLK>;
 };
 
 &timer {
@@ -80,9 +80,9 @@
 };
 
 &mac0 {
-	clocks = <&scu PCLK_MAC1>, <&scu PLL_D2PLL>;
+	clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>, <&scu ASPEED_CLK_D2PLL>;
 };
 
 &mac1 {
-	clocks = <&scu PCLK_MAC2>, <&scu PLL_D2PLL>;
+	clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>, <&scu ASPEED_CLK_D2PLL>;
 };
diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index 392fe76b27..aab7d14deb 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c
@@ -122,8 +122,7 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
 	ulong rate;
 
 	switch (clk->id) {
-	case PLL_HPLL:
-	case ARMCLK:
+	case ASPEED_CLK_HPLL:
 		/*
 		 * This ignores dynamic/static slowdown of ARMCLK and may
 		 * be inaccurate.
@@ -131,11 +130,11 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
 		rate = ast2500_get_hpll_rate(clkin,
 					     readl(&priv->scu->h_pll_param));
 		break;
-	case MCLK_DDR:
+	case ASPEED_CLK_MPLL:
 		rate = ast2500_get_mpll_rate(clkin,
 					     readl(&priv->scu->m_pll_param));
 		break;
-	case BCLK_PCLK:
+	case ASPEED_CLK_APB:
 		{
 			ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1)
 						  & SCU_PCLK_DIV_MASK)
@@ -146,7 +145,7 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
 			rate = rate / apb_div;
 		}
 		break;
-	case BCLK_SDCLK:
+	case ASPEED_CLK_SDIO:
 		{
 			ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1)
 						  & SCU_SDCLK_DIV_MASK)
@@ -157,19 +156,19 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
 			rate = rate / apb_div;
 		}
 		break;
-	case PCLK_UART1:
+	case ASPEED_CLK_GATE_UART1CLK:
 		rate = ast2500_get_uart_clk_rate(priv->scu, 1);
 		break;
-	case PCLK_UART2:
+	case ASPEED_CLK_GATE_UART2CLK:
 		rate = ast2500_get_uart_clk_rate(priv->scu, 2);
 		break;
-	case PCLK_UART3:
+	case ASPEED_CLK_GATE_UART3CLK:
 		rate = ast2500_get_uart_clk_rate(priv->scu, 3);
 		break;
-	case PCLK_UART4:
+	case ASPEED_CLK_GATE_UART4CLK:
 		rate = ast2500_get_uart_clk_rate(priv->scu, 4);
 		break;
-	case PCLK_UART5:
+	case ASPEED_CLK_GATE_UART5CLK:
 		rate = ast2500_get_uart_clk_rate(priv->scu, 5);
 		break;
 	default:
@@ -431,11 +430,10 @@ static ulong ast2500_clk_set_rate(struct clk *clk, ulong rate)
 
 	ulong new_rate;
 	switch (clk->id) {
-	case PLL_MPLL:
-	case MCLK_DDR:
+	case ASPEED_CLK_MPLL:
 		new_rate = ast2500_configure_ddr(priv->scu, rate);
 		break;
-	case PLL_D2PLL:
+	case ASPEED_CLK_D2PLL:
 		new_rate = ast2500_configure_d2pll(priv->scu, rate);
 		break;
 	default:
@@ -450,7 +448,7 @@ static int ast2500_clk_enable(struct clk *clk)
 	struct ast2500_clk_priv *priv = dev_get_priv(clk->dev);
 
 	switch (clk->id) {
-	case BCLK_SDCLK:
+	case ASPEED_CLK_SDIO:
 		if (readl(&priv->scu->clk_stop_ctrl1) & SCU_CLKSTOP_SDCLK) {
 			ast_scu_unlock(priv->scu);
 
@@ -471,13 +469,13 @@ static int ast2500_clk_enable(struct clk *clk)
 	 * configured based on whether RGMII or RMII mode has been selected
 	 * through hardware strapping.
 	 */
-	case PCLK_MAC1:
+	case ASPEED_CLK_GATE_MAC1CLK:
 		ast2500_configure_mac(priv->scu, 1);
 		break;
-	case PCLK_MAC2:
+	case ASPEED_CLK_GATE_MAC2CLK:
 		ast2500_configure_mac(priv->scu, 2);
 		break;
-	case PLL_D2PLL:
+	case ASPEED_CLK_D2PLL:
 		ast2500_configure_d2pll(priv->scu, D2PLL_DEFAULT_RATE);
 		break;
 	default:
@@ -497,9 +495,9 @@ static int ast2500_clk_ofdata_to_platdata(struct udevice *dev)
 {
 	struct ast2500_clk_priv *priv = dev_get_priv(dev);
 
-	priv->scu = dev_read_addr_ptr(dev);
-	if (!priv->scu)
-		return -EINVAL;
+	priv->scu = devfdt_get_addr_ptr(dev);
+	if (IS_ERR(priv->scu))
+		return PTR_ERR(priv->scu);
 
 	return 0;
 }
diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h
index 4803abe9f6..e6599deeb9 100644
--- a/include/dt-bindings/clock/aspeed-clock.h
+++ b/include/dt-bindings/clock/aspeed-clock.h
@@ -1,30 +1,42 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2016 Google Inc.
- */
 
-/* Core Clocks */
-#define PLL_HPLL	1
-#define PLL_DPLL	2
-#define PLL_D2PLL	3
-#define PLL_MPLL	4
-#define ARMCLK		5
-
-
-/* Bus Clocks, derived from core clocks */
-#define BCLK_PCLK	101
-#define BCLK_LHCLK	102
-#define BCLK_MACCLK	103
-#define BCLK_SDCLK	104
-#define BCLK_ARMCLK	105
-
-#define MCLK_DDR	201
-
-/* Special clocks */
-#define PCLK_UART1	501
-#define PCLK_UART2	502
-#define PCLK_UART3	503
-#define PCLK_UART4	504
-#define PCLK_UART5	505
-#define PCLK_MAC1	506
-#define PCLK_MAC2	507
+#define ASPEED_CLK_GATE_ECLK		0
+#define ASPEED_CLK_GATE_GCLK		1
+#define ASPEED_CLK_GATE_MCLK		2
+#define ASPEED_CLK_GATE_VCLK		3
+#define ASPEED_CLK_GATE_BCLK		4
+#define ASPEED_CLK_GATE_DCLK		5
+#define ASPEED_CLK_GATE_REFCLK		6
+#define ASPEED_CLK_GATE_USBPORT2CLK	7
+#define ASPEED_CLK_GATE_LCLK		8
+#define ASPEED_CLK_GATE_USBUHCICLK	9
+#define ASPEED_CLK_GATE_D1CLK		10
+#define ASPEED_CLK_GATE_YCLK		11
+#define ASPEED_CLK_GATE_USBPORT1CLK	12
+#define ASPEED_CLK_GATE_UART1CLK	13
+#define ASPEED_CLK_GATE_UART2CLK	14
+#define ASPEED_CLK_GATE_UART5CLK	15
+#define ASPEED_CLK_GATE_ESPICLK		16
+#define ASPEED_CLK_GATE_MAC1CLK		17
+#define ASPEED_CLK_GATE_MAC2CLK		18
+#define ASPEED_CLK_GATE_RSACLK		19
+#define ASPEED_CLK_GATE_UART3CLK	20
+#define ASPEED_CLK_GATE_UART4CLK	21
+#define ASPEED_CLK_GATE_SDCLK		22
+#define ASPEED_CLK_GATE_LHCCLK		23
+#define ASPEED_CLK_HPLL			24
+#define ASPEED_CLK_AHB			25
+#define ASPEED_CLK_APB			26
+#define ASPEED_CLK_UART			27
+#define ASPEED_CLK_SDIO			28
+#define ASPEED_CLK_ECLK			29
+#define ASPEED_CLK_ECLK_MUX		30
+#define ASPEED_CLK_LHCLK		31
+#define ASPEED_CLK_MAC			32
+#define ASPEED_CLK_BCLK			33
+#define ASPEED_CLK_MPLL			34
+#define ASPEED_CLK_24M			35
+#define ASPEED_CLK_MAC1RCLK		36
+#define ASPEED_CLK_MAC2RCLK		37
+#define ASPEED_CLK_DPLL		38
+#define ASPEED_CLK_D2PLL	39
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 20+ messages in thread
* [PATCH 3/3] cosmetic: aspeed: Modify for SPDX-License
  2020-08-28  7:32 [PATCH 0/3] Rename ASPEED SoC clock name Ryan Chen
                   ` (2 preceding siblings ...)
  2020-08-28  7:33 ` [PATCH 2/3] aspeed:clock: Sync with Linux kernel clock header define Ryan Chen
@ 2020-08-28  7:33 ` Ryan Chen
  2020-08-29  8:45 ` [PATCH 0/3] Rename ASPEED SoC clock name Cédric Le Goater
  2020-08-31  6:03 ` [PATCH v2 " Ryan Chen
  5 siblings, 0 replies; 20+ messages in thread
From: Ryan Chen @ 2020-08-28  7:33 UTC (permalink / raw)
  To: u-boot

Modify SPDX-License for furture patch warning

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
---
 arch/arm/dts/ast2500-u-boot.dtsi         | 1 +
 include/dt-bindings/clock/aspeed-clock.h | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi
index 29b08f16ac..51a5244766 100644
--- a/arch/arm/dts/ast2500-u-boot.dtsi
+++ b/arch/arm/dts/ast2500-u-boot.dtsi
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 #include <dt-bindings/clock/aspeed-clock.h>
 #include <dt-bindings/reset/ast2500-reset.h>
 
diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h
index e6599deeb9..a1aa8c07ce 100644
--- a/include/dt-bindings/clock/aspeed-clock.h
+++ b/include/dt-bindings/clock/aspeed-clock.h
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
+// SPDX-License-Identifier: GPL-2.0
 
 #define ASPEED_CLK_GATE_ECLK		0
 #define ASPEED_CLK_GATE_GCLK		1
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 20+ messages in thread
* [PATCH 0/3] Rename ASPEED SoC clock name
  2020-08-28  7:32 [PATCH 0/3] Rename ASPEED SoC clock name Ryan Chen
                   ` (3 preceding siblings ...)
  2020-08-28  7:33 ` [PATCH 3/3] cosmetic: aspeed: Modify for SPDX-License Ryan Chen
@ 2020-08-29  8:45 ` Cédric Le Goater
  2020-08-31  1:26   ` Ryan Chen
  2020-08-31  6:03 ` [PATCH v2 " Ryan Chen
  5 siblings, 1 reply; 20+ messages in thread
From: Cédric Le Goater @ 2020-08-29  8:45 UTC (permalink / raw)
  To: u-boot

Hello Ryan, 

On 8/28/20 9:32 AM, Ryan Chen wrote:
> This patch series refactor the exiting ASPEED clock name define sync
> with Linux kernel. And also add SPDX-License

All the patchset seems correct but the patch numbering is a bit 
confusing. I have received : 

 [1/3] cosmetic: aspeed: ast2500: Rename clock header
 [1/1] Remove not used export function header.
 [2/3] aspeed:clock: Sync with Linux kernel clock header define
 [3/3] cosmetic: aspeed: Modify for SPDX-License

Could you please merge the first two together maybe and resend ? 

Thanks,

C. 

> Ryan Chen (3):
>   cosmetic: aspeed: ast2500: Rename clock header
>   aspeed:clock: Sync with Linux kernel clock header define
>   cosmetic: aspeed: Modify for SPDX-License
> 
>  arch/arm/dts/ast2500-u-boot.dtsi             | 23 ++++++-----
>  arch/arm/mach-aspeed/ast2500/sdram_ast2500.c |  2 +-
>  drivers/clk/aspeed/clk_ast2500.c             | 40 +++++++++----------
>  include/dt-bindings/clock/aspeed-clock.h     | 42 ++++++++++++++++++++
>  include/dt-bindings/clock/ast2500-scu.h      | 30 --------------
>  5 files changed, 74 insertions(+), 63 deletions(-)
>  create mode 100644 include/dt-bindings/clock/aspeed-clock.h
>  delete mode 100644 include/dt-bindings/clock/ast2500-scu.h
> 

^ permalink raw reply	[flat|nested] 20+ messages in thread
* [PATCH 0/3] Rename ASPEED SoC clock name
  2020-08-29  8:45 ` [PATCH 0/3] Rename ASPEED SoC clock name Cédric Le Goater
@ 2020-08-31  1:26   ` Ryan Chen
  0 siblings, 0 replies; 20+ messages in thread
From: Ryan Chen @ 2020-08-31  1:26 UTC (permalink / raw)
  To: u-boot



> -----Original Message-----
> From: C?dric Le Goater <clg@kaod.org>
> Sent: Saturday, August 29, 2020 4:46 PM
> To: Ryan Chen <ryan_chen@aspeedtech.com>; ChiaWei Wang
> <chiawei_wang@aspeedtech.com>; BMC-SW <BMC-SW@aspeedtech.com>;
> lukma at denx.de; eajames at linux.ibm.com; sjg at chromium.org;
> u-boot at lists.denx.de; Joel Stanley <jmstanle@au1.ibm.com>
> Subject: Re: [PATCH 0/3] Rename ASPEED SoC clock name
> 
> Hello Ryan,
> 
> On 8/28/20 9:32 AM, Ryan Chen wrote:
> > This patch series refactor the exiting ASPEED clock name define sync
> > with Linux kernel. And also add SPDX-License
> 
> All the patchset seems correct but the patch numbering is a bit confusing. I
> have received :
> 
>  [1/3] cosmetic: aspeed: ast2500: Rename clock header  [1/1] Remove not
> used export function header.
>  [2/3] aspeed:clock: Sync with Linux kernel clock header define  [3/3]
> cosmetic: aspeed: Modify for SPDX-License
> 
> Could you please merge the first two together maybe and resend ?
> 
> Thanks,
> 
> C.
> 
Thanks the review. I will resend it for v2. 

> > Ryan Chen (3):
> >   cosmetic: aspeed: ast2500: Rename clock header
> >   aspeed:clock: Sync with Linux kernel clock header define
> >   cosmetic: aspeed: Modify for SPDX-License
> >
> >  arch/arm/dts/ast2500-u-boot.dtsi             | 23 ++++++-----
> >  arch/arm/mach-aspeed/ast2500/sdram_ast2500.c |  2 +-
> >  drivers/clk/aspeed/clk_ast2500.c             | 40 +++++++++----------
> >  include/dt-bindings/clock/aspeed-clock.h     | 42
> ++++++++++++++++++++
> >  include/dt-bindings/clock/ast2500-scu.h      | 30 --------------
> >  5 files changed, 74 insertions(+), 63 deletions(-)  create mode
> > 100644 include/dt-bindings/clock/aspeed-clock.h
> >  delete mode 100644 include/dt-bindings/clock/ast2500-scu.h
> >

^ permalink raw reply	[flat|nested] 20+ messages in thread
* [PATCH v2 0/3] Rename ASPEED SoC clock name
  2020-08-28  7:32 [PATCH 0/3] Rename ASPEED SoC clock name Ryan Chen
                   ` (4 preceding siblings ...)
  2020-08-29  8:45 ` [PATCH 0/3] Rename ASPEED SoC clock name Cédric Le Goater
@ 2020-08-31  6:03 ` Ryan Chen
  2020-08-31  6:03   ` [PATCH v2 1/3] cosmetic: aspeed: ast2500: Rename clock header Ryan Chen
                     ` (2 more replies)
  5 siblings, 3 replies; 20+ messages in thread
From: Ryan Chen @ 2020-08-31  6:03 UTC (permalink / raw)
  To: u-boot

This patch series refactor the exiting ASPEED clock name define sync with Linux kernel. And also add SPDX-License

V2 : modify patch 2/3 title form "aspeed:clock:" -> "clock:aspeed:" description

Ryan Chen (3):
  cosmetic: aspeed: ast2500: Rename clock header
  clock:aspeed: Sync with Linux kernel clock header define
  cosmetic: aspeed: Modify for SPDX-License

 arch/arm/dts/ast2500-u-boot.dtsi             | 23 ++++++-----
 arch/arm/mach-aspeed/ast2500/sdram_ast2500.c |  2 +-
 drivers/clk/aspeed/clk_ast2500.c             | 40 +++++++++----------
 include/dt-bindings/clock/aspeed-clock.h     | 42 ++++++++++++++++++++
 include/dt-bindings/clock/ast2500-scu.h      | 30 --------------
 5 files changed, 74 insertions(+), 63 deletions(-)
 create mode 100644 include/dt-bindings/clock/aspeed-clock.h
 delete mode 100644 include/dt-bindings/clock/ast2500-scu.h

-- 
2.17.1

^ permalink raw reply	[flat|nested] 20+ messages in thread
* [PATCH v2 1/3] cosmetic: aspeed: ast2500: Rename clock header
  2020-08-31  6:03 ` [PATCH v2 " Ryan Chen
@ 2020-08-31  6:03   ` Ryan Chen
  2020-09-07  2:24     ` ChiaWei Wang
                       ` (2 more replies)
  2020-08-31  6:03   ` [PATCH v2 2/3] clock:aspeed: Sync with Linux kernel clock header define Ryan Chen
  2020-08-31  6:03   ` [PATCH v2 3/3] cosmetic: aspeed: Modify for SPDX-License Ryan Chen
  2 siblings, 3 replies; 20+ messages in thread
From: Ryan Chen @ 2020-08-31  6:03 UTC (permalink / raw)
  To: u-boot

Rename the ast2500-scu.h to aspeed-clock.h.

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
---
 arch/arm/dts/ast2500-u-boot.dtsi                            | 2 +-
 arch/arm/mach-aspeed/ast2500/sdram_ast2500.c                | 2 +-
 drivers/clk/aspeed/clk_ast2500.c                            | 2 +-
 include/dt-bindings/clock/{ast2500-scu.h => aspeed-clock.h} | 0
 4 files changed, 3 insertions(+), 3 deletions(-)
 rename include/dt-bindings/clock/{ast2500-scu.h => aspeed-clock.h} (100%)

diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi
index 8ac4215745..3b119e4ace 100644
--- a/arch/arm/dts/ast2500-u-boot.dtsi
+++ b/arch/arm/dts/ast2500-u-boot.dtsi
@@ -1,4 +1,4 @@
-#include <dt-bindings/clock/ast2500-scu.h>
+#include <dt-bindings/clock/aspeed-clock.h>
 #include <dt-bindings/reset/ast2500-reset.h>
 
 #include "ast2500.dtsi"
diff --git a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
index a3adaa8a99..8536a70a19 100644
--- a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
+++ b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
@@ -19,7 +19,7 @@
 #include <asm/arch/wdt.h>
 #include <linux/err.h>
 #include <linux/kernel.h>
-#include <dt-bindings/clock/ast2500-scu.h>
+#include <dt-bindings/clock/aspeed-clock.h>
 
 /* These configuration parameters are taken from Aspeed SDK */
 #define DDR4_MR46_MODE		0x08000000
diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index d1940f1884..392fe76b27 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c
@@ -10,7 +10,7 @@
 #include <asm/io.h>
 #include <asm/arch/scu_ast2500.h>
 #include <dm/lists.h>
-#include <dt-bindings/clock/ast2500-scu.h>
+#include <dt-bindings/clock/aspeed-clock.h>
 #include <linux/delay.h>
 #include <linux/err.h>
 
diff --git a/include/dt-bindings/clock/ast2500-scu.h b/include/dt-bindings/clock/aspeed-clock.h
similarity index 100%
rename from include/dt-bindings/clock/ast2500-scu.h
rename to include/dt-bindings/clock/aspeed-clock.h
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 20+ messages in thread
* [PATCH v2 2/3] clock:aspeed: Sync with Linux kernel clock header define
  2020-08-31  6:03 ` [PATCH v2 " Ryan Chen
  2020-08-31  6:03   ` [PATCH v2 1/3] cosmetic: aspeed: ast2500: Rename clock header Ryan Chen
@ 2020-08-31  6:03   ` Ryan Chen
  2020-09-07  2:24     ` ChiaWei Wang
                       ` (2 more replies)
  2020-08-31  6:03   ` [PATCH v2 3/3] cosmetic: aspeed: Modify for SPDX-License Ryan Chen
  2 siblings, 3 replies; 20+ messages in thread
From: Ryan Chen @ 2020-08-31  6:03 UTC (permalink / raw)
  To: u-boot

v2: modify title description aspeed:clock -> clock:aspeed

Use kernel include/dt-bindings/clock/aspeed-clock.h define
for clock driver.

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
---
 arch/arm/dts/ast2500-u-boot.dtsi         | 20 +++----
 drivers/clk/aspeed/clk_ast2500.c         | 38 +++++++------
 include/dt-bindings/clock/aspeed-clock.h | 68 ++++++++++++++----------
 3 files changed, 68 insertions(+), 58 deletions(-)

diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi
index 3b119e4ace..29b08f16ac 100644
--- a/arch/arm/dts/ast2500-u-boot.dtsi
+++ b/arch/arm/dts/ast2500-u-boot.dtsi
@@ -25,7 +25,7 @@
 		reg = <0x1e6e0000 0x174
 			0x1e6e0200 0x1d4 >;
 		#reset-cells = <1>;
-		clocks = <&scu PLL_MPLL>;
+		clocks = <&scu ASPEED_CLK_MPLL>;
 		resets = <&rst AST_RESET_SDRAM>;
 	};
 
@@ -39,7 +39,7 @@
 				compatible = "aspeed,ast2500-sdhci";
 				reg = <0x1e740100>;
 				#reset-cells = <1>;
-				clocks = <&scu BCLK_SDCLK>;
+				clocks = <&scu ASPEED_CLK_SDIO>;
 				resets = <&rst AST_RESET_SDIO>;
 			};
 
@@ -47,7 +47,7 @@
 				compatible = "aspeed,ast2500-sdhci";
 				reg = <0x1e740200>;
 				#reset-cells = <1>;
-				clocks = <&scu BCLK_SDCLK>;
+				clocks = <&scu ASPEED_CLK_SDIO>;
 				resets = <&rst AST_RESET_SDIO>;
 			};
 		};
@@ -56,23 +56,23 @@
 };
 
 &uart1 {
-	clocks = <&scu PCLK_UART1>;
+	clocks = <&scu ASPEED_CLK_GATE_UART1CLK>;
 };
 
 &uart2 {
-	clocks = <&scu PCLK_UART2>;
+	clocks = <&scu ASPEED_CLK_GATE_UART2CLK>;
 };
 
 &uart3 {
-	clocks = <&scu PCLK_UART3>;
+	clocks = <&scu ASPEED_CLK_GATE_UART3CLK>;
 };
 
 &uart4 {
-	clocks = <&scu PCLK_UART4>;
+	clocks = <&scu ASPEED_CLK_GATE_UART4CLK>;
 };
 
 &uart5 {
-	clocks = <&scu PCLK_UART5>;
+	clocks = <&scu ASPEED_CLK_GATE_UART5CLK>;
 };
 
 &timer {
@@ -80,9 +80,9 @@
 };
 
 &mac0 {
-	clocks = <&scu PCLK_MAC1>, <&scu PLL_D2PLL>;
+	clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>, <&scu ASPEED_CLK_D2PLL>;
 };
 
 &mac1 {
-	clocks = <&scu PCLK_MAC2>, <&scu PLL_D2PLL>;
+	clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>, <&scu ASPEED_CLK_D2PLL>;
 };
diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index 392fe76b27..aab7d14deb 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c
@@ -122,8 +122,7 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
 	ulong rate;
 
 	switch (clk->id) {
-	case PLL_HPLL:
-	case ARMCLK:
+	case ASPEED_CLK_HPLL:
 		/*
 		 * This ignores dynamic/static slowdown of ARMCLK and may
 		 * be inaccurate.
@@ -131,11 +130,11 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
 		rate = ast2500_get_hpll_rate(clkin,
 					     readl(&priv->scu->h_pll_param));
 		break;
-	case MCLK_DDR:
+	case ASPEED_CLK_MPLL:
 		rate = ast2500_get_mpll_rate(clkin,
 					     readl(&priv->scu->m_pll_param));
 		break;
-	case BCLK_PCLK:
+	case ASPEED_CLK_APB:
 		{
 			ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1)
 						  & SCU_PCLK_DIV_MASK)
@@ -146,7 +145,7 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
 			rate = rate / apb_div;
 		}
 		break;
-	case BCLK_SDCLK:
+	case ASPEED_CLK_SDIO:
 		{
 			ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1)
 						  & SCU_SDCLK_DIV_MASK)
@@ -157,19 +156,19 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
 			rate = rate / apb_div;
 		}
 		break;
-	case PCLK_UART1:
+	case ASPEED_CLK_GATE_UART1CLK:
 		rate = ast2500_get_uart_clk_rate(priv->scu, 1);
 		break;
-	case PCLK_UART2:
+	case ASPEED_CLK_GATE_UART2CLK:
 		rate = ast2500_get_uart_clk_rate(priv->scu, 2);
 		break;
-	case PCLK_UART3:
+	case ASPEED_CLK_GATE_UART3CLK:
 		rate = ast2500_get_uart_clk_rate(priv->scu, 3);
 		break;
-	case PCLK_UART4:
+	case ASPEED_CLK_GATE_UART4CLK:
 		rate = ast2500_get_uart_clk_rate(priv->scu, 4);
 		break;
-	case PCLK_UART5:
+	case ASPEED_CLK_GATE_UART5CLK:
 		rate = ast2500_get_uart_clk_rate(priv->scu, 5);
 		break;
 	default:
@@ -431,11 +430,10 @@ static ulong ast2500_clk_set_rate(struct clk *clk, ulong rate)
 
 	ulong new_rate;
 	switch (clk->id) {
-	case PLL_MPLL:
-	case MCLK_DDR:
+	case ASPEED_CLK_MPLL:
 		new_rate = ast2500_configure_ddr(priv->scu, rate);
 		break;
-	case PLL_D2PLL:
+	case ASPEED_CLK_D2PLL:
 		new_rate = ast2500_configure_d2pll(priv->scu, rate);
 		break;
 	default:
@@ -450,7 +448,7 @@ static int ast2500_clk_enable(struct clk *clk)
 	struct ast2500_clk_priv *priv = dev_get_priv(clk->dev);
 
 	switch (clk->id) {
-	case BCLK_SDCLK:
+	case ASPEED_CLK_SDIO:
 		if (readl(&priv->scu->clk_stop_ctrl1) & SCU_CLKSTOP_SDCLK) {
 			ast_scu_unlock(priv->scu);
 
@@ -471,13 +469,13 @@ static int ast2500_clk_enable(struct clk *clk)
 	 * configured based on whether RGMII or RMII mode has been selected
 	 * through hardware strapping.
 	 */
-	case PCLK_MAC1:
+	case ASPEED_CLK_GATE_MAC1CLK:
 		ast2500_configure_mac(priv->scu, 1);
 		break;
-	case PCLK_MAC2:
+	case ASPEED_CLK_GATE_MAC2CLK:
 		ast2500_configure_mac(priv->scu, 2);
 		break;
-	case PLL_D2PLL:
+	case ASPEED_CLK_D2PLL:
 		ast2500_configure_d2pll(priv->scu, D2PLL_DEFAULT_RATE);
 		break;
 	default:
@@ -497,9 +495,9 @@ static int ast2500_clk_ofdata_to_platdata(struct udevice *dev)
 {
 	struct ast2500_clk_priv *priv = dev_get_priv(dev);
 
-	priv->scu = dev_read_addr_ptr(dev);
-	if (!priv->scu)
-		return -EINVAL;
+	priv->scu = devfdt_get_addr_ptr(dev);
+	if (IS_ERR(priv->scu))
+		return PTR_ERR(priv->scu);
 
 	return 0;
 }
diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h
index 4803abe9f6..e6599deeb9 100644
--- a/include/dt-bindings/clock/aspeed-clock.h
+++ b/include/dt-bindings/clock/aspeed-clock.h
@@ -1,30 +1,42 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2016 Google Inc.
- */
 
-/* Core Clocks */
-#define PLL_HPLL	1
-#define PLL_DPLL	2
-#define PLL_D2PLL	3
-#define PLL_MPLL	4
-#define ARMCLK		5
-
-
-/* Bus Clocks, derived from core clocks */
-#define BCLK_PCLK	101
-#define BCLK_LHCLK	102
-#define BCLK_MACCLK	103
-#define BCLK_SDCLK	104
-#define BCLK_ARMCLK	105
-
-#define MCLK_DDR	201
-
-/* Special clocks */
-#define PCLK_UART1	501
-#define PCLK_UART2	502
-#define PCLK_UART3	503
-#define PCLK_UART4	504
-#define PCLK_UART5	505
-#define PCLK_MAC1	506
-#define PCLK_MAC2	507
+#define ASPEED_CLK_GATE_ECLK		0
+#define ASPEED_CLK_GATE_GCLK		1
+#define ASPEED_CLK_GATE_MCLK		2
+#define ASPEED_CLK_GATE_VCLK		3
+#define ASPEED_CLK_GATE_BCLK		4
+#define ASPEED_CLK_GATE_DCLK		5
+#define ASPEED_CLK_GATE_REFCLK		6
+#define ASPEED_CLK_GATE_USBPORT2CLK	7
+#define ASPEED_CLK_GATE_LCLK		8
+#define ASPEED_CLK_GATE_USBUHCICLK	9
+#define ASPEED_CLK_GATE_D1CLK		10
+#define ASPEED_CLK_GATE_YCLK		11
+#define ASPEED_CLK_GATE_USBPORT1CLK	12
+#define ASPEED_CLK_GATE_UART1CLK	13
+#define ASPEED_CLK_GATE_UART2CLK	14
+#define ASPEED_CLK_GATE_UART5CLK	15
+#define ASPEED_CLK_GATE_ESPICLK		16
+#define ASPEED_CLK_GATE_MAC1CLK		17
+#define ASPEED_CLK_GATE_MAC2CLK		18
+#define ASPEED_CLK_GATE_RSACLK		19
+#define ASPEED_CLK_GATE_UART3CLK	20
+#define ASPEED_CLK_GATE_UART4CLK	21
+#define ASPEED_CLK_GATE_SDCLK		22
+#define ASPEED_CLK_GATE_LHCCLK		23
+#define ASPEED_CLK_HPLL			24
+#define ASPEED_CLK_AHB			25
+#define ASPEED_CLK_APB			26
+#define ASPEED_CLK_UART			27
+#define ASPEED_CLK_SDIO			28
+#define ASPEED_CLK_ECLK			29
+#define ASPEED_CLK_ECLK_MUX		30
+#define ASPEED_CLK_LHCLK		31
+#define ASPEED_CLK_MAC			32
+#define ASPEED_CLK_BCLK			33
+#define ASPEED_CLK_MPLL			34
+#define ASPEED_CLK_24M			35
+#define ASPEED_CLK_MAC1RCLK		36
+#define ASPEED_CLK_MAC2RCLK		37
+#define ASPEED_CLK_DPLL		38
+#define ASPEED_CLK_D2PLL	39
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 20+ messages in thread
* [PATCH v2 3/3] cosmetic: aspeed: Modify for SPDX-License
  2020-08-31  6:03 ` [PATCH v2 " Ryan Chen
  2020-08-31  6:03   ` [PATCH v2 1/3] cosmetic: aspeed: ast2500: Rename clock header Ryan Chen
  2020-08-31  6:03   ` [PATCH v2 2/3] clock:aspeed: Sync with Linux kernel clock header define Ryan Chen
@ 2020-08-31  6:03   ` Ryan Chen
  2020-09-07  2:25     ` ChiaWei Wang
                       ` (2 more replies)
  2 siblings, 3 replies; 20+ messages in thread
From: Ryan Chen @ 2020-08-31  6:03 UTC (permalink / raw)
  To: u-boot

Modify SPDX-License for furture patch warning

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
---
 arch/arm/dts/ast2500-u-boot.dtsi         | 1 +
 include/dt-bindings/clock/aspeed-clock.h | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi
index 29b08f16ac..51a5244766 100644
--- a/arch/arm/dts/ast2500-u-boot.dtsi
+++ b/arch/arm/dts/ast2500-u-boot.dtsi
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 #include <dt-bindings/clock/aspeed-clock.h>
 #include <dt-bindings/reset/ast2500-reset.h>
 
diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h
index e6599deeb9..a1aa8c07ce 100644
--- a/include/dt-bindings/clock/aspeed-clock.h
+++ b/include/dt-bindings/clock/aspeed-clock.h
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
+// SPDX-License-Identifier: GPL-2.0
 
 #define ASPEED_CLK_GATE_ECLK		0
 #define ASPEED_CLK_GATE_GCLK		1
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 20+ messages in thread
* [PATCH v2 1/3] cosmetic: aspeed: ast2500: Rename clock header
  2020-08-31  6:03   ` [PATCH v2 1/3] cosmetic: aspeed: ast2500: Rename clock header Ryan Chen
@ 2020-09-07  2:24     ` ChiaWei Wang
  2020-09-09  6:39     ` Cédric Le Goater
  2020-09-10 18:39     ` Tom Rini
  2 siblings, 0 replies; 20+ messages in thread
From: ChiaWei Wang @ 2020-09-07  2:24 UTC (permalink / raw)
  To: u-boot

> -----Original Message-----
> From: Ryan Chen <ryan_chen@aspeedtech.com>
> Sent: Monday, August 31, 2020 2:03 PM
> To: Ryan Chen <ryan_chen@aspeedtech.com>; ChiaWei Wang
> <chiawei_wang@aspeedtech.com>; Lukasz Majewski <lukma@denx.de>;
> clg at kaod.org; Eddie James <eajames@linux.ibm.com>; Simon Glass
> <sjg@chromium.org>; u-boot at lists.denx.de
> Subject: [PATCH v2 1/3] cosmetic: aspeed: ast2500: Rename clock header
> 
> Rename the ast2500-scu.h to aspeed-clock.h.
> 
> Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
> ---
>  arch/arm/dts/ast2500-u-boot.dtsi                            | 2 +-
>  arch/arm/mach-aspeed/ast2500/sdram_ast2500.c                | 2 +-
>  drivers/clk/aspeed/clk_ast2500.c                            | 2 +-
>  include/dt-bindings/clock/{ast2500-scu.h => aspeed-clock.h} | 0
>  4 files changed, 3 insertions(+), 3 deletions(-)  rename
> include/dt-bindings/clock/{ast2500-scu.h => aspeed-clock.h} (100%)
> 
Reviewed-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>

^ permalink raw reply	[flat|nested] 20+ messages in thread
* [PATCH v2 2/3] clock:aspeed: Sync with Linux kernel clock header define
  2020-08-31  6:03   ` [PATCH v2 2/3] clock:aspeed: Sync with Linux kernel clock header define Ryan Chen
@ 2020-09-07  2:24     ` ChiaWei Wang
  2020-09-09  6:47     ` Cédric Le Goater
  2020-09-10 18:39     ` Tom Rini
  2 siblings, 0 replies; 20+ messages in thread
From: ChiaWei Wang @ 2020-09-07  2:24 UTC (permalink / raw)
  To: u-boot

> -----Original Message-----
> From: Ryan Chen <ryan_chen@aspeedtech.com>
> Sent: Monday, August 31, 2020 2:03 PM
> To: Ryan Chen <ryan_chen@aspeedtech.com>; ChiaWei Wang
> <chiawei_wang@aspeedtech.com>; Lukasz Majewski <lukma@denx.de>;
> clg at kaod.org; Eddie James <eajames@linux.ibm.com>; Simon Glass
> <sjg@chromium.org>; u-boot at lists.denx.de
> Subject: [PATCH v2 2/3] clock:aspeed: Sync with Linux kernel clock header
> define
> 
> v2: modify title description aspeed:clock -> clock:aspeed
> 
> Use kernel include/dt-bindings/clock/aspeed-clock.h define for clock driver.
> 
> Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
> ---
>  arch/arm/dts/ast2500-u-boot.dtsi         | 20 +++----
>  drivers/clk/aspeed/clk_ast2500.c         | 38 +++++++------
>  include/dt-bindings/clock/aspeed-clock.h | 68 ++++++++++++++----------
>  3 files changed, 68 insertions(+), 58 deletions(-)

Reviewed-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>

^ permalink raw reply	[flat|nested] 20+ messages in thread
* [PATCH v2 3/3] cosmetic: aspeed: Modify for SPDX-License
  2020-08-31  6:03   ` [PATCH v2 3/3] cosmetic: aspeed: Modify for SPDX-License Ryan Chen
@ 2020-09-07  2:25     ` ChiaWei Wang
  2020-09-09  6:50     ` Cédric Le Goater
  2020-09-10 18:40     ` Tom Rini
  2 siblings, 0 replies; 20+ messages in thread
From: ChiaWei Wang @ 2020-09-07  2:25 UTC (permalink / raw)
  To: u-boot

> -----Original Message-----
> From: Ryan Chen <ryan_chen@aspeedtech.com>
> Sent: Monday, August 31, 2020 2:03 PM
> To: Ryan Chen <ryan_chen@aspeedtech.com>; ChiaWei Wang
> <chiawei_wang@aspeedtech.com>; Lukasz Majewski <lukma@denx.de>;
> clg at kaod.org; Eddie James <eajames@linux.ibm.com>; Simon Glass
> <sjg@chromium.org>; u-boot at lists.denx.de
> Subject: [PATCH v2 3/3] cosmetic: aspeed: Modify for SPDX-License
> 
> Modify SPDX-License for furture patch warning
> 
> Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
> ---
>  arch/arm/dts/ast2500-u-boot.dtsi         | 1 +
>  include/dt-bindings/clock/aspeed-clock.h | 2 +-
>  2 files changed, 2 insertions(+), 1 deletion(-)

Reviewed-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>

^ permalink raw reply	[flat|nested] 20+ messages in thread
* [PATCH v2 1/3] cosmetic: aspeed: ast2500: Rename clock header
  2020-08-31  6:03   ` [PATCH v2 1/3] cosmetic: aspeed: ast2500: Rename clock header Ryan Chen
  2020-09-07  2:24     ` ChiaWei Wang
@ 2020-09-09  6:39     ` Cédric Le Goater
  2020-09-10 18:39     ` Tom Rini
  2 siblings, 0 replies; 20+ messages in thread
From: Cédric Le Goater @ 2020-09-09  6:39 UTC (permalink / raw)
  To: u-boot

On 8/31/20 8:03 AM, Ryan Chen wrote:
> Rename the ast2500-scu.h to aspeed-clock.h.
> 
> Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>

Reviewed-by: C?dric Le Goater <clg@kaod.org>


> ---
>  arch/arm/dts/ast2500-u-boot.dtsi                            | 2 +-
>  arch/arm/mach-aspeed/ast2500/sdram_ast2500.c                | 2 +-
>  drivers/clk/aspeed/clk_ast2500.c                            | 2 +-
>  include/dt-bindings/clock/{ast2500-scu.h => aspeed-clock.h} | 0
>  4 files changed, 3 insertions(+), 3 deletions(-)
>  rename include/dt-bindings/clock/{ast2500-scu.h => aspeed-clock.h} (100%)
> 
> diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi
> index 8ac4215745..3b119e4ace 100644
> --- a/arch/arm/dts/ast2500-u-boot.dtsi
> +++ b/arch/arm/dts/ast2500-u-boot.dtsi
> @@ -1,4 +1,4 @@
> -#include <dt-bindings/clock/ast2500-scu.h>
> +#include <dt-bindings/clock/aspeed-clock.h>
>  #include <dt-bindings/reset/ast2500-reset.h>
>  
>  #include "ast2500.dtsi"
> diff --git a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
> index a3adaa8a99..8536a70a19 100644
> --- a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
> +++ b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
> @@ -19,7 +19,7 @@
>  #include <asm/arch/wdt.h>
>  #include <linux/err.h>
>  #include <linux/kernel.h>
> -#include <dt-bindings/clock/ast2500-scu.h>
> +#include <dt-bindings/clock/aspeed-clock.h>
>  
>  /* These configuration parameters are taken from Aspeed SDK */
>  #define DDR4_MR46_MODE		0x08000000
> diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
> index d1940f1884..392fe76b27 100644
> --- a/drivers/clk/aspeed/clk_ast2500.c
> +++ b/drivers/clk/aspeed/clk_ast2500.c
> @@ -10,7 +10,7 @@
>  #include <asm/io.h>
>  #include <asm/arch/scu_ast2500.h>
>  #include <dm/lists.h>
> -#include <dt-bindings/clock/ast2500-scu.h>
> +#include <dt-bindings/clock/aspeed-clock.h>
>  #include <linux/delay.h>
>  #include <linux/err.h>
>  
> diff --git a/include/dt-bindings/clock/ast2500-scu.h b/include/dt-bindings/clock/aspeed-clock.h
> similarity index 100%
> rename from include/dt-bindings/clock/ast2500-scu.h
> rename to include/dt-bindings/clock/aspeed-clock.h
> 

^ permalink raw reply	[flat|nested] 20+ messages in thread
* [PATCH v2 2/3] clock:aspeed: Sync with Linux kernel clock header define
  2020-08-31  6:03   ` [PATCH v2 2/3] clock:aspeed: Sync with Linux kernel clock header define Ryan Chen
  2020-09-07  2:24     ` ChiaWei Wang
@ 2020-09-09  6:47     ` Cédric Le Goater
  2020-09-10 18:39     ` Tom Rini
  2 siblings, 0 replies; 20+ messages in thread
From: Cédric Le Goater @ 2020-09-09  6:47 UTC (permalink / raw)
  To: u-boot

On 8/31/20 8:03 AM, Ryan Chen wrote:
> v2: modify title description aspeed:clock -> clock:aspeed
> 
> Use kernel include/dt-bindings/clock/aspeed-clock.h define
> for clock driver.
> 
> Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
> ---
>  arch/arm/dts/ast2500-u-boot.dtsi         | 20 +++----
>  drivers/clk/aspeed/clk_ast2500.c         | 38 +++++++------
>  include/dt-bindings/clock/aspeed-clock.h | 68 ++++++++++++++----------
>  3 files changed, 68 insertions(+), 58 deletions(-)
> 
> diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi
> index 3b119e4ace..29b08f16ac 100644
> --- a/arch/arm/dts/ast2500-u-boot.dtsi
> +++ b/arch/arm/dts/ast2500-u-boot.dtsi
> @@ -25,7 +25,7 @@
>  		reg = <0x1e6e0000 0x174
>  			0x1e6e0200 0x1d4 >;
>  		#reset-cells = <1>;
> -		clocks = <&scu PLL_MPLL>;
> +		clocks = <&scu ASPEED_CLK_MPLL>;
>  		resets = <&rst AST_RESET_SDRAM>;
>  	};
>  
> @@ -39,7 +39,7 @@
>  				compatible = "aspeed,ast2500-sdhci";
>  				reg = <0x1e740100>;
>  				#reset-cells = <1>;
> -				clocks = <&scu BCLK_SDCLK>;
> +				clocks = <&scu ASPEED_CLK_SDIO>;
>  				resets = <&rst AST_RESET_SDIO>;
>  			};
>  
> @@ -47,7 +47,7 @@
>  				compatible = "aspeed,ast2500-sdhci";
>  				reg = <0x1e740200>;
>  				#reset-cells = <1>;
> -				clocks = <&scu BCLK_SDCLK>;
> +				clocks = <&scu ASPEED_CLK_SDIO>;
>  				resets = <&rst AST_RESET_SDIO>;
>  			};
>  		};
> @@ -56,23 +56,23 @@
>  };
>  
>  &uart1 {
> -	clocks = <&scu PCLK_UART1>;
> +	clocks = <&scu ASPEED_CLK_GATE_UART1CLK>;
>  };
>  
>  &uart2 {
> -	clocks = <&scu PCLK_UART2>;
> +	clocks = <&scu ASPEED_CLK_GATE_UART2CLK>;
>  };
>  
>  &uart3 {
> -	clocks = <&scu PCLK_UART3>;
> +	clocks = <&scu ASPEED_CLK_GATE_UART3CLK>;
>  };
>  
>  &uart4 {
> -	clocks = <&scu PCLK_UART4>;
> +	clocks = <&scu ASPEED_CLK_GATE_UART4CLK>;
>  };
>  
>  &uart5 {
> -	clocks = <&scu PCLK_UART5>;
> +	clocks = <&scu ASPEED_CLK_GATE_UART5CLK>;
>  };
>  
>  &timer {
> @@ -80,9 +80,9 @@
>  };
>  
>  &mac0 {
> -	clocks = <&scu PCLK_MAC1>, <&scu PLL_D2PLL>;
> +	clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>, <&scu ASPEED_CLK_D2PLL>;
>  };
>  
>  &mac1 {
> -	clocks = <&scu PCLK_MAC2>, <&scu PLL_D2PLL>;
> +	clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>, <&scu ASPEED_CLK_D2PLL>;
>  };
> diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
> index 392fe76b27..aab7d14deb 100644
> --- a/drivers/clk/aspeed/clk_ast2500.c
> +++ b/drivers/clk/aspeed/clk_ast2500.c
> @@ -122,8 +122,7 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
>  	ulong rate;
>  
>  	switch (clk->id) {
> -	case PLL_HPLL:
> -	case ARMCLK:
> +	case ASPEED_CLK_HPLL:
>  		/*
>  		 * This ignores dynamic/static slowdown of ARMCLK and may
>  		 * be inaccurate.
> @@ -131,11 +130,11 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
>  		rate = ast2500_get_hpll_rate(clkin,
>  					     readl(&priv->scu->h_pll_param));
>  		break;
> -	case MCLK_DDR:
> +	case ASPEED_CLK_MPLL:
>  		rate = ast2500_get_mpll_rate(clkin,
>  					     readl(&priv->scu->m_pll_param));
>  		break;
> -	case BCLK_PCLK:
> +	case ASPEED_CLK_APB:
>  		{
>  			ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1)
>  						  & SCU_PCLK_DIV_MASK)
> @@ -146,7 +145,7 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
>  			rate = rate / apb_div;
>  		}
>  		break;
> -	case BCLK_SDCLK:
> +	case ASPEED_CLK_SDIO:
>  		{
>  			ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1)
>  						  & SCU_SDCLK_DIV_MASK)
> @@ -157,19 +156,19 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
>  			rate = rate / apb_div;
>  		}
>  		break;
> -	case PCLK_UART1:
> +	case ASPEED_CLK_GATE_UART1CLK:
>  		rate = ast2500_get_uart_clk_rate(priv->scu, 1);
>  		break;
> -	case PCLK_UART2:
> +	case ASPEED_CLK_GATE_UART2CLK:
>  		rate = ast2500_get_uart_clk_rate(priv->scu, 2);
>  		break;
> -	case PCLK_UART3:
> +	case ASPEED_CLK_GATE_UART3CLK:
>  		rate = ast2500_get_uart_clk_rate(priv->scu, 3);
>  		break;
> -	case PCLK_UART4:
> +	case ASPEED_CLK_GATE_UART4CLK:
>  		rate = ast2500_get_uart_clk_rate(priv->scu, 4);
>  		break;
> -	case PCLK_UART5:
> +	case ASPEED_CLK_GATE_UART5CLK:
>  		rate = ast2500_get_uart_clk_rate(priv->scu, 5);
>  		break;
>  	default:
> @@ -431,11 +430,10 @@ static ulong ast2500_clk_set_rate(struct clk *clk, ulong rate)
>  
>  	ulong new_rate;
>  	switch (clk->id) {
> -	case PLL_MPLL:
> -	case MCLK_DDR:
> +	case ASPEED_CLK_MPLL:
>  		new_rate = ast2500_configure_ddr(priv->scu, rate);
>  		break;
> -	case PLL_D2PLL:
> +	case ASPEED_CLK_D2PLL:
>  		new_rate = ast2500_configure_d2pll(priv->scu, rate);
>  		break;
>  	default:
> @@ -450,7 +448,7 @@ static int ast2500_clk_enable(struct clk *clk)
>  	struct ast2500_clk_priv *priv = dev_get_priv(clk->dev);
>  
>  	switch (clk->id) {
> -	case BCLK_SDCLK:
> +	case ASPEED_CLK_SDIO:
>  		if (readl(&priv->scu->clk_stop_ctrl1) & SCU_CLKSTOP_SDCLK) {
>  			ast_scu_unlock(priv->scu);
>  
> @@ -471,13 +469,13 @@ static int ast2500_clk_enable(struct clk *clk)
>  	 * configured based on whether RGMII or RMII mode has been selected
>  	 * through hardware strapping.
>  	 */
> -	case PCLK_MAC1:
> +	case ASPEED_CLK_GATE_MAC1CLK:
>  		ast2500_configure_mac(priv->scu, 1);
>  		break;
> -	case PCLK_MAC2:
> +	case ASPEED_CLK_GATE_MAC2CLK:
>  		ast2500_configure_mac(priv->scu, 2);
>  		break;
> -	case PLL_D2PLL:
> +	case ASPEED_CLK_D2PLL:
>  		ast2500_configure_d2pll(priv->scu, D2PLL_DEFAULT_RATE);
>  		break;
>  	default:
> @@ -497,9 +495,9 @@ static int ast2500_clk_ofdata_to_platdata(struct udevice *dev)
>  {
>  	struct ast2500_clk_priv *priv = dev_get_priv(dev);
>  
> -	priv->scu = dev_read_addr_ptr(dev);
> -	if (!priv->scu)
> -		return -EINVAL;
> +	priv->scu = devfdt_get_addr_ptr(dev);
> +	if (IS_ERR(priv->scu))
> +		return PTR_ERR(priv->scu);


This is an unrelated change. 

>  	return 0;
>  }
> diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h
> index 4803abe9f6..e6599deeb9 100644
> --- a/include/dt-bindings/clock/aspeed-clock.h
> +++ b/include/dt-bindings/clock/aspeed-clock.h
> @@ -1,30 +1,42 @@
>  /* SPDX-License-Identifier: GPL-2.0+ */
> -/*
> - * Copyright 2016 Google Inc.
> - */

I don't know how to deal with this change.

I think merging the first two patches in one patch will solve the issue 
as it would remove file ast2500-scu.h and add aspeed-clock.h.

But please move the devfdt_get_addr_ptr() change in another patch.

Thanks,

C. 

> -/* Core Clocks */
> -#define PLL_HPLL	1
> -#define PLL_DPLL	2
> -#define PLL_D2PLL	3
> -#define PLL_MPLL	4
> -#define ARMCLK		5
> -
> -
> -/* Bus Clocks, derived from core clocks */
> -#define BCLK_PCLK	101
> -#define BCLK_LHCLK	102
> -#define BCLK_MACCLK	103
> -#define BCLK_SDCLK	104
> -#define BCLK_ARMCLK	105
> -
> -#define MCLK_DDR	201
> -
> -/* Special clocks */
> -#define PCLK_UART1	501
> -#define PCLK_UART2	502
> -#define PCLK_UART3	503
> -#define PCLK_UART4	504
> -#define PCLK_UART5	505
> -#define PCLK_MAC1	506
> -#define PCLK_MAC2	507
> +#define ASPEED_CLK_GATE_ECLK		0
> +#define ASPEED_CLK_GATE_GCLK		1
> +#define ASPEED_CLK_GATE_MCLK		2
> +#define ASPEED_CLK_GATE_VCLK		3
> +#define ASPEED_CLK_GATE_BCLK		4
> +#define ASPEED_CLK_GATE_DCLK		5
> +#define ASPEED_CLK_GATE_REFCLK		6
> +#define ASPEED_CLK_GATE_USBPORT2CLK	7
> +#define ASPEED_CLK_GATE_LCLK		8
> +#define ASPEED_CLK_GATE_USBUHCICLK	9
> +#define ASPEED_CLK_GATE_D1CLK		10
> +#define ASPEED_CLK_GATE_YCLK		11
> +#define ASPEED_CLK_GATE_USBPORT1CLK	12
> +#define ASPEED_CLK_GATE_UART1CLK	13
> +#define ASPEED_CLK_GATE_UART2CLK	14
> +#define ASPEED_CLK_GATE_UART5CLK	15
> +#define ASPEED_CLK_GATE_ESPICLK		16
> +#define ASPEED_CLK_GATE_MAC1CLK		17
> +#define ASPEED_CLK_GATE_MAC2CLK		18
> +#define ASPEED_CLK_GATE_RSACLK		19
> +#define ASPEED_CLK_GATE_UART3CLK	20
> +#define ASPEED_CLK_GATE_UART4CLK	21
> +#define ASPEED_CLK_GATE_SDCLK		22
> +#define ASPEED_CLK_GATE_LHCCLK		23
> +#define ASPEED_CLK_HPLL			24
> +#define ASPEED_CLK_AHB			25
> +#define ASPEED_CLK_APB			26
> +#define ASPEED_CLK_UART			27
> +#define ASPEED_CLK_SDIO			28
> +#define ASPEED_CLK_ECLK			29
> +#define ASPEED_CLK_ECLK_MUX		30
> +#define ASPEED_CLK_LHCLK		31
> +#define ASPEED_CLK_MAC			32
> +#define ASPEED_CLK_BCLK			33
> +#define ASPEED_CLK_MPLL			34
> +#define ASPEED_CLK_24M			35
> +#define ASPEED_CLK_MAC1RCLK		36
> +#define ASPEED_CLK_MAC2RCLK		37
> +#define ASPEED_CLK_DPLL		38
> +#define ASPEED_CLK_D2PLL	39
> 

^ permalink raw reply	[flat|nested] 20+ messages in thread
* [PATCH v2 3/3] cosmetic: aspeed: Modify for SPDX-License
  2020-08-31  6:03   ` [PATCH v2 3/3] cosmetic: aspeed: Modify for SPDX-License Ryan Chen
  2020-09-07  2:25     ` ChiaWei Wang
@ 2020-09-09  6:50     ` Cédric Le Goater
  2020-09-10 18:40     ` Tom Rini
  2 siblings, 0 replies; 20+ messages in thread
From: Cédric Le Goater @ 2020-09-09  6:50 UTC (permalink / raw)
  To: u-boot

On 8/31/20 8:03 AM, Ryan Chen wrote:
> Modify SPDX-License for furture patch warning
> 
> Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
> ---
>  arch/arm/dts/ast2500-u-boot.dtsi         | 1 +
>  include/dt-bindings/clock/aspeed-clock.h | 2 +-
>  2 files changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi
> index 29b08f16ac..51a5244766 100644
> --- a/arch/arm/dts/ast2500-u-boot.dtsi
> +++ b/arch/arm/dts/ast2500-u-boot.dtsi
> @@ -1,3 +1,4 @@
> +// SPDX-License-Identifier: GPL-2.0
>  #include <dt-bindings/clock/aspeed-clock.h>
>  #include <dt-bindings/reset/ast2500-reset.h>
>  
> diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h
> index e6599deeb9..a1aa8c07ce 100644
> --- a/include/dt-bindings/clock/aspeed-clock.h
> +++ b/include/dt-bindings/clock/aspeed-clock.h
> @@ -1,4 +1,4 @@
> -/* SPDX-License-Identifier: GPL-2.0+ */
> +// SPDX-License-Identifier: GPL-2.0


But Linux has : 

/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT */

Thanks,

C.

>  
>  #define ASPEED_CLK_GATE_ECLK		0
>  #define ASPEED_CLK_GATE_GCLK		1
> 

^ permalink raw reply	[flat|nested] 20+ messages in thread
* [PATCH v2 1/3] cosmetic: aspeed: ast2500: Rename clock header
  2020-08-31  6:03   ` [PATCH v2 1/3] cosmetic: aspeed: ast2500: Rename clock header Ryan Chen
  2020-09-07  2:24     ` ChiaWei Wang
  2020-09-09  6:39     ` Cédric Le Goater
@ 2020-09-10 18:39     ` Tom Rini
  2 siblings, 0 replies; 20+ messages in thread
From: Tom Rini @ 2020-09-10 18:39 UTC (permalink / raw)
  To: u-boot

On Mon, Aug 31, 2020 at 02:03:03PM +0800, Ryan Chen wrote:

> Rename the ast2500-scu.h to aspeed-clock.h.
> 
> Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
> Reviewed-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
> Reviewed-by: C?dric Le Goater <clg@kaod.org>

Applied to u-boot/next, thanks!

-- 
Tom
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^ permalink raw reply	[flat|nested] 20+ messages in thread
* [PATCH v2 2/3] clock:aspeed: Sync with Linux kernel clock header define
  2020-08-31  6:03   ` [PATCH v2 2/3] clock:aspeed: Sync with Linux kernel clock header define Ryan Chen
  2020-09-07  2:24     ` ChiaWei Wang
  2020-09-09  6:47     ` Cédric Le Goater
@ 2020-09-10 18:39     ` Tom Rini
  2 siblings, 0 replies; 20+ messages in thread
From: Tom Rini @ 2020-09-10 18:39 UTC (permalink / raw)
  To: u-boot

On Mon, Aug 31, 2020 at 02:03:04PM +0800, Ryan Chen wrote:

> v2: modify title description aspeed:clock -> clock:aspeed
> 
> Use kernel include/dt-bindings/clock/aspeed-clock.h define
> for clock driver.
> 
> Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
> Reviewed-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>

Applied to u-boot/next, thanks!

-- 
Tom
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^ permalink raw reply	[flat|nested] 20+ messages in thread
* [PATCH v2 3/3] cosmetic: aspeed: Modify for SPDX-License
  2020-08-31  6:03   ` [PATCH v2 3/3] cosmetic: aspeed: Modify for SPDX-License Ryan Chen
  2020-09-07  2:25     ` ChiaWei Wang
  2020-09-09  6:50     ` Cédric Le Goater
@ 2020-09-10 18:40     ` Tom Rini
  2 siblings, 0 replies; 20+ messages in thread
From: Tom Rini @ 2020-09-10 18:40 UTC (permalink / raw)
  To: u-boot

On Mon, Aug 31, 2020 at 02:03:05PM +0800, Ryan Chen wrote:

> Modify SPDX-License for furture patch warning
> 
> Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
> Reviewed-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>

Applied to u-boot/next, thanks!

-- 
Tom
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^ permalink raw reply	[flat|nested] 20+ messages in thread
end of thread, other threads:[~2020-09-10 18:40 UTC | newest]

Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-08-28  7:32 [PATCH 0/3] Rename ASPEED SoC clock name Ryan Chen
2020-08-28  7:32 ` [PATCH 1/3] cosmetic: aspeed: ast2500: Rename clock header Ryan Chen
2020-08-28  7:32 ` [PATCH 1/1] Remove not used export function header Ryan Chen
2020-08-28  7:33 ` [PATCH 2/3] aspeed:clock: Sync with Linux kernel clock header define Ryan Chen
2020-08-28  7:33 ` [PATCH 3/3] cosmetic: aspeed: Modify for SPDX-License Ryan Chen
2020-08-29  8:45 ` [PATCH 0/3] Rename ASPEED SoC clock name Cédric Le Goater
2020-08-31  1:26   ` Ryan Chen
2020-08-31  6:03 ` [PATCH v2 " Ryan Chen
2020-08-31  6:03   ` [PATCH v2 1/3] cosmetic: aspeed: ast2500: Rename clock header Ryan Chen
2020-09-07  2:24     ` ChiaWei Wang
2020-09-09  6:39     ` Cédric Le Goater
2020-09-10 18:39     ` Tom Rini
2020-08-31  6:03   ` [PATCH v2 2/3] clock:aspeed: Sync with Linux kernel clock header define Ryan Chen
2020-09-07  2:24     ` ChiaWei Wang
2020-09-09  6:47     ` Cédric Le Goater
2020-09-10 18:39     ` Tom Rini
2020-08-31  6:03   ` [PATCH v2 3/3] cosmetic: aspeed: Modify for SPDX-License Ryan Chen
2020-09-07  2:25     ` ChiaWei Wang
2020-09-09  6:50     ` Cédric Le Goater
2020-09-10 18:40     ` Tom Rini

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