* [PATCH 00/12] Tegra XHCI controller ELPG support
@ 2020-08-28 1:10 JC Kuo
2020-08-28 1:10 ` [PATCH 01/12] clk: tegra: Add PLLE HW power sequencer control JC Kuo
` (11 more replies)
0 siblings, 12 replies; 15+ messages in thread
From: JC Kuo @ 2020-08-28 1:10 UTC (permalink / raw)
To: gregkh, thierry.reding, robh, jonathanh, kishon
Cc: linux-tegra, linux-usb, linux-kernel, devicetree, nkristam, JC Kuo
Tegra XHCI controler can be placed in ELPG (Engine Level PowerGated)
state for power saving when all of the connected USB devices are in
suspended state. This patch series includes clk, phy and pmc changes
that are required for properly place controller in ELPG and bring
controller out of ELPG.
JC Kuo (12):
clk: tegra: Add PLLE HW power sequencer control
clk: tegra: don't enable PLLE HW sequencer at init
phy: tegra: xusb: t210: rearrange UPHY init
phy: tegra: xusb: t210: add lane_iddq operations
phy: tegra: xusb: add sleepwalk and suspend/resume
soc/tegra: pmc: provide usb sleepwalk register map
arm64: tegra210: XUSB PADCTL add "nvidia,pmc" prop
phy: tegra: xusb: t210: support wake and sleepwalk
phy: tegra: xusb: t186: support wake and sleepwalk
arm64: tegra210/tegra186/tegra194: XUSB PADCTL irq
usb: host: xhci-tegra: unlink power domain devices
xhci: tegra: enable ELPG for runtime/system PM
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 +
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 1 +
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 2 +
drivers/clk/tegra/clk-pll.c | 12 -
drivers/clk/tegra/clk-tegra210.c | 51 +
drivers/phy/tegra/xusb-tegra186.c | 656 ++++++++
drivers/phy/tegra/xusb-tegra210.c | 1953 +++++++++++++++++-----
drivers/phy/tegra/xusb.c | 86 +-
drivers/phy/tegra/xusb.h | 23 +-
drivers/soc/tegra/pmc.c | 89 +
drivers/usb/host/xhci-tegra.c | 577 +++++--
include/linux/clk/tegra.h | 2 +
include/linux/phy/tegra/xusb.h | 13 +
13 files changed, 2957 insertions(+), 509 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 01/12] clk: tegra: Add PLLE HW power sequencer control
2020-08-28 1:10 [PATCH 00/12] Tegra XHCI controller ELPG support JC Kuo
@ 2020-08-28 1:10 ` JC Kuo
2020-08-28 1:10 ` [PATCH 02/12] clk: tegra: don't enable PLLE HW sequencer at init JC Kuo
` (10 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: JC Kuo @ 2020-08-28 1:10 UTC (permalink / raw)
To: gregkh, thierry.reding, robh, jonathanh, kishon
Cc: linux-tegra, linux-usb, linux-kernel, devicetree, nkristam, JC Kuo
PLLE has a hardware power sequencer logic which is a state machine
that can power on/off PLLE without any software intervention. The
sequencer has two inputs, one from XUSB UPHY PLL and the other from
SATA UPHY PLL. PLLE provides reference clock to XUSB and SATA UPHY
PLLs. When both of the downstream PLLs are powered-off, PLLE hardware
power sequencer will automatically power off PLLE for power saving.
XUSB and SATA UPHY PLLs also have their own hardware power sequencer
logic. XUSB UPHY PLL is shared between XUSB SuperSpeed ports and PCIE
controllers. The XUSB UPHY PLL hardware power sequencer has inputs
from XUSB and PCIE. When all of the XUSB SuperSpeed ports and PCIE
controllers are in low power state, XUSB UPHY PLL hardware power
sequencer automatically power off PLL and flags idle to PLLE hardware
power sequencer. Similar applies to SATA UPHY PLL.
PLLE hardware power sequencer has to be enabled after both downstream
sequencers are enabled.
This commit adds two helper functions:
1. tegra210_plle_hw_sequence_start() for XUSB PADCTL driver to enable
PLLE hardware sequencer at proper time.
2. tegra210_plle_hw_sequence_is_enabled() for XUSB PADCTL driver to
check whether PLLE hardware sequencer has been enabled or not.
Signed-off-by: JC Kuo <jckuo@nvidia.com>
---
drivers/clk/tegra/clk-tegra210.c | 51 ++++++++++++++++++++++++++++++++
include/linux/clk/tegra.h | 2 ++
2 files changed, 53 insertions(+)
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 68cbb98af567..255de6c23c67 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -403,6 +403,14 @@ static unsigned long tegra210_input_freq[] = {
#define PLLRE_BASE_DEFAULT_MASK 0x1c000000
#define PLLRE_MISC0_WRITE_MASK 0x67ffffff
+/* PLLE */
+#define PLLE_MISC_IDDQ_SW_CTRL (1 << 14)
+#define PLLE_AUX_USE_LOCKDET (1 << 3)
+#define PLLE_AUX_SS_SEQ_INCLUDE (1 << 31)
+#define PLLE_AUX_ENABLE_SWCTL (1 << 4)
+#define PLLE_AUX_SS_SWCTL (1 << 6)
+#define PLLE_AUX_SEQ_ENABLE (1 << 24)
+
/* PLLX */
#define PLLX_USE_DYN_RAMP 1
#define PLLX_BASE_LOCK (1 << 27)
@@ -489,6 +497,49 @@ static unsigned long tegra210_input_freq[] = {
#define PLLU_MISC0_WRITE_MASK 0xbfffffff
#define PLLU_MISC1_WRITE_MASK 0x00000007
+bool tegra210_plle_hw_sequence_is_enabled(void)
+{
+ u32 val;
+
+ val = readl_relaxed(clk_base + PLLE_AUX);
+ if (val & PLLE_AUX_SEQ_ENABLE)
+ return true;
+
+ return false;
+}
+EXPORT_SYMBOL_GPL(tegra210_plle_hw_sequence_is_enabled);
+
+int tegra210_plle_hw_sequence_start(void)
+{
+ u32 val;
+
+ if (tegra210_plle_hw_sequence_is_enabled())
+ return 0;
+
+ /* skip if PLLE is not enabled yet */
+ val = readl_relaxed(clk_base + PLLE_MISC0);
+ if (!(val & PLLE_MISC_LOCK))
+ return -EIO;
+
+ val &= ~PLLE_MISC_IDDQ_SW_CTRL;
+ writel_relaxed(val, clk_base + PLLE_MISC0);
+
+ val = readl_relaxed(clk_base + PLLE_AUX);
+ val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SS_SEQ_INCLUDE);
+ val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
+ writel_relaxed(val, clk_base + PLLE_AUX);
+
+ fence_udelay(1, clk_base);
+
+ val |= PLLE_AUX_SEQ_ENABLE;
+ writel_relaxed(val, clk_base + PLLE_AUX);
+
+ fence_udelay(1, clk_base);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(tegra210_plle_hw_sequence_start);
+
void tegra210_xusb_pll_hw_control_enable(void)
{
u32 val;
diff --git a/include/linux/clk/tegra.h b/include/linux/clk/tegra.h
index 3f01d43f0598..7a6b29ca3040 100644
--- a/include/linux/clk/tegra.h
+++ b/include/linux/clk/tegra.h
@@ -123,6 +123,8 @@ static inline void tegra_cpu_clock_resume(void)
}
#endif
+extern int tegra210_plle_hw_sequence_start(void);
+extern bool tegra210_plle_hw_sequence_is_enabled(void);
extern void tegra210_xusb_pll_hw_control_enable(void);
extern void tegra210_xusb_pll_hw_sequence_start(void);
extern void tegra210_sata_pll_hw_control_enable(void);
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 02/12] clk: tegra: don't enable PLLE HW sequencer at init
2020-08-28 1:10 [PATCH 00/12] Tegra XHCI controller ELPG support JC Kuo
2020-08-28 1:10 ` [PATCH 01/12] clk: tegra: Add PLLE HW power sequencer control JC Kuo
@ 2020-08-28 1:10 ` JC Kuo
2020-08-28 1:10 ` [PATCH 03/12] phy: tegra: xusb: t210: rearrange UPHY init JC Kuo
` (9 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: JC Kuo @ 2020-08-28 1:10 UTC (permalink / raw)
To: gregkh, thierry.reding, robh, jonathanh, kishon
Cc: linux-tegra, linux-usb, linux-kernel, devicetree, nkristam, JC Kuo
PLLE hardware power sequencer references PEX/SATA UPHY PLL hardware
power sequencers' output to enable/disable PLLE. PLLE hardware power
sequencer has to be enabled only after PEX/SATA UPHY PLL's sequencers
are enabled.
Signed-off-by: JC Kuo <jckuo@nvidia.com>
---
drivers/clk/tegra/clk-pll.c | 12 ------------
1 file changed, 12 deletions(-)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index c5cc0a2dac6f..0193cebe8c5a 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -2515,18 +2515,6 @@ static int clk_plle_tegra210_enable(struct clk_hw *hw)
pll_writel(val, PLLE_SS_CTRL, pll);
udelay(1);
- val = pll_readl_misc(pll);
- val &= ~PLLE_MISC_IDDQ_SW_CTRL;
- pll_writel_misc(val, pll);
-
- val = pll_readl(pll->params->aux_reg, pll);
- val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SS_SEQ_INCLUDE);
- val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
- pll_writel(val, pll->params->aux_reg, pll);
- udelay(1);
- val |= PLLE_AUX_SEQ_ENABLE;
- pll_writel(val, pll->params->aux_reg, pll);
-
out:
if (pll->lock)
spin_unlock_irqrestore(pll->lock, flags);
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 03/12] phy: tegra: xusb: t210: rearrange UPHY init
2020-08-28 1:10 [PATCH 00/12] Tegra XHCI controller ELPG support JC Kuo
2020-08-28 1:10 ` [PATCH 01/12] clk: tegra: Add PLLE HW power sequencer control JC Kuo
2020-08-28 1:10 ` [PATCH 02/12] clk: tegra: don't enable PLLE HW sequencer at init JC Kuo
@ 2020-08-28 1:10 ` JC Kuo
2020-08-28 1:10 ` [PATCH 04/12] phy: tegra: xusb: t210: add lane_iddq operations JC Kuo
` (8 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: JC Kuo @ 2020-08-28 1:10 UTC (permalink / raw)
To: gregkh, thierry.reding, robh, jonathanh, kishon
Cc: linux-tegra, linux-usb, linux-kernel, devicetree, nkristam, JC Kuo
This commit is a preparation for enabling XUSB SC7 support.
It rearranges Tegra210 XUSB PADCTL UPHY initialization sequence,
for the following reasons:
1. PLLE hardware power sequencer has to be enabled only after both
PEX UPHY PLL and SATA UPHY PLL are initialized.
tegra210_uphy_init() -> tegra210_pex_uphy_enable()
-> tegra210_sata_uphy_enable()
-> tegra210_plle_hw_sequence_start()
-> tegra210_aux_mux_lp0_clamp_disable()
2. Once UPHY PLL hardware power sequencer is enabled, do not assert
reset to PEX/SATA PLLs, otherwise UPHY PLL operation will be
broken.
reset_control_assert(pcie->rst) and reset_control_assert(sata->rst)
are removed from PEX/SATA UPHY disable procedure.
3. At cold boot and SC7 exit, the following bits must be cleared after
PEX/SATA lanes are out of IDDQ (IDDQ_DISABLE=1).
a. XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN,
b. XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY
c. XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN
tegra210_pex_uphy_enable() and tegra210_sata_uphy_enable() are in
charge of bringing lanes out of IDDQ, and then AUX_MUX_LP0_* bits
will be cleared by tegra210_aux_mux_lp0_clamp_disable().
4. The programming sequence in tegra210_usb3_port_enable() is required
for both cold boot and SC7 exit, and must be performed only after
PEX/SATA UPHY is initialized. Therefore, this commit moves the
programming sequence to .power_on() stub which is invoked after
.init(). PEX/SATA UPHY is initialzied in .init().
Signed-off-by: JC Kuo <jckuo@nvidia.com>
---
drivers/phy/tegra/xusb-tegra210.c | 495 ++++++++++++++++--------------
drivers/phy/tegra/xusb.c | 2 +-
drivers/phy/tegra/xusb.h | 6 +-
3 files changed, 270 insertions(+), 233 deletions(-)
diff --git a/drivers/phy/tegra/xusb-tegra210.c b/drivers/phy/tegra/xusb-tegra210.c
index 66bd4613835b..3a2d9797fb9f 100644
--- a/drivers/phy/tegra/xusb-tegra210.c
+++ b/drivers/phy/tegra/xusb-tegra210.c
@@ -256,23 +256,52 @@ to_tegra210_xusb_padctl(struct tegra_xusb_padctl *padctl)
return container_of(padctl, struct tegra210_xusb_padctl, base);
}
+static const struct tegra_xusb_lane_map tegra210_usb3_map[] = {
+ { 0, "pcie", 6 },
+ { 1, "pcie", 5 },
+ { 2, "pcie", 0 },
+ { 2, "pcie", 3 },
+ { 3, "pcie", 4 },
+ { 3, "pcie", 4 },
+ { 0, NULL, 0 }
+};
+
+static int tegra210_usb3_lane_map(struct tegra_xusb_lane *lane)
+{
+ const struct tegra_xusb_lane_map *map;
+
+ for (map = tegra210_usb3_map; map->type; map++) {
+ if (map->index == lane->index &&
+ strcmp(map->type, lane->pad->soc->name) == 0) {
+ dev_dbg(lane->pad->padctl->dev,
+ "lane = %s map to port = usb3-%d\n",
+ lane->pad->soc->lanes[lane->index].name,
+ map->port);
+ return map->port;
+ }
+ }
+
+ return -EINVAL;
+}
+
/* must be called under padctl->lock */
static int tegra210_pex_uphy_enable(struct tegra_xusb_padctl *padctl)
{
struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(padctl->pcie);
unsigned long timeout;
u32 value;
- int err;
+ int err, i;
- if (pcie->enable > 0) {
- pcie->enable++;
+ if (pcie->enable)
return 0;
- }
err = clk_prepare_enable(pcie->pll);
if (err < 0)
return err;
+ if (tegra210_plle_hw_sequence_is_enabled())
+ goto skip_pll_init;
+
err = reset_control_deassert(pcie->rst);
if (err < 0)
goto disable;
@@ -455,7 +484,14 @@ static int tegra210_pex_uphy_enable(struct tegra_xusb_padctl *padctl)
tegra210_xusb_pll_hw_sequence_start();
- pcie->enable++;
+skip_pll_init:
+ pcie->enable = true;
+
+ for (i = 0; i < padctl->pcie->soc->num_lanes; i++) {
+ value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);
+ value |= XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(i);
+ padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
+ }
return 0;
@@ -469,34 +505,42 @@ static int tegra210_pex_uphy_enable(struct tegra_xusb_padctl *padctl)
static void tegra210_pex_uphy_disable(struct tegra_xusb_padctl *padctl)
{
struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(padctl->pcie);
+ u32 value;
+ int i;
- mutex_lock(&padctl->lock);
-
- if (WARN_ON(pcie->enable == 0))
- goto unlock;
+ if (WARN_ON(!pcie->enable))
+ return;
- if (--pcie->enable > 0)
- goto unlock;
+ pcie->enable = false;
- reset_control_assert(pcie->rst);
+ for (i = 0; i < padctl->pcie->soc->num_lanes; i++) {
+ value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);
+ value &= ~XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(i);
+ padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
+ }
clk_disable_unprepare(pcie->pll);
-
-unlock:
- mutex_unlock(&padctl->lock);
}
/* must be called under padctl->lock */
-static int tegra210_sata_uphy_enable(struct tegra_xusb_padctl *padctl, bool usb)
+static int tegra210_sata_uphy_enable(struct tegra_xusb_padctl *padctl)
{
struct tegra_xusb_sata_pad *sata = to_sata_pad(padctl->sata);
+ struct tegra_xusb_lane *lane = tegra_xusb_find_lane(padctl, "sata", 0);
unsigned long timeout;
u32 value;
- int err;
+ int err, i;
+ bool usb;
- if (sata->enable > 0) {
- sata->enable++;
+ if (sata->enable)
return 0;
- }
+
+ if (!lane)
+ return 0;
+
+ if (tegra210_plle_hw_sequence_is_enabled())
+ goto skip_pll_init;
+
+ usb = tegra_xusb_lane_check(lane, "usb3-ss");
err = clk_prepare_enable(sata->pll);
if (err < 0)
@@ -697,7 +741,14 @@ static int tegra210_sata_uphy_enable(struct tegra_xusb_padctl *padctl, bool usb)
tegra210_sata_pll_hw_sequence_start();
- sata->enable++;
+skip_pll_init:
+ sata->enable = true;
+
+ for (i = 0; i < padctl->sata->soc->num_lanes; i++) {
+ value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);
+ value |= XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(i);
+ padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
+ }
return 0;
@@ -711,31 +762,26 @@ static int tegra210_sata_uphy_enable(struct tegra_xusb_padctl *padctl, bool usb)
static void tegra210_sata_uphy_disable(struct tegra_xusb_padctl *padctl)
{
struct tegra_xusb_sata_pad *sata = to_sata_pad(padctl->sata);
+ u32 value;
+ int i;
- mutex_lock(&padctl->lock);
-
- if (WARN_ON(sata->enable == 0))
- goto unlock;
+ if (WARN_ON(!sata->enable))
+ return;
- if (--sata->enable > 0)
- goto unlock;
+ sata->enable = false;
- reset_control_assert(sata->rst);
+ for (i = 0; i < padctl->sata->soc->num_lanes; i++) {
+ value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);
+ value &= ~XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(i);
+ padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
+ }
clk_disable_unprepare(sata->pll);
-
-unlock:
- mutex_unlock(&padctl->lock);
}
-static int tegra210_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
+static void tegra210_aux_mux_lp0_clamp_disable(struct tegra_xusb_padctl *padctl)
{
u32 value;
- mutex_lock(&padctl->lock);
-
- if (padctl->enable++ > 0)
- goto out;
-
value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
value &= ~XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN;
padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
@@ -751,24 +797,12 @@ static int tegra210_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
value &= ~XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN;
padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
-
-out:
- mutex_unlock(&padctl->lock);
- return 0;
}
-static int tegra210_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
+static void tegra210_aux_mux_lp0_clamp_enable(struct tegra_xusb_padctl *padctl)
{
u32 value;
- mutex_lock(&padctl->lock);
-
- if (WARN_ON(padctl->enable == 0))
- goto out;
-
- if (--padctl->enable > 0)
- goto out;
-
value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
value |= XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN;
padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
@@ -784,12 +818,36 @@ static int tegra210_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
value |= XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN;
padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
+}
+
+static int tegra210_uphy_init(struct tegra_xusb_padctl *padctl)
+{
+ if (padctl->pcie)
+ tegra210_pex_uphy_enable(padctl);
+ if (padctl->sata)
+ tegra210_sata_uphy_enable(padctl);
+
+ if (!tegra210_plle_hw_sequence_is_enabled())
+ tegra210_plle_hw_sequence_start();
+ else
+ dev_dbg(padctl->dev, "PLLE is already in HW control\n");
+
+ tegra210_aux_mux_lp0_clamp_disable(padctl);
-out:
- mutex_unlock(&padctl->lock);
return 0;
}
+static void __maybe_unused
+tegra210_uphy_deinit(struct tegra_xusb_padctl *padctl)
+{
+ tegra210_aux_mux_lp0_clamp_enable(padctl);
+
+ if (padctl->pcie)
+ tegra210_pex_uphy_disable(padctl);
+ if (padctl->sata)
+ tegra210_sata_uphy_disable(padctl);
+}
+
static int tegra210_hsic_set_idle(struct tegra_xusb_padctl *padctl,
unsigned int index, bool idle)
{
@@ -926,14 +984,12 @@ static int tegra210_usb2_phy_init(struct phy *phy)
XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_SHIFT;
padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX);
- return tegra210_xusb_padctl_enable(padctl);
+ return 0;
}
static int tegra210_usb2_phy_exit(struct phy *phy)
{
- struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
-
- return tegra210_xusb_padctl_disable(lane->pad->padctl);
+ return 0;
}
static int tegra210_xusb_padctl_vbus_override(struct tegra_xusb_padctl *padctl,
@@ -1391,14 +1447,12 @@ static int tegra210_hsic_phy_init(struct phy *phy)
XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_SHIFT;
padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX);
- return tegra210_xusb_padctl_enable(padctl);
+ return 0;
}
static int tegra210_hsic_phy_exit(struct phy *phy)
{
- struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
-
- return tegra210_xusb_padctl_disable(lane->pad->padctl);
+ return 0;
}
static int tegra210_hsic_phy_power_on(struct phy *phy)
@@ -1599,6 +1653,128 @@ static const struct tegra_xusb_lane_soc tegra210_pcie_lanes[] = {
TEGRA210_LANE("pcie-6", 0x028, 24, 0x3, pcie),
};
+static struct tegra_xusb_usb3_port *
+tegra210_lane_to_usb3_port(struct tegra_xusb_lane *lane)
+{
+ int port;
+
+ if (!lane || !lane->pad || !lane->pad->padctl)
+ return NULL;
+
+ port = tegra210_usb3_lane_map(lane);
+ if (port < 0)
+ return NULL;
+
+ return tegra_xusb_find_usb3_port(lane->pad->padctl, port);
+}
+
+static int tegra210_usb3_phy_power_on(struct phy *phy)
+{
+ struct device *dev = &phy->dev;
+ struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
+ struct tegra_xusb_padctl *padctl = lane->pad->padctl;
+ struct tegra_xusb_usb3_port *usb3 = tegra210_lane_to_usb3_port(lane);
+ unsigned int index;
+ u32 value;
+
+ if (!usb3) {
+ dev_err(dev, "no USB3 port found for lane %u\n", lane->index);
+ return -ENODEV;
+ }
+
+ index = usb3->base.index;
+
+ value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP);
+
+ if (!usb3->internal)
+ value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(index);
+ else
+ value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(index);
+
+ value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(index);
+ value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(index, usb3->port);
+ padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(index));
+ value &= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_MASK <<
+ XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_SHIFT);
+ value |= XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_VAL <<
+ XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_SHIFT;
+ padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(index));
+
+ value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(index));
+ value &= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_MASK <<
+ XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_SHIFT);
+ value |= XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_VAL <<
+ XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_SHIFT;
+ padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(index));
+
+ padctl_writel(padctl, XUSB_PADCTL_UPHY_USB3_PAD_ECTL3_RX_DFE_VAL,
+ XUSB_PADCTL_UPHY_USB3_PADX_ECTL3(index));
+
+ value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(index));
+ value &= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_MASK <<
+ XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_SHIFT);
+ value |= XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_VAL <<
+ XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_SHIFT;
+ padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(index));
+
+ padctl_writel(padctl, XUSB_PADCTL_UPHY_USB3_PAD_ECTL6_RX_EQ_CTRL_H_VAL,
+ XUSB_PADCTL_UPHY_USB3_PADX_ECTL6(index));
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
+ value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(index);
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
+
+ usleep_range(100, 200);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
+ value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(index);
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
+
+ usleep_range(100, 200);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
+ value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(index);
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
+
+ return 0;
+}
+
+static int tegra210_usb3_phy_power_off(struct phy *phy)
+{
+ struct device *dev = &phy->dev;
+ struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
+ struct tegra_xusb_padctl *padctl = lane->pad->padctl;
+ struct tegra_xusb_usb3_port *usb3 = tegra210_lane_to_usb3_port(lane);
+ unsigned int index;
+ u32 value;
+
+ if (!usb3) {
+ dev_err(dev, "no USB3 port found for lane %u\n", lane->index);
+ return -ENODEV;
+ }
+
+ index = usb3->base.index;
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
+ value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(index);
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
+
+ usleep_range(100, 200);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
+ value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(index);
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
+
+ usleep_range(250, 350);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
+ value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(index);
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
+
+ return 0;
+}
static struct tegra_xusb_lane *
tegra210_pcie_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,
unsigned int index)
@@ -1640,35 +1816,28 @@ static const struct tegra_xusb_lane_ops tegra210_pcie_lane_ops = {
static int tegra210_pcie_phy_init(struct phy *phy)
{
struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
+ struct tegra_xusb_padctl *padctl = lane->pad->padctl;
- return tegra210_xusb_padctl_enable(lane->pad->padctl);
-}
+ mutex_lock(&padctl->lock);
-static int tegra210_pcie_phy_exit(struct phy *phy)
-{
- struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
+ tegra210_uphy_init(padctl);
- return tegra210_xusb_padctl_disable(lane->pad->padctl);
+ mutex_unlock(&padctl->lock);
+
+ return 0;
}
static int tegra210_pcie_phy_power_on(struct phy *phy)
{
struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
struct tegra_xusb_padctl *padctl = lane->pad->padctl;
- u32 value;
- int err;
+ int err = 0;
mutex_lock(&padctl->lock);
- err = tegra210_pex_uphy_enable(padctl);
- if (err < 0)
- goto unlock;
-
- value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);
- value |= XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->index);
- padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
+ if (tegra_xusb_lane_check(lane, "usb3-ss"))
+ err = tegra210_usb3_phy_power_on(phy);
-unlock:
mutex_unlock(&padctl->lock);
return err;
}
@@ -1677,20 +1846,19 @@ static int tegra210_pcie_phy_power_off(struct phy *phy)
{
struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
struct tegra_xusb_padctl *padctl = lane->pad->padctl;
- u32 value;
+ int err = 0;
- value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);
- value &= ~XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->index);
- padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
+ mutex_lock(&padctl->lock);
- tegra210_pex_uphy_disable(padctl);
+ if (tegra_xusb_lane_check(lane, "usb3-ss"))
+ err = tegra210_usb3_phy_power_off(phy);
- return 0;
+ mutex_unlock(&padctl->lock);
+ return err;
}
static const struct phy_ops tegra210_pcie_phy_ops = {
.init = tegra210_pcie_phy_init,
- .exit = tegra210_pcie_phy_exit,
.power_on = tegra210_pcie_phy_power_on,
.power_off = tegra210_pcie_phy_power_off,
.owner = THIS_MODULE,
@@ -1811,35 +1979,27 @@ static const struct tegra_xusb_lane_ops tegra210_sata_lane_ops = {
static int tegra210_sata_phy_init(struct phy *phy)
{
struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
+ struct tegra_xusb_padctl *padctl = lane->pad->padctl;
- return tegra210_xusb_padctl_enable(lane->pad->padctl);
-}
+ mutex_lock(&padctl->lock);
-static int tegra210_sata_phy_exit(struct phy *phy)
-{
- struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
+ tegra210_uphy_init(padctl);
- return tegra210_xusb_padctl_disable(lane->pad->padctl);
+ mutex_unlock(&padctl->lock);
+ return 0;
}
static int tegra210_sata_phy_power_on(struct phy *phy)
{
struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
struct tegra_xusb_padctl *padctl = lane->pad->padctl;
- u32 value;
- int err;
+ int err = 0;
mutex_lock(&padctl->lock);
- err = tegra210_sata_uphy_enable(padctl, false);
- if (err < 0)
- goto unlock;
-
- value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);
- value |= XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->index);
- padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
+ if (tegra_xusb_lane_check(lane, "usb3-ss"))
+ err = tegra210_usb3_phy_power_on(phy);
-unlock:
mutex_unlock(&padctl->lock);
return err;
}
@@ -1848,20 +2008,19 @@ static int tegra210_sata_phy_power_off(struct phy *phy)
{
struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
struct tegra_xusb_padctl *padctl = lane->pad->padctl;
- u32 value;
+ int err = 0;
- value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);
- value &= ~XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->index);
- padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
+ mutex_lock(&padctl->lock);
- tegra210_sata_uphy_disable(lane->pad->padctl);
+ if (tegra_xusb_lane_check(lane, "usb3-ss"))
+ err = tegra210_usb3_phy_power_off(phy);
- return 0;
+ mutex_unlock(&padctl->lock);
+ return err;
}
static const struct phy_ops tegra210_sata_phy_ops = {
.init = tegra210_sata_phy_init,
- .exit = tegra210_sata_phy_exit,
.power_on = tegra210_sata_phy_power_on,
.power_off = tegra210_sata_phy_power_off,
.owner = THIS_MODULE,
@@ -1984,137 +2143,13 @@ static const struct tegra_xusb_port_ops tegra210_hsic_port_ops = {
static int tegra210_usb3_port_enable(struct tegra_xusb_port *port)
{
- struct tegra_xusb_usb3_port *usb3 = to_usb3_port(port);
- struct tegra_xusb_padctl *padctl = port->padctl;
- struct tegra_xusb_lane *lane = usb3->base.lane;
- unsigned int index = port->index;
- u32 value;
- int err;
-
- value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP);
-
- if (!usb3->internal)
- value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(index);
- else
- value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(index);
-
- value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(index);
- value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(index, usb3->port);
- padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP);
-
- /*
- * TODO: move this code into the PCIe/SATA PHY ->power_on() callbacks
- * and conditionalize based on mux function? This seems to work, but
- * might not be the exact proper sequence.
- */
- err = regulator_enable(usb3->supply);
- if (err < 0)
- return err;
-
- value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(index));
- value &= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_MASK <<
- XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_SHIFT);
- value |= XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_VAL <<
- XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_SHIFT;
- padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(index));
-
- value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(index));
- value &= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_MASK <<
- XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_SHIFT);
- value |= XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_VAL <<
- XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_SHIFT;
- padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(index));
-
- padctl_writel(padctl, XUSB_PADCTL_UPHY_USB3_PAD_ECTL3_RX_DFE_VAL,
- XUSB_PADCTL_UPHY_USB3_PADX_ECTL3(index));
-
- value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(index));
- value &= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_MASK <<
- XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_SHIFT);
- value |= XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_VAL <<
- XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_SHIFT;
- padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(index));
-
- padctl_writel(padctl, XUSB_PADCTL_UPHY_USB3_PAD_ECTL6_RX_EQ_CTRL_H_VAL,
- XUSB_PADCTL_UPHY_USB3_PADX_ECTL6(index));
-
- if (lane->pad == padctl->sata)
- err = tegra210_sata_uphy_enable(padctl, true);
- else
- err = tegra210_pex_uphy_enable(padctl);
-
- if (err) {
- dev_err(&port->dev, "%s: failed to enable UPHY: %d\n",
- __func__, err);
- return err;
- }
-
- value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
- value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(index);
- padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
-
- usleep_range(100, 200);
-
- value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
- value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(index);
- padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
-
- usleep_range(100, 200);
-
- value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
- value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(index);
- padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
-
return 0;
}
static void tegra210_usb3_port_disable(struct tegra_xusb_port *port)
{
- struct tegra_xusb_usb3_port *usb3 = to_usb3_port(port);
- struct tegra_xusb_padctl *padctl = port->padctl;
- struct tegra_xusb_lane *lane = port->lane;
- unsigned int index = port->index;
- u32 value;
-
- value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
- value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(index);
- padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
-
- usleep_range(100, 200);
-
- value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
- value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(index);
- padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
-
- usleep_range(250, 350);
-
- value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
- value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(index);
- padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
-
- if (lane->pad == padctl->sata)
- tegra210_sata_uphy_disable(padctl);
- else
- tegra210_pex_uphy_disable(padctl);
-
- regulator_disable(usb3->supply);
-
- value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP);
- value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(index);
- value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(index, 0x7);
- padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP);
}
-static const struct tegra_xusb_lane_map tegra210_usb3_map[] = {
- { 0, "pcie", 6 },
- { 1, "pcie", 5 },
- { 2, "pcie", 0 },
- { 2, "pcie", 3 },
- { 3, "pcie", 4 },
- { 3, "pcie", 4 },
- { 0, NULL, 0 }
-};
-
static struct tegra_xusb_lane *
tegra210_usb3_port_map(struct tegra_xusb_port *port)
{
diff --git a/drivers/phy/tegra/xusb.c b/drivers/phy/tegra/xusb.c
index de4a46fe1763..b48b590aa0c1 100644
--- a/drivers/phy/tegra/xusb.c
+++ b/drivers/phy/tegra/xusb.c
@@ -376,7 +376,7 @@ static int tegra_xusb_setup_pads(struct tegra_xusb_padctl *padctl)
return 0;
}
-static bool tegra_xusb_lane_check(struct tegra_xusb_lane *lane,
+bool tegra_xusb_lane_check(struct tegra_xusb_lane *lane,
const char *function)
{
const char *func = lane->soc->funcs[lane->function];
diff --git a/drivers/phy/tegra/xusb.h b/drivers/phy/tegra/xusb.h
index ea35af747066..0c828694cf2d 100644
--- a/drivers/phy/tegra/xusb.h
+++ b/drivers/phy/tegra/xusb.h
@@ -128,6 +128,8 @@ struct tegra_xusb_lane_ops {
void (*remove)(struct tegra_xusb_lane *lane);
};
+bool tegra_xusb_lane_check(struct tegra_xusb_lane *lane, const char *function);
+
/*
* pads
*/
@@ -230,7 +232,7 @@ struct tegra_xusb_pcie_pad {
struct reset_control *rst;
struct clk *pll;
- unsigned int enable;
+ bool enable;
};
static inline struct tegra_xusb_pcie_pad *
@@ -245,7 +247,7 @@ struct tegra_xusb_sata_pad {
struct reset_control *rst;
struct clk *pll;
- unsigned int enable;
+ bool enable;
};
static inline struct tegra_xusb_sata_pad *
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 04/12] phy: tegra: xusb: t210: add lane_iddq operations
2020-08-28 1:10 [PATCH 00/12] Tegra XHCI controller ELPG support JC Kuo
` (2 preceding siblings ...)
2020-08-28 1:10 ` [PATCH 03/12] phy: tegra: xusb: t210: rearrange UPHY init JC Kuo
@ 2020-08-28 1:10 ` JC Kuo
2020-08-28 1:10 ` [PATCH 05/12] phy: tegra: xusb: add sleepwalk and suspend/resume JC Kuo
` (7 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: JC Kuo @ 2020-08-28 1:10 UTC (permalink / raw)
To: gregkh, thierry.reding, robh, jonathanh, kishon
Cc: linux-tegra, linux-usb, linux-kernel, devicetree, nkristam, JC Kuo
As per Tegra210 TRM, before changing lane assignments, driver should
keep lanes in IDDQ and sleep state; after changing lane assignments,
driver should bring lanes out of IDDQ.
This commit implements the required operations.
Signed-off-by: JC Kuo <jckuo@nvidia.com>
---
drivers/phy/tegra/xusb-tegra210.c | 94 +++++++++++++++++++++++++++++++
drivers/phy/tegra/xusb.c | 6 ++
drivers/phy/tegra/xusb.h | 4 +-
3 files changed, 103 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/tegra/xusb-tegra210.c b/drivers/phy/tegra/xusb-tegra210.c
index 3a2d9797fb9f..fe1ab440424d 100644
--- a/drivers/phy/tegra/xusb-tegra210.c
+++ b/drivers/phy/tegra/xusb-tegra210.c
@@ -198,6 +198,18 @@
#define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_TERM_EN BIT(18)
#define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_MODE_OVRD BIT(13)
+#define XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(x) (0x464 + (x) * 0x40)
+#define XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_IDDQ BIT(0)
+#define XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_IDDQ_OVRD BIT(1)
+#define XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_SLEEP_MASK (0x3 << 4)
+#define XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_SLEEP_VAL (0x3 << 4)
+#define XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_PWR_OVRD BIT(24)
+#define XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_IDDQ BIT(8)
+#define XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_IDDQ_OVRD BIT(9)
+#define XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_SLEEP_MASK (0x3 << 12)
+#define XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_SLEEP_VAL (0x3 << 12)
+#define XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_PWR_OVRD BIT(25)
+
#define XUSB_PADCTL_UPHY_PLL_S0_CTL1 0x860
#define XUSB_PADCTL_UPHY_PLL_S0_CTL2 0x864
@@ -209,6 +221,7 @@
#define XUSB_PADCTL_UPHY_PLL_S0_CTL8 0x87c
#define XUSB_PADCTL_UPHY_MISC_PAD_S0_CTL1 0x960
+#define XUSB_PADCTL_UPHY_MISC_PAD_S0_CTL2 0x964
#define XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(x) (0xa60 + (x) * 0x40)
#define XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_SHIFT 16
@@ -1636,6 +1649,63 @@ static const struct tegra_xusb_pad_soc tegra210_hsic_pad = {
.ops = &tegra210_hsic_ops,
};
+static void
+tegra210_uphy_lane_iddq_enable(struct tegra_xusb_padctl *padctl, unsigned lane)
+{
+ u32 val, offset;
+
+ if (lane <= 6)
+ offset = XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(lane);
+ else if (lane == 7)
+ offset = XUSB_PADCTL_UPHY_MISC_PAD_S0_CTL2;
+ else {
+ WARN(true, "invalid lane %u\n", lane);
+ return;
+ }
+
+ val = padctl_readl(padctl, offset);
+ val |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_IDDQ_OVRD;
+ val |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_IDDQ_OVRD;
+ val |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_PWR_OVRD;
+ val |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_PWR_OVRD;
+ val |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_IDDQ;
+ val &= ~XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_SLEEP_MASK;
+ val |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_SLEEP_VAL;
+ val |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_IDDQ;
+ val &= ~XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_SLEEP_MASK;
+ val |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_SLEEP_VAL;
+ padctl_writel(padctl, val, offset);
+}
+
+static void
+tegra210_uphy_lane_iddq_disable(struct tegra_xusb_padctl *padctl, unsigned lane)
+{
+ u32 val, offset;
+
+ if (lane <= 6)
+ offset = XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(lane);
+ else if (lane == 7)
+ offset = XUSB_PADCTL_UPHY_MISC_PAD_S0_CTL2;
+ else {
+ WARN(true, "invalid lane %d\n", lane);
+ return;
+ }
+
+ val = padctl_readl(padctl, offset);
+ val &= ~XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_IDDQ_OVRD;
+ val &= ~XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_IDDQ_OVRD;
+ val &= ~XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_PWR_OVRD;
+ val &= ~XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_PWR_OVRD;
+ val |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_IDDQ;
+ val &= ~XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_SLEEP_MASK;
+ val |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_SLEEP_VAL;
+ val |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_IDDQ;
+ val &= ~XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_SLEEP_MASK;
+ val |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_SLEEP_VAL;
+ padctl_writel(padctl, val, offset);
+}
+
+
static const char *tegra210_pcie_functions[] = {
"pcie-x1",
"usb3-ss",
@@ -1808,9 +1878,21 @@ static void tegra210_pcie_lane_remove(struct tegra_xusb_lane *lane)
kfree(pcie);
}
+static void tegra210_pcie_lane_iddq_enable(struct tegra_xusb_lane *lane)
+{
+ tegra210_uphy_lane_iddq_enable(lane->pad->padctl, lane->index);
+}
+
+static void tegra210_pcie_lane_iddq_disable(struct tegra_xusb_lane *lane)
+{
+ tegra210_uphy_lane_iddq_disable(lane->pad->padctl, lane->index);
+}
+
static const struct tegra_xusb_lane_ops tegra210_pcie_lane_ops = {
.probe = tegra210_pcie_lane_probe,
.remove = tegra210_pcie_lane_remove,
+ .iddq_enable = tegra210_pcie_lane_iddq_enable,
+ .iddq_disable = tegra210_pcie_lane_iddq_disable,
};
static int tegra210_pcie_phy_init(struct phy *phy)
@@ -1971,9 +2053,21 @@ static void tegra210_sata_lane_remove(struct tegra_xusb_lane *lane)
kfree(sata);
}
+static void tegra210_sata_lane_iddq_enable(struct tegra_xusb_lane *lane)
+{
+ tegra210_uphy_lane_iddq_enable(lane->pad->padctl, lane->index + 7);
+}
+
+static void tegra210_sata_lane_iddq_disable(struct tegra_xusb_lane *lane)
+{
+ tegra210_uphy_lane_iddq_disable(lane->pad->padctl, lane->index + 7);
+}
+
static const struct tegra_xusb_lane_ops tegra210_sata_lane_ops = {
.probe = tegra210_sata_lane_probe,
.remove = tegra210_sata_lane_remove,
+ .iddq_enable = tegra210_sata_lane_iddq_enable,
+ .iddq_disable = tegra210_sata_lane_iddq_disable,
};
static int tegra210_sata_phy_init(struct phy *phy)
diff --git a/drivers/phy/tegra/xusb.c b/drivers/phy/tegra/xusb.c
index b48b590aa0c1..74abd67e3a31 100644
--- a/drivers/phy/tegra/xusb.c
+++ b/drivers/phy/tegra/xusb.c
@@ -321,11 +321,17 @@ static void tegra_xusb_lane_program(struct tegra_xusb_lane *lane)
if (soc->num_funcs < 2)
return;
+ if (lane->pad->ops->iddq_enable && lane->pad->ops->iddq_disable)
+ lane->pad->ops->iddq_enable(lane);
+
/* choose function */
value = padctl_readl(padctl, soc->offset);
value &= ~(soc->mask << soc->shift);
value |= lane->function << soc->shift;
padctl_writel(padctl, value, soc->offset);
+
+ if (lane->pad->ops->iddq_enable && lane->pad->ops->iddq_disable)
+ lane->pad->ops->iddq_disable(lane);
}
static void tegra_xusb_pad_program(struct tegra_xusb_pad *pad)
diff --git a/drivers/phy/tegra/xusb.h b/drivers/phy/tegra/xusb.h
index 0c828694cf2d..485b692a3b15 100644
--- a/drivers/phy/tegra/xusb.h
+++ b/drivers/phy/tegra/xusb.h
@@ -22,6 +22,7 @@ struct phy;
struct phy_provider;
struct platform_device;
struct regulator;
+struct tegra_xusb_padctl;
/*
* lanes
@@ -126,6 +127,8 @@ struct tegra_xusb_lane_ops {
struct device_node *np,
unsigned int index);
void (*remove)(struct tegra_xusb_lane *lane);
+ void (*iddq_enable)(struct tegra_xusb_lane *lane);
+ void (*iddq_disable)(struct tegra_xusb_lane *lane);
};
bool tegra_xusb_lane_check(struct tegra_xusb_lane *lane, const char *function);
@@ -134,7 +137,6 @@ bool tegra_xusb_lane_check(struct tegra_xusb_lane *lane, const char *function);
* pads
*/
struct tegra_xusb_pad_soc;
-struct tegra_xusb_padctl;
struct tegra_xusb_pad_ops {
struct tegra_xusb_pad *(*probe)(struct tegra_xusb_padctl *padctl,
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 05/12] phy: tegra: xusb: add sleepwalk and suspend/resume
2020-08-28 1:10 [PATCH 00/12] Tegra XHCI controller ELPG support JC Kuo
` (3 preceding siblings ...)
2020-08-28 1:10 ` [PATCH 04/12] phy: tegra: xusb: t210: add lane_iddq operations JC Kuo
@ 2020-08-28 1:10 ` JC Kuo
2020-08-28 1:10 ` [PATCH 06/12] soc/tegra: pmc: provide usb sleepwalk register map JC Kuo
` (6 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: JC Kuo @ 2020-08-28 1:10 UTC (permalink / raw)
To: gregkh, thierry.reding, robh, jonathanh, kishon
Cc: linux-tegra, linux-usb, linux-kernel, devicetree, nkristam, JC Kuo
This commit adds sleepwalk/wake and suspend/resume interfaces
to Tegra XUSB PHY driver.
Tegra XUSB host controller driver makes use of sleepwalk functions
to enable/disable sleepwalk circuit which is in always-on partition
can respond to USB resume signals when controller is not powered.
Sleepwalk can be enabled/disabled for any USB phy individually.
- tegra_xusb_padctl_enable_phy_sleepwalk()
- tegra_xusb_padctl_disable_phy_sleepwalk()
Tegra XUSB host controller driver makes use of wake functions to
enable/disable/query wake circuit which is in always-on partition
can wake system up when USB resume happens.
Wake circuit can be enabled/disabled for any USB phy individually.
- tegra_xusb_padctl_enable_phy_wake()
- tegra_xusb_padctl_disable_phy_wake()
- tegra_xusb_padctl_remote_wake_detected()
This commit also adds two system suspend stubs that can be used to
save and restore XUSB PADCTL context during system suspend and
resume.
- tegra_xusb_padctl_suspend_noirq()
- tegra_xusb_padctl_resume_noirq()
Signed-off-by: JC Kuo <jckuo@nvidia.com>
---
drivers/phy/tegra/xusb.c | 78 ++++++++++++++++++++++++++++++++++
drivers/phy/tegra/xusb.h | 13 ++++++
include/linux/phy/tegra/xusb.h | 13 ++++++
3 files changed, 104 insertions(+)
diff --git a/drivers/phy/tegra/xusb.c b/drivers/phy/tegra/xusb.c
index 74abd67e3a31..3a1551c42c29 100644
--- a/drivers/phy/tegra/xusb.c
+++ b/drivers/phy/tegra/xusb.c
@@ -1274,10 +1274,36 @@ static int tegra_xusb_padctl_remove(struct platform_device *pdev)
return err;
}
+static int tegra_xusb_padctl_suspend_noirq(struct device *dev)
+{
+ struct tegra_xusb_padctl *padctl = dev_get_drvdata(dev);
+
+ if (padctl->soc && padctl->soc->ops && padctl->soc->ops->suspend_noirq)
+ return padctl->soc->ops->suspend_noirq(padctl);
+
+ return 0;
+}
+
+static int tegra_xusb_padctl_resume_noirq(struct device *dev)
+{
+ struct tegra_xusb_padctl *padctl = dev_get_drvdata(dev);
+
+ if (padctl->soc && padctl->soc->ops && padctl->soc->ops->resume_noirq)
+ return padctl->soc->ops->resume_noirq(padctl);
+
+ return 0;
+}
+
+static const struct dev_pm_ops tegra_xusb_padctl_pm_ops = {
+ SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_xusb_padctl_suspend_noirq,
+ tegra_xusb_padctl_resume_noirq)
+};
+
static struct platform_driver tegra_xusb_padctl_driver = {
.driver = {
.name = "tegra-xusb-padctl",
.of_match_table = tegra_xusb_padctl_of_match,
+ .pm = &tegra_xusb_padctl_pm_ops,
},
.probe = tegra_xusb_padctl_probe,
.remove = tegra_xusb_padctl_remove,
@@ -1344,6 +1370,58 @@ int tegra_xusb_padctl_hsic_set_idle(struct tegra_xusb_padctl *padctl,
}
EXPORT_SYMBOL_GPL(tegra_xusb_padctl_hsic_set_idle);
+int tegra_xusb_padctl_enable_phy_sleepwalk(struct tegra_xusb_padctl *padctl,
+ struct phy *phy,
+ enum usb_device_speed speed)
+{
+ if (padctl->soc->ops->enable_phy_sleepwalk)
+ return padctl->soc->ops->enable_phy_sleepwalk(padctl, phy,
+ speed);
+
+ return -ENOTSUPP;
+}
+EXPORT_SYMBOL_GPL(tegra_xusb_padctl_enable_phy_sleepwalk);
+
+int tegra_xusb_padctl_disable_phy_sleepwalk(struct tegra_xusb_padctl *padctl,
+ struct phy *phy)
+{
+ if (padctl->soc->ops->disable_phy_sleepwalk)
+ return padctl->soc->ops->disable_phy_sleepwalk(padctl, phy);
+
+ return -ENOTSUPP;
+}
+EXPORT_SYMBOL_GPL(tegra_xusb_padctl_disable_phy_sleepwalk);
+
+int tegra_xusb_padctl_enable_phy_wake(struct tegra_xusb_padctl *padctl,
+ struct phy *phy)
+{
+ if (padctl->soc->ops->enable_phy_wake)
+ return padctl->soc->ops->enable_phy_wake(padctl, phy);
+
+ return -ENOTSUPP;
+}
+EXPORT_SYMBOL_GPL(tegra_xusb_padctl_enable_phy_wake);
+
+int tegra_xusb_padctl_disable_phy_wake(struct tegra_xusb_padctl *padctl,
+ struct phy *phy)
+{
+ if (padctl->soc->ops->disable_phy_wake)
+ return padctl->soc->ops->disable_phy_wake(padctl, phy);
+
+ return -ENOTSUPP;
+}
+EXPORT_SYMBOL_GPL(tegra_xusb_padctl_disable_phy_wake);
+
+int tegra_xusb_padctl_remote_wake_detected(struct tegra_xusb_padctl *padctl,
+ struct phy *phy)
+{
+ if (padctl->soc->ops->remote_wake_detected)
+ return padctl->soc->ops->remote_wake_detected(phy);
+
+ return -ENOTSUPP;
+}
+EXPORT_SYMBOL_GPL(tegra_xusb_padctl_remote_wake_detected);
+
int tegra_xusb_padctl_usb3_set_lfps_detect(struct tegra_xusb_padctl *padctl,
unsigned int port, bool enable)
{
diff --git a/drivers/phy/tegra/xusb.h b/drivers/phy/tegra/xusb.h
index 485b692a3b15..c1c4ea3ce050 100644
--- a/drivers/phy/tegra/xusb.h
+++ b/drivers/phy/tegra/xusb.h
@@ -11,6 +11,7 @@
#include <linux/mutex.h>
#include <linux/workqueue.h>
+#include <linux/usb/ch9.h>
#include <linux/usb/otg.h>
#include <linux/usb/role.h>
@@ -392,6 +393,8 @@ struct tegra_xusb_padctl_ops {
const struct tegra_xusb_padctl_soc *soc);
void (*remove)(struct tegra_xusb_padctl *padctl);
+ int (*suspend_noirq)(struct tegra_xusb_padctl *padctl);
+ int (*resume_noirq)(struct tegra_xusb_padctl *padctl);
int (*usb3_save_context)(struct tegra_xusb_padctl *padctl,
unsigned int index);
int (*hsic_set_idle)(struct tegra_xusb_padctl *padctl,
@@ -400,6 +403,16 @@ struct tegra_xusb_padctl_ops {
unsigned int index, bool enable);
int (*vbus_override)(struct tegra_xusb_padctl *padctl, bool set);
int (*utmi_port_reset)(struct phy *phy);
+ int (*enable_phy_sleepwalk)(struct tegra_xusb_padctl *padctl,
+ struct phy *phy,
+ enum usb_device_speed speed);
+ int (*disable_phy_sleepwalk)(struct tegra_xusb_padctl *padctl,
+ struct phy *phy);
+ int (*enable_phy_wake)(struct tegra_xusb_padctl *padctl,
+ struct phy *phy);
+ int (*disable_phy_wake)(struct tegra_xusb_padctl *padctl,
+ struct phy *phy);
+ int (*remote_wake_detected)(struct phy *phy);
};
struct tegra_xusb_padctl_soc {
diff --git a/include/linux/phy/tegra/xusb.h b/include/linux/phy/tegra/xusb.h
index 71d956935405..9621e69067e1 100644
--- a/include/linux/phy/tegra/xusb.h
+++ b/include/linux/phy/tegra/xusb.h
@@ -8,6 +8,7 @@
struct tegra_xusb_padctl;
struct device;
+enum usb_device_speed;
struct tegra_xusb_padctl *tegra_xusb_padctl_get(struct device *dev);
void tegra_xusb_padctl_put(struct tegra_xusb_padctl *padctl);
@@ -23,4 +24,16 @@ int tegra_xusb_padctl_set_vbus_override(struct tegra_xusb_padctl *padctl,
int tegra_phy_xusb_utmi_port_reset(struct phy *phy);
int tegra_xusb_padctl_get_usb3_companion(struct tegra_xusb_padctl *padctl,
unsigned int port);
+int tegra_xusb_padctl_enable_phy_sleepwalk(struct tegra_xusb_padctl *padctl,
+ struct phy *phy,
+ enum usb_device_speed speed);
+int tegra_xusb_padctl_disable_phy_sleepwalk(struct tegra_xusb_padctl *padctl,
+ struct phy *phy);
+int tegra_xusb_padctl_enable_phy_wake(struct tegra_xusb_padctl *padctl,
+ struct phy *phy);
+int tegra_xusb_padctl_disable_phy_wake(struct tegra_xusb_padctl *padctl,
+ struct phy *phy);
+int tegra_xusb_padctl_remote_wake_detected(struct tegra_xusb_padctl *padctl,
+ struct phy *phy);
+
#endif /* PHY_TEGRA_XUSB_H */
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 06/12] soc/tegra: pmc: provide usb sleepwalk register map
2020-08-28 1:10 [PATCH 00/12] Tegra XHCI controller ELPG support JC Kuo
` (4 preceding siblings ...)
2020-08-28 1:10 ` [PATCH 05/12] phy: tegra: xusb: add sleepwalk and suspend/resume JC Kuo
@ 2020-08-28 1:10 ` JC Kuo
2020-08-28 10:53 ` kernel test robot
2020-08-28 1:10 ` [PATCH 07/12] arm64: tegra210: XUSB PADCTL add "nvidia,pmc" prop JC Kuo
` (5 subsequent siblings)
11 siblings, 1 reply; 15+ messages in thread
From: JC Kuo @ 2020-08-28 1:10 UTC (permalink / raw)
To: gregkh, thierry.reding, robh, jonathanh, kishon
Cc: linux-tegra, linux-usb, linux-kernel, devicetree, nkristam, JC Kuo
This commit implements a register map which grants USB (UTMI and HSIC)
sleepwalk registers access to USB phy drivers. The USB sleepwalk logic
is in PMC hardware block but USB phy drivers have the best knowledge
of proper programming sequence. This approach prevents using custom
pmc APIs.
Signed-off-by: JC Kuo <jckuo@nvidia.com>
---
drivers/soc/tegra/pmc.c | 89 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 89 insertions(+)
diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
index d332e5d9abac..81504559b62d 100644
--- a/drivers/soc/tegra/pmc.c
+++ b/drivers/soc/tegra/pmc.c
@@ -43,6 +43,7 @@
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
+#include <linux/regmap.h>
#include <soc/tegra/common.h>
#include <soc/tegra/fuse.h>
@@ -102,6 +103,9 @@
#define PMC_PWR_DET_VALUE 0xe4
+#define PMC_USB_DEBOUNCE_DEL 0xec
+#define PMC_USB_AO 0xf0
+
#define PMC_SCRATCH41 0x140
#define PMC_WAKE2_MASK 0x160
@@ -133,6 +137,13 @@
#define IO_DPD2_STATUS 0x1c4
#define SEL_DPD_TIM 0x1c8
+#define PMC_UTMIP_UHSIC_TRIGGERS 0x1ec
+#define PMC_UTMIP_UHSIC_SAVED_STATE 0x1f0
+
+#define PMC_UTMIP_TERM_PAD_CFG 0x1f8
+#define PMC_UTMIP_UHSIC_SLEEP_CFG 0x1fc
+#define PMC_UTMIP_UHSIC_FAKE 0x218
+
#define PMC_SCRATCH54 0x258
#define PMC_SCRATCH54_DATA_SHIFT 8
#define PMC_SCRATCH54_ADDR_SHIFT 0
@@ -145,8 +156,18 @@
#define PMC_SCRATCH55_CHECKSUM_SHIFT 16
#define PMC_SCRATCH55_I2CSLV1_SHIFT 0
+#define PMC_UTMIP_UHSIC_LINE_WAKEUP 0x26c
+
+#define PMC_UTMIP_BIAS_MASTER_CNTRL 0x270
+#define PMC_UTMIP_MASTER_CONFIG 0x274
+#define PMC_UTMIP_UHSIC2_TRIGGERS 0x27c
+#define PMC_UTMIP_MASTER2_CONFIG 0x29c
+
#define GPU_RG_CNTRL 0x2d4
+#define PMC_UTMIP_PAD_CFG0 0x4c0
+#define PMC_UTMIP_UHSIC_SLEEP_CFG1 0x4d0
+#define PMC_UTMIP_SLEEPWALK_P3 0x4e0
/* Tegra186 and later */
#define WAKE_AOWAKE_CNTRL(x) (0x000 + ((x) << 2))
#define WAKE_AOWAKE_CNTRL_LEVEL (1 << 3)
@@ -334,6 +355,7 @@ struct tegra_pmc_soc {
const struct pmc_clk_init_data *pmc_clks_data;
unsigned int num_pmc_clks;
bool has_blink_output;
+ bool has_usb_sleepwalk;
};
static const char * const tegra186_reset_sources[] = {
@@ -2495,6 +2517,67 @@ static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
err);
}
+#define regmap_reg(x) regmap_reg_range(x, x)
+static const struct regmap_range pmc_usb_sleepwalk_ranges[] = {
+ regmap_reg_range(PMC_USB_DEBOUNCE_DEL, PMC_USB_AO),
+ regmap_reg_range(PMC_UTMIP_UHSIC_TRIGGERS, PMC_UTMIP_UHSIC_SAVED_STATE),
+ regmap_reg_range(PMC_UTMIP_TERM_PAD_CFG, PMC_UTMIP_UHSIC_FAKE),
+ regmap_reg(PMC_UTMIP_UHSIC_LINE_WAKEUP),
+ regmap_reg_range(PMC_UTMIP_BIAS_MASTER_CNTRL, PMC_UTMIP_MASTER_CONFIG),
+ regmap_reg_range(PMC_UTMIP_UHSIC2_TRIGGERS, PMC_UTMIP_MASTER2_CONFIG),
+ regmap_reg_range(PMC_UTMIP_PAD_CFG0, PMC_UTMIP_UHSIC_SLEEP_CFG1),
+ regmap_reg(PMC_UTMIP_SLEEPWALK_P3),
+};
+
+static const struct regmap_access_table pmc_usb_sleepwalk_table = {
+ .yes_ranges = pmc_usb_sleepwalk_ranges,
+ .n_yes_ranges = ARRAY_SIZE(pmc_usb_sleepwalk_ranges),
+};
+
+int tegra_pmc_regmap_readl(void *context, unsigned int reg, unsigned int *val)
+{
+ struct tegra_pmc *pmc = context;
+
+ *val = tegra_pmc_readl(pmc, reg);
+ return 0;
+}
+
+int tegra_pmc_regmap_writel(void *context, unsigned int reg, unsigned int val)
+{
+ struct tegra_pmc *pmc = context;
+
+ tegra_pmc_writel(pmc, val, reg);
+ return 0;
+}
+
+static const struct regmap_config usb_sleepwalk_regmap_config = {
+ .name = "usb_sleepwalk",
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .fast_io = true,
+ .rd_table = &pmc_usb_sleepwalk_table,
+ .wr_table = &pmc_usb_sleepwalk_table,
+ .reg_read = tegra_pmc_regmap_readl,
+ .reg_write = tegra_pmc_regmap_writel,
+};
+
+static int tegra_pmc_regmap_init(struct tegra_pmc *pmc)
+{
+ struct regmap *regmap;
+
+ if (pmc->soc->has_usb_sleepwalk) {
+ regmap = devm_regmap_init(pmc->dev, NULL, (__force void *)pmc,
+ &usb_sleepwalk_regmap_config);
+ if (IS_ERR(regmap)) {
+ dev_err(pmc->dev, "failed to allocate register map\n");
+ return PTR_ERR(regmap);
+ }
+ }
+
+ return 0;
+}
+
static int tegra_pmc_probe(struct platform_device *pdev)
{
void __iomem *base;
@@ -2613,6 +2696,10 @@ static int tegra_pmc_probe(struct platform_device *pdev)
pmc->base = base;
mutex_unlock(&pmc->powergates_lock);
+ err = tegra_pmc_regmap_init(pmc);
+ if (err < 0)
+ goto cleanup_powergates;
+
tegra_pmc_clock_register(pmc, pdev->dev.of_node);
platform_set_drvdata(pdev, pmc);
@@ -2976,6 +3063,7 @@ static const struct tegra_pmc_soc tegra124_pmc_soc = {
.pmc_clks_data = tegra_pmc_clks_data,
.num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
.has_blink_output = true,
+ .has_usb_sleepwalk = true,
};
static const char * const tegra210_powergates[] = {
@@ -3094,6 +3182,7 @@ static const struct tegra_pmc_soc tegra210_pmc_soc = {
.pmc_clks_data = tegra_pmc_clks_data,
.num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
.has_blink_output = true,
+ .has_usb_sleepwalk = true,
};
#define TEGRA186_IO_PAD_TABLE(_pad) \
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 07/12] arm64: tegra210: XUSB PADCTL add "nvidia,pmc" prop
2020-08-28 1:10 [PATCH 00/12] Tegra XHCI controller ELPG support JC Kuo
` (5 preceding siblings ...)
2020-08-28 1:10 ` [PATCH 06/12] soc/tegra: pmc: provide usb sleepwalk register map JC Kuo
@ 2020-08-28 1:10 ` JC Kuo
2020-08-28 1:10 ` [PATCH 08/12] phy: tegra: xusb: t210: support wake and sleepwalk JC Kuo
` (4 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: JC Kuo @ 2020-08-28 1:10 UTC (permalink / raw)
To: gregkh, thierry.reding, robh, jonathanh, kishon
Cc: linux-tegra, linux-usb, linux-kernel, devicetree, nkristam, JC Kuo
PMC driver provides USB sleepwalk registers access to XUSB PADCTL
driver. This commit adds a "nvidia,pmc" property which points to
PMC node to XUSB PADCTL device node.
Signed-off-by: JC Kuo <jckuo@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 829f786af133..67c90a0ea32e 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -1040,6 +1040,7 @@ padctl: padctl@7009f000 {
reg = <0x0 0x7009f000 0x0 0x1000>;
resets = <&tegra_car 142>;
reset-names = "padctl";
+ nvidia,pmc = <&tegra_pmc>;
status = "disabled";
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 08/12] phy: tegra: xusb: t210: support wake and sleepwalk
2020-08-28 1:10 [PATCH 00/12] Tegra XHCI controller ELPG support JC Kuo
` (6 preceding siblings ...)
2020-08-28 1:10 ` [PATCH 07/12] arm64: tegra210: XUSB PADCTL add "nvidia,pmc" prop JC Kuo
@ 2020-08-28 1:10 ` JC Kuo
2020-08-28 1:10 ` [PATCH 09/12] phy: tegra: xusb: t186: " JC Kuo
` (3 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: JC Kuo @ 2020-08-28 1:10 UTC (permalink / raw)
To: gregkh, thierry.reding, robh, jonathanh, kishon
Cc: linux-tegra, linux-usb, linux-kernel, devicetree, nkristam, JC Kuo
This commit implements Tegra210 XUSB PADCTL wake and sleepwalk
routines. Sleepwalk logic is in PMC (always-on) hardware block.
PMC driver provides managed access to the sleepwalk registers
via regmap framework.
Signed-off-by: JC Kuo <jckuo@nvidia.com>
---
drivers/phy/tegra/xusb-tegra210.c | 1094 ++++++++++++++++++++++++++++-
1 file changed, 1079 insertions(+), 15 deletions(-)
diff --git a/drivers/phy/tegra/xusb-tegra210.c b/drivers/phy/tegra/xusb-tegra210.c
index fe1ab440424d..1c03f4ec4b59 100644
--- a/drivers/phy/tegra/xusb-tegra210.c
+++ b/drivers/phy/tegra/xusb-tegra210.c
@@ -16,6 +16,8 @@
#include <linux/regulator/consumer.h>
#include <linux/reset.h>
#include <linux/slab.h>
+#include <linux/regmap.h>
+#include <linux/of_platform.h>
#include <soc/tegra/fuse.h>
@@ -52,6 +54,20 @@
#define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(x, v) (((v) & 0x7) << ((x) * 5))
#define XUSB_PADCTL_SS_PORT_MAP_PORT_DISABLED 0x7
+#define XUSB_PADCTL_ELPG_PROGRAM_0 0x20
+#define USB2_PORT_WAKE_INTERRUPT_ENABLE(x) BIT((x))
+#define USB2_PORT_WAKEUP_EVENT(x) BIT((x) + 7)
+#define SS_PORT_WAKE_INTERRUPT_ENABLE(x) BIT((x) + 14)
+#define SS_PORT_WAKEUP_EVENT(x) BIT((x) + 21)
+#define USB2_HSIC_PORT_WAKE_INTERRUPT_ENABLE(x) BIT((x) + 28)
+#define USB2_HSIC_PORT_WAKEUP_EVENT(x) BIT((x) + 30)
+#define ALL_WAKE_EVENTS ( \
+ USB2_PORT_WAKEUP_EVENT(0) | USB2_PORT_WAKEUP_EVENT(1) | \
+ USB2_PORT_WAKEUP_EVENT(2) | USB2_PORT_WAKEUP_EVENT(3) | \
+ SS_PORT_WAKEUP_EVENT(0) | SS_PORT_WAKEUP_EVENT(1) | \
+ SS_PORT_WAKEUP_EVENT(2) | SS_PORT_WAKEUP_EVENT(3) | \
+ USB2_HSIC_PORT_WAKEUP_EVENT(0))
+
#define XUSB_PADCTL_ELPG_PROGRAM1 0x024
#define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN (1 << 31)
#define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 30)
@@ -90,6 +106,8 @@
#define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR (1 << 2)
#define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DISC_OVRD (1 << 1)
#define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_CHRP_OVRD (1 << 0)
+#define RPD_CTRL(x) (((x) & 0x1f) << 26)
+#define RPD_CTRL_VALUE(x) (((x) >> 26) & 0x1f)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0 0x284
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD (1 << 11)
@@ -108,6 +126,8 @@
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_SHIFT 12
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_MASK 0x7f
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_VAL 0x1e
+#define TCTRL_VALUE(x) (((x) & 0x3f) >> 0)
+#define PCTRL_VALUE(x) (((x) >> 6) & 0x3f)
#define XUSB_PADCTL_HSIC_PADX_CTL0(x) (0x300 + (x) * 0x20)
#define XUSB_PADCTL_HSIC_PAD_CTL0_RPU_STROBE (1 << 18)
@@ -251,16 +271,161 @@
#define XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_FLOATING 8
#define XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_GROUNDED 0
+/* USB2 SLEEPWALK registers */
+#define UTMIP(_port, _offset1, _offset2) \
+ (((_port) <= 2) ? (_offset1) : (_offset2))
+
+#define PMC_UTMIP_UHSIC_SLEEP_CFG(x) UTMIP(x, 0x1fc, 0x4d0)
+#define UTMIP_MASTER_ENABLE(x) UTMIP(x, BIT(8 * (x)), BIT(0))
+#define UTMIP_FSLS_USE_PMC(x) UTMIP(x, BIT(8 * (x) + 1), \
+ BIT(1))
+#define UTMIP_PCTRL_USE_PMC(x) UTMIP(x, BIT(8 * (x) + 2), \
+ BIT(2))
+#define UTMIP_TCTRL_USE_PMC(x) UTMIP(x, BIT(8 * (x) + 3), \
+ BIT(3))
+#define UTMIP_WAKE_VAL(_port, _value) (((_value) & 0xf) << \
+ (UTMIP(_port, 8 * (_port) + 4, 4)))
+#define UTMIP_WAKE_VAL_NONE(_port) UTMIP_WAKE_VAL(_port, 12)
+#define UTMIP_WAKE_VAL_ANY(_port) UTMIP_WAKE_VAL(_port, 15)
+
+#define PMC_UTMIP_UHSIC_SLEEP_CFG1 (0x4d0)
+#define UTMIP_RPU_SWITC_LOW_USE_PMC_PX(x) BIT((x) + 8)
+#define UTMIP_RPD_CTRL_USE_PMC_PX(x) BIT((x) + 16)
+
+#define PMC_UTMIP_MASTER_CONFIG (0x274)
+#define UTMIP_PWR(x) UTMIP(x, BIT(x), BIT(4))
+#define UHSIC_PWR(x) BIT(3)
+
+#define PMC_USB_DEBOUNCE_DEL (0xec)
+#define DEBOUNCE_VAL(x) (((x) & 0xffff) << 0)
+#define UTMIP_LINE_DEB_CNT(x) (((x) & 0xf) << 16)
+#define UHSIC_LINE_DEB_CNT(x) (((x) & 0xf) << 20)
+
+#define PMC_UTMIP_UHSIC_FAKE(x) UTMIP(x, 0x218, 0x294)
+#define UTMIP_FAKE_USBOP_VAL(x) UTMIP(x, BIT(4 * (x)), BIT(8))
+#define UTMIP_FAKE_USBON_VAL(x) UTMIP(x, BIT(4 * (x) + 1), \
+ BIT(9))
+#define UTMIP_FAKE_USBOP_EN(x) UTMIP(x, BIT(4 * (x) + 2), \
+ BIT(10))
+#define UTMIP_FAKE_USBON_EN(x) UTMIP(x, BIT(4 * (x) + 3), \
+ BIT(11))
+
+#define PMC_UTMIP_UHSIC_SLEEPWALK_CFG(x) UTMIP(x, 0x200, 0x288)
+#define UTMIP_LINEVAL_WALK_EN(x) UTMIP(x, BIT(8 * (x) + 7), \
+ BIT(15))
+
+#define PMC_USB_AO (0xf0)
+#define USBOP_VAL_PD(x) UTMIP(x, BIT(4 * (x)), BIT(20))
+#define USBON_VAL_PD(x) UTMIP(x, BIT(4 * (x) + 1), \
+ BIT(21))
+#define STROBE_VAL_PD(x) BIT(12)
+#define DATA0_VAL_PD(x) BIT(13)
+#define DATA1_VAL_PD BIT(24)
+
+#define PMC_UTMIP_UHSIC_SAVED_STATE(x) UTMIP(x, 0x1f0, 0x280)
+#define SPEED(_port, _value) (((_value) & 0x3) << \
+ (UTMIP(_port, 8 * (_port), 8)))
+#define UTMI_HS(_port) SPEED(_port, 0)
+#define UTMI_FS(_port) SPEED(_port, 1)
+#define UTMI_LS(_port) SPEED(_port, 2)
+#define UTMI_RST(_port) SPEED(_port, 3)
+
+#define PMC_UTMIP_UHSIC_TRIGGERS (0x1ec)
+#define UTMIP_CLR_WALK_PTR(x) UTMIP(x, BIT(x), BIT(16))
+#define UTMIP_CAP_CFG(x) UTMIP(x, BIT((x) + 4), BIT(17))
+#define UTMIP_CLR_WAKE_ALARM(x) UTMIP(x, BIT((x) + 12), \
+ BIT(19))
+#define UHSIC_CLR_WALK_PTR BIT(3)
+#define UHSIC_CLR_WAKE_ALARM BIT(15)
+
+#define PMC_UTMIP_SLEEPWALK_PX(x) UTMIP(x, 0x204 + (4 * (x)), \
+ 0x4e0)
+/* phase A */
+#define UTMIP_USBOP_RPD_A BIT(0)
+#define UTMIP_USBON_RPD_A BIT(1)
+#define UTMIP_AP_A BIT(4)
+#define UTMIP_AN_A BIT(5)
+#define UTMIP_HIGHZ_A BIT(6)
+/* phase B */
+#define UTMIP_USBOP_RPD_B BIT(8)
+#define UTMIP_USBON_RPD_B BIT(9)
+#define UTMIP_AP_B BIT(12)
+#define UTMIP_AN_B BIT(13)
+#define UTMIP_HIGHZ_B BIT(14)
+/* phase C */
+#define UTMIP_USBOP_RPD_C BIT(16)
+#define UTMIP_USBON_RPD_C BIT(17)
+#define UTMIP_AP_C BIT(20)
+#define UTMIP_AN_C BIT(21)
+#define UTMIP_HIGHZ_C BIT(22)
+/* phase D */
+#define UTMIP_USBOP_RPD_D BIT(24)
+#define UTMIP_USBON_RPD_D BIT(25)
+#define UTMIP_AP_D BIT(28)
+#define UTMIP_AN_D BIT(29)
+#define UTMIP_HIGHZ_D BIT(30)
+
+#define PMC_UTMIP_UHSIC_LINE_WAKEUP (0x26c)
+#define UTMIP_LINE_WAKEUP_EN(x) UTMIP(x, BIT(x), BIT(4))
+#define UHSIC_LINE_WAKEUP_EN BIT(3)
+
+#define PMC_UTMIP_TERM_PAD_CFG (0x1f8)
+#define PCTRL_VAL(x) (((x) & 0x3f) << 1)
+#define TCTRL_VAL(x) (((x) & 0x3f) << 7)
+
+#define PMC_UTMIP_PAD_CFGX(x) (0x4c0 + (4 * (x)))
+#define RPD_CTRL_PX(x) (((x) & 0x1f) << 22)
+
+#define PMC_UHSIC_SLEEP_CFG PMC_UTMIP_UHSIC_SLEEP_CFG(0)
+#define UHSIC_MASTER_ENABLE BIT(24)
+#define UHSIC_WAKE_VAL(_value) (((_value) & 0xf) << 28)
+#define UHSIC_WAKE_VAL_SD10 UHSIC_WAKE_VAL(2)
+#define UHSIC_WAKE_VAL_NONE UHSIC_WAKE_VAL(12)
+
+#define PMC_UHSIC_FAKE PMC_UTMIP_UHSIC_FAKE(0)
+#define UHSIC_FAKE_STROBE_VAL BIT(12)
+#define UHSIC_FAKE_DATA_VAL BIT(13)
+#define UHSIC_FAKE_STROBE_EN BIT(14)
+#define UHSIC_FAKE_DATA_EN BIT(15)
+
+#define PMC_UHSIC_SAVED_STATE PMC_UTMIP_UHSIC_SAVED_STATE(0)
+#define UHSIC_MODE(_value) (((_value) & 0x1) << 24)
+#define UHSIC_HS UHSIC_MODE(0)
+#define UHSIC_RST UHSIC_MODE(1)
+
+#define PMC_UHSIC_SLEEPWALK_CFG PMC_UTMIP_UHSIC_SLEEPWALK_CFG(0)
+#define UHSIC_WAKE_WALK_EN BIT(30)
+#define UHSIC_LINEVAL_WALK_EN BIT(31)
+
+#define PMC_UHSIC_SLEEPWALK_P0 (0x210)
+#define UHSIC_DATA0_RPD_A BIT(1)
+#define UHSIC_DATA0_RPU_B BIT(11)
+#define UHSIC_DATA0_RPU_C BIT(19)
+#define UHSIC_DATA0_RPU_D BIT(27)
+#define UHSIC_STROBE_RPU_A BIT(2)
+#define UHSIC_STROBE_RPD_B BIT(8)
+#define UHSIC_STROBE_RPD_C BIT(16)
+#define UHSIC_STROBE_RPD_D BIT(24)
+
struct tegra210_xusb_fuse_calibration {
u32 hs_curr_level[4];
u32 hs_term_range_adj;
u32 rpd_ctrl;
};
+struct tegra210_xusb_padctl_context {
+ u32 usb2_pad_mux;
+ u32 usb2_port_cap;
+ u32 ss_port_map;
+ u32 usb3_pad_mux;
+};
+
struct tegra210_xusb_padctl {
struct tegra_xusb_padctl base;
struct tegra210_xusb_fuse_calibration fuse;
+ struct tegra210_xusb_padctl_context context;
+ struct regmap *pmc_reg;
};
static inline struct tegra210_xusb_padctl *
@@ -886,6 +1051,671 @@ static int tegra210_hsic_set_idle(struct tegra_xusb_padctl *padctl,
return 0;
}
+static int tegra210_usb3_enable_phy_sleepwalk(struct phy *phy)
+{
+ struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
+ struct tegra_xusb_padctl *padctl = lane->pad->padctl;
+ int port = tegra210_usb3_lane_map(lane);
+ struct device *dev = padctl->dev;
+ u32 value;
+
+ if (port < 0) {
+ dev_err(dev, "invalid usb3 port number\n");
+ return -EINVAL;
+ }
+
+ dev_dbg(dev, "phy enable sleepwalk usb3 %d\n", port);
+
+ mutex_lock(&padctl->lock);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
+ value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(port);
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
+
+ usleep_range(100, 200);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
+ value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(port);
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
+
+ usleep_range(250, 350);
+
+ mutex_unlock(&padctl->lock);
+
+ return 0;
+}
+
+static int tegra210_usb3_disable_phy_sleepwalk(struct phy *phy)
+{
+ struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
+ struct tegra_xusb_padctl *padctl = lane->pad->padctl;
+ int port = tegra210_usb3_lane_map(lane);
+ struct device *dev = padctl->dev;
+ u32 value;
+
+ if (port < 0) {
+ dev_err(dev, "invalid usb3 port number\n");
+ return -EINVAL;
+ }
+
+ dev_dbg(dev, "phy disable sleepwalk usb3 %d\n", port);
+
+ mutex_lock(&padctl->lock);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
+ value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(port);
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
+
+ usleep_range(100, 200);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
+ value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(port);
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
+
+ mutex_unlock(&padctl->lock);
+
+ return 0;
+}
+
+static int tegra210_usb3_enable_phy_wake(struct phy *phy)
+{
+ struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
+ struct tegra_xusb_padctl *padctl = lane->pad->padctl;
+ int port = tegra210_usb3_lane_map(lane);
+ struct device *dev = padctl->dev;
+ u32 value;
+
+ if (port < 0) {
+ dev_err(dev, "invalid usb3 port number\n");
+ return -EINVAL;
+ }
+
+ dev_dbg(dev, "phy enable wake usb3 %d\n", port);
+
+ mutex_lock(&padctl->lock);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
+ value &= ~ALL_WAKE_EVENTS;
+ value |= SS_PORT_WAKEUP_EVENT(port);
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);
+
+ usleep_range(10, 20);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
+ value &= ~ALL_WAKE_EVENTS;
+ value |= SS_PORT_WAKE_INTERRUPT_ENABLE(port);
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);
+
+ mutex_unlock(&padctl->lock);
+
+ return 0;
+}
+
+static int tegra210_usb3_disable_phy_wake(struct phy *phy)
+{
+ struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
+ struct tegra_xusb_padctl *padctl = lane->pad->padctl;
+ int port = tegra210_usb3_lane_map(lane);
+ struct device *dev = padctl->dev;
+ u32 value;
+
+ if (port < 0) {
+ dev_err(dev, "invalid usb3 port number\n");
+ return -EINVAL;
+ }
+
+ dev_dbg(dev, "phy disable wake usb3 %d\n", port);
+
+ mutex_lock(&padctl->lock);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
+ value &= ~ALL_WAKE_EVENTS;
+ value &= ~SS_PORT_WAKE_INTERRUPT_ENABLE(port);
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);
+
+ usleep_range(10, 20);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
+ value &= ~ALL_WAKE_EVENTS;
+ value |= SS_PORT_WAKEUP_EVENT(port);
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);
+
+ mutex_unlock(&padctl->lock);
+
+ return 0;
+}
+
+static int tegra210_utmi_enable_phy_wake(struct phy *phy)
+{
+ struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
+ struct tegra_xusb_padctl *padctl = lane->pad->padctl;
+ unsigned int index = lane->index;
+ struct device *dev = padctl->dev;
+ u32 value;
+
+ dev_dbg(dev, "phy enable wake on usb2 %d\n", index);
+
+ mutex_lock(&padctl->lock);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
+ value &= ~ALL_WAKE_EVENTS;
+ value |= USB2_PORT_WAKEUP_EVENT(index);
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);
+
+ usleep_range(10, 20);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
+ value &= ~ALL_WAKE_EVENTS;
+ value |= USB2_PORT_WAKE_INTERRUPT_ENABLE(index);
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);
+
+ mutex_unlock(&padctl->lock);
+
+ return 0;
+}
+
+static int tegra210_utmi_disable_phy_wake(struct phy *phy)
+{
+ struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
+ struct tegra_xusb_padctl *padctl = lane->pad->padctl;
+ unsigned int index = lane->index;
+ struct device *dev = padctl->dev;
+ u32 value;
+
+ dev_dbg(dev, "phy disable wake on usb2 %d\n", index);
+
+ mutex_lock(&padctl->lock);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
+ value &= ~ALL_WAKE_EVENTS;
+ value &= ~USB2_PORT_WAKE_INTERRUPT_ENABLE(index);
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);
+
+ usleep_range(10, 20);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
+ value &= ~ALL_WAKE_EVENTS;
+ value |= USB2_PORT_WAKEUP_EVENT(index);
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);
+
+ mutex_unlock(&padctl->lock);
+
+ return 0;
+}
+
+static int tegra210_hsic_enable_phy_wake(struct phy *phy)
+{
+ struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
+ struct tegra_xusb_padctl *padctl = lane->pad->padctl;
+ unsigned int index = lane->index;
+ struct device *dev = padctl->dev;
+ u32 value;
+
+ dev_dbg(dev, "phy enable wake on hsic %d\n", index);
+
+ mutex_lock(&padctl->lock);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
+ value &= ~ALL_WAKE_EVENTS;
+ value |= USB2_HSIC_PORT_WAKEUP_EVENT(index);
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);
+
+ usleep_range(10, 20);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
+ value &= ~ALL_WAKE_EVENTS;
+ value |= USB2_HSIC_PORT_WAKE_INTERRUPT_ENABLE(index);
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);
+
+ mutex_unlock(&padctl->lock);
+
+ return 0;
+}
+
+static int tegra210_hsic_disable_phy_wake(struct phy *phy)
+{
+ struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
+ struct tegra_xusb_padctl *padctl = lane->pad->padctl;
+ unsigned int index = lane->index;
+ struct device *dev = padctl->dev;
+ u32 value;
+
+ dev_dbg(dev, "phy disable wake on hsic %d\n", index);
+
+ mutex_lock(&padctl->lock);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
+ value &= ~ALL_WAKE_EVENTS;
+ value &= ~USB2_HSIC_PORT_WAKE_INTERRUPT_ENABLE(index);
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);
+
+ usleep_range(10, 20);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
+ value &= ~ALL_WAKE_EVENTS;
+ value |= USB2_HSIC_PORT_WAKEUP_EVENT(index);
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);
+
+ mutex_unlock(&padctl->lock);
+
+ return 0;
+}
+
+static int tegra210_usb3_phy_remote_wake_detected(
+ struct tegra_xusb_padctl *padctl, int port)
+{
+ u32 value;
+
+ if (port < 0) {
+ dev_err(padctl->dev, "invalid usb3 port number %d\n",
+ port);
+ return false;
+ }
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
+ if ((value & SS_PORT_WAKE_INTERRUPT_ENABLE(port)) &&
+ (value & SS_PORT_WAKEUP_EVENT(port)))
+ return true;
+ else
+ return false;
+}
+
+static int tegra210_utmi_phy_remote_wake_detected(
+ struct tegra_xusb_padctl *padctl, int port)
+{
+ u32 value;
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
+ if ((value & USB2_PORT_WAKE_INTERRUPT_ENABLE(port)) &&
+ (value & USB2_PORT_WAKEUP_EVENT(port)))
+ return true;
+ else
+ return false;
+}
+
+static int tegra210_hsic_phy_remote_wake_detected(
+ struct tegra_xusb_padctl *padctl, int port)
+{
+ u32 value;
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
+ if ((value & USB2_HSIC_PORT_WAKE_INTERRUPT_ENABLE(port)) &&
+ (value & USB2_HSIC_PORT_WAKEUP_EVENT(port)))
+ return true;
+ else
+ return false;
+}
+
+#define padctl_pmc_readl(_priv, _offset) \
+({ \
+ int rc; \
+ u32 val; \
+ rc = regmap_read(_priv->pmc_reg, _offset, &val); \
+ if (rc) \
+ return rc; \
+ val; \
+})
+
+#define padctl_pmc_writel(_priv, _val, _offset) \
+do { \
+ int rc; \
+ rc = regmap_write(_priv->pmc_reg, _offset, _val); \
+ if (rc) \
+ return rc; \
+} while (0)
+
+/* T210 USB2 SLEEPWALK APIs */
+int tegra_pmc_utmi_enable_phy_sleepwalk(struct phy *phy,
+ enum usb_device_speed speed)
+{
+ struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
+ struct tegra_xusb_padctl *padctl = lane->pad->padctl;
+ struct tegra210_xusb_padctl *priv = to_tegra210_xusb_padctl(padctl);
+ struct device *dev = padctl->dev;
+ unsigned int port = lane->index;
+ u32 val, tctrl, pctrl, rpd_ctrl;
+
+ if (speed > USB_SPEED_HIGH)
+ return -EINVAL;
+
+ dev_dbg(dev, "phy enable sleepwalk usb2 %d speed %d\n", port, speed);
+
+ val = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
+ tctrl = TCTRL_VALUE(val);
+ pctrl = PCTRL_VALUE(val);
+
+ val = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(port));
+ rpd_ctrl = RPD_CTRL_VALUE(val);
+
+ /* ensure sleepwalk logic is disabled */
+ val = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
+ val &= ~UTMIP_MASTER_ENABLE(port);
+ padctl_pmc_writel(priv, val, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
+
+ /* ensure sleepwalk logics are in low power mode */
+ val = padctl_pmc_readl(priv, PMC_UTMIP_MASTER_CONFIG);
+ val |= UTMIP_PWR(port);
+ padctl_pmc_writel(priv, val, PMC_UTMIP_MASTER_CONFIG);
+
+ /* set debounce time */
+ val = padctl_pmc_readl(priv, PMC_USB_DEBOUNCE_DEL);
+ val &= ~UTMIP_LINE_DEB_CNT(~0);
+ val |= UTMIP_LINE_DEB_CNT(0x1);
+ padctl_pmc_writel(priv, val, PMC_USB_DEBOUNCE_DEL);
+
+ /* ensure fake events of sleepwalk logic are desiabled */
+ val = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_FAKE(port));
+ val &= ~(UTMIP_FAKE_USBOP_VAL(port) | UTMIP_FAKE_USBON_VAL(port) |
+ UTMIP_FAKE_USBOP_EN(port) | UTMIP_FAKE_USBON_EN(port));
+ padctl_pmc_writel(priv, val, PMC_UTMIP_UHSIC_FAKE(port));
+
+ /* ensure wake events of sleepwalk logic are not latched */
+ val = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_LINE_WAKEUP);
+ val &= ~UTMIP_LINE_WAKEUP_EN(port);
+ padctl_pmc_writel(priv, val, PMC_UTMIP_UHSIC_LINE_WAKEUP);
+
+ /* disable wake event triggers of sleepwalk logic */
+ val = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
+ val &= ~UTMIP_WAKE_VAL(port, ~0);
+ val |= UTMIP_WAKE_VAL_NONE(port);
+ padctl_pmc_writel(priv, val, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
+
+ /* power down the line state detectors of the pad */
+ val = padctl_pmc_readl(priv, PMC_USB_AO);
+ val |= (USBOP_VAL_PD(port) | USBON_VAL_PD(port));
+ padctl_pmc_writel(priv, val, PMC_USB_AO);
+
+ /* save state per speed */
+ val = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SAVED_STATE(port));
+ val &= ~SPEED(port, ~0);
+ if (speed == USB_SPEED_HIGH)
+ val |= UTMI_HS(port);
+ else if (speed == USB_SPEED_FULL)
+ val |= UTMI_FS(port);
+ else if (speed == USB_SPEED_LOW)
+ val |= UTMI_LS(port);
+ else
+ val |= UTMI_RST(port);
+ padctl_pmc_writel(priv, val, PMC_UTMIP_UHSIC_SAVED_STATE(port));
+
+ /* enable the trigger of the sleepwalk logic */
+ val = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEPWALK_CFG(port));
+ val |= UTMIP_LINEVAL_WALK_EN(port);
+ padctl_pmc_writel(priv, val, PMC_UTMIP_UHSIC_SLEEPWALK_CFG(port));
+
+ /* reset the walk pointer and clear the alarm of the sleepwalk logic,
+ * as well as capture the configuration of the USB2.0 pad
+ */
+ val = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_TRIGGERS);
+ val |= (UTMIP_CLR_WALK_PTR(port) | UTMIP_CLR_WAKE_ALARM(port) |
+ UTMIP_CAP_CFG(port));
+ padctl_pmc_writel(priv, val, PMC_UTMIP_UHSIC_TRIGGERS);
+
+ /* program electrical parameters read from XUSB PADCTL */
+ val = padctl_pmc_readl(priv, PMC_UTMIP_TERM_PAD_CFG);
+ val &= ~(TCTRL_VAL(~0) | PCTRL_VAL(~0));
+ val |= (TCTRL_VAL(tctrl) | PCTRL_VAL(pctrl));
+ padctl_pmc_writel(priv, val, PMC_UTMIP_TERM_PAD_CFG);
+
+ val = padctl_pmc_readl(priv, PMC_UTMIP_PAD_CFGX(port));
+ val &= ~RPD_CTRL_PX(~0);
+ val |= RPD_CTRL_PX(rpd_ctrl);
+ padctl_pmc_writel(priv, val, PMC_UTMIP_PAD_CFGX(port));
+
+ /* setup the pull-ups and pull-downs of the signals during the four
+ * stages of sleepwalk.
+ * if device is connected, program sleepwalk logic to maintain a J and
+ * keep driving K upon seeing remote wake.
+ */
+ val = padctl_pmc_readl(priv, PMC_UTMIP_SLEEPWALK_PX(port));
+ val = (UTMIP_USBOP_RPD_A | UTMIP_USBOP_RPD_B | UTMIP_USBOP_RPD_C |
+ UTMIP_USBOP_RPD_D);
+ val |= (UTMIP_USBON_RPD_A | UTMIP_USBON_RPD_B | UTMIP_USBON_RPD_C |
+ UTMIP_USBON_RPD_D);
+ if (speed == USB_SPEED_UNKNOWN) {
+ val |= (UTMIP_HIGHZ_A | UTMIP_HIGHZ_B | UTMIP_HIGHZ_C |
+ UTMIP_HIGHZ_D);
+ } else if ((speed == USB_SPEED_HIGH) || (speed == USB_SPEED_FULL)) {
+ /* J state: D+/D- = high/low, K state: D+/D- = low/high */
+ val |= UTMIP_HIGHZ_A;
+ val |= UTMIP_AP_A;
+ val |= (UTMIP_AN_B | UTMIP_AN_C | UTMIP_AN_D);
+ } else if (speed == USB_SPEED_LOW) {
+ /* J state: D+/D- = low/high, K state: D+/D- = high/low */
+ val |= UTMIP_HIGHZ_A;
+ val |= UTMIP_AN_A;
+ val |= (UTMIP_AP_B | UTMIP_AP_C | UTMIP_AP_D);
+ }
+ padctl_pmc_writel(priv, val, PMC_UTMIP_SLEEPWALK_PX(port));
+
+ /* power up the line state detectors of the pad */
+ val = padctl_pmc_readl(priv, PMC_USB_AO);
+ val &= ~(USBOP_VAL_PD(port) | USBON_VAL_PD(port));
+ padctl_pmc_writel(priv, val, PMC_USB_AO);
+
+ usleep_range(50, 100);
+
+ /* switch the electric control of the USB2.0 pad to PMC */
+ val = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
+ val |= (UTMIP_FSLS_USE_PMC(port) | UTMIP_PCTRL_USE_PMC(port) |
+ UTMIP_TCTRL_USE_PMC(port));
+ padctl_pmc_writel(priv, val, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
+
+ val = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG1);
+ val |= (UTMIP_RPD_CTRL_USE_PMC_PX(port) |
+ UTMIP_RPU_SWITC_LOW_USE_PMC_PX(port));
+ padctl_pmc_writel(priv, val, PMC_UTMIP_UHSIC_SLEEP_CFG1);
+
+ /* set the wake signaling trigger events */
+ val = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
+ val &= ~UTMIP_WAKE_VAL(port, ~0);
+ val |= UTMIP_WAKE_VAL_ANY(port);
+ padctl_pmc_writel(priv, val, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
+
+ /* enable the wake detection */
+ val = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
+ val |= UTMIP_MASTER_ENABLE(port);
+ padctl_pmc_writel(priv, val, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
+
+ val = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_LINE_WAKEUP);
+ val |= UTMIP_LINE_WAKEUP_EN(port);
+ padctl_pmc_writel(priv, val, PMC_UTMIP_UHSIC_LINE_WAKEUP);
+
+ return 0;
+}
+
+int tegra_pmc_utmi_disable_phy_sleepwalk(struct phy *phy)
+{
+ struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
+ struct tegra_xusb_padctl *padctl = lane->pad->padctl;
+ struct tegra210_xusb_padctl *priv = to_tegra210_xusb_padctl(padctl);
+ struct device *dev = padctl->dev;
+ unsigned int port = lane->index;
+ u32 value;
+
+ dev_dbg(dev, "phy disable sleepwalk usb2 %d\n", port);
+
+ /* disable the wake detection */
+ value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
+ value &= ~UTMIP_MASTER_ENABLE(port);
+ padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
+
+ value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_LINE_WAKEUP);
+ value &= ~UTMIP_LINE_WAKEUP_EN(port);
+ padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_LINE_WAKEUP);
+
+ /* switch the electric control of the USB2.0 pad to XUSB or USB2 */
+ value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
+ value &= ~(UTMIP_FSLS_USE_PMC(port) | UTMIP_PCTRL_USE_PMC(port) |
+ UTMIP_TCTRL_USE_PMC(port));
+ padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
+
+ value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG1);
+ value &= ~(UTMIP_RPD_CTRL_USE_PMC_PX(port) |
+ UTMIP_RPU_SWITC_LOW_USE_PMC_PX(port));
+ padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG1);
+
+ /* disable wake event triggers of sleepwalk logic */
+ value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
+ value &= ~UTMIP_WAKE_VAL(port, ~0);
+ value |= UTMIP_WAKE_VAL_NONE(port);
+ padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
+
+ /* power down the line state detectors of the port */
+ value = padctl_pmc_readl(priv, PMC_USB_AO);
+ value |= (USBOP_VAL_PD(port) | USBON_VAL_PD(port));
+ padctl_pmc_writel(priv, value, PMC_USB_AO);
+
+ /* clear alarm of the sleepwalk logic */
+ value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_TRIGGERS);
+ value |= UTMIP_CLR_WAKE_ALARM(port);
+ padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_TRIGGERS);
+
+ return 0;
+}
+
+int tegra_pmc_hsic_enable_phy_sleepwalk(struct phy *phy)
+{
+ struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
+ struct tegra_xusb_padctl *padctl = lane->pad->padctl;
+ struct tegra210_xusb_padctl *priv = to_tegra210_xusb_padctl(padctl);
+ struct device *dev = padctl->dev;
+ unsigned int port = lane->index;
+ u32 value;
+
+ dev_dbg(dev, "phy enable sleepwalk hsic %d\n", port);
+
+ /* ensure sleepwalk logic is disabled */
+ value = padctl_pmc_readl(priv, PMC_UHSIC_SLEEP_CFG);
+ value &= ~UHSIC_MASTER_ENABLE;
+ padctl_pmc_writel(priv, value, PMC_UHSIC_SLEEP_CFG);
+
+ /* ensure sleepwalk logics are in low power mode */
+ value = padctl_pmc_readl(priv, PMC_UTMIP_MASTER_CONFIG);
+ value |= UHSIC_PWR(port);
+ padctl_pmc_writel(priv, value, PMC_UTMIP_MASTER_CONFIG);
+
+ /* set debounce time */
+ value = padctl_pmc_readl(priv, PMC_USB_DEBOUNCE_DEL);
+ value &= ~UHSIC_LINE_DEB_CNT(~0);
+ value |= UHSIC_LINE_DEB_CNT(0x1);
+ padctl_pmc_writel(priv, value, PMC_USB_DEBOUNCE_DEL);
+
+ /* ensure fake events of sleepwalk logic are desiabled */
+ value = padctl_pmc_readl(priv, PMC_UHSIC_FAKE);
+ value &= ~(UHSIC_FAKE_STROBE_VAL | UHSIC_FAKE_DATA_VAL |
+ UHSIC_FAKE_STROBE_EN | UHSIC_FAKE_DATA_EN);
+ padctl_pmc_writel(priv, value, PMC_UHSIC_FAKE);
+
+ /* ensure wake events of sleepwalk logic are not latched */
+ value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_LINE_WAKEUP);
+ value &= ~UHSIC_LINE_WAKEUP_EN;
+ padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_LINE_WAKEUP);
+
+ /* disable wake event triggers of sleepwalk logic */
+ value = padctl_pmc_readl(priv, PMC_UHSIC_SLEEP_CFG);
+ value &= ~UHSIC_WAKE_VAL(~0);
+ value |= UHSIC_WAKE_VAL_NONE;
+ padctl_pmc_writel(priv, value, PMC_UHSIC_SLEEP_CFG);
+
+ /* power down the line state detectors of the port */
+ value = padctl_pmc_readl(priv, PMC_USB_AO);
+ value |= (STROBE_VAL_PD(port) | DATA0_VAL_PD(port) | DATA1_VAL_PD);
+ padctl_pmc_writel(priv, value, PMC_USB_AO);
+
+ /* save state, HSIC always comes up as HS */
+ value = padctl_pmc_readl(priv, PMC_UHSIC_SAVED_STATE);
+ value &= ~UHSIC_MODE(~0);
+ value |= UHSIC_HS;
+ padctl_pmc_writel(priv, value, PMC_UHSIC_SAVED_STATE);
+
+ /* enable the trigger of the sleepwalk logic */
+ value = padctl_pmc_readl(priv, PMC_UHSIC_SLEEPWALK_CFG);
+ value |= (UHSIC_WAKE_WALK_EN | UHSIC_LINEVAL_WALK_EN);
+ padctl_pmc_writel(priv, value, PMC_UHSIC_SLEEPWALK_CFG);
+
+ /* reset the walk pointer and clear the alarm of the sleepwalk logic,
+ * as well as capture the configuration of the USB2.0 port
+ */
+ value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_TRIGGERS);
+ value |= (UHSIC_CLR_WALK_PTR | UHSIC_CLR_WAKE_ALARM);
+ padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_TRIGGERS);
+
+ /* setup the pull-ups and pull-downs of the signals during the four
+ * stages of sleepwalk.
+ * maintain a HSIC IDLE and keep driving HSIC RESUME upon remote wake
+ */
+ value = padctl_pmc_readl(priv, PMC_UHSIC_SLEEPWALK_P0);
+ value = (UHSIC_DATA0_RPD_A | UHSIC_DATA0_RPU_B | UHSIC_DATA0_RPU_C |
+ UHSIC_DATA0_RPU_D);
+ value |= (UHSIC_STROBE_RPU_A | UHSIC_STROBE_RPD_B | UHSIC_STROBE_RPD_C |
+ UHSIC_STROBE_RPD_D);
+ padctl_pmc_writel(priv, value, PMC_UHSIC_SLEEPWALK_P0);
+
+ /* power up the line state detectors of the port */
+ value = padctl_pmc_readl(priv, PMC_USB_AO);
+ value &= ~(STROBE_VAL_PD(port) | DATA0_VAL_PD(port) | DATA1_VAL_PD);
+ padctl_pmc_writel(priv, value, PMC_USB_AO);
+
+ usleep_range(50, 100);
+
+ /* set the wake signaling trigger events */
+ value = padctl_pmc_readl(priv, PMC_UHSIC_SLEEP_CFG);
+ value &= ~UHSIC_WAKE_VAL(~0);
+ value |= UHSIC_WAKE_VAL_SD10;
+ padctl_pmc_writel(priv, value, PMC_UHSIC_SLEEP_CFG);
+
+ /* enable the wake detection */
+ value = padctl_pmc_readl(priv, PMC_UHSIC_SLEEP_CFG);
+ value |= UHSIC_MASTER_ENABLE;
+ padctl_pmc_writel(priv, value, PMC_UHSIC_SLEEP_CFG);
+
+ value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_LINE_WAKEUP);
+ value |= UHSIC_LINE_WAKEUP_EN;
+ padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_LINE_WAKEUP);
+
+ return 0;
+}
+
+int tegra_pmc_hsic_disable_phy_sleepwalk(struct phy *phy)
+{
+ struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
+ struct tegra_xusb_padctl *padctl = lane->pad->padctl;
+ struct tegra210_xusb_padctl *priv = to_tegra210_xusb_padctl(padctl);
+ struct device *dev = padctl->dev;
+ unsigned int port = lane->index;
+ u32 value;
+
+ dev_dbg(dev, "phy disable sleepwalk hsic %d\n", port);
+
+ /* disable the wake detection */
+ value = padctl_pmc_readl(priv, PMC_UHSIC_SLEEP_CFG);
+ value &= ~UHSIC_MASTER_ENABLE;
+ padctl_pmc_writel(priv, value, PMC_UHSIC_SLEEP_CFG);
+
+ value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_LINE_WAKEUP);
+ value &= ~UHSIC_LINE_WAKEUP_EN;
+ padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_LINE_WAKEUP);
+
+ /* disable wake event triggers of sleepwalk logic */
+ value = padctl_pmc_readl(priv, PMC_UHSIC_SLEEP_CFG);
+ value &= ~UHSIC_WAKE_VAL(~0);
+ value |= UHSIC_WAKE_VAL_NONE;
+ padctl_pmc_writel(priv, value, PMC_UHSIC_SLEEP_CFG);
+
+ /* power down the line state detectors of the port */
+ value = padctl_pmc_readl(priv, PMC_USB_AO);
+ value |= (STROBE_VAL_PD(port) | DATA0_VAL_PD(port) | DATA1_VAL_PD);
+ padctl_pmc_writel(priv, value, PMC_USB_AO);
+
+ /* clear alarm of the sleepwalk logic */
+ value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_TRIGGERS);
+ value |= UHSIC_CLR_WAKE_ALARM;
+ padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_TRIGGERS);
+
+ return 0;
+}
+
static int tegra210_usb3_set_lfps_detect(struct tegra_xusb_padctl *padctl,
unsigned int index, bool enable)
{
@@ -988,8 +1818,23 @@ static int tegra210_usb2_phy_init(struct phy *phy)
{
struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
struct tegra_xusb_padctl *padctl = lane->pad->padctl;
+ unsigned int index = lane->index;
+ struct tegra_xusb_usb2_port *port;
+ int err;
u32 value;
+ port = tegra_xusb_find_usb2_port(padctl, index);
+ if (!port) {
+ dev_err(&phy->dev, "no port found for USB2 lane %u\n", index);
+ return -ENODEV;
+ }
+
+ err = regulator_enable(port->supply);
+ if (err)
+ return err;
+
+ mutex_lock(&padctl->lock);
+
value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX);
value &= ~(XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_MASK <<
XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_SHIFT);
@@ -997,11 +1842,29 @@ static int tegra210_usb2_phy_init(struct phy *phy)
XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_SHIFT;
padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX);
+ mutex_unlock(&padctl->lock);
+
return 0;
}
static int tegra210_usb2_phy_exit(struct phy *phy)
{
+ struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
+ struct tegra_xusb_padctl *padctl = lane->pad->padctl;
+ unsigned int index = lane->index;
+ struct tegra_xusb_usb2_port *port;
+ int err;
+
+ port = tegra_xusb_find_usb2_port(padctl, index);
+ if (!port) {
+ dev_err(&phy->dev, "no port found for USB2 lane %u\n", index);
+ return -ENODEV;
+ }
+
+ err = regulator_disable(port->supply);
+ if (err)
+ return err;
+
return 0;
}
@@ -1122,6 +1985,8 @@ static int tegra210_usb2_phy_power_on(struct phy *phy)
priv = to_tegra210_xusb_padctl(padctl);
+ mutex_lock(&padctl->lock);
+
if (port->usb3_port_fake != -1) {
value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP);
value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(
@@ -1215,14 +2080,6 @@ static int tegra210_usb2_phy_power_on(struct phy *phy)
padctl_writel(padctl, value,
XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL1(index));
- if (port->supply && port->mode == USB_DR_MODE_HOST) {
- err = regulator_enable(port->supply);
- if (err)
- return err;
- }
-
- mutex_lock(&padctl->lock);
-
if (pad->enable > 0) {
pad->enable++;
mutex_unlock(&padctl->lock);
@@ -1231,7 +2088,7 @@ static int tegra210_usb2_phy_power_on(struct phy *phy)
err = clk_prepare_enable(pad->clk);
if (err)
- goto disable_regulator;
+ goto out;
value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
value &= ~((XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_MASK <<
@@ -1263,8 +2120,7 @@ static int tegra210_usb2_phy_power_on(struct phy *phy)
return 0;
-disable_regulator:
- regulator_disable(port->supply);
+out:
mutex_unlock(&padctl->lock);
return err;
}
@@ -1275,12 +2131,12 @@ static int tegra210_usb2_phy_power_off(struct phy *phy)
struct tegra_xusb_usb2_pad *pad = to_usb2_pad(lane->pad);
struct tegra_xusb_padctl *padctl = lane->pad->padctl;
struct tegra_xusb_usb2_port *port;
+ unsigned int index = lane->index;
u32 value;
- port = tegra_xusb_find_usb2_port(padctl, lane->index);
+ port = tegra_xusb_find_usb2_port(padctl, index);
if (!port) {
- dev_err(&phy->dev, "no port found for USB2 lane %u\n",
- lane->index);
+ dev_err(&phy->dev, "no port found for USB2 lane %u\n", index);
return -ENODEV;
}
@@ -1318,12 +2174,19 @@ static int tegra210_usb2_phy_power_off(struct phy *phy)
if (--pad->enable > 0)
goto out;
+ value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
+ value |= XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD;
+ padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
+
+ value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
+ value |= XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR;
+ padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
+
value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
value |= XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD;
padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
out:
- regulator_disable(port->supply);
mutex_unlock(&padctl->lock);
return 0;
}
@@ -2120,6 +2983,120 @@ static const struct phy_ops tegra210_sata_phy_ops = {
.owner = THIS_MODULE,
};
+static inline bool is_usb3_phy(struct phy *phy)
+{
+ return (phy->ops == &tegra210_pcie_phy_ops ||
+ phy->ops == &tegra210_sata_phy_ops);
+}
+
+static inline bool is_hsic_phy(struct phy *phy)
+{
+ return phy->ops == &tegra210_hsic_phy_ops;
+}
+
+static inline bool is_utmi_phy(struct phy *phy)
+{
+ return phy->ops == &tegra210_usb2_phy_ops;
+}
+
+static int
+tegra210_xusb_padctl_enable_phy_wake(struct tegra_xusb_padctl *padctl,
+ struct phy *phy)
+{
+ if (!phy)
+ return 0;
+
+ if (is_usb3_phy(phy))
+ return tegra210_usb3_enable_phy_wake(phy);
+ else if (is_utmi_phy(phy))
+ return tegra210_utmi_enable_phy_wake(phy);
+ else if (is_hsic_phy(phy))
+ return tegra210_hsic_enable_phy_wake(phy);
+ else
+ return -EINVAL;
+}
+
+static int
+tegra210_xusb_padctl_disable_phy_wake(struct tegra_xusb_padctl *padctl,
+ struct phy *phy)
+{
+ if (!phy)
+ return 0;
+
+ if (is_usb3_phy(phy))
+ return tegra210_usb3_disable_phy_wake(phy);
+ else if (is_utmi_phy(phy))
+ return tegra210_utmi_disable_phy_wake(phy);
+ else if (is_hsic_phy(phy))
+ return tegra210_hsic_disable_phy_wake(phy);
+ else
+ return -EINVAL;
+}
+
+int tegra210_xusb_padctl_remote_wake_detected(struct phy *phy)
+{
+ struct tegra_xusb_lane *lane;
+ struct tegra_xusb_padctl *padctl;
+
+ if (!phy)
+ return 0;
+
+ lane = phy_get_drvdata(phy);
+ padctl = lane->pad->padctl;
+
+ if (is_utmi_phy(phy))
+ return tegra210_utmi_phy_remote_wake_detected(padctl,
+ lane->index);
+ else if (is_hsic_phy(phy))
+ return tegra210_hsic_phy_remote_wake_detected(padctl,
+ lane->index);
+ else if (is_usb3_phy(phy))
+ return tegra210_usb3_phy_remote_wake_detected(padctl,
+ tegra210_usb3_lane_map(lane));
+
+ return -EINVAL;
+}
+
+static int
+tegra210_xusb_padctl_enable_phy_sleepwalk(struct tegra_xusb_padctl *padctl,
+ struct phy *phy,
+ enum usb_device_speed speed)
+{
+ if (!phy)
+ return 0;
+
+ if (is_usb3_phy(phy))
+ return tegra210_usb3_enable_phy_sleepwalk(phy);
+ else if (is_utmi_phy(phy))
+ return tegra_pmc_utmi_enable_phy_sleepwalk(phy, speed);
+ else if (is_hsic_phy(phy))
+ return tegra_pmc_hsic_enable_phy_sleepwalk(phy);
+ else
+ return -EINVAL;
+
+ return 0;
+}
+
+static int
+tegra210_xusb_padctl_disable_phy_sleepwalk(struct tegra_xusb_padctl *padctl,
+ struct phy *phy)
+{
+ if (!phy)
+ return 0;
+
+ if (is_usb3_phy(phy))
+ return tegra210_usb3_disable_phy_sleepwalk(phy);
+ else if (is_utmi_phy(phy))
+ return tegra_pmc_utmi_disable_phy_sleepwalk(phy);
+ else if (is_hsic_phy(phy))
+ return tegra_pmc_hsic_disable_phy_sleepwalk(phy);
+ else
+ return -EINVAL;
+
+ return 0;
+}
+
+
static struct tegra_xusb_pad *
tegra210_sata_pad_probe(struct tegra_xusb_padctl *padctl,
const struct tegra_xusb_pad_soc *soc,
@@ -2317,6 +3294,8 @@ tegra210_xusb_padctl_probe(struct device *dev,
const struct tegra_xusb_padctl_soc *soc)
{
struct tegra210_xusb_padctl *padctl;
+ struct device_node *node, *np = dev->of_node;
+ struct platform_device *pmc_dev;
int err;
padctl = devm_kzalloc(dev, sizeof(*padctl), GFP_KERNEL);
@@ -2330,6 +3309,24 @@ tegra210_xusb_padctl_probe(struct device *dev,
if (err < 0)
return ERR_PTR(err);
+ node = of_parse_phandle(np, "nvidia,pmc", 0);
+ if (!node) {
+ dev_err(dev, "nvidia,pmc property is missing\n");
+ return ERR_PTR(-ENODEV);
+ }
+
+ pmc_dev = of_find_device_by_node(node);
+ if (!pmc_dev) {
+ dev_err(dev, "pmc device is not available\n");
+ return ERR_PTR(-ENODEV);
+ }
+
+ padctl->pmc_reg = dev_get_regmap(&pmc_dev->dev, "usb_sleepwalk");
+ if (!padctl->pmc_reg) {
+ dev_err(dev, "pmc regmap is not available.\n");
+ return ERR_PTR(-ENODEV);
+ }
+
return &padctl->base;
}
@@ -2337,13 +3334,80 @@ static void tegra210_xusb_padctl_remove(struct tegra_xusb_padctl *padctl)
{
}
+static void tegra210_xusb_padctl_save(struct tegra_xusb_padctl *padctl)
+{
+ struct tegra210_xusb_padctl *priv = to_tegra210_xusb_padctl(padctl);
+
+ priv->context.usb2_pad_mux =
+ padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX);
+ priv->context.usb2_port_cap =
+ padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP);
+ priv->context.ss_port_map =
+ padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP);
+ priv->context.usb3_pad_mux =
+ padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);
+}
+
+static void tegra210_xusb_padctl_restore(struct tegra_xusb_padctl *padctl)
+{
+ struct tegra210_xusb_padctl *priv = to_tegra210_xusb_padctl(padctl);
+ int i;
+
+ padctl_writel(padctl, priv->context.usb2_pad_mux,
+ XUSB_PADCTL_USB2_PAD_MUX);
+ padctl_writel(padctl, priv->context.usb2_port_cap,
+ XUSB_PADCTL_USB2_PORT_CAP);
+ padctl_writel(padctl, priv->context.ss_port_map,
+ XUSB_PADCTL_SS_PORT_MAP);
+
+ for (i = 0; i <= 7; i ++)
+ tegra210_uphy_lane_iddq_enable(padctl, i);
+
+ padctl_writel(padctl, priv->context.usb3_pad_mux,
+ XUSB_PADCTL_USB3_PAD_MUX);
+
+ for (i = 0; i <= 7; i ++)
+ tegra210_uphy_lane_iddq_disable(padctl, i);
+}
+
+static int tegra210_xusb_padctl_suspend_noirq(struct tegra_xusb_padctl *padctl)
+{
+ mutex_lock(&padctl->lock);
+
+ tegra210_uphy_deinit(padctl);
+
+ tegra210_xusb_padctl_save(padctl);
+
+ mutex_unlock(&padctl->lock);
+ return 0;
+}
+
+static int tegra210_xusb_padctl_resume_noirq(struct tegra_xusb_padctl *padctl)
+{
+ mutex_lock(&padctl->lock);
+
+ tegra210_xusb_padctl_restore(padctl);
+
+ tegra210_uphy_init(padctl);
+
+ mutex_unlock(&padctl->lock);
+ return 0;
+}
+
static const struct tegra_xusb_padctl_ops tegra210_xusb_padctl_ops = {
.probe = tegra210_xusb_padctl_probe,
.remove = tegra210_xusb_padctl_remove,
+ .suspend_noirq = tegra210_xusb_padctl_suspend_noirq,
+ .resume_noirq = tegra210_xusb_padctl_resume_noirq,
.usb3_set_lfps_detect = tegra210_usb3_set_lfps_detect,
.hsic_set_idle = tegra210_hsic_set_idle,
.vbus_override = tegra210_xusb_padctl_vbus_override,
.utmi_port_reset = tegra210_utmi_port_reset,
+ .enable_phy_sleepwalk = tegra210_xusb_padctl_enable_phy_sleepwalk,
+ .disable_phy_sleepwalk = tegra210_xusb_padctl_disable_phy_sleepwalk,
+ .enable_phy_wake = tegra210_xusb_padctl_enable_phy_wake,
+ .disable_phy_wake = tegra210_xusb_padctl_disable_phy_wake,
+ .remote_wake_detected = tegra210_xusb_padctl_remote_wake_detected,
};
static const char * const tegra210_xusb_padctl_supply_names[] = {
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 09/12] phy: tegra: xusb: t186: support wake and sleepwalk
2020-08-28 1:10 [PATCH 00/12] Tegra XHCI controller ELPG support JC Kuo
` (7 preceding siblings ...)
2020-08-28 1:10 ` [PATCH 08/12] phy: tegra: xusb: t210: support wake and sleepwalk JC Kuo
@ 2020-08-28 1:10 ` JC Kuo
2020-08-28 1:10 ` [PATCH 10/12] arm64: tegra210/tegra186/tegra194: XUSB PADCTL irq JC Kuo
` (2 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: JC Kuo @ 2020-08-28 1:10 UTC (permalink / raw)
To: gregkh, thierry.reding, robh, jonathanh, kishon
Cc: linux-tegra, linux-usb, linux-kernel, devicetree, nkristam, JC Kuo
This commit implements Tegra186/Tegra194 XUSB PADCTL/AO wake and
sleepwalk operations.
Signed-off-by: JC Kuo <jckuo@nvidia.com>
---
drivers/phy/tegra/xusb-tegra186.c | 656 ++++++++++++++++++++++++++++++
1 file changed, 656 insertions(+)
diff --git a/drivers/phy/tegra/xusb-tegra186.c b/drivers/phy/tegra/xusb-tegra186.c
index 5d64f69b39a9..ffa6bfb1e1ee 100644
--- a/drivers/phy/tegra/xusb-tegra186.c
+++ b/drivers/phy/tegra/xusb-tegra186.c
@@ -113,6 +113,117 @@
#define ID_OVERRIDE_FLOATING ID_OVERRIDE(8)
#define ID_OVERRIDE_GROUNDED ID_OVERRIDE(0)
+/* XUSB AO registers */
+#define XUSB_AO_USB_DEBOUNCE_DEL (0x4)
+#define UHSIC_LINE_DEB_CNT(x) (((x) & 0xf) << 4)
+#define UTMIP_LINE_DEB_CNT(x) ((x) & 0xf)
+
+#define XUSB_AO_UTMIP_TRIGGERS(x) (0x40 + (x) * 4)
+#define CLR_WALK_PTR (1 << 0)
+#define CAP_CFG (1 << 1)
+#define CLR_WAKE_ALARM (1 << 3)
+
+#define XUSB_AO_UHSIC_TRIGGERS(x) (0x60 + (x) * 4)
+#define HSIC_CLR_WALK_PTR (1 << 0)
+#define HSIC_CLR_WAKE_ALARM (1 << 3)
+#define HSIC_CAP_CFG (1 << 4)
+
+#define XUSB_AO_UTMIP_SAVED_STATE(x) (0x70 + (x) * 4)
+#define SPEED(x) ((x) & 0x3)
+#define UTMI_HS SPEED(0)
+#define UTMI_FS SPEED(1)
+#define UTMI_LS SPEED(2)
+#define UTMI_RST SPEED(3)
+
+#define XUSB_AO_UHSIC_SAVED_STATE(x) (0x90 + (x) * 4)
+#define MODE(x) ((x) & 0x1)
+#define MODE_HS MODE(0)
+#define MODE_RST MODE(1)
+
+#define XUSB_AO_UTMIP_SLEEPWALK_CFG(x) (0xd0 + (x) * 4)
+#define XUSB_AO_UHSIC_SLEEPWALK_CFG(x) (0xf0 + (x) * 4)
+#define FAKE_USBOP_VAL (1 << 0)
+#define FAKE_USBON_VAL (1 << 1)
+#define FAKE_USBOP_EN (1 << 2)
+#define FAKE_USBON_EN (1 << 3)
+#define FAKE_STROBE_VAL (1 << 0)
+#define FAKE_DATA_VAL (1 << 1)
+#define FAKE_STROBE_EN (1 << 2)
+#define FAKE_DATA_EN (1 << 3)
+#define WAKE_WALK_EN (1 << 14)
+#define MASTER_ENABLE (1 << 15)
+#define LINEVAL_WALK_EN (1 << 16)
+#define WAKE_VAL(x) (((x) & 0xf) << 17)
+#define WAKE_VAL_NONE WAKE_VAL(12)
+#define WAKE_VAL_ANY WAKE_VAL(15)
+#define WAKE_VAL_DS10 WAKE_VAL(2)
+#define LINE_WAKEUP_EN (1 << 21)
+#define MASTER_CFG_SEL (1 << 22)
+
+#define XUSB_AO_UTMIP_SLEEPWALK(x) (0x100 + (x) * 4)
+/* phase A */
+#define USBOP_RPD_A (1 << 0)
+#define USBON_RPD_A (1 << 1)
+#define AP_A (1 << 4)
+#define AN_A (1 << 5)
+#define HIGHZ_A (1 << 6)
+/* phase B */
+#define USBOP_RPD_B (1 << 8)
+#define USBON_RPD_B (1 << 9)
+#define AP_B (1 << 12)
+#define AN_B (1 << 13)
+#define HIGHZ_B (1 << 14)
+/* phase C */
+#define USBOP_RPD_C (1 << 16)
+#define USBON_RPD_C (1 << 17)
+#define AP_C (1 << 20)
+#define AN_C (1 << 21)
+#define HIGHZ_C (1 << 22)
+/* phase D */
+#define USBOP_RPD_D (1 << 24)
+#define USBON_RPD_D (1 << 25)
+#define AP_D (1 << 28)
+#define AN_D (1 << 29)
+#define HIGHZ_D (1 << 30)
+
+#define XUSB_AO_UHSIC_SLEEPWALK(x) (0x120 + (x) * 4)
+/* phase A */
+#define RPD_STROBE_A (1 << 0)
+#define RPD_DATA0_A (1 << 1)
+#define RPU_STROBE_A (1 << 2)
+#define RPU_DATA0_A (1 << 3)
+/* phase B */
+#define RPD_STROBE_B (1 << 8)
+#define RPD_DATA0_B (1 << 9)
+#define RPU_STROBE_B (1 << 10)
+#define RPU_DATA0_B (1 << 11)
+/* phase C */
+#define RPD_STROBE_C (1 << 16)
+#define RPD_DATA0_C (1 << 17)
+#define RPU_STROBE_C (1 << 18)
+#define RPU_DATA0_C (1 << 19)
+/* phase D */
+#define RPD_STROBE_D (1 << 24)
+#define RPD_DATA0_D (1 << 25)
+#define RPU_STROBE_D (1 << 26)
+#define RPU_DATA0_D (1 << 27)
+
+#define XUSB_AO_UTMIP_PAD_CFG(x) (0x130 + (x) * 4)
+#define FSLS_USE_XUSB_AO (1 << 3)
+#define TRK_CTRL_USE_XUSB_AO (1 << 4)
+#define RPD_CTRL_USE_XUSB_AO (1 << 5)
+#define RPU_USE_XUSB_AO (1 << 6)
+#define VREG_USE_XUSB_AO (1 << 7)
+#define USBOP_VAL_PD (1 << 8)
+#define USBON_VAL_PD (1 << 9)
+#define E_DPD_OVRD_EN (1 << 10)
+#define E_DPD_OVRD_VAL (1 << 11)
+
+#define XUSB_AO_UHSIC_PAD_CFG(x) (0x150 + (x) * 4)
+#define STROBE_VAL_PD (1 << 0)
+#define DATA0_VAL_PD (1 << 1)
+#define USE_XUSB_AO (1 << 4)
+
#define TEGRA186_LANE(_name, _offset, _shift, _mask, _type) \
{ \
.name = _name, \
@@ -130,16 +241,43 @@ struct tegra_xusb_fuse_calibration {
u32 rpd_ctrl;
};
+struct tegra186_xusb_padctl_context {
+ u32 vbus_id;
+ u32 usb2_pad_mux;
+ u32 usb2_port_cap;
+ u32 ss_port_cap;
+};
+
struct tegra186_xusb_padctl {
struct tegra_xusb_padctl base;
+ void __iomem *ao_regs;
struct tegra_xusb_fuse_calibration calib;
/* UTMI bias and tracking */
struct clk *usb2_trk_clk;
unsigned int bias_pad_enable;
+
+ /* padctl context */
+ struct tegra186_xusb_padctl_context context;
};
+static inline void ao_writel(struct tegra186_xusb_padctl *priv, u32 value,
+ unsigned long offset)
+{
+ dev_dbg(priv->base.dev, "ao %08lx < %08x\n", offset, value);
+ writel(value, priv->ao_regs + offset);
+}
+
+static inline u32 ao_readl(struct tegra186_xusb_padctl *priv,
+ unsigned long offset)
+{
+ u32 value = readl(priv->ao_regs + offset);
+
+ dev_dbg(priv->base.dev, "ao %08lx > %08x\n", offset, value);
+ return value;
+}
+
static inline struct tegra186_xusb_padctl *
to_tegra186_xusb_padctl(struct tegra_xusb_padctl *padctl)
{
@@ -475,6 +613,238 @@ static int tegra186_utmi_phy_power_off(struct phy *phy)
return 0;
}
+static int tegra186_utmi_phy_enable_sleepwalk(struct phy *phy,
+ enum usb_device_speed speed)
+{
+ struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
+ struct tegra_xusb_padctl *padctl = lane->pad->padctl;
+ struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
+ unsigned int index = lane->index;
+ struct device *dev = padctl->dev;
+ u32 value;
+
+ dev_dbg(dev, "phy enable sleepwalk UTMI %d speed %d\n", index, speed);
+
+ mutex_lock(&padctl->lock);
+
+ /* ensure sleepwalk logic is disabled */
+ value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
+ value &= ~MASTER_ENABLE;
+ ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
+
+ /* ensure sleepwalk logics are in low power mode */
+ value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
+ value |= MASTER_CFG_SEL;
+ ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
+
+ /* set debounce time */
+ value = ao_readl(priv, XUSB_AO_USB_DEBOUNCE_DEL);
+ value &= ~UTMIP_LINE_DEB_CNT(~0);
+ value |= UTMIP_LINE_DEB_CNT(1);
+ ao_writel(priv, value, XUSB_AO_USB_DEBOUNCE_DEL);
+
+ /* ensure fake events of sleepwalk logic are desiabled */
+ value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
+ value &= ~(FAKE_USBOP_VAL | FAKE_USBON_VAL |
+ FAKE_USBOP_EN | FAKE_USBON_EN);
+ ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
+
+ /* ensure wake events of sleepwalk logic are not latched */
+ value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
+ value &= ~LINE_WAKEUP_EN;
+ ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
+
+ /* disable wake event triggers of sleepwalk logic */
+ value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
+ value &= ~WAKE_VAL(~0);
+ value |= WAKE_VAL_NONE;
+ ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
+
+ /* power down the line state detectors of the pad */
+ value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index));
+ value |= (USBOP_VAL_PD | USBON_VAL_PD);
+ ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index));
+
+ /* save state per speed */
+ value = ao_readl(priv, XUSB_AO_UTMIP_SAVED_STATE(index));
+ value &= ~SPEED(~0);
+ if (speed == USB_SPEED_HIGH)
+ value |= UTMI_HS;
+ else if (speed == USB_SPEED_FULL)
+ value |= UTMI_FS;
+ else if (speed == USB_SPEED_LOW)
+ value |= UTMI_LS;
+ else
+ value |= UTMI_RST;
+ ao_writel(priv, value, XUSB_AO_UTMIP_SAVED_STATE(index));
+
+ /* enable the trigger of the sleepwalk logic */
+ value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
+ value |= LINEVAL_WALK_EN;
+ value &= ~WAKE_WALK_EN;
+ ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
+
+ /* reset the walk pointer and clear the alarm of the sleepwalk logic,
+ * as well as capture the configuration of the USB2.0 pad
+ */
+ value = ao_readl(priv, XUSB_AO_UTMIP_TRIGGERS(index));
+ value |= (CLR_WALK_PTR | CLR_WAKE_ALARM | CAP_CFG);
+ ao_writel(priv, value, XUSB_AO_UTMIP_TRIGGERS(index));
+
+ /* setup the pull-ups and pull-downs of the signals during the four
+ * stages of sleepwalk.
+ * if device is connected, program sleepwalk logic to maintain a J and
+ * keep driving K upon seeing remote wake.
+ */
+ value = (USBOP_RPD_A | USBOP_RPD_B | USBOP_RPD_C | USBOP_RPD_D);
+ value |= (USBON_RPD_A | USBON_RPD_B | USBON_RPD_C | USBON_RPD_D);
+ if (speed == USB_SPEED_UNKNOWN) {
+ value |= (HIGHZ_A | HIGHZ_B | HIGHZ_C | HIGHZ_D);
+ } else if ((speed == USB_SPEED_HIGH) || (speed == USB_SPEED_FULL)) {
+ /* J state: D+/D- = high/low, K state: D+/D- = low/high */
+ value |= HIGHZ_A;
+ value |= (AP_A);
+ value |= (AN_B | AN_C | AN_D);
+ } else if (speed == USB_SPEED_LOW) {
+ /* J state: D+/D- = low/high, K state: D+/D- = high/low */
+ value |= HIGHZ_A;
+ value |= AN_A;
+ value |= (AP_B | AP_C | AP_D);
+ }
+ ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK(index));
+
+ /* power up the line state detectors of the pad */
+ value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index));
+ value &= ~(USBOP_VAL_PD | USBON_VAL_PD);
+ ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index));
+
+ usleep_range(150, 200);
+
+ /* switch the electric control of the USB2.0 pad to XUSB_AO */
+ value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index));
+ value |= (FSLS_USE_XUSB_AO | TRK_CTRL_USE_XUSB_AO |
+ RPD_CTRL_USE_XUSB_AO | RPU_USE_XUSB_AO | VREG_USE_XUSB_AO);
+ ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index));
+
+ /* set the wake signaling trigger events */
+ value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
+ value &= ~WAKE_VAL(~0);
+ value |= WAKE_VAL_ANY;
+ ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
+
+ /* enable the wake detection */
+ value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
+ value |= (MASTER_ENABLE | LINE_WAKEUP_EN);
+ ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
+
+ mutex_unlock(&padctl->lock);
+
+ return 0;
+}
+
+static int tegra186_utmi_phy_disable_sleepwalk(struct phy *phy)
+{
+ struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
+ struct tegra_xusb_padctl *padctl = lane->pad->padctl;
+ struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
+ unsigned int index = lane->index;
+ struct device *dev = padctl->dev;
+ u32 value;
+
+ dev_dbg(dev, "phy disable sleepwalk UTMI %d\n", index);
+
+ mutex_lock(&padctl->lock);
+
+ /* disable the wake detection */
+ value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
+ value &= ~(MASTER_ENABLE | LINE_WAKEUP_EN);
+ ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
+
+ /* switch the electric control of the USB2.0 pad to XUSB vcore logic */
+ value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index));
+ value &= ~(FSLS_USE_XUSB_AO | TRK_CTRL_USE_XUSB_AO |
+ RPD_CTRL_USE_XUSB_AO | RPU_USE_XUSB_AO | VREG_USE_XUSB_AO);
+ ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index));
+
+ /* disable wake event triggers of sleepwalk logic */
+ value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
+ value &= ~WAKE_VAL(~0);
+ value |= WAKE_VAL_NONE;
+ ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
+
+ /* power down the line state detectors of the port */
+ value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index));
+ value |= (USBOP_VAL_PD | USBON_VAL_PD);
+ ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index));
+
+ /* clear alarm of the sleepwalk logic */
+ value = ao_readl(priv, XUSB_AO_UTMIP_TRIGGERS(index));
+ value |= CLR_WAKE_ALARM;
+ ao_writel(priv, value, XUSB_AO_UTMIP_TRIGGERS(index));
+
+ mutex_unlock(&padctl->lock);
+
+ return 0;
+}
+
+static int tegra186_utmi_phy_enable_wake(struct phy *phy)
+{
+ struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
+ struct tegra_xusb_padctl *padctl = lane->pad->padctl;
+ unsigned int index = lane->index;
+ struct device *dev = padctl->dev;
+ u32 value;
+
+ dev_dbg(dev, "phy enable wake UTMI %d\n", index);
+
+ mutex_lock(&padctl->lock);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
+ value &= ~ALL_WAKE_EVENTS;
+ value |= USB2_PORT_WAKEUP_EVENT(index);
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
+
+ usleep_range(10, 20);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
+ value &= ~ALL_WAKE_EVENTS;
+ value |= USB2_PORT_WAKE_INTERRUPT_ENABLE(index);
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
+
+ mutex_unlock(&padctl->lock);
+
+ return 0;
+}
+
+static int tegra186_utmi_phy_disable_wake(struct phy *phy)
+{
+ struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
+ struct tegra_xusb_padctl *padctl = lane->pad->padctl;
+ unsigned int index = lane->index;
+ struct device *dev = padctl->dev;
+ u32 value;
+
+ dev_dbg(dev, "phy disable wake UTMI %d\n", index);
+
+ mutex_lock(&padctl->lock);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
+ value &= ~ALL_WAKE_EVENTS;
+ value &= ~USB2_PORT_WAKE_INTERRUPT_ENABLE(index);
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
+
+ usleep_range(10, 20);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
+ value &= ~ALL_WAKE_EVENTS;
+ value |= USB2_PORT_WAKEUP_EVENT(index);
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
+
+ mutex_unlock(&padctl->lock);
+
+ return 0;
+}
+
static int tegra186_utmi_phy_init(struct phy *phy)
{
struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
@@ -538,6 +908,11 @@ static const struct phy_ops utmi_phy_ops = {
.owner = THIS_MODULE,
};
+static inline bool is_utmi_phy(struct phy *phy)
+{
+ return phy->ops == &utmi_phy_ops;
+}
+
static struct tegra_xusb_pad *
tegra186_usb2_pad_probe(struct tegra_xusb_padctl *padctl,
const struct tegra_xusb_pad_soc *soc,
@@ -790,6 +1165,120 @@ static int tegra186_usb3_phy_power_off(struct phy *phy)
return 0;
}
+static int tegra186_usb3_phy_enable_sleepwalk(struct phy *phy)
+{
+ struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
+ struct tegra_xusb_padctl *padctl = lane->pad->padctl;
+ unsigned int index = lane->index;
+ struct device *dev = padctl->dev;
+ u32 value;
+
+ dev_dbg(dev, "phy enable sleepwalk USB3 %d\n", index);
+
+ mutex_lock(&padctl->lock);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
+ value |= SSPX_ELPG_CLAMP_EN_EARLY(index);
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
+
+ usleep_range(100, 200);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
+ value |= SSPX_ELPG_CLAMP_EN(index);
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
+
+ usleep_range(250, 350);
+
+ mutex_unlock(&padctl->lock);
+
+ return 0;
+}
+
+static int tegra186_usb3_phy_disable_sleepwalk(struct phy *phy)
+{
+ struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
+ struct tegra_xusb_padctl *padctl = lane->pad->padctl;
+ unsigned int index = lane->index;
+ struct device *dev = padctl->dev;
+ u32 value;
+
+ dev_dbg(dev, "phy disable sleepwalk USB3 %d\n", index);
+
+ mutex_lock(&padctl->lock);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
+ value &= ~SSPX_ELPG_CLAMP_EN_EARLY(index);
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
+
+ usleep_range(100, 200);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
+ value &= ~SSPX_ELPG_CLAMP_EN(index);
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
+
+ mutex_unlock(&padctl->lock);
+
+ return 0;
+}
+
+static int tegra186_usb3_phy_enable_wake(struct phy *phy)
+{
+ struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
+ struct tegra_xusb_padctl *padctl = lane->pad->padctl;
+ unsigned int index = lane->index;
+ struct device *dev = padctl->dev;
+ u32 value;
+
+ dev_dbg(dev, "phy enable wake USB3 %d\n", index);
+
+ mutex_lock(&padctl->lock);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
+ value &= ~ALL_WAKE_EVENTS;
+ value |= SS_PORT_WAKEUP_EVENT(index);
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
+
+ usleep_range(10, 20);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
+ value &= ~ALL_WAKE_EVENTS;
+ value |= SS_PORT_WAKE_INTERRUPT_ENABLE(index);
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
+
+ mutex_unlock(&padctl->lock);
+
+ return 0;
+}
+
+static int tegra186_usb3_phy_disable_wake(struct phy *phy)
+{
+ struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
+ struct tegra_xusb_padctl *padctl = lane->pad->padctl;
+ unsigned int index = lane->index;
+ struct device *dev = padctl->dev;
+ u32 value;
+
+ dev_dbg(dev, "phy disable wake USB3 %d\n", index);
+
+ mutex_lock(&padctl->lock);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
+ value &= ~ALL_WAKE_EVENTS;
+ value &= ~SS_PORT_WAKE_INTERRUPT_ENABLE(index);
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
+
+ usleep_range(10, 20);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
+ value &= ~ALL_WAKE_EVENTS;
+ value |= SS_PORT_WAKEUP_EVENT(index);
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
+
+ mutex_unlock(&padctl->lock);
+
+ return 0;
+}
+
static int tegra186_usb3_phy_init(struct phy *phy)
{
return 0;
@@ -808,6 +1297,11 @@ static const struct phy_ops usb3_phy_ops = {
.owner = THIS_MODULE,
};
+static inline bool is_usb3_phy(struct phy *phy)
+{
+ return phy->ops == &usb3_phy_ops;
+}
+
static struct tegra_xusb_pad *
tegra186_usb3_pad_probe(struct tegra_xusb_padctl *padctl,
const struct tegra_xusb_pad_soc *soc,
@@ -913,7 +1407,9 @@ static struct tegra_xusb_padctl *
tegra186_xusb_padctl_probe(struct device *dev,
const struct tegra_xusb_padctl_soc *soc)
{
+ struct platform_device *pdev = to_platform_device(dev);
struct tegra186_xusb_padctl *priv;
+ struct resource *res;
int err;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
@@ -923,6 +1419,11 @@ tegra186_xusb_padctl_probe(struct device *dev,
priv->base.dev = dev;
priv->base.soc = soc;
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ao");
+ priv->ao_regs = devm_ioremap_resource(dev, res);
+ if (IS_ERR(priv->ao_regs))
+ return priv->ao_regs;
+
err = tegra186_xusb_read_fuse_calibration(priv);
if (err < 0)
return ERR_PTR(err);
@@ -930,6 +1431,154 @@ tegra186_xusb_padctl_probe(struct device *dev,
return &priv->base;
}
+static void tegra186_xusb_padctl_save(struct tegra_xusb_padctl *padctl)
+{
+ struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
+
+ priv->context.vbus_id = padctl_readl(padctl, USB2_VBUS_ID);
+ priv->context.usb2_pad_mux =
+ padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX);
+ priv->context.usb2_port_cap =
+ padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP);
+ priv->context.ss_port_cap =
+ padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CAP);
+}
+
+static void tegra186_xusb_padctl_restore(struct tegra_xusb_padctl *padctl)
+{
+ struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
+
+ padctl_writel(padctl, priv->context.usb2_pad_mux,
+ XUSB_PADCTL_USB2_PAD_MUX);
+ padctl_writel(padctl, priv->context.usb2_port_cap,
+ XUSB_PADCTL_USB2_PORT_CAP);
+ padctl_writel(padctl, priv->context.ss_port_cap,
+ XUSB_PADCTL_SS_PORT_CAP);
+ padctl_writel(padctl, priv->context.vbus_id, USB2_VBUS_ID);
+}
+
+static int tegra186_xusb_padctl_suspend_noirq(struct tegra_xusb_padctl *padctl)
+{
+ tegra186_xusb_padctl_save(padctl);
+
+ return 0;
+}
+
+static int tegra186_xusb_padctl_resume_noirq(struct tegra_xusb_padctl *padctl)
+{
+ tegra186_xusb_padctl_restore(padctl);
+
+ return 0;
+}
+
+static int
+tegra186_xusb_padctl_enable_phy_sleepwalk(struct tegra_xusb_padctl *padctl,
+ struct phy *phy,
+ enum usb_device_speed speed)
+{
+ if (!phy)
+ return 0;
+
+ if (is_usb3_phy(phy))
+ return tegra186_usb3_phy_enable_sleepwalk(phy);
+ else if (is_utmi_phy(phy))
+ return tegra186_utmi_phy_enable_sleepwalk(phy, speed);
+ else
+ return -EINVAL;
+}
+
+static int
+tegra186_xusb_padctl_disable_phy_sleepwalk(struct tegra_xusb_padctl *padctl,
+ struct phy *phy)
+{
+ if (!phy)
+ return 0;
+
+ if (is_usb3_phy(phy))
+ return tegra186_usb3_phy_disable_sleepwalk(phy);
+ else if (is_utmi_phy(phy))
+ return tegra186_utmi_phy_disable_sleepwalk(phy);
+ else
+ return -EINVAL;
+}
+
+static int
+tegra186_xusb_padctl_enable_phy_wake(struct tegra_xusb_padctl *padctl,
+ struct phy *phy)
+{
+ if (!phy)
+ return 0;
+
+ if (is_usb3_phy(phy))
+ return tegra186_usb3_phy_enable_wake(phy);
+ else if (is_utmi_phy(phy))
+ return tegra186_utmi_phy_enable_wake(phy);
+ else
+ return -EINVAL;
+}
+
+static int
+tegra186_xusb_padctl_disable_phy_wake(struct tegra_xusb_padctl *padctl,
+ struct phy *phy)
+{
+ if (!phy)
+ return 0;
+
+ if (is_usb3_phy(phy))
+ return tegra186_usb3_phy_disable_wake(phy);
+ else if (is_utmi_phy(phy))
+ return tegra186_utmi_phy_disable_wake(phy);
+ else
+ return -EINVAL;
+}
+
+static int tegra186_usb3_phy_remote_wake_detected(
+ struct tegra_xusb_padctl *padctl, int port)
+{
+ u32 value;
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
+ if ((value & SS_PORT_WAKE_INTERRUPT_ENABLE(port)) &&
+ (value & SS_PORT_WAKEUP_EVENT(port)))
+ return true;
+ else
+ return false;
+}
+
+static int tegra186_utmi_phy_remote_wake_detected(
+ struct tegra_xusb_padctl *padctl, int port)
+{
+ u32 value;
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
+ if ((value & USB2_PORT_WAKE_INTERRUPT_ENABLE(port)) &&
+ (value & USB2_PORT_WAKEUP_EVENT(port)))
+ return true;
+ else
+ return false;
+}
+
+int tegra186_xusb_padctl_remote_wake_detected(struct phy *phy)
+{
+ struct tegra_xusb_lane *lane;
+ struct tegra_xusb_padctl *padctl;
+ unsigned int index;
+
+ if (!phy)
+ return 0;
+
+ lane = phy_get_drvdata(phy);
+ padctl = lane->pad->padctl;
+ index = lane->index;
+
+ if (is_utmi_phy(phy))
+ return tegra186_utmi_phy_remote_wake_detected(padctl, index);
+ else if (is_usb3_phy(phy))
+ return tegra186_usb3_phy_remote_wake_detected(padctl, index);
+ else
+ return -EINVAL;
+}
+
static void tegra186_xusb_padctl_remove(struct tegra_xusb_padctl *padctl)
{
}
@@ -937,7 +1586,14 @@ static void tegra186_xusb_padctl_remove(struct tegra_xusb_padctl *padctl)
static const struct tegra_xusb_padctl_ops tegra186_xusb_padctl_ops = {
.probe = tegra186_xusb_padctl_probe,
.remove = tegra186_xusb_padctl_remove,
+ .suspend_noirq = tegra186_xusb_padctl_suspend_noirq,
+ .resume_noirq = tegra186_xusb_padctl_resume_noirq,
.vbus_override = tegra186_xusb_padctl_vbus_override,
+ .enable_phy_sleepwalk = tegra186_xusb_padctl_enable_phy_sleepwalk,
+ .disable_phy_sleepwalk = tegra186_xusb_padctl_disable_phy_sleepwalk,
+ .enable_phy_wake = tegra186_xusb_padctl_enable_phy_wake,
+ .disable_phy_wake = tegra186_xusb_padctl_disable_phy_wake,
+ .remote_wake_detected = tegra186_xusb_padctl_remote_wake_detected,
};
#if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC)
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 10/12] arm64: tegra210/tegra186/tegra194: XUSB PADCTL irq
2020-08-28 1:10 [PATCH 00/12] Tegra XHCI controller ELPG support JC Kuo
` (8 preceding siblings ...)
2020-08-28 1:10 ` [PATCH 09/12] phy: tegra: xusb: t186: " JC Kuo
@ 2020-08-28 1:10 ` JC Kuo
2020-08-28 1:10 ` [PATCH 11/12] usb: host: xhci-tegra: unlink power domain devices JC Kuo
2020-08-28 1:10 ` [PATCH 12/12] xhci: tegra: enable ELPG for runtime/system PM JC Kuo
11 siblings, 0 replies; 15+ messages in thread
From: JC Kuo @ 2020-08-28 1:10 UTC (permalink / raw)
To: gregkh, thierry.reding, robh, jonathanh, kishon
Cc: linux-tegra, linux-usb, linux-kernel, devicetree, nkristam, JC Kuo
This commit adds "interrupts" property to Tegra210/Tegra186/Tegra194
XUSB PADCTL node. XUSB PADCTL interrupt will be raised when USB wake
event happens. This is required for supporting XUSB host controller
ELPG.
Signed-off-by: JC Kuo <jckuo@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 +
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 1 +
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 1 +
3 files changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 34d249d85da7..454a857e5e56 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -466,6 +466,7 @@ padctl: padctl@3520000 {
reg = <0x0 0x03520000 0x0 0x1000>,
<0x0 0x03540000 0x0 0x1000>;
reg-names = "padctl", "ao";
+ interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>;
reset-names = "padctl";
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 48160f48003a..2b5216a34c06 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -561,6 +561,7 @@ xusb_padctl: padctl@3520000 {
reg = <0x03520000 0x1000>,
<0x03540000 0x1000>;
reg-names = "padctl", "ao";
+ interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>;
reset-names = "padctl";
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 67c90a0ea32e..2ba526779ee5 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -1041,6 +1041,7 @@ padctl: padctl@7009f000 {
resets = <&tegra_car 142>;
reset-names = "padctl";
nvidia,pmc = <&tegra_pmc>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 11/12] usb: host: xhci-tegra: unlink power domain devices
2020-08-28 1:10 [PATCH 00/12] Tegra XHCI controller ELPG support JC Kuo
` (9 preceding siblings ...)
2020-08-28 1:10 ` [PATCH 10/12] arm64: tegra210/tegra186/tegra194: XUSB PADCTL irq JC Kuo
@ 2020-08-28 1:10 ` JC Kuo
2020-08-28 1:10 ` [PATCH 12/12] xhci: tegra: enable ELPG for runtime/system PM JC Kuo
11 siblings, 0 replies; 15+ messages in thread
From: JC Kuo @ 2020-08-28 1:10 UTC (permalink / raw)
To: gregkh, thierry.reding, robh, jonathanh, kishon
Cc: linux-tegra, linux-usb, linux-kernel, devicetree, nkristam, JC Kuo
This commit unlinks xhci-tegra platform device with ss/host power
domain devices. Reasons for this change is - at elpg entry, phy
sleepwalk and wake configuration need to be done before powering
down ss/host partitions, and phy need be powered off after powering
down ss/host partitions. Sequence looks like roughly below:
tegra_xusb_enter_elpg() -> xhci_suspend()
-> enable phy sleepwalk and wake if needed
-> power down ss/host partitions
-> power down phy
If ss/host power domains are linked to xhci-tegra platform device, we
are not able to perform the sequence like above.
This commit introduces:
1. tegra_xusb_unpowergate_partitions() to power up ss and host
partitions together. If ss/host power domain devices are
available, it invokes pm_runtime_get_sync() to request power
driver to power up partitions; If power domain devices are not
available, tegra_powergate_sequence_power_up() will be used to
power up partitions.
2. tegra_xusb_powergate_partitions() to power down ss and host
partitions together. If ss/host power domain devices are
available, it invokes pm_runtime_put_sync() to request power
driver to power down partitions; If power domain devices are not
available, tegra_powergate_power_off() will be used to power down
partitions.
Signed-off-by: JC Kuo <jckuo@nvidia.com>
---
drivers/usb/host/xhci-tegra.c | 202 +++++++++++++++++++---------------
1 file changed, 111 insertions(+), 91 deletions(-)
diff --git a/drivers/usb/host/xhci-tegra.c b/drivers/usb/host/xhci-tegra.c
index 934be1686352..ce6526c2caf6 100644
--- a/drivers/usb/host/xhci-tegra.c
+++ b/drivers/usb/host/xhci-tegra.c
@@ -249,8 +249,6 @@ struct tegra_xusb {
struct device *genpd_dev_host;
struct device *genpd_dev_ss;
- struct device_link *genpd_dl_host;
- struct device_link *genpd_dl_ss;
struct phy **phys;
unsigned int num_phys;
@@ -814,36 +812,12 @@ static void tegra_xusb_phy_disable(struct tegra_xusb *tegra)
static int tegra_xusb_runtime_suspend(struct device *dev)
{
- struct tegra_xusb *tegra = dev_get_drvdata(dev);
-
- regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
- tegra_xusb_clk_disable(tegra);
-
return 0;
}
static int tegra_xusb_runtime_resume(struct device *dev)
{
- struct tegra_xusb *tegra = dev_get_drvdata(dev);
- int err;
-
- err = tegra_xusb_clk_enable(tegra);
- if (err) {
- dev_err(dev, "failed to enable clocks: %d\n", err);
- return err;
- }
-
- err = regulator_bulk_enable(tegra->soc->num_supplies, tegra->supplies);
- if (err) {
- dev_err(dev, "failed to enable regulators: %d\n", err);
- goto disable_clk;
- }
-
return 0;
-
-disable_clk:
- tegra_xusb_clk_disable(tegra);
- return err;
}
#ifdef CONFIG_PM_SLEEP
@@ -1019,10 +993,6 @@ static int tegra_xusb_load_firmware(struct tegra_xusb *tegra)
static void tegra_xusb_powerdomain_remove(struct device *dev,
struct tegra_xusb *tegra)
{
- if (tegra->genpd_dl_ss)
- device_link_del(tegra->genpd_dl_ss);
- if (tegra->genpd_dl_host)
- device_link_del(tegra->genpd_dl_host);
if (!IS_ERR_OR_NULL(tegra->genpd_dev_ss))
dev_pm_domain_detach(tegra->genpd_dev_ss, true);
if (!IS_ERR_OR_NULL(tegra->genpd_dev_host))
@@ -1048,20 +1018,88 @@ static int tegra_xusb_powerdomain_init(struct device *dev,
return err;
}
- tegra->genpd_dl_host = device_link_add(dev, tegra->genpd_dev_host,
- DL_FLAG_PM_RUNTIME |
- DL_FLAG_STATELESS);
- if (!tegra->genpd_dl_host) {
- dev_err(dev, "adding host device link failed!\n");
- return -ENODEV;
+ return 0;
+}
+
+static int tegra_xusb_unpowergate_partitions(struct tegra_xusb *tegra)
+{
+ struct device *dev = tegra->dev;
+ bool use_genpd;
+ int rc;
+
+ use_genpd = of_property_read_bool(dev->of_node, "power-domains");
+
+ if (use_genpd) {
+ rc = pm_runtime_get_sync(tegra->genpd_dev_ss);
+ if (rc < 0) {
+ dev_err(dev, "failed to enable XUSB SS partition\n");
+ return rc;
+ }
+
+ rc = pm_runtime_get_sync(tegra->genpd_dev_host);
+ if (rc < 0) {
+ dev_err(dev, "failed to enable XUSB Host partition\n");
+ pm_runtime_put_sync(tegra->genpd_dev_ss);
+ return rc;
+ }
+ } else {
+ rc = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBA,
+ tegra->ss_clk,
+ tegra->ss_rst);
+ if (rc < 0) {
+ dev_err(dev, "failed to enable XUSB SS partition\n");
+ return rc;
+ }
+
+ rc = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBC,
+ tegra->host_clk,
+ tegra->host_rst);
+ if (rc < 0) {
+ dev_err(dev, "failed to enable XUSB Host partition\n");
+ tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA);
+ return rc;
+ }
}
- tegra->genpd_dl_ss = device_link_add(dev, tegra->genpd_dev_ss,
- DL_FLAG_PM_RUNTIME |
- DL_FLAG_STATELESS);
- if (!tegra->genpd_dl_ss) {
- dev_err(dev, "adding superspeed device link failed!\n");
- return -ENODEV;
+ return 0;
+}
+
+static int tegra_xusb_powergate_partitions(struct tegra_xusb *tegra)
+{
+ struct device *dev = tegra->dev;
+ bool use_genpd;
+ int rc;
+
+ use_genpd = of_property_read_bool(dev->of_node, "power-domains");
+
+ if (use_genpd) {
+ rc = pm_runtime_put_sync(tegra->genpd_dev_host);
+ if (rc < 0) {
+ dev_err(dev, "failed to disable XUSB Host partition\n");
+ return rc;
+ }
+
+ rc = pm_runtime_put_sync(tegra->genpd_dev_ss);
+ if (rc < 0) {
+ dev_err(dev, "failed to disable XUSB SS partition\n");
+ pm_runtime_get_sync(tegra->genpd_dev_host);
+ return rc;
+ }
+ } else {
+ rc = tegra_powergate_power_off(TEGRA_POWERGATE_XUSBC);
+ if (rc < 0) {
+ dev_err(dev, "failed to disable XUSB Host partition\n");
+ return rc;
+ }
+
+ rc = tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA);
+ if (rc < 0) {
+ dev_err(dev, "failed to disable XUSB SS partition\n");
+ tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBC,
+ tegra->host_clk,
+ tegra->host_rst);
+ return rc;
+ }
}
return 0;
@@ -1425,25 +1463,6 @@ static int tegra_xusb_probe(struct platform_device *pdev)
err);
goto put_padctl;
}
-
- err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBA,
- tegra->ss_clk,
- tegra->ss_rst);
- if (err) {
- dev_err(&pdev->dev,
- "failed to enable XUSBA domain: %d\n", err);
- goto put_padctl;
- }
-
- err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBC,
- tegra->host_clk,
- tegra->host_rst);
- if (err) {
- tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA);
- dev_err(&pdev->dev,
- "failed to enable XUSBC domain: %d\n", err);
- goto put_padctl;
- }
} else {
err = tegra_xusb_powerdomain_init(&pdev->dev, tegra);
if (err)
@@ -1518,10 +1537,22 @@ static int tegra_xusb_probe(struct platform_device *pdev)
*/
platform_set_drvdata(pdev, tegra);
+ err = tegra_xusb_clk_enable(tegra);
+ if (err) {
+ dev_err(tegra->dev, "failed to enable clocks: %d\n", err);
+ goto put_hcd;
+ }
+
+ err = regulator_bulk_enable(tegra->soc->num_supplies, tegra->supplies);
+ if (err) {
+ dev_err(tegra->dev, "failed to enable regulators: %d\n", err);
+ goto disable_clk;
+ }
+
err = tegra_xusb_phy_enable(tegra);
if (err < 0) {
dev_err(&pdev->dev, "failed to enable PHYs: %d\n", err);
- goto put_hcd;
+ goto disable_regulator;
}
/*
@@ -1540,30 +1571,22 @@ static int tegra_xusb_probe(struct platform_device *pdev)
goto disable_phy;
}
- pm_runtime_enable(&pdev->dev);
-
- if (!pm_runtime_enabled(&pdev->dev))
- err = tegra_xusb_runtime_resume(&pdev->dev);
- else
- err = pm_runtime_get_sync(&pdev->dev);
-
- if (err < 0) {
- dev_err(&pdev->dev, "failed to enable device: %d\n", err);
+ err = tegra_xusb_unpowergate_partitions(tegra);
+ if (err)
goto free_firmware;
- }
tegra_xusb_config(tegra);
err = tegra_xusb_load_firmware(tegra);
if (err < 0) {
dev_err(&pdev->dev, "failed to load firmware: %d\n", err);
- goto put_rpm;
+ goto powergate;
}
err = usb_add_hcd(tegra->hcd, tegra->xhci_irq, IRQF_SHARED);
if (err < 0) {
dev_err(&pdev->dev, "failed to add USB HCD: %d\n", err);
- goto put_rpm;
+ goto powergate;
}
device_wakeup_enable(tegra->hcd->self.controller);
@@ -1615,24 +1638,21 @@ static int tegra_xusb_probe(struct platform_device *pdev)
usb_put_hcd(xhci->shared_hcd);
remove_usb2:
usb_remove_hcd(tegra->hcd);
-put_rpm:
- if (!pm_runtime_status_suspended(&pdev->dev))
- tegra_xusb_runtime_suspend(&pdev->dev);
-put_hcd:
- usb_put_hcd(tegra->hcd);
+powergate:
+ tegra_xusb_powergate_partitions(tegra);
free_firmware:
dma_free_coherent(&pdev->dev, tegra->fw.size, tegra->fw.virt,
tegra->fw.phys);
disable_phy:
tegra_xusb_phy_disable(tegra);
- pm_runtime_disable(&pdev->dev);
+disable_regulator:
+ regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
+disable_clk:
+ tegra_xusb_clk_disable(tegra);
+put_hcd:
+ usb_put_hcd(tegra->hcd);
put_powerdomains:
- if (!of_property_read_bool(pdev->dev.of_node, "power-domains")) {
- tegra_powergate_power_off(TEGRA_POWERGATE_XUSBC);
- tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA);
- } else {
- tegra_xusb_powerdomain_remove(&pdev->dev, tegra);
- }
+ tegra_xusb_powerdomain_remove(&pdev->dev, tegra);
put_padctl:
tegra_xusb_padctl_put(tegra->padctl);
return err;
@@ -1657,15 +1677,15 @@ static int tegra_xusb_remove(struct platform_device *pdev)
pm_runtime_put_sync(&pdev->dev);
pm_runtime_disable(&pdev->dev);
- if (!of_property_read_bool(pdev->dev.of_node, "power-domains")) {
- tegra_powergate_power_off(TEGRA_POWERGATE_XUSBC);
- tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA);
- } else {
+ tegra_xusb_powergate_partitions(tegra);
+
+ if (of_property_read_bool(pdev->dev.of_node, "power-domains")) {
tegra_xusb_powerdomain_remove(&pdev->dev, tegra);
}
tegra_xusb_phy_disable(tegra);
-
+ tegra_xusb_clk_disable(tegra);
+ regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
tegra_xusb_padctl_put(tegra->padctl);
return 0;
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 12/12] xhci: tegra: enable ELPG for runtime/system PM
2020-08-28 1:10 [PATCH 00/12] Tegra XHCI controller ELPG support JC Kuo
` (10 preceding siblings ...)
2020-08-28 1:10 ` [PATCH 11/12] usb: host: xhci-tegra: unlink power domain devices JC Kuo
@ 2020-08-28 1:10 ` JC Kuo
11 siblings, 0 replies; 15+ messages in thread
From: JC Kuo @ 2020-08-28 1:10 UTC (permalink / raw)
To: gregkh, thierry.reding, robh, jonathanh, kishon
Cc: linux-tegra, linux-usb, linux-kernel, devicetree, nkristam, JC Kuo
This commit implements the complete programming sequence for ELPG
entry and exit.
1. At ELPG entry, invokes tegra_xusb_padctl_enable_phy_sleepwalk()
and tegra_xusb_padctl_enable_phy_wake() to configure XUSB PADCTL
sleepwalk and wake detection circuits to maintain USB lines level
and respond to wake events (wake-on-connect, wake-on-disconnect,
device-initiated-wake).
2. At ELPG exit, invokes tegra_xusb_padctl_disable_phy_sleepwalk()
and tegra_xusb_padctl_disable_phy_wake() to disarm sleepwalk and
wake detection circuits.
At runtime suspend, XUSB host controller can enter ELPG to reduce
power consumption. When XUSB PADCTL wake detection circuit detects
a wake event, an interrupt will be raised. xhci-tegra driver then
will invoke pm_runtime_resume() for xhci-tegra.
Runtime resume could also be triggered by protocol drivers, this is
the host-initiated-wake event. At runtime resume, xhci-tegra driver
brings XUSB host controller out of ELPG to handle the wake events.
The same ELPG enter/exit procedure will be performed for system
suspend/resume path so USB devices can remain connected across SC7.
Signed-off-by: JC Kuo <jckuo@nvidia.com>
---
drivers/usb/host/xhci-tegra.c | 391 +++++++++++++++++++++++++++++++---
1 file changed, 361 insertions(+), 30 deletions(-)
diff --git a/drivers/usb/host/xhci-tegra.c b/drivers/usb/host/xhci-tegra.c
index ce6526c2caf6..9530cfc83f45 100644
--- a/drivers/usb/host/xhci-tegra.c
+++ b/drivers/usb/host/xhci-tegra.c
@@ -15,9 +15,11 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_device.h>
+#include <linux/of_irq.h>
#include <linux/phy/phy.h>
#include <linux/phy/tegra/xusb.h>
#include <linux/platform_device.h>
+#include <linux/usb/ch9.h>
#include <linux/pm.h>
#include <linux/pm_domain.h>
#include <linux/pm_runtime.h>
@@ -224,6 +226,7 @@ struct tegra_xusb {
int xhci_irq;
int mbox_irq;
+ int padctl_irq;
void __iomem *ipfs_base;
void __iomem *fpci_base;
@@ -268,10 +271,13 @@ struct tegra_xusb {
dma_addr_t phys;
} fw;
+ bool suspended;
struct tegra_xusb_context context;
};
static struct hc_driver __read_mostly tegra_xhci_hc_driver;
+static int tegra_xusb_exit_elpg(struct tegra_xusb *tegra, bool runtime);
+static int tegra_xusb_enter_elpg(struct tegra_xusb *tegra, bool runtime);
static inline u32 fpci_readl(struct tegra_xusb *tegra, unsigned int offset)
{
@@ -657,6 +663,9 @@ static irqreturn_t tegra_xusb_mbox_thread(int irq, void *data)
mutex_lock(&tegra->lock);
+ if (pm_runtime_suspended(tegra->dev) || tegra->suspended)
+ goto out;
+
value = fpci_readl(tegra, tegra->soc->mbox.data_out);
tegra_xusb_mbox_unpack(&msg, value);
@@ -670,6 +679,7 @@ static irqreturn_t tegra_xusb_mbox_thread(int irq, void *data)
tegra_xusb_mbox_handle(tegra, &msg);
+out:
mutex_unlock(&tegra->lock);
return IRQ_HANDLED;
}
@@ -812,12 +822,27 @@ static void tegra_xusb_phy_disable(struct tegra_xusb *tegra)
static int tegra_xusb_runtime_suspend(struct device *dev)
{
- return 0;
+ struct tegra_xusb *tegra = dev_get_drvdata(dev);
+ int ret;
+
+ synchronize_irq(tegra->mbox_irq);
+ mutex_lock(&tegra->lock);
+ ret = tegra_xusb_enter_elpg(tegra, true);
+ mutex_unlock(&tegra->lock);
+
+ return ret;
}
static int tegra_xusb_runtime_resume(struct device *dev)
{
- return 0;
+ struct tegra_xusb *tegra = dev_get_drvdata(dev);
+ int err;
+
+ mutex_lock(&tegra->lock);
+ err = tegra_xusb_exit_elpg(tegra, true);
+ mutex_unlock(&tegra->lock);
+
+ return err;
}
#ifdef CONFIG_PM_SLEEP
@@ -1121,6 +1146,22 @@ static int __tegra_xusb_enable_firmware_messages(struct tegra_xusb *tegra)
return err;
}
+static irqreturn_t tegra_xusb_padctl_irq(int irq, void *data)
+{
+ struct tegra_xusb *tegra = data;
+
+ mutex_lock(&tegra->lock);
+ if (tegra->suspended) {
+ mutex_unlock(&tegra->lock);
+ return IRQ_HANDLED;
+ }
+ mutex_unlock(&tegra->lock);
+
+ pm_runtime_resume(tegra->dev);
+
+ return IRQ_HANDLED;
+}
+
static int tegra_xusb_enable_firmware_messages(struct tegra_xusb *tegra)
{
int err;
@@ -1244,6 +1285,51 @@ static void tegra_xhci_id_work(struct work_struct *work)
}
}
+static bool is_usb2_otg_phy(struct tegra_xusb *tegra, int index)
+{
+ return (tegra->usbphy[index] != NULL);
+}
+
+static bool is_usb3_otg_phy(struct tegra_xusb *tegra, int index)
+{
+ struct tegra_xusb_padctl *padctl = tegra->padctl;
+ int i, port;
+
+ for (i = 0; i < tegra->num_usb_phys; i++) {
+ if (is_usb2_otg_phy(tegra, i)) {
+ port = tegra_xusb_padctl_get_usb3_companion(padctl,i);
+ if (index == port)
+ return true;
+ }
+ }
+
+ return false;
+}
+
+static bool is_host_mode_phy(struct tegra_xusb *tegra, int phy_type, int index)
+{
+ if (strcmp(tegra->soc->phy_types[phy_type].name, "hsic") == 0)
+ return true;
+
+ if (strcmp(tegra->soc->phy_types[phy_type].name, "usb2") == 0) {
+ if (is_usb2_otg_phy(tegra, index)) {
+ return ((index == tegra->otg_usb2_port) &&
+ tegra->host_mode);
+ } else
+ return true;
+ }
+
+ if (strcmp(tegra->soc->phy_types[phy_type].name, "usb3") == 0) {
+ if (is_usb3_otg_phy(tegra, index)) {
+ return ((index == tegra->otg_usb3_port) &&
+ tegra->host_mode);
+ } else
+ return true;
+ }
+
+ return false;
+}
+
static int tegra_xusb_get_usb2_port(struct tegra_xusb *tegra,
struct usb_phy *usbphy)
{
@@ -1336,6 +1422,7 @@ static void tegra_xusb_deinit_usb_phy(struct tegra_xusb *tegra)
static int tegra_xusb_probe(struct platform_device *pdev)
{
struct tegra_xusb *tegra;
+ struct device_node *np;
struct resource *regs;
struct xhci_hcd *xhci;
unsigned int i, j, k;
@@ -1383,6 +1470,14 @@ static int tegra_xusb_probe(struct platform_device *pdev)
if (IS_ERR(tegra->padctl))
return PTR_ERR(tegra->padctl);
+ np = of_parse_phandle(pdev->dev.of_node, "nvidia,xusb-padctl", 0);
+ if (!np)
+ return -ENODEV;
+
+ tegra->padctl_irq = of_irq_get(np, 0);
+ if (tegra->padctl_irq < 0)
+ return tegra->padctl_irq;
+
tegra->host_clk = devm_clk_get(&pdev->dev, "xusb_host");
if (IS_ERR(tegra->host_clk)) {
err = PTR_ERR(tegra->host_clk);
@@ -1527,6 +1622,7 @@ static int tegra_xusb_probe(struct platform_device *pdev)
goto put_powerdomains;
}
+ tegra->hcd->skip_phy_initialization = 1;
tegra->hcd->regs = tegra->regs;
tegra->hcd->rsrc_start = regs->start;
tegra->hcd->rsrc_len = resource_size(regs);
@@ -1609,12 +1705,6 @@ static int tegra_xusb_probe(struct platform_device *pdev)
goto put_usb3;
}
- err = tegra_xusb_enable_firmware_messages(tegra);
- if (err < 0) {
- dev_err(&pdev->dev, "failed to enable messages: %d\n", err);
- goto remove_usb3;
- }
-
err = devm_request_threaded_irq(&pdev->dev, tegra->mbox_irq,
tegra_xusb_mbox_irq,
tegra_xusb_mbox_thread, 0,
@@ -1624,12 +1714,40 @@ static int tegra_xusb_probe(struct platform_device *pdev)
goto remove_usb3;
}
+ err = devm_request_threaded_irq(&pdev->dev, tegra->padctl_irq,
+ NULL,
+ tegra_xusb_padctl_irq,
+ IRQF_ONESHOT |
+ IRQF_TRIGGER_HIGH,
+ dev_name(&pdev->dev), tegra);
+ if (err < 0) {
+ dev_err(&pdev->dev, "failed to request padctl IRQ: %d\n", err);
+ goto remove_usb3;
+ }
+
+ err = tegra_xusb_enable_firmware_messages(tegra);
+ if (err < 0) {
+ dev_err(&pdev->dev, "failed to enable messages: %d\n", err);
+ goto remove_usb3;
+ }
+
err = tegra_xusb_init_usb_phy(tegra);
if (err < 0) {
dev_err(&pdev->dev, "failed to init USB PHY: %d\n", err);
goto remove_usb3;
}
+ /* Enable wake for both USB 2.0 and USB 3.0 roothubs */
+ device_init_wakeup(&tegra->hcd->self.root_hub->dev, true);
+ device_init_wakeup(&xhci->shared_hcd->self.root_hub->dev, true);
+ device_init_wakeup(tegra->dev, true);
+
+ pm_runtime_use_autosuspend(tegra->dev);
+ pm_runtime_set_autosuspend_delay(tegra->dev, 2000);
+ pm_runtime_mark_last_busy(tegra->dev);
+ pm_runtime_set_active(tegra->dev);
+ pm_runtime_enable(tegra->dev);
+
return 0;
remove_usb3:
@@ -1665,6 +1783,7 @@ static int tegra_xusb_remove(struct platform_device *pdev)
tegra_xusb_deinit_usb_phy(tegra);
+ pm_runtime_get_sync(&pdev->dev);
usb_remove_hcd(xhci->shared_hcd);
usb_put_hcd(xhci->shared_hcd);
xhci->shared_hcd = NULL;
@@ -1674,8 +1793,8 @@ static int tegra_xusb_remove(struct platform_device *pdev)
dma_free_coherent(&pdev->dev, tegra->fw.size, tegra->fw.virt,
tegra->fw.phys);
- pm_runtime_put_sync(&pdev->dev);
pm_runtime_disable(&pdev->dev);
+ pm_runtime_put(&pdev->dev);
tegra_xusb_powergate_partitions(tegra);
@@ -1717,9 +1836,17 @@ static bool xhci_hub_ports_suspended(struct xhci_hub *hub)
static int tegra_xusb_check_ports(struct tegra_xusb *tegra)
{
struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
+ struct xhci_hub *rhub = xhci_get_rhub(xhci->main_hcd);
+ struct xhci_bus_state *bus_state = &rhub->bus_state;
unsigned long flags;
int err = 0;
+ if (bus_state->bus_suspended) {
+ /* xusb_hub_suspend() has just directed one or more USB2 port(s)
+ * to U3 state, it takes 3ms to enter U3. */
+ usleep_range(3000, 4000);
+ }
+
spin_lock_irqsave(&xhci->lock, flags);
if (!xhci_hub_ports_suspended(&xhci->usb2_rhub) ||
@@ -1765,45 +1892,184 @@ static void tegra_xusb_restore_context(struct tegra_xusb *tegra)
}
}
-static int tegra_xusb_enter_elpg(struct tegra_xusb *tegra, bool wakeup)
+static enum usb_device_speed
+tegra_xhci_portsc_to_speed(struct tegra_xusb *tegra, u32 portsc)
+{
+ if (DEV_LOWSPEED(portsc))
+ return USB_SPEED_LOW;
+ else if (DEV_HIGHSPEED(portsc))
+ return USB_SPEED_HIGH;
+ else if (DEV_FULLSPEED(portsc))
+ return USB_SPEED_FULL;
+ else if (DEV_SUPERSPEED_ANY(portsc))
+ return USB_SPEED_SUPER;
+ else
+ return USB_SPEED_UNKNOWN;
+}
+
+static void tegra_xhci_enable_phy_sleepwalk_wake(struct tegra_xusb *tegra)
+{
+ struct tegra_xusb_padctl *padctl = tegra->padctl;
+ struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
+ enum usb_device_speed speed;
+ struct phy *phy;
+ int index, offset;
+ int i, j, k;
+ struct xhci_hub *rhub;
+ u32 portsc;
+
+ for (i = 0, k = 0; i < tegra->soc->num_types; i++) {
+ if (strcmp(tegra->soc->phy_types[i].name, "usb3") == 0)
+ rhub = &xhci->usb3_rhub;
+ else
+ rhub = &xhci->usb2_rhub;
+
+ if (strcmp(tegra->soc->phy_types[i].name, "hsic") == 0)
+ offset = tegra->soc->ports.usb2.count;
+ else
+ offset = 0;
+
+ for (j = 0; j < tegra->soc->phy_types[i].num; j++) {
+ phy = tegra->phys[k++];
+
+ if (!phy)
+ continue;
+
+ index = j + offset;
+
+ if (index >= rhub->num_ports)
+ continue;
+
+ if (!is_host_mode_phy(tegra, i, j))
+ continue;
+
+ portsc = readl(rhub->ports[index]->addr);
+ speed = tegra_xhci_portsc_to_speed(tegra, portsc);
+ tegra_xusb_padctl_enable_phy_sleepwalk(padctl, phy,
+ speed);
+ tegra_xusb_padctl_enable_phy_wake(padctl, phy);
+ }
+ }
+}
+
+static void tegra_xhci_disable_phy_wake(struct tegra_xusb *tegra)
+{
+ struct tegra_xusb_padctl *padctl = tegra->padctl;
+ int i;
+
+ for (i = 0; i < tegra->num_phys; i++) {
+ if (!tegra->phys[i])
+ continue;
+
+ tegra_xusb_padctl_disable_phy_wake(padctl, tegra->phys[i]);
+ }
+}
+
+static void tegra_xhci_disable_phy_sleepwalk(struct tegra_xusb *tegra)
+{
+ struct tegra_xusb_padctl *padctl = tegra->padctl;
+ int i;
+
+ for (i = 0; i < tegra->num_phys; i++) {
+ if (!tegra->phys[i])
+ continue;
+
+ tegra_xusb_padctl_disable_phy_sleepwalk(padctl, tegra->phys[i]);
+ }
+}
+
+static int tegra_xusb_enter_elpg(struct tegra_xusb *tegra, bool runtime)
{
struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
+ struct device *dev = tegra->dev;
+ bool wakeup = runtime ? true : device_may_wakeup(dev);
+ unsigned int i;
int err;
+ u32 usbcmd;
+
+ dev_dbg(dev, "entering ELPG\n");
+
+ usbcmd = readl(&xhci->op_regs->command);
+ usbcmd &= ~CMD_EIE;
+ writel(usbcmd, &xhci->op_regs->command);
err = tegra_xusb_check_ports(tegra);
if (err < 0) {
dev_err(tegra->dev, "not all ports suspended: %d\n", err);
- return err;
+ goto out;
}
err = xhci_suspend(xhci, wakeup);
if (err < 0) {
dev_err(tegra->dev, "failed to suspend XHCI: %d\n", err);
- return err;
+ goto out;
}
tegra_xusb_save_context(tegra);
- tegra_xusb_phy_disable(tegra);
+
+ if (wakeup)
+ tegra_xhci_enable_phy_sleepwalk_wake(tegra);
+
+ tegra_xusb_powergate_partitions(tegra);
+
+ for (i = 0; i < tegra->num_phys; i++) {
+ if (!tegra->phys[i])
+ continue;
+
+ phy_power_off(tegra->phys[i]);
+ if (!wakeup)
+ phy_exit(tegra->phys[i]);
+ }
tegra_xusb_clk_disable(tegra);
- return 0;
+out:
+ if (!err)
+ dev_dbg(tegra->dev, "entering ELPG done\n");
+ else {
+ usbcmd = readl(&xhci->op_regs->command);
+ usbcmd |= CMD_EIE;
+ writel(usbcmd, &xhci->op_regs->command);
+
+ dev_dbg(tegra->dev, "entering ELPG failed\n");
+ pm_runtime_mark_last_busy(tegra->dev);
+ }
+
+ return err;
}
-static int tegra_xusb_exit_elpg(struct tegra_xusb *tegra, bool wakeup)
+static int tegra_xusb_exit_elpg(struct tegra_xusb *tegra, bool runtime)
{
struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
+ struct device *dev = tegra->dev;
+ bool wakeup = runtime ? true : device_may_wakeup(dev);
+ unsigned int i;
+ u32 usbcmd;
int err;
+ dev_dbg(dev, "exiting ELPG\n");
+ pm_runtime_mark_last_busy(tegra->dev);
+
err = tegra_xusb_clk_enable(tegra);
if (err < 0) {
dev_err(tegra->dev, "failed to enable clocks: %d\n", err);
- return err;
+ goto out;
}
- err = tegra_xusb_phy_enable(tegra);
- if (err < 0) {
- dev_err(tegra->dev, "failed to enable PHYs: %d\n", err);
- goto disable_clk;
+ err = tegra_xusb_unpowergate_partitions(tegra);
+ if (err)
+ goto disable_clks;
+
+ if (wakeup)
+ tegra_xhci_disable_phy_wake(tegra);
+
+ for (i = 0; i < tegra->num_phys; i++) {
+ if (!tegra->phys[i])
+ continue;
+
+ if (!wakeup)
+ phy_init(tegra->phys[i]);
+
+ phy_power_on(tegra->phys[i]);
}
tegra_xusb_config(tegra);
@@ -1821,31 +2087,78 @@ static int tegra_xusb_exit_elpg(struct tegra_xusb *tegra, bool wakeup)
goto disable_phy;
}
- err = xhci_resume(xhci, true);
+ if (wakeup)
+ tegra_xhci_disable_phy_sleepwalk(tegra);
+
+ err = xhci_resume(xhci, 0);
if (err < 0) {
dev_err(tegra->dev, "failed to resume XHCI: %d\n", err);
goto disable_phy;
}
- return 0;
+ usbcmd = readl(&xhci->op_regs->command);
+ usbcmd |= CMD_EIE;
+ writel(usbcmd, &xhci->op_regs->command);
+
+ goto out;
disable_phy:
- tegra_xusb_phy_disable(tegra);
-disable_clk:
+ for (i = 0; i < tegra->num_phys; i++) {
+ if (!tegra->phys[i])
+ continue;
+
+ phy_power_off(tegra->phys[i]);
+ if (!wakeup)
+ phy_exit(tegra->phys[i]);
+ }
+ tegra_xusb_powergate_partitions(tegra);
+disable_clks:
tegra_xusb_clk_disable(tegra);
+out:
+ if (!err)
+ dev_dbg(dev, "exiting ELPG done\n");
+ else
+ dev_dbg(dev, "exiting ELPG failed\n");
+
return err;
}
static int tegra_xusb_suspend(struct device *dev)
{
struct tegra_xusb *tegra = dev_get_drvdata(dev);
- bool wakeup = device_may_wakeup(dev);
int err;
synchronize_irq(tegra->mbox_irq);
-
mutex_lock(&tegra->lock);
- err = tegra_xusb_enter_elpg(tegra, wakeup);
+
+ if (pm_runtime_suspended(dev)) {
+ err = tegra_xusb_exit_elpg(tegra, true);
+ if (err < 0)
+ goto out;
+ }
+
+ err = tegra_xusb_enter_elpg(tegra, false);
+ if (err < 0) {
+ if (pm_runtime_suspended(dev)) {
+ pm_runtime_disable(dev);
+ pm_runtime_set_active(dev);
+ pm_runtime_enable(dev);
+ }
+
+ goto out;
+ }
+
+out:
+ if (!err) {
+ tegra->suspended = true;
+ pm_runtime_disable(dev);
+
+ if (device_may_wakeup(dev)) {
+ if (enable_irq_wake(tegra->padctl_irq))
+ dev_err(dev, "failed to enable padctl wakes\n");
+ }
+ }
+
mutex_unlock(&tegra->lock);
return err;
@@ -1854,14 +2167,32 @@ static int tegra_xusb_suspend(struct device *dev)
static int tegra_xusb_resume(struct device *dev)
{
struct tegra_xusb *tegra = dev_get_drvdata(dev);
- bool wakeup = device_may_wakeup(dev);
int err;
mutex_lock(&tegra->lock);
- err = tegra_xusb_exit_elpg(tegra, wakeup);
+
+ if (!tegra->suspended) {
+ mutex_unlock(&tegra->lock);
+ return 0;
+ }
+
+ err = tegra_xusb_exit_elpg(tegra, false);
+ if (err < 0) {
+ mutex_unlock(&tegra->lock);
+ return err;
+ }
+
+ if (device_may_wakeup(dev)) {
+ if (disable_irq_wake(tegra->padctl_irq))
+ dev_err(dev, "failed to disable padctl wakes\n");
+ }
+ tegra->suspended = false;
mutex_unlock(&tegra->lock);
- return err;
+ pm_runtime_set_active(dev);
+ pm_runtime_enable(dev);
+
+ return 0;
}
#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 06/12] soc/tegra: pmc: provide usb sleepwalk register map
2020-08-28 1:10 ` [PATCH 06/12] soc/tegra: pmc: provide usb sleepwalk register map JC Kuo
@ 2020-08-28 10:53 ` kernel test robot
0 siblings, 0 replies; 15+ messages in thread
From: kernel test robot @ 2020-08-28 10:53 UTC (permalink / raw)
To: JC Kuo, gregkh, thierry.reding, robh, jonathanh, kishon
Cc: kbuild-all, linux-tegra, linux-usb, linux-kernel, devicetree, nkristam
[-- Attachment #1: Type: text/plain, Size: 2609 bytes --]
Hi JC,
I love your patch! Perhaps something to improve:
[auto build test WARNING on tegra/for-next]
[also build test WARNING on robh/for-next usb/usb-testing char-misc/char-misc-testing staging/staging-testing driver-core/driver-core-testing v5.9-rc2 next-20200827]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/JC-Kuo/Tegra-XHCI-controller-ELPG-support/20200828-091337
base: https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git for-next
config: arm-multi_v7_defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
>> drivers/soc/tegra/pmc.c:2537:5: warning: no previous prototype for 'tegra_pmc_regmap_readl' [-Wmissing-prototypes]
2537 | int tegra_pmc_regmap_readl(void *context, unsigned int reg, unsigned int *val)
| ^~~~~~~~~~~~~~~~~~~~~~
>> drivers/soc/tegra/pmc.c:2545:5: warning: no previous prototype for 'tegra_pmc_regmap_writel' [-Wmissing-prototypes]
2545 | int tegra_pmc_regmap_writel(void *context, unsigned int reg, unsigned int val)
| ^~~~~~~~~~~~~~~~~~~~~~~
# https://github.com/0day-ci/linux/commit/56def0140d21d6eeb92615ae6ec5f7e25095c37f
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review JC-Kuo/Tegra-XHCI-controller-ELPG-support/20200828-091337
git checkout 56def0140d21d6eeb92615ae6ec5f7e25095c37f
vim +/tegra_pmc_regmap_readl +2537 drivers/soc/tegra/pmc.c
2536
> 2537 int tegra_pmc_regmap_readl(void *context, unsigned int reg, unsigned int *val)
2538 {
2539 struct tegra_pmc *pmc = context;
2540
2541 *val = tegra_pmc_readl(pmc, reg);
2542 return 0;
2543 }
2544
> 2545 int tegra_pmc_regmap_writel(void *context, unsigned int reg, unsigned int val)
2546 {
2547 struct tegra_pmc *pmc = context;
2548
2549 tegra_pmc_writel(pmc, val, reg);
2550 return 0;
2551 }
2552
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 53062 bytes --]
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 06/12] soc/tegra: pmc: provide usb sleepwalk register map
@ 2020-08-28 10:53 ` kernel test robot
0 siblings, 0 replies; 15+ messages in thread
From: kernel test robot @ 2020-08-28 10:53 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 2670 bytes --]
Hi JC,
I love your patch! Perhaps something to improve:
[auto build test WARNING on tegra/for-next]
[also build test WARNING on robh/for-next usb/usb-testing char-misc/char-misc-testing staging/staging-testing driver-core/driver-core-testing v5.9-rc2 next-20200827]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/JC-Kuo/Tegra-XHCI-controller-ELPG-support/20200828-091337
base: https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git for-next
config: arm-multi_v7_defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
>> drivers/soc/tegra/pmc.c:2537:5: warning: no previous prototype for 'tegra_pmc_regmap_readl' [-Wmissing-prototypes]
2537 | int tegra_pmc_regmap_readl(void *context, unsigned int reg, unsigned int *val)
| ^~~~~~~~~~~~~~~~~~~~~~
>> drivers/soc/tegra/pmc.c:2545:5: warning: no previous prototype for 'tegra_pmc_regmap_writel' [-Wmissing-prototypes]
2545 | int tegra_pmc_regmap_writel(void *context, unsigned int reg, unsigned int val)
| ^~~~~~~~~~~~~~~~~~~~~~~
# https://github.com/0day-ci/linux/commit/56def0140d21d6eeb92615ae6ec5f7e25095c37f
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review JC-Kuo/Tegra-XHCI-controller-ELPG-support/20200828-091337
git checkout 56def0140d21d6eeb92615ae6ec5f7e25095c37f
vim +/tegra_pmc_regmap_readl +2537 drivers/soc/tegra/pmc.c
2536
> 2537 int tegra_pmc_regmap_readl(void *context, unsigned int reg, unsigned int *val)
2538 {
2539 struct tegra_pmc *pmc = context;
2540
2541 *val = tegra_pmc_readl(pmc, reg);
2542 return 0;
2543 }
2544
> 2545 int tegra_pmc_regmap_writel(void *context, unsigned int reg, unsigned int val)
2546 {
2547 struct tegra_pmc *pmc = context;
2548
2549 tegra_pmc_writel(pmc, val, reg);
2550 return 0;
2551 }
2552
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 53062 bytes --]
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2020-08-28 11:05 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-08-28 1:10 [PATCH 00/12] Tegra XHCI controller ELPG support JC Kuo
2020-08-28 1:10 ` [PATCH 01/12] clk: tegra: Add PLLE HW power sequencer control JC Kuo
2020-08-28 1:10 ` [PATCH 02/12] clk: tegra: don't enable PLLE HW sequencer at init JC Kuo
2020-08-28 1:10 ` [PATCH 03/12] phy: tegra: xusb: t210: rearrange UPHY init JC Kuo
2020-08-28 1:10 ` [PATCH 04/12] phy: tegra: xusb: t210: add lane_iddq operations JC Kuo
2020-08-28 1:10 ` [PATCH 05/12] phy: tegra: xusb: add sleepwalk and suspend/resume JC Kuo
2020-08-28 1:10 ` [PATCH 06/12] soc/tegra: pmc: provide usb sleepwalk register map JC Kuo
2020-08-28 10:53 ` kernel test robot
2020-08-28 10:53 ` kernel test robot
2020-08-28 1:10 ` [PATCH 07/12] arm64: tegra210: XUSB PADCTL add "nvidia,pmc" prop JC Kuo
2020-08-28 1:10 ` [PATCH 08/12] phy: tegra: xusb: t210: support wake and sleepwalk JC Kuo
2020-08-28 1:10 ` [PATCH 09/12] phy: tegra: xusb: t186: " JC Kuo
2020-08-28 1:10 ` [PATCH 10/12] arm64: tegra210/tegra186/tegra194: XUSB PADCTL irq JC Kuo
2020-08-28 1:10 ` [PATCH 11/12] usb: host: xhci-tegra: unlink power domain devices JC Kuo
2020-08-28 1:10 ` [PATCH 12/12] xhci: tegra: enable ELPG for runtime/system PM JC Kuo
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