[PATCH v2 0/9] IPQ40xx: Improve support

[PATCH v2 0/9] IPQ40xx: Improve support

[Robert Marko]

This patch series builds on the previously merged basic
Qualcomm IPQ40xx series support.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>

Robert Marko (9):
  dt-bindings: clock: import Qualcomm IPQ4019 bindings
  IPQ40xx: clk: Use dt-bindings instead of hardcoding
  IPQ40xx: Add SMEM support
  reset: Add IPQ40xx reset controller driver
  IPQ40xx: Add reset controller support
  phy: add driver for Qualcomm IPQ40xx USB PHY
  usb: dwc3: Make PHY functions depend on CONFIG_USB_DWC3
  usb: xhci: Add Qualcomm DWC3 xHCI driver
  IPQ40xx: Add USB nodes

 MAINTAINERS                                   |   6 +
 arch/arm/Kconfig                              |   3 +
 arch/arm/dts/qcom-ipq4019.dtsi                |  67 ++++++-
 arch/arm/mach-ipq40xx/clock-ipq4019.c         |   4 +-
 .../usb/qcom-dwc3-ipq.txt                     |  34 ++++
 drivers/phy/Kconfig                           |   6 +
 drivers/phy/Makefile                          |   1 +
 drivers/phy/phy-qcom-ipq4019-usb.c            | 145 +++++++++++++++
 drivers/reset/Kconfig                         |   8 +
 drivers/reset/Makefile                        |   1 +
 drivers/reset/reset-ipq4019.c                 | 173 ++++++++++++++++++
 drivers/smem/Kconfig                          |   2 +-
 drivers/usb/host/Kconfig                      |   6 +
 drivers/usb/host/Makefile                     |   1 +
 drivers/usb/host/xhci-ipq.c                   | 117 ++++++++++++
 include/dt-bindings/clock/qcom,ipq4019-gcc.h  |  96 ++++++++++
 .../dt-bindings/reset/qcom,ipq4019-reset.h    |  92 ++++++++++
 include/dwc3-uboot.h                          |   2 +-
 18 files changed, 760 insertions(+), 4 deletions(-)
 create mode 100644 doc/device-tree-bindings/usb/qcom-dwc3-ipq.txt
 create mode 100644 drivers/phy/phy-qcom-ipq4019-usb.c
 create mode 100644 drivers/reset/reset-ipq4019.c
 create mode 100644 drivers/usb/host/xhci-ipq.c
 create mode 100644 include/dt-bindings/clock/qcom,ipq4019-gcc.h
 create mode 100644 include/dt-bindings/reset/qcom,ipq4019-reset.h

-- 
2.26.2

[PATCH v2 1/9] dt-bindings: clock: import Qualcomm IPQ4019 bindings

[Robert Marko]

Import Qualcomm IPQ4019 GCC bindings from Linux.
This will enable using bindings instead of raw clock numbers both in the driver and DTS like Linux does.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
---
 MAINTAINERS                                  |  1 +
 include/dt-bindings/clock/qcom,ipq4019-gcc.h | 96 ++++++++++++++++++++
 2 files changed, 97 insertions(+)
 create mode 100644 include/dt-bindings/clock/qcom,ipq4019-gcc.h

diff --git a/MAINTAINERS b/MAINTAINERS
index bebe87b4d1..c0e902a424 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -237,6 +237,7 @@ M:	Luka Kovacic <luka.kovacic@sartura.hr>
 M:	Luka Perkov <luka.perkov@sartura.hr>
 S:	Maintained
 F:	arch/arm/mach-ipq40xx/
+F:	include/dt-bindings/clock/qcom,ipq4019-gcc.h
 
 ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX ARMADA-7K/8K
 M:	Stefan Roese <sr@denx.de>
diff --git a/include/dt-bindings/clock/qcom,ipq4019-gcc.h b/include/dt-bindings/clock/qcom,ipq4019-gcc.h
new file mode 100644
index 0000000000..7130e222e4
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,ipq4019-gcc.h
@@ -0,0 +1,96 @@
+/* Copyright (c) 2015 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+#ifndef __QCOM_CLK_IPQ4019_H__
+#define __QCOM_CLK_IPQ4019_H__
+
+#define GCC_DUMMY_CLK					0
+#define AUDIO_CLK_SRC					1
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC			2
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC			3
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC			4
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC			5
+#define BLSP1_UART1_APPS_CLK_SRC			6
+#define BLSP1_UART2_APPS_CLK_SRC			7
+#define GCC_USB3_MOCK_UTMI_CLK_SRC			8
+#define GCC_APPS_CLK_SRC				9
+#define GCC_APPS_AHB_CLK_SRC				10
+#define GP1_CLK_SRC					11
+#define GP2_CLK_SRC					12
+#define GP3_CLK_SRC					13
+#define SDCC1_APPS_CLK_SRC				14
+#define FEPHY_125M_DLY_CLK_SRC				15
+#define WCSS2G_CLK_SRC					16
+#define WCSS5G_CLK_SRC					17
+#define GCC_APSS_AHB_CLK				18
+#define GCC_AUDIO_AHB_CLK				19
+#define GCC_AUDIO_PWM_CLK				20
+#define GCC_BLSP1_AHB_CLK				21
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK			22
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK			23
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK			24
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK			25
+#define GCC_BLSP1_UART1_APPS_CLK			26
+#define GCC_BLSP1_UART2_APPS_CLK			27
+#define GCC_DCD_XO_CLK					28
+#define GCC_GP1_CLK					29
+#define GCC_GP2_CLK					30
+#define GCC_GP3_CLK					31
+#define GCC_BOOT_ROM_AHB_CLK				32
+#define GCC_CRYPTO_AHB_CLK				33
+#define GCC_CRYPTO_AXI_CLK				34
+#define GCC_CRYPTO_CLK					35
+#define GCC_ESS_CLK					36
+#define GCC_IMEM_AXI_CLK				37
+#define GCC_IMEM_CFG_AHB_CLK				38
+#define GCC_PCIE_AHB_CLK				39
+#define GCC_PCIE_AXI_M_CLK				40
+#define GCC_PCIE_AXI_S_CLK				41
+#define GCC_PCNOC_AHB_CLK				42
+#define GCC_PRNG_AHB_CLK				43
+#define GCC_QPIC_AHB_CLK				44
+#define GCC_QPIC_CLK					45
+#define GCC_SDCC1_AHB_CLK				46
+#define GCC_SDCC1_APPS_CLK				47
+#define GCC_SNOC_PCNOC_AHB_CLK				48
+#define GCC_SYS_NOC_125M_CLK				49
+#define GCC_SYS_NOC_AXI_CLK				50
+#define GCC_TCSR_AHB_CLK				51
+#define GCC_TLMM_AHB_CLK				52
+#define GCC_USB2_MASTER_CLK				53
+#define GCC_USB2_SLEEP_CLK				54
+#define GCC_USB2_MOCK_UTMI_CLK				55
+#define GCC_USB3_MASTER_CLK				56
+#define GCC_USB3_SLEEP_CLK				57
+#define GCC_USB3_MOCK_UTMI_CLK				58
+#define GCC_WCSS2G_CLK					59
+#define GCC_WCSS2G_REF_CLK				60
+#define GCC_WCSS2G_RTC_CLK				61
+#define GCC_WCSS5G_CLK					62
+#define GCC_WCSS5G_REF_CLK				63
+#define GCC_WCSS5G_RTC_CLK				64
+#define GCC_APSS_DDRPLL_VCO				65
+#define GCC_SDCC_PLLDIV_CLK				66
+#define GCC_FEPLL_VCO					67
+#define GCC_FEPLL125_CLK				68
+#define GCC_FEPLL125DLY_CLK				69
+#define GCC_FEPLL200_CLK				70
+#define GCC_FEPLL500_CLK				71
+#define GCC_FEPLL_WCSS2G_CLK				72
+#define GCC_FEPLL_WCSS5G_CLK				73
+#define GCC_APSS_CPU_PLLDIV_CLK				74
+#define GCC_PCNOC_AHB_CLK_SRC				75
+
+#endif
-- 
2.26.2

[PATCH v2 2/9] IPQ40xx: clk: Use dt-bindings instead of hardcoding

[Robert Marko]

Its common to use dt-bindings instead of hard-coding clocks or resets.
So lets use the imported Linux GCC bindings on IPQ40xx target.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
---
 arch/arm/dts/qcom-ipq4019.dtsi        | 3 ++-
 arch/arm/mach-ipq40xx/clock-ipq4019.c | 4 +++-
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/qcom-ipq4019.dtsi b/arch/arm/dts/qcom-ipq4019.dtsi
index 5f78bc5ab9..7b3b5e0248 100644
--- a/arch/arm/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/dts/qcom-ipq4019.dtsi
@@ -10,6 +10,7 @@
 #include "skeleton.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/pinctrl/pinctrl-snapdragon.h>
+#include <dt-bindings/clock/qcom,ipq4019-gcc.h>
 
 / {
 	#address-cells = <1>;
@@ -61,7 +62,7 @@
 		blsp1_uart1: serial at 78af000 {
 			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 			reg = <0x78af000 0x200>;
-			clock = <&gcc 26>;
+			clock = <&gcc GCC_BLSP1_UART1_APPS_CLK>;
 			bit-rate = <0xFF>;
 			status = "disabled";
 			u-boot,dm-pre-reloc;
diff --git a/arch/arm/mach-ipq40xx/clock-ipq4019.c b/arch/arm/mach-ipq40xx/clock-ipq4019.c
index 7cf98a203c..83a688e625 100644
--- a/arch/arm/mach-ipq40xx/clock-ipq4019.c
+++ b/arch/arm/mach-ipq40xx/clock-ipq4019.c
@@ -13,6 +13,8 @@
 #include <dm.h>
 #include <errno.h>
 
+#include <dt-bindings/clock/qcom,ipq4019-gcc.h>
+
 struct msm_clk_priv {
 	phys_addr_t base;
 };
@@ -20,7 +22,7 @@ struct msm_clk_priv {
 ulong msm_set_rate(struct clk *clk, ulong rate)
 {
 	switch (clk->id) {
-	case 26: /*UART1*/
+	case GCC_BLSP1_UART1_APPS_CLK: /*UART1*/
 		/* This clock is already initialized by SBL1 */
 		return 0; 
 		break;
-- 
2.26.2

[PATCH v2 3/9] IPQ40xx: Add SMEM support

[Robert Marko]

There is already existing driver for SMEM so lets enable it for IPQ40xx as well.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
---
 arch/arm/Kconfig               | 2 ++
 arch/arm/dts/qcom-ipq4019.dtsi | 5 +++++
 drivers/smem/Kconfig           | 2 +-
 3 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 80702c23d3..ee378f03f4 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -767,8 +767,10 @@ config ARCH_IPQ40XX
 	select DM
 	select DM_GPIO
 	select DM_SERIAL
+	select MSM_SMEM
 	select PINCTRL
 	select CLK
+	select SMEM
 	select OF_CONTROL
 	imply CMD_DM
 
diff --git a/arch/arm/dts/qcom-ipq4019.dtsi b/arch/arm/dts/qcom-ipq4019.dtsi
index 7b3b5e0248..dd69d0a5b2 100644
--- a/arch/arm/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/dts/qcom-ipq4019.dtsi
@@ -39,6 +39,11 @@
 		};
 	};
 
+	smem {
+		compatible = "qcom,smem";
+		memory-region = <&smem_mem>;
+	};
+
 	soc: soc {
 		#address-cells = <1>;
 		#size-cells = <1>;
diff --git a/drivers/smem/Kconfig b/drivers/smem/Kconfig
index 7169d0f205..73d51b3a7a 100644
--- a/drivers/smem/Kconfig
+++ b/drivers/smem/Kconfig
@@ -15,7 +15,7 @@ config SANDBOX_SMEM
 config MSM_SMEM
     bool "Qualcomm Shared Memory Manager (SMEM)"
     depends on DM
-    depends on ARCH_SNAPDRAGON
+    depends on ARCH_SNAPDRAGON || ARCH_IPQ40XX
     help
       Enable support for the Qualcomm Shared Memory Manager.
       The driver provides an interface to items in a heap shared among all
-- 
2.26.2

[PATCH v2 4/9] reset: Add IPQ40xx reset controller driver

[Robert Marko]

On Qualcomm IPQ40xx SoC series, GCC clock IP also handles the resets.
So since this will be needed by further drivers, lets add a driver for the reset controller.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
---
 MAINTAINERS                                   |   2 +
 drivers/reset/Kconfig                         |   8 +
 drivers/reset/Makefile                        |   1 +
 drivers/reset/reset-ipq4019.c                 | 173 ++++++++++++++++++
 .../dt-bindings/reset/qcom,ipq4019-reset.h    |  92 ++++++++++
 5 files changed, 276 insertions(+)
 create mode 100644 drivers/reset/reset-ipq4019.c
 create mode 100644 include/dt-bindings/reset/qcom,ipq4019-reset.h

diff --git a/MAINTAINERS b/MAINTAINERS
index c0e902a424..f4fc823e4e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -238,6 +238,8 @@ M:	Luka Perkov <luka.perkov@sartura.hr>
 S:	Maintained
 F:	arch/arm/mach-ipq40xx/
 F:	include/dt-bindings/clock/qcom,ipq4019-gcc.h
+F:	include/dt-bindings/reset/qcom,ipq4019-reset.h
+F:	drivers/reset/reset-ipq4019.c
 
 ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX ARMADA-7K/8K
 M:	Stefan Roese <sr@denx.de>
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 253902ff57..3fdfe4a6cb 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -148,6 +148,14 @@ config RESET_IMX7
 	help
 	  Support for reset controller on i.MX7/8 SoCs.
 
+config RESET_IPQ419
+	bool "Reset driver for Qualcomm IPQ40xx SoCs"
+	depends on DM_RESET && ARCH_IPQ40XX
+	default y
+	help
+	  Support for reset controller on Qualcomm
+	  IPQ40xx SoCs.
+
 config RESET_SIFIVE
 	bool "Reset Driver for SiFive SoC's"
 	depends on DM_RESET && CLK_SIFIVE_FU540_PRCI && TARGET_SIFIVE_FU540
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 3c7f066ae3..5176da5885 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_RESET_MTMIPS) += reset-mtmips.o
 obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
 obj-$(CONFIG_RESET_HISILICON) += reset-hisilicon.o
 obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
+obj-$(CONFIG_RESET_IPQ419) += reset-ipq4019.o
 obj-$(CONFIG_RESET_SIFIVE) += reset-sifive.o
 obj-$(CONFIG_RESET_SYSCON) += reset-syscon.o
 obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o
diff --git a/drivers/reset/reset-ipq4019.c b/drivers/reset/reset-ipq4019.c
new file mode 100644
index 0000000000..f216db4ce5
--- /dev/null
+++ b/drivers/reset/reset-ipq4019.c
@@ -0,0 +1,173 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020 Sartura Ltd.
+ *
+ * Author: Robert Marko <robert.marko@sartura.hr>
+ *
+ * Based on Linux driver
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <dm.h>
+#include <dt-bindings/reset/qcom,ipq4019-reset.h>
+#include <reset-uclass.h>
+#include <linux/bitops.h>
+#include <malloc.h>
+
+struct ipq4019_reset_priv {
+	phys_addr_t base;
+};
+
+struct qcom_reset_map {
+	unsigned int reg;
+	u8 bit;
+};
+
+static const struct qcom_reset_map gcc_ipq4019_resets[] = {
+	[WIFI0_CPU_INIT_RESET] = { 0x1f008, 5 },
+	[WIFI0_RADIO_SRIF_RESET] = { 0x1f008, 4 },
+	[WIFI0_RADIO_WARM_RESET] = { 0x1f008, 3 },
+	[WIFI0_RADIO_COLD_RESET] = { 0x1f008, 2 },
+	[WIFI0_CORE_WARM_RESET] = { 0x1f008, 1 },
+	[WIFI0_CORE_COLD_RESET] = { 0x1f008, 0 },
+	[WIFI1_CPU_INIT_RESET] = { 0x20008, 5 },
+	[WIFI1_RADIO_SRIF_RESET] = { 0x20008, 4 },
+	[WIFI1_RADIO_WARM_RESET] = { 0x20008, 3 },
+	[WIFI1_RADIO_COLD_RESET] = { 0x20008, 2 },
+	[WIFI1_CORE_WARM_RESET] = { 0x20008, 1 },
+	[WIFI1_CORE_COLD_RESET] = { 0x20008, 0 },
+	[USB3_UNIPHY_PHY_ARES] = { 0x1e038, 5 },
+	[USB3_HSPHY_POR_ARES] = { 0x1e038, 4 },
+	[USB3_HSPHY_S_ARES] = { 0x1e038, 2 },
+	[USB2_HSPHY_POR_ARES] = { 0x1e01c, 4 },
+	[USB2_HSPHY_S_ARES] = { 0x1e01c, 2 },
+	[PCIE_PHY_AHB_ARES] = { 0x1d010, 11 },
+	[PCIE_AHB_ARES] = { 0x1d010, 10 },
+	[PCIE_PWR_ARES] = { 0x1d010, 9 },
+	[PCIE_PIPE_STICKY_ARES] = { 0x1d010, 8 },
+	[PCIE_AXI_M_STICKY_ARES] = { 0x1d010, 7 },
+	[PCIE_PHY_ARES] = { 0x1d010, 6 },
+	[PCIE_PARF_XPU_ARES] = { 0x1d010, 5 },
+	[PCIE_AXI_S_XPU_ARES] = { 0x1d010, 4 },
+	[PCIE_AXI_M_VMIDMT_ARES] = { 0x1d010, 3 },
+	[PCIE_PIPE_ARES] = { 0x1d010, 2 },
+	[PCIE_AXI_S_ARES] = { 0x1d010, 1 },
+	[PCIE_AXI_M_ARES] = { 0x1d010, 0 },
+	[ESS_RESET] = { 0x12008, 0},
+	[GCC_BLSP1_BCR] = {0x01000, 0},
+	[GCC_BLSP1_QUP1_BCR] = {0x02000, 0},
+	[GCC_BLSP1_UART1_BCR] = {0x02038, 0},
+	[GCC_BLSP1_QUP2_BCR] = {0x03008, 0},
+	[GCC_BLSP1_UART2_BCR] = {0x03028, 0},
+	[GCC_BIMC_BCR] = {0x04000, 0},
+	[GCC_TLMM_BCR] = {0x05000, 0},
+	[GCC_IMEM_BCR] = {0x0E000, 0},
+	[GCC_ESS_BCR] = {0x12008, 0},
+	[GCC_PRNG_BCR] = {0x13000, 0},
+	[GCC_BOOT_ROM_BCR] = {0x13008, 0},
+	[GCC_CRYPTO_BCR] = {0x16000, 0},
+	[GCC_SDCC1_BCR] = {0x18000, 0},
+	[GCC_SEC_CTRL_BCR] = {0x1A000, 0},
+	[GCC_AUDIO_BCR] = {0x1B008, 0},
+	[GCC_QPIC_BCR] = {0x1C000, 0},
+	[GCC_PCIE_BCR] = {0x1D000, 0},
+	[GCC_USB2_BCR] = {0x1E008, 0},
+	[GCC_USB2_PHY_BCR] = {0x1E018, 0},
+	[GCC_USB3_BCR] = {0x1E024, 0},
+	[GCC_USB3_PHY_BCR] = {0x1E034, 0},
+	[GCC_SYSTEM_NOC_BCR] = {0x21000, 0},
+	[GCC_PCNOC_BCR] = {0x2102C, 0},
+	[GCC_DCD_BCR] = {0x21038, 0},
+	[GCC_SNOC_BUS_TIMEOUT0_BCR] = {0x21064, 0},
+	[GCC_SNOC_BUS_TIMEOUT1_BCR] = {0x2106C, 0},
+	[GCC_SNOC_BUS_TIMEOUT2_BCR] = {0x21074, 0},
+	[GCC_SNOC_BUS_TIMEOUT3_BCR] = {0x2107C, 0},
+	[GCC_PCNOC_BUS_TIMEOUT0_BCR] = {0x21084, 0},
+	[GCC_PCNOC_BUS_TIMEOUT1_BCR] = {0x2108C, 0},
+	[GCC_PCNOC_BUS_TIMEOUT2_BCR] = {0x21094, 0},
+	[GCC_PCNOC_BUS_TIMEOUT3_BCR] = {0x2109C, 0},
+	[GCC_PCNOC_BUS_TIMEOUT4_BCR] = {0x210A4, 0},
+	[GCC_PCNOC_BUS_TIMEOUT5_BCR] = {0x210AC, 0},
+	[GCC_PCNOC_BUS_TIMEOUT6_BCR] = {0x210B4, 0},
+	[GCC_PCNOC_BUS_TIMEOUT7_BCR] = {0x210BC, 0},
+	[GCC_PCNOC_BUS_TIMEOUT8_BCR] = {0x210C4, 0},
+	[GCC_PCNOC_BUS_TIMEOUT9_BCR] = {0x210CC, 0},
+	[GCC_TCSR_BCR] = {0x22000, 0},
+	[GCC_MPM_BCR] = {0x24000, 0},
+	[GCC_SPDM_BCR] = {0x25000, 0},
+};
+
+static int ipq4019_reset_assert(struct reset_ctl *rst)
+{
+	struct ipq4019_reset_priv *priv = dev_get_priv(rst->dev);
+	const struct qcom_reset_map *reset_map = gcc_ipq4019_resets;
+	const struct qcom_reset_map *map;
+	u32 value;
+
+	map = &reset_map[rst->id];
+
+	value = readl(priv->base + map->reg);
+	value |= BIT(map->bit);
+	writel(value, priv->base + map->reg);
+
+	return 0;
+}
+
+static int ipq4019_reset_deassert(struct reset_ctl *rst)
+{
+	struct ipq4019_reset_priv *priv = dev_get_priv(rst->dev);
+	const struct qcom_reset_map *reset_map = gcc_ipq4019_resets;
+	const struct qcom_reset_map *map;
+	u32 value;
+
+	map = &reset_map[rst->id];
+
+	value = readl(priv->base + map->reg);
+	value &= ~BIT(map->bit);
+	writel(value, priv->base + map->reg);
+
+	return 0;
+}
+
+static int ipq4019_reset_free(struct reset_ctl *rst)
+{
+	return 0;
+}
+
+static int ipq4019_reset_request(struct reset_ctl *rst)
+{
+	return 0;
+}
+
+static const struct reset_ops ipq4019_reset_ops = {
+	.request = ipq4019_reset_request,
+	.rfree = ipq4019_reset_free,
+	.rst_assert = ipq4019_reset_assert,
+	.rst_deassert = ipq4019_reset_deassert,
+};
+
+static const struct udevice_id ipq4019_reset_ids[] = {
+	{ .compatible = "qcom,gcc-reset-ipq4019" },
+	{ }
+};
+
+static int ipq4019_reset_probe(struct udevice *dev)
+{
+	struct ipq4019_reset_priv *priv = dev_get_priv(dev);
+
+	priv->base = dev_read_addr(dev);
+	if (priv->base == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	return 0;
+}
+
+U_BOOT_DRIVER(ipq4019_reset) = {
+	.name = "ipq4019_reset",
+	.id = UCLASS_RESET,
+	.of_match = ipq4019_reset_ids,
+	.ops = &ipq4019_reset_ops,
+	.probe = ipq4019_reset_probe,
+	.priv_auto_alloc_size = sizeof(struct ipq4019_reset_priv),
+};
diff --git a/include/dt-bindings/reset/qcom,ipq4019-reset.h b/include/dt-bindings/reset/qcom,ipq4019-reset.h
new file mode 100644
index 0000000000..ed047d7402
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,ipq4019-reset.h
@@ -0,0 +1,92 @@
+/* Copyright (c) 2015 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+#ifndef __QCOM_RESET_IPQ4019_H__
+#define __QCOM_RESET_IPQ4019_H__
+
+#define WIFI0_CPU_INIT_RESET				0
+#define WIFI0_RADIO_SRIF_RESET				1
+#define WIFI0_RADIO_WARM_RESET				2
+#define WIFI0_RADIO_COLD_RESET				3
+#define WIFI0_CORE_WARM_RESET				4
+#define WIFI0_CORE_COLD_RESET				5
+#define WIFI1_CPU_INIT_RESET				6
+#define WIFI1_RADIO_SRIF_RESET				7
+#define WIFI1_RADIO_WARM_RESET				8
+#define WIFI1_RADIO_COLD_RESET				9
+#define WIFI1_CORE_WARM_RESET				10
+#define WIFI1_CORE_COLD_RESET				11
+#define USB3_UNIPHY_PHY_ARES				12
+#define USB3_HSPHY_POR_ARES				13
+#define USB3_HSPHY_S_ARES				14
+#define USB2_HSPHY_POR_ARES				15
+#define USB2_HSPHY_S_ARES				16
+#define PCIE_PHY_AHB_ARES				17
+#define PCIE_AHB_ARES					18
+#define PCIE_PWR_ARES					19
+#define PCIE_PIPE_STICKY_ARES				20
+#define PCIE_AXI_M_STICKY_ARES				21
+#define PCIE_PHY_ARES					22
+#define PCIE_PARF_XPU_ARES				23
+#define PCIE_AXI_S_XPU_ARES				24
+#define PCIE_AXI_M_VMIDMT_ARES				25
+#define PCIE_PIPE_ARES					26
+#define PCIE_AXI_S_ARES					27
+#define PCIE_AXI_M_ARES					28
+#define ESS_RESET					29
+#define GCC_BLSP1_BCR					30
+#define GCC_BLSP1_QUP1_BCR				31
+#define GCC_BLSP1_UART1_BCR				32
+#define GCC_BLSP1_QUP2_BCR				33
+#define GCC_BLSP1_UART2_BCR				34
+#define GCC_BIMC_BCR					35
+#define GCC_TLMM_BCR					36
+#define GCC_IMEM_BCR					37
+#define GCC_ESS_BCR					38
+#define GCC_PRNG_BCR					39
+#define GCC_BOOT_ROM_BCR				40
+#define GCC_CRYPTO_BCR					41
+#define GCC_SDCC1_BCR					42
+#define GCC_SEC_CTRL_BCR				43
+#define GCC_AUDIO_BCR					44
+#define GCC_QPIC_BCR					45
+#define GCC_PCIE_BCR					46
+#define GCC_USB2_BCR					47
+#define GCC_USB2_PHY_BCR				48
+#define GCC_USB3_BCR					49
+#define GCC_USB3_PHY_BCR				50
+#define GCC_SYSTEM_NOC_BCR				51
+#define GCC_PCNOC_BCR					52
+#define GCC_DCD_BCR					53
+#define GCC_SNOC_BUS_TIMEOUT0_BCR			54
+#define GCC_SNOC_BUS_TIMEOUT1_BCR			55
+#define GCC_SNOC_BUS_TIMEOUT2_BCR			56
+#define GCC_SNOC_BUS_TIMEOUT3_BCR			57
+#define GCC_PCNOC_BUS_TIMEOUT0_BCR			58
+#define GCC_PCNOC_BUS_TIMEOUT1_BCR			59
+#define GCC_PCNOC_BUS_TIMEOUT2_BCR			60
+#define GCC_PCNOC_BUS_TIMEOUT3_BCR			61
+#define GCC_PCNOC_BUS_TIMEOUT4_BCR			62
+#define GCC_PCNOC_BUS_TIMEOUT5_BCR			63
+#define GCC_PCNOC_BUS_TIMEOUT6_BCR			64
+#define GCC_PCNOC_BUS_TIMEOUT7_BCR			65
+#define GCC_PCNOC_BUS_TIMEOUT8_BCR			66
+#define GCC_PCNOC_BUS_TIMEOUT9_BCR			67
+#define GCC_TCSR_BCR					68
+#define GCC_QDSS_BCR					69
+#define GCC_MPM_BCR					70
+#define GCC_SPDM_BCR					71
+
+#endif
-- 
2.26.2

[PATCH v2 5/9] IPQ40xx: Add reset controller support

[Robert Marko]

Since we have a driver for the reset controller, lets add the necessary node.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
---
 arch/arm/Kconfig               | 1 +
 arch/arm/dts/qcom-ipq4019.dtsi | 9 +++++++++
 2 files changed, 10 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ee378f03f4..68d6d1afd6 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -767,6 +767,7 @@ config ARCH_IPQ40XX
 	select DM
 	select DM_GPIO
 	select DM_SERIAL
+	select DM_RESET
 	select MSM_SMEM
 	select PINCTRL
 	select CLK
diff --git a/arch/arm/dts/qcom-ipq4019.dtsi b/arch/arm/dts/qcom-ipq4019.dtsi
index dd69d0a5b2..7b15df38d8 100644
--- a/arch/arm/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/dts/qcom-ipq4019.dtsi
@@ -11,6 +11,7 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/pinctrl/pinctrl-snapdragon.h>
 #include <dt-bindings/clock/qcom,ipq4019-gcc.h>
+#include <dt-bindings/reset/qcom,ipq4019-reset.h>
 
 / {
 	#address-cells = <1>;
@@ -58,6 +59,14 @@
 			u-boot,dm-pre-reloc;
 		};
 
+		reset: gcc-reset at 1800000 {
+			compatible = "qcom,gcc-reset-ipq4019";
+			reg = <0x1800000 0x60000>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			u-boot,dm-pre-reloc;
+		};
+
 		pinctrl: qcom,tlmm at 1000000 {
 			compatible = "qcom,tlmm-ipq4019";
 			reg = <0x1000000 0x300000>;
-- 
2.26.2

[PATCH v2 6/9] phy: add driver for Qualcomm IPQ40xx USB PHY

[Robert Marko]

Add a driver to setup the USB PHY-s on Qualcomm IPQ40xx series SoCs.
The driver sets up HS and SS phys.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
---
 MAINTAINERS                        |   1 +
 drivers/phy/Kconfig                |   6 ++
 drivers/phy/Makefile               |   1 +
 drivers/phy/phy-qcom-ipq4019-usb.c | 145 +++++++++++++++++++++++++++++
 4 files changed, 153 insertions(+)
 create mode 100644 drivers/phy/phy-qcom-ipq4019-usb.c

diff --git a/MAINTAINERS b/MAINTAINERS
index f4fc823e4e..d8d2c6278b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -240,6 +240,7 @@ F:	arch/arm/mach-ipq40xx/
 F:	include/dt-bindings/clock/qcom,ipq4019-gcc.h
 F:	include/dt-bindings/reset/qcom,ipq4019-reset.h
 F:	drivers/reset/reset-ipq4019.c
+F:	drivers/phy/phy-qcom-ipq4019-usb.c
 
 ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX ARMADA-7K/8K
 M:	Stefan Roese <sr@denx.de>
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 9c775107e9..8da00a259d 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -125,6 +125,12 @@ config STI_USB_PHY
 	  used by USB2 and USB3 Host controllers available on
 	  STiH407 SoC families.
 
+config PHY_QCOM_IPQ4019_USB
+	tristate "Qualcomm IPQ4019 USB PHY driver"
+	depends on PHY && ARCH_IPQ40XX
+	help
+	  Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s.
+
 config PHY_RCAR_GEN2
 	tristate "Renesas R-Car Gen2 USB PHY"
 	depends on PHY && RCAR_GEN2
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 74e8d931d3..009f353baf 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_PHY_SANDBOX) += sandbox-phy.o
 obj-$(CONFIG_$(SPL_)PIPE3_PHY) += ti-pipe3-phy.o
 obj-$(CONFIG_AM654_PHY) += phy-ti-am654.o
 obj-$(CONFIG_STI_USB_PHY) += sti_usb_phy.o
+obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o
 obj-$(CONFIG_PHY_RCAR_GEN2) += phy-rcar-gen2.o
 obj-$(CONFIG_PHY_RCAR_GEN3) += phy-rcar-gen3.o
 obj-$(CONFIG_PHY_STM32_USBPHYC) += phy-stm32-usbphyc.o
diff --git a/drivers/phy/phy-qcom-ipq4019-usb.c b/drivers/phy/phy-qcom-ipq4019-usb.c
new file mode 100644
index 0000000000..465f0d3a01
--- /dev/null
+++ b/drivers/phy/phy-qcom-ipq4019-usb.c
@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 Sartura Ltd.
+ *
+ * Author: Robert Marko <robert.marko@sartura.hr>
+ *
+ * Based on Linux driver
+ */
+
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <generic-phy.h>
+#include <log.h>
+#include <reset.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+
+struct ipq4019_usb_phy {
+	phys_addr_t			base;
+	struct reset_ctl	por_rst;
+	struct reset_ctl	srif_rst;
+};
+
+static int ipq4019_ss_phy_power_off(struct phy *_phy)
+{
+	struct ipq4019_usb_phy *phy = dev_get_priv(_phy->dev);
+
+	reset_assert(&phy->por_rst);
+	mdelay(10);
+
+	return 0;
+}
+
+static int ipq4019_ss_phy_power_on(struct phy *_phy)
+{
+	struct ipq4019_usb_phy *phy = dev_get_priv(_phy->dev);
+
+	ipq4019_ss_phy_power_off(_phy);
+
+	reset_deassert(&phy->por_rst);
+
+	return 0;
+}
+
+static struct phy_ops ipq4019_usb_ss_phy_ops = {
+	.power_on = ipq4019_ss_phy_power_on,
+	.power_off = ipq4019_ss_phy_power_off,
+};
+
+static int ipq4019_usb_ss_phy_probe(struct udevice *dev)
+{
+	struct ipq4019_usb_phy *phy = dev_get_priv(dev);
+	int ret;
+
+	phy->base = dev_read_addr(dev);
+	if (phy->base == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	ret = reset_get_by_name(dev, "por_rst", &phy->por_rst);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static const struct udevice_id ipq4019_usb_ss_phy_ids[] = {
+	{ .compatible = "qcom,usb-ss-ipq4019-phy" },
+	{ }
+};
+
+U_BOOT_DRIVER(ipq4019_usb_ss_phy) = {
+	.name		= "ipq4019-usb-ss-phy",
+	.id		= UCLASS_PHY,
+	.of_match	= ipq4019_usb_ss_phy_ids,
+	.ops		= &ipq4019_usb_ss_phy_ops,
+	.probe		= ipq4019_usb_ss_phy_probe,
+	.priv_auto_alloc_size = sizeof(struct ipq4019_usb_phy),
+};
+
+static int ipq4019_hs_phy_power_off(struct phy *_phy)
+{
+	struct ipq4019_usb_phy *phy = dev_get_priv(_phy->dev);
+
+	reset_assert(&phy->por_rst);
+	mdelay(10);
+
+	reset_assert(&phy->srif_rst);
+	mdelay(10);
+
+	return 0;
+}
+
+static int ipq4019_hs_phy_power_on(struct phy *_phy)
+{
+	struct ipq4019_usb_phy *phy = dev_get_priv(_phy->dev);
+
+	ipq4019_hs_phy_power_off(_phy);
+
+	reset_deassert(&phy->srif_rst);
+	mdelay(10);
+
+	reset_deassert(&phy->por_rst);
+
+	return 0;
+}
+
+static struct phy_ops ipq4019_usb_hs_phy_ops = {
+	.power_on = ipq4019_hs_phy_power_on,
+	.power_off = ipq4019_hs_phy_power_off,
+};
+
+static int ipq4019_usb_hs_phy_probe(struct udevice *dev)
+{
+	struct ipq4019_usb_phy *phy = dev_get_priv(dev);
+	int ret;
+
+	phy->base = dev_read_addr(dev);
+	if (phy->base == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	ret = reset_get_by_name(dev, "por_rst", &phy->por_rst);
+	if (ret)
+		return ret;
+
+	ret = reset_get_by_name(dev, "srif_rst", &phy->srif_rst);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static const struct udevice_id ipq4019_usb_hs_phy_ids[] = {
+	{ .compatible = "qcom,usb-hs-ipq4019-phy" },
+	{ }
+};
+
+U_BOOT_DRIVER(ipq4019_usb_hs_phy) = {
+	.name		= "ipq4019-usb-hs-phy",
+	.id		= UCLASS_PHY,
+	.of_match	= ipq4019_usb_hs_phy_ids,
+	.ops		= &ipq4019_usb_hs_phy_ops,
+	.probe		= ipq4019_usb_hs_phy_probe,
+	.priv_auto_alloc_size = sizeof(struct ipq4019_usb_phy),
+};
-- 
2.26.2

[PATCH v2 7/9] usb: dwc3: Make PHY functions depend on CONFIG_USB_DWC3

[Robert Marko]

PHY handling functions should depend also on CONFIG_USB_DWC3 aka DM DWC3 version.
Otherwise when using the non DM version with PHY subsystem enabled there will be a linking error due to missing dwc3_setup_phy and dwc3_shutdown_phy.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
---
 include/dwc3-uboot.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/dwc3-uboot.h b/include/dwc3-uboot.h
index e08530ec4e..5eb0822d74 100644
--- a/include/dwc3-uboot.h
+++ b/include/dwc3-uboot.h
@@ -47,7 +47,7 @@ void dwc3_uboot_exit(int index);
 void dwc3_uboot_handle_interrupt(int index);
 
 struct phy;
-#if CONFIG_IS_ENABLED(PHY) && CONFIG_IS_ENABLED(DM_USB)
+#if CONFIG_IS_ENABLED(PHY) && CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(CONFIG_USB_DWC3)
 int dwc3_setup_phy(struct udevice *dev, struct phy_bulk *phys);
 int dwc3_shutdown_phy(struct udevice *dev, struct phy_bulk *phys);
 #else
-- 
2.26.2

[PATCH v2 8/9] usb: xhci: Add Qualcomm DWC3 xHCI driver

[Robert Marko]

Add driver for Qualcomm DWC3 based dual role xHCI USB controller.
Currently tested on IPQ40xx, but should support other Qualcomm SoC families as well.

Only host mode is supported.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
---
 MAINTAINERS                                   |   2 +
 .../usb/qcom-dwc3-ipq.txt                     |  34 +++++
 drivers/usb/host/Kconfig                      |   6 +
 drivers/usb/host/Makefile                     |   1 +
 drivers/usb/host/xhci-ipq.c                   | 117 ++++++++++++++++++
 5 files changed, 160 insertions(+)
 create mode 100644 doc/device-tree-bindings/usb/qcom-dwc3-ipq.txt
 create mode 100644 drivers/usb/host/xhci-ipq.c

diff --git a/MAINTAINERS b/MAINTAINERS
index d8d2c6278b..99828f656a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -241,6 +241,8 @@ F:	include/dt-bindings/clock/qcom,ipq4019-gcc.h
 F:	include/dt-bindings/reset/qcom,ipq4019-reset.h
 F:	drivers/reset/reset-ipq4019.c
 F:	drivers/phy/phy-qcom-ipq4019-usb.c
+F:	doc/device-tree-bindings/usb/qcom-dwc3-ipq.txt
+F:	drivers/usb/host/xhci-ipq.c
 
 ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX ARMADA-7K/8K
 M:	Stefan Roese <sr@denx.de>
diff --git a/doc/device-tree-bindings/usb/qcom-dwc3-ipq.txt b/doc/device-tree-bindings/usb/qcom-dwc3-ipq.txt
new file mode 100644
index 0000000000..a910a06fa2
--- /dev/null
+++ b/doc/device-tree-bindings/usb/qcom-dwc3-ipq.txt
@@ -0,0 +1,34 @@
+Qualcomm SuperSpeed DWC3 USB SoC controller
+
+This controller is integrated in IPQ40xx SoC-s.
+It is a dual role USB3.0/USB2.0 controller.
+
+Required properties :
+ - compatible: must be "qcom,dwc3-ipq"
+ - reg: should contain address and length of the standard XHCI
+   register set for the device.
+ - #address-cells: must be 1
+ - #size-cells: must be 1
+ - phys: list of PHY specifiers
+ - phy-names: shall be "usb2-phy" and "usb3-phy"(In case of USB3.0 only)
+
+Example:
+	usb3: xhci at 8a00000 {
+		compatible = "qcom,dwc3-ipq";
+		reg = <0x8a00000 0xcd00>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
+		phy-names = "usb2-phy", "usb3-phy";
+		status = "disabled";
+	};
+
+	usb2: xhci at 6000000 {
+		compatible = "qcom,dwc3-ipq";
+		reg = <0x6000000 0xcd00>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		phys = <&usb2_hs_phy>;
+		phy-names = "usb2-phy";
+		status = "disabled";
+	};
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 1c374a7bd8..7e0b1ab4ce 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -93,6 +93,12 @@ config USB_XHCI_BRCM
 	  USB controller based on the Broadcom USB3 IP Core.
 	  Supports USB2/3 functionality.
 
+config USB_XHCI_IPQ
+	bool "Support for Qualcomm IPQ on-chip DWC3 xHCI USB controller"
+	depends on DM_USB && PHY && USB_XHCI_DWC3 && ARCH_IPQ40XX 
+	help
+	  Enables support for the on-chip xHCI DWC3 controller on Qualcomm IPQ SoCs.
+
 endif # USB_XHCI_HCD
 
 config USB_EHCI_HCD
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 29d4f87e38..0fa9c8f32a 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -55,6 +55,7 @@ obj-$(CONFIG_USB_XHCI_MVEBU) += xhci-mvebu.o
 obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
 obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
 obj-$(CONFIG_USB_XHCI_RCAR) += xhci-rcar.o
+obj-$(CONFIG_USB_XHCI_IPQ) += xhci-ipq.o
 obj-$(CONFIG_USB_XHCI_STI) += dwc3-sti-glue.o
 
 # designware
diff --git a/drivers/usb/host/xhci-ipq.c b/drivers/usb/host/xhci-ipq.c
new file mode 100644
index 0000000000..840f074819
--- /dev/null
+++ b/drivers/usb/host/xhci-ipq.c
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2020 Sartura Ltd.
+ *
+ * Qualcomm DWC3 controller driver
+ *
+ * Author: Robert Marko <robert.marko@sartura.hr>
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <generic-phy.h>
+#include <linux/compat.h>
+#include <linux/errno.h>
+#include <linux/usb/dwc3.h>
+#include <usb.h>
+#include <usb/xhci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct ipq_xhci_priv {
+	phys_addr_t					hcd_base;
+	struct xhci_ctrl 			ctrl;
+	struct xhci_hccr 			*hcd;
+	struct dwc3 				*dwc3_reg;
+	struct phy_bulk 			phys;
+};
+
+static int ipq_xhci_core_init(struct ipq_xhci_priv *ipq)
+{
+	int ret;
+
+	ret = dwc3_core_init(ipq->dwc3_reg);
+	if (ret) {
+		return ret;
+	}
+
+	/* We are hard-coding DWC3 core to Host Mode */
+	dwc3_set_mode(ipq->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
+
+	return ret;
+}
+
+static int ipq_xhci_core_exit(struct udevice *dev)
+{
+	struct ipq_xhci_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = generic_phy_power_off_bulk(&priv->phys);
+	ret |= generic_phy_exit_bulk(&priv->phys);
+	return ret;
+}
+
+static int ipq_xhci_usb_remove(struct udevice *dev)
+{
+	int ret;
+	ret = xhci_deregister(dev);
+
+	if (ret != 0) {
+		dev_err(dev, "XHCI deregistration failed\n");
+		return ret;
+	}
+
+	ipq_xhci_core_exit(dev);
+
+	return ret;
+}
+
+static int ipq_xhci_usb_probe(struct udevice *dev)
+{
+	struct ipq_xhci_priv *priv = dev_get_priv(dev);
+	struct xhci_hcor *hcor;
+	int ret;
+
+	priv->hcd_base = dev_read_addr(dev);
+	if (priv->hcd_base == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	ret = generic_phy_get_bulk(dev, &priv->phys);
+	if (ret)
+		return ret;
+
+	priv->hcd = (struct xhci_hccr *)priv->hcd_base;
+	priv->dwc3_reg = (struct dwc3 *)((char *)(priv->hcd) + DWC3_REG_OFFSET);
+	hcor = (struct xhci_hcor *)((uint32_t)priv->hcd +
+			HC_LENGTH(xhci_readl(&priv->hcd->cr_capbase)));
+
+	ret = generic_phy_power_on_bulk(&priv->phys);
+	if (ret)
+		generic_phy_exit_bulk(&priv->phys);
+
+	ret = ipq_xhci_core_init(priv);
+
+	if (ret) {
+		dev_err(dev, "Error initializing the XHCI controller\n");
+		return ret;
+	}
+
+	return xhci_register(dev, priv->hcd, hcor);
+}
+
+static const struct udevice_id ipq_xhci_match_ids[] = {
+	{ .compatible = "qcom,dwc3-ipq" },
+	{}
+};
+
+U_BOOT_DRIVER(usb_xhci) = {
+	.name	= "ipq_hci",
+	.id	= UCLASS_USB,
+	.of_match = ipq_xhci_match_ids,
+	.probe = ipq_xhci_usb_probe,
+	.remove = ipq_xhci_usb_remove,
+	.ops	= &xhci_usb_ops,
+	.priv_auto_alloc_size = sizeof(struct ipq_xhci_priv),
+	.flags	= DM_FLAG_ALLOC_PRIV_DMA,
+};
-- 
2.26.2

[PATCH v2 9/9] IPQ40xx: Add USB nodes

[Robert Marko]

There are drivers to support built in USB controller and PHY-s now, so lets add the USB nodes to DTSI.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
---
 arch/arm/dts/qcom-ipq4019.dtsi | 50 ++++++++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)

diff --git a/arch/arm/dts/qcom-ipq4019.dtsi b/arch/arm/dts/qcom-ipq4019.dtsi
index 7b15df38d8..494b2205a5 100644
--- a/arch/arm/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/dts/qcom-ipq4019.dtsi
@@ -90,5 +90,55 @@
 			gpio-bank-name="soc";
 			#gpio-cells = <2>;
 		};
+
+		usb3_ss_phy: ssphy at 9a000 {
+			compatible = "qcom,usb-ss-ipq4019-phy";
+			#phy-cells = <0>;
+			reg = <0x9a000 0x800>;
+			reg-names = "phy_base";
+			resets = <&reset USB3_UNIPHY_PHY_ARES>;
+			reset-names = "por_rst";
+			status = "disabled";
+		};
+
+		usb3_hs_phy: hsphy at a6000 {
+			compatible = "qcom,usb-hs-ipq4019-phy";
+			#phy-cells = <0>;
+			reg = <0xa6000 0x40>;
+			reg-names = "phy_base";
+			resets = <&reset USB3_HSPHY_POR_ARES>, <&reset USB3_HSPHY_S_ARES>;
+			reset-names = "por_rst", "srif_rst";
+			status = "disabled";
+		};
+
+		usb3: xhci at 8a00000 {
+			compatible = "qcom,dwc3-ipq";
+			reg = <0x8a00000 0xcd00>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
+			phy-names = "usb2-phy", "usb3-phy";
+			status = "disabled";
+		};
+
+		usb2_hs_phy: hsphy at a8000 {
+			compatible = "qcom,usb-hs-ipq4019-phy";
+			#phy-cells = <0>;
+			reg = <0xa8000 0x40>;
+			reg-names = "phy_base";
+			resets = <&reset USB2_HSPHY_POR_ARES>, <&reset USB2_HSPHY_S_ARES>;
+			reset-names = "por_rst", "srif_rst";
+			status = "disabled";
+		};
+
+		usb2: xhci at 6000000 {
+			compatible = "qcom,dwc3-ipq";
+			reg = <0x6000000 0xcd00>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			phys = <&usb2_hs_phy>;
+			phy-names = "usb2-phy";
+			status = "disabled";
+		};
 	};
 };
-- 
2.26.2

[PATCH v2 7/9] usb: dwc3: Make PHY functions depend on CONFIG_USB_DWC3

[Tom Rini]

On Tue, Sep 01, 2020 at 07:23:00PM +0200, Robert Marko wrote:

> PHY handling functions should depend also on CONFIG_USB_DWC3 aka DM DWC3 version.
> Otherwise when using the non DM version with PHY subsystem enabled there will be a linking error due to missing dwc3_setup_phy and dwc3_shutdown_phy.
> 
> Signed-off-by: Robert Marko <robert.marko@sartura.hr>
> Cc: Luka Perkov <luka.perkov@sartura.hr>
> ---
>  include/dwc3-uboot.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/include/dwc3-uboot.h b/include/dwc3-uboot.h
> index e08530ec4e..5eb0822d74 100644
> --- a/include/dwc3-uboot.h
> +++ b/include/dwc3-uboot.h
> @@ -47,7 +47,7 @@ void dwc3_uboot_exit(int index);
>  void dwc3_uboot_handle_interrupt(int index);
>  
>  struct phy;
> -#if CONFIG_IS_ENABLED(PHY) && CONFIG_IS_ENABLED(DM_USB)
> +#if CONFIG_IS_ENABLED(PHY) && CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(CONFIG_USB_DWC3)
>  int dwc3_setup_phy(struct udevice *dev, struct phy_bulk *phys);
>  int dwc3_shutdown_phy(struct udevice *dev, struct phy_bulk *phys);
>  #else

This should be CONFIG_IS_ENABLED(USB_DWC3).

-- 
Tom
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[PATCH v2 8/9] usb: xhci: Add Qualcomm DWC3 xHCI driver

[Tom Rini]

On Tue, Sep 01, 2020 at 07:23:01PM +0200, Robert Marko wrote:

> Add driver for Qualcomm DWC3 based dual role xHCI USB controller.
> Currently tested on IPQ40xx, but should support other Qualcomm SoC families as well.
> 
> Only host mode is supported.
> 
> Signed-off-by: Robert Marko <robert.marko@sartura.hr>
> Cc: Luka Perkov <luka.perkov@sartura.hr>
> ---
>  MAINTAINERS                                   |   2 +
>  .../usb/qcom-dwc3-ipq.txt                     |  34 +++++
>  drivers/usb/host/Kconfig                      |   6 +
>  drivers/usb/host/Makefile                     |   1 +
>  drivers/usb/host/xhci-ipq.c                   | 117 ++++++++++++++++++
>  5 files changed, 160 insertions(+)
>  create mode 100644 doc/device-tree-bindings/usb/qcom-dwc3-ipq.txt
>  create mode 100644 drivers/usb/host/xhci-ipq.c
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index d8d2c6278b..99828f656a 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -241,6 +241,8 @@ F:	include/dt-bindings/clock/qcom,ipq4019-gcc.h
>  F:	include/dt-bindings/reset/qcom,ipq4019-reset.h
>  F:	drivers/reset/reset-ipq4019.c
>  F:	drivers/phy/phy-qcom-ipq4019-usb.c
> +F:	doc/device-tree-bindings/usb/qcom-dwc3-ipq.txt
> +F:	drivers/usb/host/xhci-ipq.c
>  
>  ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX ARMADA-7K/8K
>  M:	Stefan Roese <sr@denx.de>
> diff --git a/doc/device-tree-bindings/usb/qcom-dwc3-ipq.txt b/doc/device-tree-bindings/usb/qcom-dwc3-ipq.txt
> new file mode 100644
> index 0000000000..a910a06fa2
> --- /dev/null
> +++ b/doc/device-tree-bindings/usb/qcom-dwc3-ipq.txt
> @@ -0,0 +1,34 @@
> +Qualcomm SuperSpeed DWC3 USB SoC controller
> +
> +This controller is integrated in IPQ40xx SoC-s.
> +It is a dual role USB3.0/USB2.0 controller.
> +
> +Required properties :
> + - compatible: must be "qcom,dwc3-ipq"
> + - reg: should contain address and length of the standard XHCI
> +   register set for the device.
> + - #address-cells: must be 1
> + - #size-cells: must be 1
> + - phys: list of PHY specifiers
> + - phy-names: shall be "usb2-phy" and "usb3-phy"(In case of USB3.0 only)
> +
> +Example:
> +	usb3: xhci at 8a00000 {
> +		compatible = "qcom,dwc3-ipq";
> +		reg = <0x8a00000 0xcd00>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
> +		phy-names = "usb2-phy", "usb3-phy";
> +		status = "disabled";
> +	};
> +
> +	usb2: xhci at 6000000 {
> +		compatible = "qcom,dwc3-ipq";
> +		reg = <0x6000000 0xcd00>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		phys = <&usb2_hs_phy>;
> +		phy-names = "usb2-phy";
> +		status = "disabled";
> +	};
> diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
> index 1c374a7bd8..7e0b1ab4ce 100644
> --- a/drivers/usb/host/Kconfig
> +++ b/drivers/usb/host/Kconfig
> @@ -93,6 +93,12 @@ config USB_XHCI_BRCM
>  	  USB controller based on the Broadcom USB3 IP Core.
>  	  Supports USB2/3 functionality.
>  
> +config USB_XHCI_IPQ
> +	bool "Support for Qualcomm IPQ on-chip DWC3 xHCI USB controller"
> +	depends on DM_USB && PHY && USB_XHCI_DWC3 && ARCH_IPQ40XX 
> +	help
> +	  Enables support for the on-chip xHCI DWC3 controller on Qualcomm IPQ SoCs.
> +
>  endif # USB_XHCI_HCD
>  
>  config USB_EHCI_HCD
> diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
> index 29d4f87e38..0fa9c8f32a 100644
> --- a/drivers/usb/host/Makefile
> +++ b/drivers/usb/host/Makefile
> @@ -55,6 +55,7 @@ obj-$(CONFIG_USB_XHCI_MVEBU) += xhci-mvebu.o
>  obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
>  obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
>  obj-$(CONFIG_USB_XHCI_RCAR) += xhci-rcar.o
> +obj-$(CONFIG_USB_XHCI_IPQ) += xhci-ipq.o
>  obj-$(CONFIG_USB_XHCI_STI) += dwc3-sti-glue.o
>  
>  # designware
> diff --git a/drivers/usb/host/xhci-ipq.c b/drivers/usb/host/xhci-ipq.c
> new file mode 100644
> index 0000000000..840f074819
> --- /dev/null
> +++ b/drivers/usb/host/xhci-ipq.c
> @@ -0,0 +1,117 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2020 Sartura Ltd.
> + *
> + * Qualcomm DWC3 controller driver
> + *
> + * Author: Robert Marko <robert.marko@sartura.hr>
> + *
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <generic-phy.h>
> +#include <linux/compat.h>
> +#include <linux/errno.h>
> +#include <linux/usb/dwc3.h>
> +#include <usb.h>
> +#include <usb/xhci.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +struct ipq_xhci_priv {
> +	phys_addr_t					hcd_base;
> +	struct xhci_ctrl 			ctrl;
> +	struct xhci_hccr 			*hcd;
> +	struct dwc3 				*dwc3_reg;
> +	struct phy_bulk 			phys;
> +};
> +
> +static int ipq_xhci_core_init(struct ipq_xhci_priv *ipq)
> +{
> +	int ret;
> +
> +	ret = dwc3_core_init(ipq->dwc3_reg);
> +	if (ret) {
> +		return ret;
> +	}
> +
> +	/* We are hard-coding DWC3 core to Host Mode */
> +	dwc3_set_mode(ipq->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
> +
> +	return ret;
> +}
> +
> +static int ipq_xhci_core_exit(struct udevice *dev)
> +{
> +	struct ipq_xhci_priv *priv = dev_get_priv(dev);
> +	int ret;
> +
> +	ret = generic_phy_power_off_bulk(&priv->phys);
> +	ret |= generic_phy_exit_bulk(&priv->phys);
> +	return ret;
> +}
> +
> +static int ipq_xhci_usb_remove(struct udevice *dev)
> +{
> +	int ret;
> +	ret = xhci_deregister(dev);
> +
> +	if (ret != 0) {
> +		dev_err(dev, "XHCI deregistration failed\n");
> +		return ret;
> +	}
> +
> +	ipq_xhci_core_exit(dev);
> +
> +	return ret;
> +}
> +
> +static int ipq_xhci_usb_probe(struct udevice *dev)
> +{
> +	struct ipq_xhci_priv *priv = dev_get_priv(dev);
> +	struct xhci_hcor *hcor;
> +	int ret;
> +
> +	priv->hcd_base = dev_read_addr(dev);
> +	if (priv->hcd_base == FDT_ADDR_T_NONE)
> +		return -EINVAL;
> +
> +	ret = generic_phy_get_bulk(dev, &priv->phys);
> +	if (ret)
> +		return ret;
> +
> +	priv->hcd = (struct xhci_hccr *)priv->hcd_base;
> +	priv->dwc3_reg = (struct dwc3 *)((char *)(priv->hcd) + DWC3_REG_OFFSET);
> +	hcor = (struct xhci_hcor *)((uint32_t)priv->hcd +
> +			HC_LENGTH(xhci_readl(&priv->hcd->cr_capbase)));
> +
> +	ret = generic_phy_power_on_bulk(&priv->phys);
> +	if (ret)
> +		generic_phy_exit_bulk(&priv->phys);
> +
> +	ret = ipq_xhci_core_init(priv);
> +
> +	if (ret) {
> +		dev_err(dev, "Error initializing the XHCI controller\n");
> +		return ret;
> +	}
> +
> +	return xhci_register(dev, priv->hcd, hcor);
> +}
> +
> +static const struct udevice_id ipq_xhci_match_ids[] = {
> +	{ .compatible = "qcom,dwc3-ipq" },
> +	{}
> +};
> +
> +U_BOOT_DRIVER(usb_xhci) = {
> +	.name	= "ipq_hci",
> +	.id	= UCLASS_USB,
> +	.of_match = ipq_xhci_match_ids,
> +	.probe = ipq_xhci_usb_probe,
> +	.remove = ipq_xhci_usb_remove,
> +	.ops	= &xhci_usb_ops,
> +	.priv_auto_alloc_size = sizeof(struct ipq_xhci_priv),
> +	.flags	= DM_FLAG_ALLOC_PRIV_DMA,
> +};

Adding USB maintainer.

-- 
Tom
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[PATCH v2 8/9] usb: xhci: Add Qualcomm DWC3 xHCI driver

[Marek Vasut]

On 9/10/20 3:30 PM, Tom Rini wrote:
> On Tue, Sep 01, 2020 at 07:23:01PM +0200, Robert Marko wrote:
> 
>> Add driver for Qualcomm DWC3 based dual role xHCI USB controller.
>> Currently tested on IPQ40xx, but should support other Qualcomm SoC families as well.
>>
>> Only host mode is supported.
>>
>> Signed-off-by: Robert Marko <robert.marko@sartura.hr>
>> Cc: Luka Perkov <luka.perkov@sartura.hr>
>> ---
>>  MAINTAINERS                                   |   2 +
>>  .../usb/qcom-dwc3-ipq.txt                     |  34 +++++
>>  drivers/usb/host/Kconfig                      |   6 +
>>  drivers/usb/host/Makefile                     |   1 +
>>  drivers/usb/host/xhci-ipq.c                   | 117 ++++++++++++++++++
>>  5 files changed, 160 insertions(+)
>>  create mode 100644 doc/device-tree-bindings/usb/qcom-dwc3-ipq.txt
>>  create mode 100644 drivers/usb/host/xhci-ipq.c
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index d8d2c6278b..99828f656a 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -241,6 +241,8 @@ F:	include/dt-bindings/clock/qcom,ipq4019-gcc.h
>>  F:	include/dt-bindings/reset/qcom,ipq4019-reset.h
>>  F:	drivers/reset/reset-ipq4019.c
>>  F:	drivers/phy/phy-qcom-ipq4019-usb.c
>> +F:	doc/device-tree-bindings/usb/qcom-dwc3-ipq.txt
>> +F:	drivers/usb/host/xhci-ipq.c
>>  
>>  ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX ARMADA-7K/8K
>>  M:	Stefan Roese <sr@denx.de>
>> diff --git a/doc/device-tree-bindings/usb/qcom-dwc3-ipq.txt b/doc/device-tree-bindings/usb/qcom-dwc3-ipq.txt
>> new file mode 100644
>> index 0000000000..a910a06fa2
>> --- /dev/null
>> +++ b/doc/device-tree-bindings/usb/qcom-dwc3-ipq.txt
>> @@ -0,0 +1,34 @@
>> +Qualcomm SuperSpeed DWC3 USB SoC controller
>> +
>> +This controller is integrated in IPQ40xx SoC-s.
>> +It is a dual role USB3.0/USB2.0 controller.
>> +
>> +Required properties :
>> + - compatible: must be "qcom,dwc3-ipq"
>> + - reg: should contain address and length of the standard XHCI
>> +   register set for the device.
>> + - #address-cells: must be 1
>> + - #size-cells: must be 1
>> + - phys: list of PHY specifiers
>> + - phy-names: shall be "usb2-phy" and "usb3-phy"(In case of USB3.0 only)
>> +
>> +Example:
>> +	usb3: xhci at 8a00000 {
>> +		compatible = "qcom,dwc3-ipq";
>> +		reg = <0x8a00000 0xcd00>;
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +		phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
>> +		phy-names = "usb2-phy", "usb3-phy";
>> +		status = "disabled";
>> +	};
>> +
>> +	usb2: xhci at 6000000 {
>> +		compatible = "qcom,dwc3-ipq";
>> +		reg = <0x6000000 0xcd00>;
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +		phys = <&usb2_hs_phy>;
>> +		phy-names = "usb2-phy";
>> +		status = "disabled";
>> +	};
>> diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
>> index 1c374a7bd8..7e0b1ab4ce 100644
>> --- a/drivers/usb/host/Kconfig
>> +++ b/drivers/usb/host/Kconfig
>> @@ -93,6 +93,12 @@ config USB_XHCI_BRCM
>>  	  USB controller based on the Broadcom USB3 IP Core.
>>  	  Supports USB2/3 functionality.
>>  
>> +config USB_XHCI_IPQ
>> +	bool "Support for Qualcomm IPQ on-chip DWC3 xHCI USB controller"
>> +	depends on DM_USB && PHY && USB_XHCI_DWC3 && ARCH_IPQ40XX 
>> +	help
>> +	  Enables support for the on-chip xHCI DWC3 controller on Qualcomm IPQ SoCs.
>> +
>>  endif # USB_XHCI_HCD
>>  
>>  config USB_EHCI_HCD
>> diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
>> index 29d4f87e38..0fa9c8f32a 100644
>> --- a/drivers/usb/host/Makefile
>> +++ b/drivers/usb/host/Makefile
>> @@ -55,6 +55,7 @@ obj-$(CONFIG_USB_XHCI_MVEBU) += xhci-mvebu.o
>>  obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
>>  obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
>>  obj-$(CONFIG_USB_XHCI_RCAR) += xhci-rcar.o
>> +obj-$(CONFIG_USB_XHCI_IPQ) += xhci-ipq.o
>>  obj-$(CONFIG_USB_XHCI_STI) += dwc3-sti-glue.o
>>  
>>  # designware
>> diff --git a/drivers/usb/host/xhci-ipq.c b/drivers/usb/host/xhci-ipq.c
>> new file mode 100644
>> index 0000000000..840f074819
>> --- /dev/null
>> +++ b/drivers/usb/host/xhci-ipq.c
>> @@ -0,0 +1,117 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Copyright (c) 2020 Sartura Ltd.
>> + *
>> + * Qualcomm DWC3 controller driver
>> + *
>> + * Author: Robert Marko <robert.marko@sartura.hr>
>> + *
>> + */
>> +
>> +#include <common.h>
>> +#include <dm.h>
>> +#include <generic-phy.h>
>> +#include <linux/compat.h>
>> +#include <linux/errno.h>
>> +#include <linux/usb/dwc3.h>
>> +#include <usb.h>
>> +#include <usb/xhci.h>
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +struct ipq_xhci_priv {
>> +	phys_addr_t					hcd_base;
>> +	struct xhci_ctrl 			ctrl;
>> +	struct xhci_hccr 			*hcd;
>> +	struct dwc3 				*dwc3_reg;
>> +	struct phy_bulk 			phys;
>> +};
>> +
>> +static int ipq_xhci_core_init(struct ipq_xhci_priv *ipq)
>> +{
>> +	int ret;
>> +
>> +	ret = dwc3_core_init(ipq->dwc3_reg);
>> +	if (ret) {
>> +		return ret;
>> +	}
>> +
>> +	/* We are hard-coding DWC3 core to Host Mode */
>> +	dwc3_set_mode(ipq->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
>> +
>> +	return ret;
>> +}
>> +
>> +static int ipq_xhci_core_exit(struct udevice *dev)
>> +{
>> +	struct ipq_xhci_priv *priv = dev_get_priv(dev);
>> +	int ret;
>> +
>> +	ret = generic_phy_power_off_bulk(&priv->phys);
>> +	ret |= generic_phy_exit_bulk(&priv->phys);
>> +	return ret;
>> +}
>> +
>> +static int ipq_xhci_usb_remove(struct udevice *dev)
>> +{
>> +	int ret;
>> +	ret = xhci_deregister(dev);
>> +
>> +	if (ret != 0) {
>> +		dev_err(dev, "XHCI deregistration failed\n");
>> +		return ret;
>> +	}
>> +
>> +	ipq_xhci_core_exit(dev);
>> +
>> +	return ret;
>> +}
>> +
>> +static int ipq_xhci_usb_probe(struct udevice *dev)
>> +{
>> +	struct ipq_xhci_priv *priv = dev_get_priv(dev);
>> +	struct xhci_hcor *hcor;
>> +	int ret;
>> +
>> +	priv->hcd_base = dev_read_addr(dev);
>> +	if (priv->hcd_base == FDT_ADDR_T_NONE)
>> +		return -EINVAL;
>> +
>> +	ret = generic_phy_get_bulk(dev, &priv->phys);
>> +	if (ret)
>> +		return ret;
>> +
>> +	priv->hcd = (struct xhci_hccr *)priv->hcd_base;
>> +	priv->dwc3_reg = (struct dwc3 *)((char *)(priv->hcd) + DWC3_REG_OFFSET);
>> +	hcor = (struct xhci_hcor *)((uint32_t)priv->hcd +
>> +			HC_LENGTH(xhci_readl(&priv->hcd->cr_capbase)));
>> +
>> +	ret = generic_phy_power_on_bulk(&priv->phys);
>> +	if (ret)
>> +		generic_phy_exit_bulk(&priv->phys);
>> +
>> +	ret = ipq_xhci_core_init(priv);
>> +
>> +	if (ret) {
>> +		dev_err(dev, "Error initializing the XHCI controller\n");
>> +		return ret;
>> +	}
>> +
>> +	return xhci_register(dev, priv->hcd, hcor);
>> +}
>> +
>> +static const struct udevice_id ipq_xhci_match_ids[] = {
>> +	{ .compatible = "qcom,dwc3-ipq" },
>> +	{}
>> +};
>> +
>> +U_BOOT_DRIVER(usb_xhci) = {
>> +	.name	= "ipq_hci",
>> +	.id	= UCLASS_USB,
>> +	.of_match = ipq_xhci_match_ids,
>> +	.probe = ipq_xhci_usb_probe,
>> +	.remove = ipq_xhci_usb_remove,
>> +	.ops	= &xhci_usb_ops,
>> +	.priv_auto_alloc_size = sizeof(struct ipq_xhci_priv),
>> +	.flags	= DM_FLAG_ALLOC_PRIV_DMA,
>> +};
> 
> Adding USB maintainer.

And adding Bin, since it's XHCI.

[PATCH v2 8/9] usb: xhci: Add Qualcomm DWC3 xHCI driver

[Robert Marko]

On Thu, Sep 10, 2020 at 3:37 PM Marek Vasut <marex@denx.de> wrote:
>
> On 9/10/20 3:30 PM, Tom Rini wrote:
> > On Tue, Sep 01, 2020 at 07:23:01PM +0200, Robert Marko wrote:
> >
> >> Add driver for Qualcomm DWC3 based dual role xHCI USB controller.
> >> Currently tested on IPQ40xx, but should support other Qualcomm SoC families as well.
> >>
> >> Only host mode is supported.
> >>
> >> Signed-off-by: Robert Marko <robert.marko@sartura.hr>
> >> Cc: Luka Perkov <luka.perkov@sartura.hr>
> >> ---
> >>  MAINTAINERS                                   |   2 +
> >>  .../usb/qcom-dwc3-ipq.txt                     |  34 +++++
> >>  drivers/usb/host/Kconfig                      |   6 +
> >>  drivers/usb/host/Makefile                     |   1 +
> >>  drivers/usb/host/xhci-ipq.c                   | 117 ++++++++++++++++++
> >>  5 files changed, 160 insertions(+)
> >>  create mode 100644 doc/device-tree-bindings/usb/qcom-dwc3-ipq.txt
> >>  create mode 100644 drivers/usb/host/xhci-ipq.c
> >>
> >> diff --git a/MAINTAINERS b/MAINTAINERS
> >> index d8d2c6278b..99828f656a 100644
> >> --- a/MAINTAINERS
> >> +++ b/MAINTAINERS
> >> @@ -241,6 +241,8 @@ F:       include/dt-bindings/clock/qcom,ipq4019-gcc.h
> >>  F:  include/dt-bindings/reset/qcom,ipq4019-reset.h
> >>  F:  drivers/reset/reset-ipq4019.c
> >>  F:  drivers/phy/phy-qcom-ipq4019-usb.c
> >> +F:  doc/device-tree-bindings/usb/qcom-dwc3-ipq.txt
> >> +F:  drivers/usb/host/xhci-ipq.c
> >>
> >>  ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX ARMADA-7K/8K
> >>  M:  Stefan Roese <sr@denx.de>
> >> diff --git a/doc/device-tree-bindings/usb/qcom-dwc3-ipq.txt b/doc/device-tree-bindings/usb/qcom-dwc3-ipq.txt
> >> new file mode 100644
> >> index 0000000000..a910a06fa2
> >> --- /dev/null
> >> +++ b/doc/device-tree-bindings/usb/qcom-dwc3-ipq.txt
> >> @@ -0,0 +1,34 @@
> >> +Qualcomm SuperSpeed DWC3 USB SoC controller
> >> +
> >> +This controller is integrated in IPQ40xx SoC-s.
> >> +It is a dual role USB3.0/USB2.0 controller.
> >> +
> >> +Required properties :
> >> + - compatible: must be "qcom,dwc3-ipq"
> >> + - reg: should contain address and length of the standard XHCI
> >> +   register set for the device.
> >> + - #address-cells: must be 1
> >> + - #size-cells: must be 1
> >> + - phys: list of PHY specifiers
> >> + - phy-names: shall be "usb2-phy" and "usb3-phy"(In case of USB3.0 only)
> >> +
> >> +Example:
> >> +    usb3: xhci at 8a00000 {
> >> +            compatible = "qcom,dwc3-ipq";
> >> +            reg = <0x8a00000 0xcd00>;
> >> +            #address-cells = <1>;
> >> +            #size-cells = <1>;
> >> +            phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
> >> +            phy-names = "usb2-phy", "usb3-phy";
> >> +            status = "disabled";
> >> +    };
> >> +
> >> +    usb2: xhci at 6000000 {
> >> +            compatible = "qcom,dwc3-ipq";
> >> +            reg = <0x6000000 0xcd00>;
> >> +            #address-cells = <1>;
> >> +            #size-cells = <1>;
> >> +            phys = <&usb2_hs_phy>;
> >> +            phy-names = "usb2-phy";
> >> +            status = "disabled";
> >> +    };
> >> diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
> >> index 1c374a7bd8..7e0b1ab4ce 100644
> >> --- a/drivers/usb/host/Kconfig
> >> +++ b/drivers/usb/host/Kconfig
> >> @@ -93,6 +93,12 @@ config USB_XHCI_BRCM
> >>        USB controller based on the Broadcom USB3 IP Core.
> >>        Supports USB2/3 functionality.
> >>
> >> +config USB_XHCI_IPQ
> >> +    bool "Support for Qualcomm IPQ on-chip DWC3 xHCI USB controller"
> >> +    depends on DM_USB && PHY && USB_XHCI_DWC3 && ARCH_IPQ40XX
> >> +    help
> >> +      Enables support for the on-chip xHCI DWC3 controller on Qualcomm IPQ SoCs.
> >> +
> >>  endif # USB_XHCI_HCD
> >>
> >>  config USB_EHCI_HCD
> >> diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
> >> index 29d4f87e38..0fa9c8f32a 100644
> >> --- a/drivers/usb/host/Makefile
> >> +++ b/drivers/usb/host/Makefile
> >> @@ -55,6 +55,7 @@ obj-$(CONFIG_USB_XHCI_MVEBU) += xhci-mvebu.o
> >>  obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
> >>  obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
> >>  obj-$(CONFIG_USB_XHCI_RCAR) += xhci-rcar.o
> >> +obj-$(CONFIG_USB_XHCI_IPQ) += xhci-ipq.o
> >>  obj-$(CONFIG_USB_XHCI_STI) += dwc3-sti-glue.o
> >>
> >>  # designware
> >> diff --git a/drivers/usb/host/xhci-ipq.c b/drivers/usb/host/xhci-ipq.c
> >> new file mode 100644
> >> index 0000000000..840f074819
> >> --- /dev/null
> >> +++ b/drivers/usb/host/xhci-ipq.c
> >> @@ -0,0 +1,117 @@
> >> +// SPDX-License-Identifier: GPL-2.0+
> >> +/*
> >> + * Copyright (c) 2020 Sartura Ltd.
> >> + *
> >> + * Qualcomm DWC3 controller driver
> >> + *
> >> + * Author: Robert Marko <robert.marko@sartura.hr>
> >> + *
> >> + */
> >> +
> >> +#include <common.h>
> >> +#include <dm.h>
> >> +#include <generic-phy.h>
> >> +#include <linux/compat.h>
> >> +#include <linux/errno.h>
> >> +#include <linux/usb/dwc3.h>
> >> +#include <usb.h>
> >> +#include <usb/xhci.h>
> >> +
> >> +DECLARE_GLOBAL_DATA_PTR;
> >> +
> >> +struct ipq_xhci_priv {
> >> +    phys_addr_t                                     hcd_base;
> >> +    struct xhci_ctrl                        ctrl;
> >> +    struct xhci_hccr                        *hcd;
> >> +    struct dwc3                             *dwc3_reg;
> >> +    struct phy_bulk                         phys;
> >> +};
> >> +
> >> +static int ipq_xhci_core_init(struct ipq_xhci_priv *ipq)
> >> +{
> >> +    int ret;
> >> +
> >> +    ret = dwc3_core_init(ipq->dwc3_reg);
> >> +    if (ret) {
> >> +            return ret;
> >> +    }
> >> +
> >> +    /* We are hard-coding DWC3 core to Host Mode */
> >> +    dwc3_set_mode(ipq->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
> >> +
> >> +    return ret;
> >> +}
> >> +
> >> +static int ipq_xhci_core_exit(struct udevice *dev)
> >> +{
> >> +    struct ipq_xhci_priv *priv = dev_get_priv(dev);
> >> +    int ret;
> >> +
> >> +    ret = generic_phy_power_off_bulk(&priv->phys);
> >> +    ret |= generic_phy_exit_bulk(&priv->phys);
> >> +    return ret;
> >> +}
> >> +
> >> +static int ipq_xhci_usb_remove(struct udevice *dev)
> >> +{
> >> +    int ret;
> >> +    ret = xhci_deregister(dev);
> >> +
> >> +    if (ret != 0) {
> >> +            dev_err(dev, "XHCI deregistration failed\n");
> >> +            return ret;
> >> +    }
> >> +
> >> +    ipq_xhci_core_exit(dev);
> >> +
> >> +    return ret;
> >> +}
> >> +
> >> +static int ipq_xhci_usb_probe(struct udevice *dev)
> >> +{
> >> +    struct ipq_xhci_priv *priv = dev_get_priv(dev);
> >> +    struct xhci_hcor *hcor;
> >> +    int ret;
> >> +
> >> +    priv->hcd_base = dev_read_addr(dev);
> >> +    if (priv->hcd_base == FDT_ADDR_T_NONE)
> >> +            return -EINVAL;
> >> +
> >> +    ret = generic_phy_get_bulk(dev, &priv->phys);
> >> +    if (ret)
> >> +            return ret;
> >> +
> >> +    priv->hcd = (struct xhci_hccr *)priv->hcd_base;
> >> +    priv->dwc3_reg = (struct dwc3 *)((char *)(priv->hcd) + DWC3_REG_OFFSET);
> >> +    hcor = (struct xhci_hcor *)((uint32_t)priv->hcd +
> >> +                    HC_LENGTH(xhci_readl(&priv->hcd->cr_capbase)));
> >> +
> >> +    ret = generic_phy_power_on_bulk(&priv->phys);
> >> +    if (ret)
> >> +            generic_phy_exit_bulk(&priv->phys);
> >> +
> >> +    ret = ipq_xhci_core_init(priv);
> >> +
> >> +    if (ret) {
> >> +            dev_err(dev, "Error initializing the XHCI controller\n");
> >> +            return ret;
> >> +    }
> >> +
> >> +    return xhci_register(dev, priv->hcd, hcor);
> >> +}
> >> +
> >> +static const struct udevice_id ipq_xhci_match_ids[] = {
> >> +    { .compatible = "qcom,dwc3-ipq" },
> >> +    {}
> >> +};
> >> +
> >> +U_BOOT_DRIVER(usb_xhci) = {
> >> +    .name   = "ipq_hci",
> >> +    .id     = UCLASS_USB,
> >> +    .of_match = ipq_xhci_match_ids,
> >> +    .probe = ipq_xhci_usb_probe,
> >> +    .remove = ipq_xhci_usb_remove,
> >> +    .ops    = &xhci_usb_ops,
> >> +    .priv_auto_alloc_size = sizeof(struct ipq_xhci_priv),
> >> +    .flags  = DM_FLAG_ALLOC_PRIV_DMA,
> >> +};
> >
> > Adding USB maintainer.
>
> And adding Bin, since it's XHCI.

No need to bother reviewing this, I dropped it in the next patch
series that will be sent in a couple of minutes
Regards Robert

[PATCH v2 7/9] usb: dwc3: Make PHY functions depend on CONFIG_USB_DWC3

[Robert Marko]

On Thu, Sep 10, 2020 at 3:30 PM Tom Rini <trini@konsulko.com> wrote:
>
> On Tue, Sep 01, 2020 at 07:23:00PM +0200, Robert Marko wrote:
>
> > PHY handling functions should depend also on CONFIG_USB_DWC3 aka DM DWC3 version.
> > Otherwise when using the non DM version with PHY subsystem enabled there will be a linking error due to missing dwc3_setup_phy and dwc3_shutdown_phy.
> >
> > Signed-off-by: Robert Marko <robert.marko@sartura.hr>
> > Cc: Luka Perkov <luka.perkov@sartura.hr>
> > ---
> >  include/dwc3-uboot.h | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/include/dwc3-uboot.h b/include/dwc3-uboot.h
> > index e08530ec4e..5eb0822d74 100644
> > --- a/include/dwc3-uboot.h
> > +++ b/include/dwc3-uboot.h
> > @@ -47,7 +47,7 @@ void dwc3_uboot_exit(int index);
> >  void dwc3_uboot_handle_interrupt(int index);
> >
> >  struct phy;
> > -#if CONFIG_IS_ENABLED(PHY) && CONFIG_IS_ENABLED(DM_USB)
> > +#if CONFIG_IS_ENABLED(PHY) && CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(CONFIG_USB_DWC3)
> >  int dwc3_setup_phy(struct udevice *dev, struct phy_bulk *phys);
> >  int dwc3_shutdown_phy(struct udevice *dev, struct phy_bulk *phys);
> >  #else
>
> This should be CONFIG_IS_ENABLED(USB_DWC3).
This was dropped in v3 that will be sent out soon.
Regards
Robert
>
> --
> Tom