From: Lars Povlsen <lars.povlsen@microchip.com> To: Linus Walleij <linus.walleij@linaro.org> Cc: Lars Povlsen <lars.povlsen@microchip.com>, Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>, <devicetree@vger.kernel.org>, <linux-gpio@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>, Alexandre Belloni <alexandre.belloni@bootlin.com> Subject: [PATCH v2 3/3] arm64: dts: sparx5: Add SGPIO devices Date: Thu, 3 Sep 2020 15:35:28 +0200 [thread overview] Message-ID: <20200903133528.8595-4-lars.povlsen@microchip.com> (raw) In-Reply-To: <20200903133528.8595-1-lars.povlsen@microchip.com> This adds SGPIO devices for the Sparx5 SoC and configures it for the applicable reference boards. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 52 +++++++++++++++++++ .../boot/dts/microchip/sparx5_pcb125.dts | 5 ++ .../dts/microchip/sparx5_pcb134_board.dtsi | 5 ++ .../dts/microchip/sparx5_pcb135_board.dtsi | 5 ++ 4 files changed, 67 insertions(+) diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 5408486b4d3b..3cbf8824a545 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -232,6 +232,22 @@ si2_pins: si2-pins { function = "si2"; }; + sgpio0_pins: sgpio-pins { + pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3"; + function = "sg0"; + }; + + sgpio1_pins: sgpio1-pins { + pins = "GPIO_4", "GPIO_5", "GPIO_12", "GPIO_13"; + function = "sg1"; + }; + + sgpio2_pins: sgpio2-pins { + pins = "GPIO_30", "GPIO_31", "GPIO_32", + "GPIO_33"; + function = "sg2"; + }; + uart_pins: uart-pins { pins = "GPIO_10", "GPIO_11"; function = "uart"; @@ -262,6 +278,42 @@ emmc_pins: emmc-pins { }; }; + sgpio0: gpio@61101036c { + compatible = "microchip,sparx5-sgpio"; + status = "disabled"; + clocks = <&sys_clk>; + pinctrl-0 = <&sgpio0_pins>; + pinctrl-names = "default"; + reg = <0x6 0x1101036c 0x100>; + gpio-controller; + gpio-ranges = <&sgpio0 0 0 192>; + #gpio-cells = <4>; + }; + + sgpio1: gpio@611010484 { + compatible = "microchip,sparx5-sgpio"; + status = "disabled"; + clocks = <&sys_clk>; + pinctrl-0 = <&sgpio1_pins>; + pinctrl-names = "default"; + reg = <0x6 0x11010484 0x100>; + gpio-controller; + gpio-ranges = <&sgpio1 0 0 192>; + #gpio-cells = <4>; + }; + + sgpio2: gpio@61101059c { + compatible = "microchip,sparx5-sgpio"; + status = "disabled"; + clocks = <&sys_clk>; + pinctrl-0 = <&sgpio2_pins>; + pinctrl-names = "default"; + reg = <0x6 0x1101059c 0x100>; + gpio-controller; + gpio-ranges = <&sgpio2 0 0 192>; + #gpio-cells = <4>; + }; + i2c0: i2c@600101000 { compatible = "snps,designware-i2c"; status = "disabled"; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts index 6b2da7c7520c..9baa085d7861 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts @@ -69,6 +69,11 @@ spi-flash@9 { }; }; +&sgpio0 { + status = "okay"; + microchip,sgpio-port-ranges = <0 23>; +}; + &i2c1 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi index 35984785d611..65336be31fd9 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi @@ -54,6 +54,11 @@ spi-flash@9 { }; }; +&sgpio2 { + status = "okay"; + microchip,sgpio-port-ranges = <0 0 11 31>; +}; + &gpio { i2cmux_pins_i: i2cmux-pins-i { pins = "GPIO_16", "GPIO_17", "GPIO_18", "GPIO_19", diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi index 7de66806b14b..5ea2d0910c2b 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi @@ -67,6 +67,11 @@ spi-flash@9 { }; }; +&sgpio2 { + status = "okay"; + microchip,sgpio-port-ranges = <0 0 16 18 28 31>; +}; + &axi { i2c0_imux: i2c0-imux@0 { compatible = "i2c-mux-pinctrl"; -- 2.27.0
WARNING: multiple messages have this Message-ID (diff)
From: Lars Povlsen <lars.povlsen@microchip.com> To: Linus Walleij <linus.walleij@linaro.org> Cc: devicetree@vger.kernel.org, Alexandre Belloni <alexandre.belloni@bootlin.com>, linux-kernel@vger.kernel.org, Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>, linux-gpio@vger.kernel.org, Lars Povlsen <lars.povlsen@microchip.com>, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 3/3] arm64: dts: sparx5: Add SGPIO devices Date: Thu, 3 Sep 2020 15:35:28 +0200 [thread overview] Message-ID: <20200903133528.8595-4-lars.povlsen@microchip.com> (raw) In-Reply-To: <20200903133528.8595-1-lars.povlsen@microchip.com> This adds SGPIO devices for the Sparx5 SoC and configures it for the applicable reference boards. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 52 +++++++++++++++++++ .../boot/dts/microchip/sparx5_pcb125.dts | 5 ++ .../dts/microchip/sparx5_pcb134_board.dtsi | 5 ++ .../dts/microchip/sparx5_pcb135_board.dtsi | 5 ++ 4 files changed, 67 insertions(+) diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 5408486b4d3b..3cbf8824a545 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -232,6 +232,22 @@ si2_pins: si2-pins { function = "si2"; }; + sgpio0_pins: sgpio-pins { + pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3"; + function = "sg0"; + }; + + sgpio1_pins: sgpio1-pins { + pins = "GPIO_4", "GPIO_5", "GPIO_12", "GPIO_13"; + function = "sg1"; + }; + + sgpio2_pins: sgpio2-pins { + pins = "GPIO_30", "GPIO_31", "GPIO_32", + "GPIO_33"; + function = "sg2"; + }; + uart_pins: uart-pins { pins = "GPIO_10", "GPIO_11"; function = "uart"; @@ -262,6 +278,42 @@ emmc_pins: emmc-pins { }; }; + sgpio0: gpio@61101036c { + compatible = "microchip,sparx5-sgpio"; + status = "disabled"; + clocks = <&sys_clk>; + pinctrl-0 = <&sgpio0_pins>; + pinctrl-names = "default"; + reg = <0x6 0x1101036c 0x100>; + gpio-controller; + gpio-ranges = <&sgpio0 0 0 192>; + #gpio-cells = <4>; + }; + + sgpio1: gpio@611010484 { + compatible = "microchip,sparx5-sgpio"; + status = "disabled"; + clocks = <&sys_clk>; + pinctrl-0 = <&sgpio1_pins>; + pinctrl-names = "default"; + reg = <0x6 0x11010484 0x100>; + gpio-controller; + gpio-ranges = <&sgpio1 0 0 192>; + #gpio-cells = <4>; + }; + + sgpio2: gpio@61101059c { + compatible = "microchip,sparx5-sgpio"; + status = "disabled"; + clocks = <&sys_clk>; + pinctrl-0 = <&sgpio2_pins>; + pinctrl-names = "default"; + reg = <0x6 0x1101059c 0x100>; + gpio-controller; + gpio-ranges = <&sgpio2 0 0 192>; + #gpio-cells = <4>; + }; + i2c0: i2c@600101000 { compatible = "snps,designware-i2c"; status = "disabled"; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts index 6b2da7c7520c..9baa085d7861 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts @@ -69,6 +69,11 @@ spi-flash@9 { }; }; +&sgpio0 { + status = "okay"; + microchip,sgpio-port-ranges = <0 23>; +}; + &i2c1 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi index 35984785d611..65336be31fd9 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi @@ -54,6 +54,11 @@ spi-flash@9 { }; }; +&sgpio2 { + status = "okay"; + microchip,sgpio-port-ranges = <0 0 11 31>; +}; + &gpio { i2cmux_pins_i: i2cmux-pins-i { pins = "GPIO_16", "GPIO_17", "GPIO_18", "GPIO_19", diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi index 7de66806b14b..5ea2d0910c2b 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi @@ -67,6 +67,11 @@ spi-flash@9 { }; }; +&sgpio2 { + status = "okay"; + microchip,sgpio-port-ranges = <0 0 16 18 28 31>; +}; + &axi { i2c0_imux: i2c0-imux@0 { compatible = "i2c-mux-pinctrl"; -- 2.27.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-09-03 15:01 UTC|newest] Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-09-03 13:35 [PATCH v2 0/3] pinctrl: Adding support for Microchip/Microsemi serial GPIO controller Lars Povlsen 2020-09-03 13:35 ` Lars Povlsen 2020-09-03 13:35 ` [PATCH v2 1/3] dt-bindings: pinctrl: Add bindings for pinctrl-mchp-sgpio driver Lars Povlsen 2020-09-03 13:35 ` Lars Povlsen 2020-09-12 10:50 ` Linus Walleij 2020-09-12 10:50 ` Linus Walleij 2020-09-13 19:11 ` Lars Povlsen 2020-09-13 19:11 ` Lars Povlsen 2020-09-30 9:21 ` Linus Walleij 2020-09-30 9:21 ` Linus Walleij 2020-10-05 8:21 ` Lars Povlsen 2020-10-05 8:21 ` Lars Povlsen 2020-09-03 13:35 ` [PATCH v2 2/3] pinctrl: pinctrl-mchp-sgpio: Add pinctrl driver for Microsemi Serial GPIO Lars Povlsen 2020-09-03 13:35 ` Lars Povlsen 2020-09-12 11:11 ` Linus Walleij 2020-09-12 11:11 ` Linus Walleij 2020-09-13 19:28 ` Lars Povlsen 2020-09-13 19:28 ` Lars Povlsen 2020-09-03 13:35 ` Lars Povlsen [this message] 2020-09-03 13:35 ` [PATCH v2 3/3] arm64: dts: sparx5: Add SGPIO devices Lars Povlsen
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