* [PATCH] arch64: dts: qcom: sm8250: add uart nodes
@ 2020-09-09 10:32 Dmitry Baryshkov
2020-09-09 10:32 ` Dmitry Baryshkov
0 siblings, 1 reply; 4+ messages in thread
From: Dmitry Baryshkov @ 2020-09-09 10:32 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson
Cc: Manivannan Sadhasivam, linux-arm-msm, Rob Herring
Currently sm8250.dtsi only defines default debug uart. Port rest uart
nodes from the downstream dtsi file.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 74 ++++++++++++++++++++++++++++
1 file changed, 74 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index e5525df69946..552fa3df9e4f 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -551,6 +551,17 @@ spi17: spi@88c000 {
status = "disabled";
};
+ uart17: serial@88c000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x0088c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart17_default>;
+ interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
i2c18: i2c@890000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00890000 0 0x4000>;
@@ -577,6 +588,17 @@ spi18: spi@890000 {
status = "disabled";
};
+ uart18: serial@890000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00890000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart18_default>;
+ interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
i2c19: i2c@894000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00894000 0 0x4000>;
@@ -693,6 +715,17 @@ spi2: spi@988000 {
status = "disabled";
};
+ uart2: serial@988000 {
+ compatible = "qcom,geni-debug-uart";
+ reg = <0 0x00988000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart2_default>;
+ interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
i2c3: i2c@98c000 {
compatible = "qcom,geni-i2c";
reg = <0 0x0098c000 0 0x4000>;
@@ -797,6 +830,17 @@ spi6: spi@998000 {
status = "disabled";
};
+ uart6: serial@998000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00998000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart6_default>;
+ interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
i2c7: i2c@99c000 {
compatible = "qcom,geni-i2c";
reg = <0 0x0099c000 0 0x4000>;
@@ -2410,6 +2454,21 @@ config {
};
};
+ qup_uart2_default: qup-uart2-default {
+ mux {
+ pins = "gpio117", "gpio118";
+ function = "qup2";
+ };
+ };
+
+ qup_uart6_default: qup-uart6-default {
+ mux {
+ pins = "gpio16", "gpio17",
+ "gpio18", "gpio19";
+ function = "qup6";
+ };
+ };
+
qup_uart12_default: qup-uart12-default {
mux {
pins = "gpio34", "gpio35";
@@ -2417,6 +2476,21 @@ mux {
};
};
+ qup_uart17_default: qup-uart17-default {
+ mux {
+ pins = "gpio52", "gpio53",
+ "gpio54", "gpio55";
+ function = "qup17";
+ };
+ };
+
+ qup_uart18_default: qup-uart18-default {
+ mux {
+ pins = "gpio58", "gpio59";
+ function = "qup18";
+ };
+ };
+
pri_mi2s_sck_active: pri-mi2s-sck-active {
mux {
pins = "gpio138";
--
2.28.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH] arch64: dts: qcom: sm8250: add uart nodes
2020-09-09 10:32 [PATCH] arch64: dts: qcom: sm8250: add uart nodes Dmitry Baryshkov
@ 2020-09-09 10:32 ` Dmitry Baryshkov
2020-09-14 9:32 ` Dmitry Baryshkov
2020-09-14 10:32 ` Manivannan Sadhasivam
0 siblings, 2 replies; 4+ messages in thread
From: Dmitry Baryshkov @ 2020-09-09 10:32 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson
Cc: Manivannan Sadhasivam, linux-arm-msm, Rob Herring
Currently sm8250.dtsi only defines default debug uart. Port rest uart
nodes from the downstream dtsi file.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 74 ++++++++++++++++++++++++++++
1 file changed, 74 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index e5525df69946..552fa3df9e4f 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -551,6 +551,17 @@ spi17: spi@88c000 {
status = "disabled";
};
+ uart17: serial@88c000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x0088c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart17_default>;
+ interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
i2c18: i2c@890000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00890000 0 0x4000>;
@@ -577,6 +588,17 @@ spi18: spi@890000 {
status = "disabled";
};
+ uart18: serial@890000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00890000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart18_default>;
+ interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
i2c19: i2c@894000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00894000 0 0x4000>;
@@ -693,6 +715,17 @@ spi2: spi@988000 {
status = "disabled";
};
+ uart2: serial@988000 {
+ compatible = "qcom,geni-debug-uart";
+ reg = <0 0x00988000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart2_default>;
+ interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
i2c3: i2c@98c000 {
compatible = "qcom,geni-i2c";
reg = <0 0x0098c000 0 0x4000>;
@@ -797,6 +830,17 @@ spi6: spi@998000 {
status = "disabled";
};
+ uart6: serial@998000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00998000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart6_default>;
+ interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
i2c7: i2c@99c000 {
compatible = "qcom,geni-i2c";
reg = <0 0x0099c000 0 0x4000>;
@@ -2410,6 +2454,21 @@ config {
};
};
+ qup_uart2_default: qup-uart2-default {
+ mux {
+ pins = "gpio117", "gpio118";
+ function = "qup2";
+ };
+ };
+
+ qup_uart6_default: qup-uart6-default {
+ mux {
+ pins = "gpio16", "gpio17",
+ "gpio18", "gpio19";
+ function = "qup6";
+ };
+ };
+
qup_uart12_default: qup-uart12-default {
mux {
pins = "gpio34", "gpio35";
@@ -2417,6 +2476,21 @@ mux {
};
};
+ qup_uart17_default: qup-uart17-default {
+ mux {
+ pins = "gpio52", "gpio53",
+ "gpio54", "gpio55";
+ function = "qup17";
+ };
+ };
+
+ qup_uart18_default: qup-uart18-default {
+ mux {
+ pins = "gpio58", "gpio59";
+ function = "qup18";
+ };
+ };
+
pri_mi2s_sck_active: pri-mi2s-sck-active {
mux {
pins = "gpio138";
--
2.28.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] arch64: dts: qcom: sm8250: add uart nodes
2020-09-09 10:32 ` Dmitry Baryshkov
@ 2020-09-14 9:32 ` Dmitry Baryshkov
2020-09-14 10:32 ` Manivannan Sadhasivam
1 sibling, 0 replies; 4+ messages in thread
From: Dmitry Baryshkov @ 2020-09-14 9:32 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson
Cc: Manivannan Sadhasivam, linux-arm-msm, Rob Herring
On 09/09/2020 13:32, Dmitry Baryshkov wrote:
> Currently sm8250.dtsi only defines default debug uart. Port rest uart
> nodes from the downstream dtsi file.
Gracious ping for this patch
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sm8250.dtsi | 74 ++++++++++++++++++++++++++++
> 1 file changed, 74 insertions(+)
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] arch64: dts: qcom: sm8250: add uart nodes
2020-09-09 10:32 ` Dmitry Baryshkov
2020-09-14 9:32 ` Dmitry Baryshkov
@ 2020-09-14 10:32 ` Manivannan Sadhasivam
1 sibling, 0 replies; 4+ messages in thread
From: Manivannan Sadhasivam @ 2020-09-14 10:32 UTC (permalink / raw)
To: Dmitry Baryshkov; +Cc: Andy Gross, Bjorn Andersson, linux-arm-msm, Rob Herring
On Wed, Sep 09, 2020 at 01:32:38PM +0300, Dmitry Baryshkov wrote:
> Currently sm8250.dtsi only defines default debug uart. Port rest uart
> nodes from the downstream dtsi file.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Thanks,
Mani
> ---
> arch/arm64/boot/dts/qcom/sm8250.dtsi | 74 ++++++++++++++++++++++++++++
> 1 file changed, 74 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> index e5525df69946..552fa3df9e4f 100644
> --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> @@ -551,6 +551,17 @@ spi17: spi@88c000 {
> status = "disabled";
> };
>
> + uart17: serial@88c000 {
> + compatible = "qcom,geni-uart";
> + reg = <0 0x0088c000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_uart17_default>;
> + interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> i2c18: i2c@890000 {
> compatible = "qcom,geni-i2c";
> reg = <0 0x00890000 0 0x4000>;
> @@ -577,6 +588,17 @@ spi18: spi@890000 {
> status = "disabled";
> };
>
> + uart18: serial@890000 {
> + compatible = "qcom,geni-uart";
> + reg = <0 0x00890000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_uart18_default>;
> + interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> i2c19: i2c@894000 {
> compatible = "qcom,geni-i2c";
> reg = <0 0x00894000 0 0x4000>;
> @@ -693,6 +715,17 @@ spi2: spi@988000 {
> status = "disabled";
> };
>
> + uart2: serial@988000 {
> + compatible = "qcom,geni-debug-uart";
> + reg = <0 0x00988000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_uart2_default>;
> + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> i2c3: i2c@98c000 {
> compatible = "qcom,geni-i2c";
> reg = <0 0x0098c000 0 0x4000>;
> @@ -797,6 +830,17 @@ spi6: spi@998000 {
> status = "disabled";
> };
>
> + uart6: serial@998000 {
> + compatible = "qcom,geni-uart";
> + reg = <0 0x00998000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_uart6_default>;
> + interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> i2c7: i2c@99c000 {
> compatible = "qcom,geni-i2c";
> reg = <0 0x0099c000 0 0x4000>;
> @@ -2410,6 +2454,21 @@ config {
> };
> };
>
> + qup_uart2_default: qup-uart2-default {
> + mux {
> + pins = "gpio117", "gpio118";
> + function = "qup2";
> + };
> + };
> +
> + qup_uart6_default: qup-uart6-default {
> + mux {
> + pins = "gpio16", "gpio17",
> + "gpio18", "gpio19";
> + function = "qup6";
> + };
> + };
> +
> qup_uart12_default: qup-uart12-default {
> mux {
> pins = "gpio34", "gpio35";
> @@ -2417,6 +2476,21 @@ mux {
> };
> };
>
> + qup_uart17_default: qup-uart17-default {
> + mux {
> + pins = "gpio52", "gpio53",
> + "gpio54", "gpio55";
> + function = "qup17";
> + };
> + };
> +
> + qup_uart18_default: qup-uart18-default {
> + mux {
> + pins = "gpio58", "gpio59";
> + function = "qup18";
> + };
> + };
> +
> pri_mi2s_sck_active: pri-mi2s-sck-active {
> mux {
> pins = "gpio138";
> --
> 2.28.0
>
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2020-09-14 10:33 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2020-09-09 10:32 [PATCH] arch64: dts: qcom: sm8250: add uart nodes Dmitry Baryshkov
2020-09-09 10:32 ` Dmitry Baryshkov
2020-09-14 9:32 ` Dmitry Baryshkov
2020-09-14 10:32 ` Manivannan Sadhasivam
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