* [Intel-gfx] [v6 00/11] Enable HDR on MCA LSPCON based Gen9 devices
@ 2020-09-14 21:00 Uma Shankar
2020-09-14 21:00 ` [Intel-gfx] [v6 01/11] drm/i915/display: Add HDR Capability detection for LSPCON Uma Shankar
` (13 more replies)
0 siblings, 14 replies; 31+ messages in thread
From: Uma Shankar @ 2020-09-14 21:00 UTC (permalink / raw)
To: intel-gfx
Gen9 hardware supports HDMI2.0 through LSPCON chips. Extending HDR
support for MCA and Parade LSPCON based GEN9 devices.
SOC will drive LSPCON as DP and send HDR metadata as standard
DP SDP packets. LSPCON will be set to operate in PCON mode,
will receive the metadata and create Dynamic Range and
Mastering Infoframe (DRM packets) and send it to HDR capable
HDMI sink devices.
v2: Fixed Ville's review comments. Suppressed some warnings.
Patch 8 of the series is marked "Not for Merge" and is just for
reference to userspace people to incorporate in order to support
10bit content with 4K@60 resolutions.
v3: Added Infoframe readout support for DRM infoframes.
Addressed Jani Nikula's review comments.
v4: Addressed Ville's review comments and added proper bitmask for
enabled infoframes. Series also incorporates Ville's patch for stopping
infoframes to be sent to DVI sinks. Extended the same for DRM as well.
v5: Created separate helper function for lspcon_infoframes_enabled as per
Ville's suggestion.
v6: Rebase
Note: Patch 11 of the series is for reference to userspace, not to be
merged to driver.
Uma Shankar (10):
drm/i915/display: Add HDR Capability detection for LSPCON
drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon
drm/i915/display: Attach HDR property for capable Gen9 devices
drm/i915/display: Enable BT2020 for HDR on LSPCON devices
drm/i915/display: Enable HDR for Parade based lspcon
drm/i915/display: Implement infoframes readback for LSPCON
drm/i915/display: Implement DRM infoframe read for LSPCON
drm/i915/lspcon: Create separate infoframe_enabled helper
drm/i915/lspcon: Do not send DRM infoframes to non-HDMI sinks
drm/i915/display: [NOT FOR MERGE] Reduce blanking to support
4k60@10bpp for LSPCON
Ville Syrjälä (1):
drm/i915/lspcon: Do not send infoframes to non-HDMI sinks
drivers/gpu/drm/i915/display/intel_ddi.c | 30 ++--
.../drm/i915/display/intel_display_types.h | 2 +
drivers/gpu/drm/i915/display/intel_dp.c | 24 ++-
drivers/gpu/drm/i915/display/intel_hdmi.c | 20 +++
drivers/gpu/drm/i915/display/intel_lspcon.c | 170 ++++++++++++++++--
drivers/gpu/drm/i915/display/intel_lspcon.h | 11 +-
6 files changed, 230 insertions(+), 27 deletions(-)
--
2.26.2
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^ permalink raw reply [flat|nested] 31+ messages in thread
* [Intel-gfx] [v6 01/11] drm/i915/display: Add HDR Capability detection for LSPCON
2020-09-14 21:00 [Intel-gfx] [v6 00/11] Enable HDR on MCA LSPCON based Gen9 devices Uma Shankar
@ 2020-09-14 21:00 ` Uma Shankar
2020-09-14 21:00 ` [Intel-gfx] [v6 02/11] drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon Uma Shankar
` (12 subsequent siblings)
13 siblings, 0 replies; 31+ messages in thread
From: Uma Shankar @ 2020-09-14 21:00 UTC (permalink / raw)
To: intel-gfx
LSPCON firmware exposes HDR capability through LPCON_CAPABILITIES
DPCD register. LSPCON implementations capable of supporting
HDR set HDR_CAPABILITY bit in LSPCON_CAPABILITIES to 1. This patch
reads the same, detects the HDR capability and adds this to
intel_lspcon struct.
v2: Addressed Jani Nikula's review comment and fixed the HDR
capability detection logic
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
.../drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_lspcon.c | 30 +++++++++++++++++++
2 files changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index b2d0edacc58c..5cf4e7a591e0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1396,6 +1396,7 @@ struct intel_lspcon {
bool active;
enum drm_lspcon_mode mode;
enum lspcon_vendor vendor;
+ bool hdr_supported;
};
struct intel_digital_port {
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c
index dc1b35559afd..8e8c7a02ab51 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -35,6 +35,8 @@
#define LSPCON_VENDOR_PARADE_OUI 0x001CF8
#define LSPCON_VENDOR_MCA_OUI 0x0060AD
+#define DPCD_MCA_LSPCON_HDR_STATUS 0x70003
+
/* AUX addresses to write MCA AVI IF */
#define LSPCON_MCA_AVI_IF_WRITE_OFFSET 0x5C0
#define LSPCON_MCA_AVI_IF_CTRL 0x5DF
@@ -104,6 +106,32 @@ static bool lspcon_detect_vendor(struct intel_lspcon *lspcon)
return true;
}
+static void lspcon_detect_hdr_capability(struct intel_lspcon *lspcon)
+{
+ struct intel_digital_port *intel_dig_port =
+ container_of(lspcon, struct intel_digital_port, lspcon);
+ struct drm_device *dev = intel_dig_port->base.base.dev;
+ struct intel_dp *dp = lspcon_to_intel_dp(lspcon);
+ u8 hdr_caps;
+ int ret;
+
+ /* Enable HDR for MCA based LSPCON devices */
+ if (lspcon->vendor == LSPCON_VENDOR_MCA)
+ ret = drm_dp_dpcd_read(&dp->aux, DPCD_MCA_LSPCON_HDR_STATUS,
+ &hdr_caps, 1);
+ else
+ return;
+
+ if (ret < 0) {
+ drm_dbg_kms(dev, "hdr capability detection failed\n");
+ lspcon->hdr_supported = false;
+ return;
+ } else if (hdr_caps & 0x1) {
+ drm_dbg_kms(dev, "lspcon capable of HDR\n");
+ lspcon->hdr_supported = true;
+ }
+}
+
static enum drm_lspcon_mode lspcon_get_current_mode(struct intel_lspcon *lspcon)
{
enum drm_lspcon_mode current_mode;
@@ -581,6 +609,8 @@ bool lspcon_init(struct intel_digital_port *dig_port)
return false;
}
+ lspcon_detect_hdr_capability(lspcon);
+
connector->ycbcr_420_allowed = true;
lspcon->active = true;
DRM_DEBUG_KMS("Success: LSPCON init\n");
--
2.26.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [Intel-gfx] [v6 02/11] drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon
2020-09-14 21:00 [Intel-gfx] [v6 00/11] Enable HDR on MCA LSPCON based Gen9 devices Uma Shankar
2020-09-14 21:00 ` [Intel-gfx] [v6 01/11] drm/i915/display: Add HDR Capability detection for LSPCON Uma Shankar
@ 2020-09-14 21:00 ` Uma Shankar
2020-09-29 16:12 ` Ville Syrjälä
2020-09-14 21:00 ` [Intel-gfx] [v6 03/11] drm/i915/display: Attach HDR property for capable Gen9 devices Uma Shankar
` (11 subsequent siblings)
13 siblings, 1 reply; 31+ messages in thread
From: Uma Shankar @ 2020-09-14 21:00 UTC (permalink / raw)
To: intel-gfx
Gen9 hardware supports HDMI2.0 through LSPCON chips.
Extending HDR support for MCA LSPCON based GEN9 devices.
SOC will drive LSPCON as DP and send HDR metadata as standard
DP SDP packets. LSPCON will be set to operate in PCON mode,
will receive the metadata and create Dynamic Range and
Mastering Infoframe (DRM packets) and send it to HDR capable
HDMI sink devices.
v2: Re-used hsw infoframe write implementation for HDR metadata
for LSPCON as per Ville's suggestion.
v3: Addressed Jani Nikula's review comments.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 10 ++++++
drivers/gpu/drm/i915/display/intel_lspcon.c | 37 +++++++++++++++------
drivers/gpu/drm/i915/display/intel_lspcon.h | 5 ++-
3 files changed, 40 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 0978b0d8f4c6..1e40ed473fb9 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -590,6 +590,16 @@ static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
return val & mask;
}
+void lspcon_drm_write_infoframe(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ unsigned int type,
+ const void *frame, ssize_t len)
+{
+ drm_dbg_kms(encoder->base.dev, "Update HDR metadata for lspcon\n");
+ /* It uses the legacy hsw implementation for the same */
+ hsw_write_infoframe(encoder, crtc_state, type, frame, len);
+}
+
static const u8 infoframe_type_to_idx[] = {
HDMI_PACKET_TYPE_GENERAL_CONTROL,
HDMI_PACKET_TYPE_GAMUT_METADATA,
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c
index 8e8c7a02ab51..5e2d7ca1d20f 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -461,27 +461,42 @@ void lspcon_write_infoframe(struct intel_encoder *encoder,
unsigned int type,
const void *frame, ssize_t len)
{
- bool ret;
+ bool ret = true;
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder);
- /* LSPCON only needs AVI IF */
- if (type != HDMI_INFOFRAME_TYPE_AVI)
+ /*
+ * Supporting HDR on MCA LSPCON
+ * Todo: Add support for Parade later
+ */
+ if (type == HDMI_PACKET_TYPE_GAMUT_METADATA &&
+ lspcon->vendor != LSPCON_VENDOR_MCA)
return;
- if (lspcon->vendor == LSPCON_VENDOR_MCA)
- ret = _lspcon_write_avi_infoframe_mca(&intel_dp->aux,
- frame, len);
- else
- ret = _lspcon_write_avi_infoframe_parade(&intel_dp->aux,
- frame, len);
+ switch (type) {
+ case HDMI_INFOFRAME_TYPE_AVI:
+ if (lspcon->vendor == LSPCON_VENDOR_MCA)
+ ret = _lspcon_write_avi_infoframe_mca(&intel_dp->aux,
+ frame, len);
+ else
+ ret = _lspcon_write_avi_infoframe_parade(&intel_dp->aux,
+ frame, len);
+ break;
+ case HDMI_PACKET_TYPE_GAMUT_METADATA:
+ lspcon_drm_write_infoframe(encoder, crtc_state,
+ HDMI_PACKET_TYPE_GAMUT_METADATA,
+ frame, VIDEO_DIP_DATA_SIZE);
+ break;
+ default:
+ return;
+ }
if (!ret) {
- DRM_ERROR("Failed to write AVI infoframes\n");
+ DRM_ERROR("Failed to write infoframes\n");
return;
}
- DRM_DEBUG_DRIVER("AVI infoframes updated successfully\n");
+ DRM_DEBUG_DRIVER("Infoframes updated successfully\n");
}
void lspcon_read_infoframe(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h b/drivers/gpu/drm/i915/display/intel_lspcon.h
index 1cffe8a42a08..3fac05535731 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.h
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.h
@@ -34,5 +34,8 @@ u32 lspcon_infoframes_enabled(struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config);
void lspcon_ycbcr420_config(struct drm_connector *connector,
struct intel_crtc_state *crtc_state);
-
+void lspcon_drm_write_infoframe(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ unsigned int type,
+ const void *frame, ssize_t len);
#endif /* __INTEL_LSPCON_H__ */
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [Intel-gfx] [v6 03/11] drm/i915/display: Attach HDR property for capable Gen9 devices
2020-09-14 21:00 [Intel-gfx] [v6 00/11] Enable HDR on MCA LSPCON based Gen9 devices Uma Shankar
2020-09-14 21:00 ` [Intel-gfx] [v6 01/11] drm/i915/display: Add HDR Capability detection for LSPCON Uma Shankar
2020-09-14 21:00 ` [Intel-gfx] [v6 02/11] drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon Uma Shankar
@ 2020-09-14 21:00 ` Uma Shankar
2020-09-29 16:14 ` Ville Syrjälä
2020-09-14 21:00 ` [Intel-gfx] [v6 04/11] drm/i915/display: Enable BT2020 for HDR on LSPCON devices Uma Shankar
` (10 subsequent siblings)
13 siblings, 1 reply; 31+ messages in thread
From: Uma Shankar @ 2020-09-14 21:00 UTC (permalink / raw)
To: intel-gfx
Attach HDR property for Gen9 devices with MCA LSPCON
chips.
v2: Cleaned HDR property attachment logic based on capability
as per Jani Nikula's suggestion.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_lspcon.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c
index 5e2d7ca1d20f..fd05210f4405 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -626,6 +626,11 @@ bool lspcon_init(struct intel_digital_port *dig_port)
lspcon_detect_hdr_capability(lspcon);
+ if (lspcon->hdr_supported)
+ drm_object_attach_property(&connector->base,
+ connector->dev->mode_config.hdr_output_metadata_property,
+ 0);
+
connector->ycbcr_420_allowed = true;
lspcon->active = true;
DRM_DEBUG_KMS("Success: LSPCON init\n");
--
2.26.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [Intel-gfx] [v6 04/11] drm/i915/display: Enable BT2020 for HDR on LSPCON devices
2020-09-14 21:00 [Intel-gfx] [v6 00/11] Enable HDR on MCA LSPCON based Gen9 devices Uma Shankar
` (2 preceding siblings ...)
2020-09-14 21:00 ` [Intel-gfx] [v6 03/11] drm/i915/display: Attach HDR property for capable Gen9 devices Uma Shankar
@ 2020-09-14 21:00 ` Uma Shankar
2020-09-29 16:18 ` Ville Syrjälä
2020-09-14 21:00 ` [Intel-gfx] [v6 05/11] drm/i915/display: Enable HDR for Parade based lspcon Uma Shankar
` (9 subsequent siblings)
13 siblings, 1 reply; 31+ messages in thread
From: Uma Shankar @ 2020-09-14 21:00 UTC (permalink / raw)
To: intel-gfx
Enable Colorspace as BT2020 if driving HDR content.Sending Colorimetry
data for HDR using AVI infoframe. LSPCON firmware expects this and though
SOC drives DP, for HDMI panel AVI infoframe is sent to the LSPCON device
which transfers the same to HDMI sink.
v2: Dropped state managed in drm core as per Jani Nikula's suggestion.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_lspcon.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c
index fd05210f4405..b0ca494f1110 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -507,6 +507,11 @@ void lspcon_read_infoframe(struct intel_encoder *encoder,
/* FIXME implement this */
}
+/* HDMI HDR Colorspace Spec Definitions */
+#define NORMAL_COLORIMETRY_MASK 0x3
+#define EXTENDED_COLORIMETRY_MASK 0x7
+#define HDMI_COLORIMETRY_BT2020_YCC ((3 << 0) | (6 << 2) | (0 << 5))
+
void lspcon_set_infoframes(struct intel_encoder *encoder,
bool enable,
const struct intel_crtc_state *crtc_state,
@@ -551,6 +556,19 @@ void lspcon_set_infoframes(struct intel_encoder *encoder,
HDMI_QUANTIZATION_RANGE_LIMITED :
HDMI_QUANTIZATION_RANGE_FULL);
+ /*
+ * Set BT2020 colorspace if driving HDR data
+ * ToDo: Make this generic and expose all colorspaces for lspcon
+ */
+ if (lspcon->active && lspcon->hdr_supported) {
+ frame.avi.colorimetry =
+ HDMI_COLORIMETRY_BT2020_YCC &
+ NORMAL_COLORIMETRY_MASK;
+ frame.avi.extended_colorimetry =
+ (HDMI_COLORIMETRY_BT2020_YCC >> 2) &
+ EXTENDED_COLORIMETRY_MASK;
+ }
+
ret = hdmi_infoframe_pack(&frame, buf, sizeof(buf));
if (ret < 0) {
DRM_ERROR("Failed to pack AVI IF\n");
--
2.26.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [Intel-gfx] [v6 05/11] drm/i915/display: Enable HDR for Parade based lspcon
2020-09-14 21:00 [Intel-gfx] [v6 00/11] Enable HDR on MCA LSPCON based Gen9 devices Uma Shankar
` (3 preceding siblings ...)
2020-09-14 21:00 ` [Intel-gfx] [v6 04/11] drm/i915/display: Enable BT2020 for HDR on LSPCON devices Uma Shankar
@ 2020-09-14 21:00 ` Uma Shankar
2020-09-29 16:19 ` Ville Syrjälä
2020-09-14 21:00 ` [Intel-gfx] [v6 06/11] drm/i915/display: Implement infoframes readback for LSPCON Uma Shankar
` (8 subsequent siblings)
13 siblings, 1 reply; 31+ messages in thread
From: Uma Shankar @ 2020-09-14 21:00 UTC (permalink / raw)
To: intel-gfx; +Cc: Vipin Anand
Enable HDR for LSPCON based on Parade along with MCA.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Vipin Anand <vipin.anand@intel.com>
---
drivers/gpu/drm/i915/display/intel_lspcon.c | 19 ++++++++-----------
1 file changed, 8 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c
index b0ca494f1110..60863b825cc5 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -36,6 +36,7 @@
#define LSPCON_VENDOR_MCA_OUI 0x0060AD
#define DPCD_MCA_LSPCON_HDR_STATUS 0x70003
+#define DPCD_PARADE_LSPCON_HDR_STATUS 0x00511
/* AUX addresses to write MCA AVI IF */
#define LSPCON_MCA_AVI_IF_WRITE_OFFSET 0x5C0
@@ -112,16 +113,20 @@ static void lspcon_detect_hdr_capability(struct intel_lspcon *lspcon)
container_of(lspcon, struct intel_digital_port, lspcon);
struct drm_device *dev = intel_dig_port->base.base.dev;
struct intel_dp *dp = lspcon_to_intel_dp(lspcon);
+ u32 lspcon_hdr_status_reg;
u8 hdr_caps;
int ret;
- /* Enable HDR for MCA based LSPCON devices */
if (lspcon->vendor == LSPCON_VENDOR_MCA)
- ret = drm_dp_dpcd_read(&dp->aux, DPCD_MCA_LSPCON_HDR_STATUS,
- &hdr_caps, 1);
+ lspcon_hdr_status_reg = DPCD_MCA_LSPCON_HDR_STATUS;
+ else if (lspcon->vendor == LSPCON_VENDOR_PARADE)
+ lspcon_hdr_status_reg = DPCD_PARADE_LSPCON_HDR_STATUS;
else
return;
+ ret = drm_dp_dpcd_read(&dp->aux, lspcon_hdr_status_reg,
+ &hdr_caps, 1);
+
if (ret < 0) {
drm_dbg_kms(dev, "hdr capability detection failed\n");
lspcon->hdr_supported = false;
@@ -465,14 +470,6 @@ void lspcon_write_infoframe(struct intel_encoder *encoder,
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder);
- /*
- * Supporting HDR on MCA LSPCON
- * Todo: Add support for Parade later
- */
- if (type == HDMI_PACKET_TYPE_GAMUT_METADATA &&
- lspcon->vendor != LSPCON_VENDOR_MCA)
- return;
-
switch (type) {
case HDMI_INFOFRAME_TYPE_AVI:
if (lspcon->vendor == LSPCON_VENDOR_MCA)
--
2.26.2
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [Intel-gfx] [v6 06/11] drm/i915/display: Implement infoframes readback for LSPCON
2020-09-14 21:00 [Intel-gfx] [v6 00/11] Enable HDR on MCA LSPCON based Gen9 devices Uma Shankar
` (4 preceding siblings ...)
2020-09-14 21:00 ` [Intel-gfx] [v6 05/11] drm/i915/display: Enable HDR for Parade based lspcon Uma Shankar
@ 2020-09-14 21:00 ` Uma Shankar
2020-09-29 16:20 ` Ville Syrjälä
2020-09-14 21:00 ` [Intel-gfx] [v6 07/11] drm/i915/display: Implement DRM infoframe read " Uma Shankar
` (7 subsequent siblings)
13 siblings, 1 reply; 31+ messages in thread
From: Uma Shankar @ 2020-09-14 21:00 UTC (permalink / raw)
To: intel-gfx
Implemented Infoframes enabled readback for LSPCON devices.
This will help align the implementation with state readback
infrastructure.
v2: Added proper bitmask of enabled infoframes as per Ville's
recommendation.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_lspcon.c | 57 ++++++++++++++++++++-
1 file changed, 55 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c
index 60863b825cc5..565913b8e656 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -576,11 +576,64 @@ void lspcon_set_infoframes(struct intel_encoder *encoder,
buf, ret);
}
+static bool _lspcon_read_avi_infoframe_enabled_mca(struct drm_dp_aux *aux)
+{
+ int ret;
+ u32 val = 0;
+ u16 reg = LSPCON_MCA_AVI_IF_CTRL;
+
+ ret = drm_dp_dpcd_read(aux, reg, &val, 1);
+ if (ret < 0) {
+ DRM_ERROR("DPCD read failed, address 0x%x\n", reg);
+ return false;
+ }
+
+ return val & LSPCON_MCA_AVI_IF_KICKOFF;
+}
+
+static bool _lspcon_read_avi_infoframe_enabled_parade(struct drm_dp_aux *aux)
+{
+ int ret;
+ u32 val = 0;
+ u16 reg = LSPCON_PARADE_AVI_IF_CTRL;
+
+ ret = drm_dp_dpcd_read(aux, reg, &val, 1);
+ if (ret < 0) {
+ DRM_ERROR("DPCD read failed, address 0x%x\n", reg);
+ return false;
+ }
+
+ return val & LSPCON_PARADE_AVI_IF_KICKOFF;
+}
+
u32 lspcon_infoframes_enabled(struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config)
{
- /* FIXME actually read this from the hw */
- return 0;
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+ struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder);
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ bool infoframes_enabled;
+ u32 val = 0;
+ u32 mask, tmp;
+
+ if (lspcon->vendor == LSPCON_VENDOR_MCA)
+ infoframes_enabled = _lspcon_read_avi_infoframe_enabled_mca(&intel_dp->aux);
+ else
+ infoframes_enabled = _lspcon_read_avi_infoframe_enabled_parade(&intel_dp->aux);
+
+ if (infoframes_enabled)
+ val |= VIDEO_DIP_ENABLE_AVI_HSW;
+
+ if (lspcon->hdr_supported) {
+ tmp = intel_de_read(dev_priv,
+ HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
+ mask = VIDEO_DIP_ENABLE_GMP_HSW;
+
+ if (tmp & mask)
+ val |= mask;
+ }
+
+ return val;
}
void lspcon_resume(struct intel_lspcon *lspcon)
--
2.26.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [Intel-gfx] [v6 07/11] drm/i915/display: Implement DRM infoframe read for LSPCON
2020-09-14 21:00 [Intel-gfx] [v6 00/11] Enable HDR on MCA LSPCON based Gen9 devices Uma Shankar
` (5 preceding siblings ...)
2020-09-14 21:00 ` [Intel-gfx] [v6 06/11] drm/i915/display: Implement infoframes readback for LSPCON Uma Shankar
@ 2020-09-14 21:00 ` Uma Shankar
2020-09-29 16:22 ` Ville Syrjälä
2020-09-14 21:00 ` [Intel-gfx] [v6 08/11] drm/i915/lspcon: Create separate infoframe_enabled helper Uma Shankar
` (6 subsequent siblings)
13 siblings, 1 reply; 31+ messages in thread
From: Uma Shankar @ 2020-09-14 21:00 UTC (permalink / raw)
To: intel-gfx
Implement Read back of HDR metadata infoframes i.e Dynamic Range
and Mastering Infoframe for LSPCON devices.
v2: Added proper bitmask of enabled infoframes as per Ville's
recommendation.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 10 ++++++++++
drivers/gpu/drm/i915/display/intel_lspcon.c | 6 +++++-
drivers/gpu/drm/i915/display/intel_lspcon.h | 4 ++++
3 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 1e40ed473fb9..02b0b5921bed 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -600,6 +600,16 @@ void lspcon_drm_write_infoframe(struct intel_encoder *encoder,
hsw_write_infoframe(encoder, crtc_state, type, frame, len);
}
+void lspcon_drm_read_infoframe(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ unsigned int type,
+ void *frame, ssize_t len)
+{
+ drm_dbg_kms(encoder->base.dev, "Read HDR metadata for lspcon\n");
+ /* It uses the legacy hsw implementation for the same */
+ hsw_read_infoframe(encoder, crtc_state, type, frame, len);
+}
+
static const u8 infoframe_type_to_idx[] = {
HDMI_PACKET_TYPE_GENERAL_CONTROL,
HDMI_PACKET_TYPE_GAMUT_METADATA,
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c
index 565913b8e656..ee77a5381cb5 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -501,7 +501,11 @@ void lspcon_read_infoframe(struct intel_encoder *encoder,
unsigned int type,
void *frame, ssize_t len)
{
- /* FIXME implement this */
+ /* FIXME implement for AVI Infoframe as well */
+ if (type == HDMI_PACKET_TYPE_GAMUT_METADATA)
+ lspcon_drm_read_infoframe(encoder, crtc_state,
+ HDMI_PACKET_TYPE_GAMUT_METADATA,
+ frame, VIDEO_DIP_DATA_SIZE);
}
/* HDMI HDR Colorspace Spec Definitions */
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h b/drivers/gpu/drm/i915/display/intel_lspcon.h
index 3fac05535731..1b9fb531128e 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.h
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.h
@@ -38,4 +38,8 @@ void lspcon_drm_write_infoframe(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
unsigned int type,
const void *frame, ssize_t len);
+void lspcon_drm_read_infoframe(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ unsigned int type,
+ void *frame, ssize_t len);
#endif /* __INTEL_LSPCON_H__ */
--
2.26.2
_______________________________________________
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^ permalink raw reply related [flat|nested] 31+ messages in thread
* [Intel-gfx] [v6 08/11] drm/i915/lspcon: Create separate infoframe_enabled helper
2020-09-14 21:00 [Intel-gfx] [v6 00/11] Enable HDR on MCA LSPCON based Gen9 devices Uma Shankar
` (6 preceding siblings ...)
2020-09-14 21:00 ` [Intel-gfx] [v6 07/11] drm/i915/display: Implement DRM infoframe read " Uma Shankar
@ 2020-09-14 21:00 ` Uma Shankar
2020-09-14 21:00 ` [Intel-gfx] [v6 09/11] drm/i915/lspcon: Do not send infoframes to non-HDMI sinks Uma Shankar
` (5 subsequent siblings)
13 siblings, 0 replies; 31+ messages in thread
From: Uma Shankar @ 2020-09-14 21:00 UTC (permalink / raw)
To: intel-gfx
Lspcon has Infoframes as well as DIP for HDR metadata(DRM Infoframe).
Create a separate mechanism for lspcon compared to HDMI in order to
address the same and ensure future scalability.
Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 10 +++++++---
drivers/gpu/drm/i915/display/intel_lspcon.c | 18 ++++++++++++++++++
drivers/gpu/drm/i915/display/intel_lspcon.h | 2 ++
3 files changed, 27 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 6af080542c96..1b601b04f62f 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4307,6 +4307,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+ struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
u32 temp, flags = 0;
/* XXX: DSI transcoder paranoia */
@@ -4392,9 +4393,12 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
pipe_config->fec_enable);
}
- pipe_config->infoframes.enable |=
- intel_hdmi_infoframes_enabled(encoder, pipe_config);
-
+ if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink)
+ pipe_config->infoframes.enable |=
+ intel_lspcon_infoframes_enabled(encoder, pipe_config);
+ else
+ pipe_config->infoframes.enable |=
+ intel_hdmi_infoframes_enabled(encoder, pipe_config);
break;
case TRANS_DDI_MODE_SELECT_DP_MST:
pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c
index ee77a5381cb5..5b2d96a80b49 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -30,6 +30,7 @@
#include "intel_display_types.h"
#include "intel_dp.h"
#include "intel_lspcon.h"
+#include "intel_hdmi.h"
/* LSPCON OUI Vendor ID(signatures) */
#define LSPCON_VENDOR_PARADE_OUI 0x001CF8
@@ -640,6 +641,23 @@ u32 lspcon_infoframes_enabled(struct intel_encoder *encoder,
return val;
}
+u32 intel_lspcon_infoframes_enabled(struct intel_encoder *encoder,
+ const struct intel_crtc_state *pipe_config)
+{
+ struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+ u32 val, enabled = 0;
+
+ val = dig_port->infoframes_enabled(encoder, pipe_config);
+
+ if (val & VIDEO_DIP_ENABLE_AVI_HSW)
+ enabled |= intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
+
+ if (val & VIDEO_DIP_ENABLE_GMP_HSW)
+ enabled |= intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
+
+ return enabled;
+}
+
void lspcon_resume(struct intel_lspcon *lspcon)
{
enum drm_lspcon_mode expected_mode;
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h b/drivers/gpu/drm/i915/display/intel_lspcon.h
index 1b9fb531128e..86305cc3a2d8 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.h
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.h
@@ -42,4 +42,6 @@ void lspcon_drm_read_infoframe(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
unsigned int type,
void *frame, ssize_t len);
+u32 intel_lspcon_infoframes_enabled(struct intel_encoder *encoder,
+ const struct intel_crtc_state *pipe_config);
#endif /* __INTEL_LSPCON_H__ */
--
2.26.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [Intel-gfx] [v6 09/11] drm/i915/lspcon: Do not send infoframes to non-HDMI sinks
2020-09-14 21:00 [Intel-gfx] [v6 00/11] Enable HDR on MCA LSPCON based Gen9 devices Uma Shankar
` (7 preceding siblings ...)
2020-09-14 21:00 ` [Intel-gfx] [v6 08/11] drm/i915/lspcon: Create separate infoframe_enabled helper Uma Shankar
@ 2020-09-14 21:00 ` Uma Shankar
2020-09-14 21:00 ` [Intel-gfx] [v6 10/11] drm/i915/lspcon: Do not send DRM " Uma Shankar
` (4 subsequent siblings)
13 siblings, 0 replies; 31+ messages in thread
From: Uma Shankar @ 2020-09-14 21:00 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Non-HDMI sinks shouldn't be sent infoframes. Check for that when
using LSPCON.
FIXME: How do we turn off infoframes once enabled? Do we even
have to?
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 10 ++++------
drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 7 ++++++-
3 files changed, 11 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 1b601b04f62f..8ce9bad4df91 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3581,19 +3581,17 @@ static void intel_ddi_pre_enable(struct intel_atomic_state *state,
intel_ddi_pre_enable_hdmi(state, encoder, crtc_state,
conn_state);
} else {
- struct intel_lspcon *lspcon =
- enc_to_intel_lspcon(encoder);
+ struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
intel_ddi_pre_enable_dp(state, encoder, crtc_state,
conn_state);
- if (lspcon->active) {
- struct intel_digital_port *dig_port =
- enc_to_dig_port(encoder);
+ /* FIXME precompute everything properly */
+ /* FIXME how do we turn infoframes off again? */
+ if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink)
dig_port->set_infoframes(encoder,
crtc_state->has_infoframe,
crtc_state, conn_state);
- }
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 5cf4e7a591e0..bb6b72bfd72d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1279,6 +1279,7 @@ struct intel_dp {
u8 sink_count;
bool link_mst;
bool link_trained;
+ bool has_hdmi_sink;
bool has_audio;
bool reset_link_params;
u8 dpcd[DP_RECEIVER_CAP_SIZE];
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 8a673d0d7051..60bf01a8b4ad 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6069,7 +6069,11 @@ intel_dp_set_edid(struct intel_dp *intel_dp)
edid = intel_dp_get_edid(intel_dp);
intel_connector->detect_edid = edid;
- intel_dp->has_audio = drm_detect_monitor_audio(edid);
+ if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
+ intel_dp->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
+ intel_dp->has_audio = drm_detect_monitor_audio(edid);
+ }
+
drm_dp_cec_set_edid(&intel_dp->aux, edid);
intel_dp->edid_quirks = drm_dp_get_edid_quirks(edid);
}
@@ -6083,6 +6087,7 @@ intel_dp_unset_edid(struct intel_dp *intel_dp)
kfree(intel_connector->detect_edid);
intel_connector->detect_edid = NULL;
+ intel_dp->has_hdmi_sink = false;
intel_dp->has_audio = false;
intel_dp->edid_quirks = 0;
}
--
2.26.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [Intel-gfx] [v6 10/11] drm/i915/lspcon: Do not send DRM infoframes to non-HDMI sinks
2020-09-14 21:00 [Intel-gfx] [v6 00/11] Enable HDR on MCA LSPCON based Gen9 devices Uma Shankar
` (8 preceding siblings ...)
2020-09-14 21:00 ` [Intel-gfx] [v6 09/11] drm/i915/lspcon: Do not send infoframes to non-HDMI sinks Uma Shankar
@ 2020-09-14 21:00 ` Uma Shankar
2020-09-14 21:00 ` [Intel-gfx] [v6 11/11] drm/i915/display: [NOT FOR MERGE] Reduce blanking to support 4k60@10bpp for LSPCON Uma Shankar
` (3 subsequent siblings)
13 siblings, 0 replies; 31+ messages in thread
From: Uma Shankar @ 2020-09-14 21:00 UTC (permalink / raw)
To: intel-gfx
Non-HDMI sinks shouldn't be sent Dynamic Range and Mastering infoframes.
Check for that when using LSPCON.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 8ce9bad4df91..81b3f4bdbe15 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3844,6 +3844,7 @@ static void intel_enable_ddi_dp(struct intel_atomic_state *state,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+ struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
enum port port = encoder->port;
if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
@@ -3851,7 +3852,14 @@ static void intel_enable_ddi_dp(struct intel_atomic_state *state,
intel_edp_backlight_on(crtc_state, conn_state);
intel_psr_enable(intel_dp, crtc_state, conn_state);
- intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
+
+ if (dig_port->lspcon.active) {
+ if (dig_port->dp.has_hdmi_sink)
+ intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
+ } else {
+ intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
+ }
+
intel_edp_drrs_enable(intel_dp, crtc_state);
if (crtc_state->has_audio)
--
2.26.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [Intel-gfx] [v6 11/11] drm/i915/display: [NOT FOR MERGE] Reduce blanking to support 4k60@10bpp for LSPCON
2020-09-14 21:00 [Intel-gfx] [v6 00/11] Enable HDR on MCA LSPCON based Gen9 devices Uma Shankar
` (9 preceding siblings ...)
2020-09-14 21:00 ` [Intel-gfx] [v6 10/11] drm/i915/lspcon: Do not send DRM " Uma Shankar
@ 2020-09-14 21:00 ` Uma Shankar
2020-09-14 21:39 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable HDR on MCA LSPCON based Gen9 devices (rev6) Patchwork
` (2 subsequent siblings)
13 siblings, 0 replies; 31+ messages in thread
From: Uma Shankar @ 2020-09-14 21:00 UTC (permalink / raw)
To: intel-gfx
Blanking needs to be reduced to incorporate DP and HDMI timing/link
bandwidth limitations for CEA modes (4k@60 at 10 bpp). DP can drive
17.28Gbs while 4k modes (VIC97 etc) at 10 bpp required 17.8 Gbps.
This will cause mode to blank out. Reduced Htotal by shortening the
back porch and front porch within permissible limits.
Note: This is for reference for userspace, not to be merged in kernel.
v2: This is marked as Not for merge and the responsibilty to program
these custom timings will be on userspace. This patch is just for
reference purposes. This is based on Ville's recommendation.
v3: updated commit message.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 60bf01a8b4ad..c7ee13cd54e5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -640,8 +640,10 @@ intel_dp_mode_valid(struct drm_connector *connector,
{
struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
struct intel_connector *intel_connector = to_intel_connector(connector);
+ struct intel_encoder *intel_encoder = intel_attached_encoder(intel_connector);
struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
struct drm_i915_private *dev_priv = to_i915(connector->dev);
+ struct intel_lspcon *lspcon = enc_to_intel_lspcon(intel_encoder);
int target_clock = mode->clock;
int max_rate, mode_rate, max_lanes, max_link_clock;
int max_dotclk;
@@ -663,6 +665,21 @@ intel_dp_mode_valid(struct drm_connector *connector,
target_clock = fixed_mode->clock;
}
+ /*
+ * Reducing Blanking to incorporate DP and HDMI timing/link bandwidth
+ * limitations for CEA modes (4k@60 at 10 bpp). DP can drive 17.28Gbs
+ * while 4k modes (VIC97 etc) at 10 bpp required 17.8 Gbps. This will
+ * cause mode to blank out. Reduced Htotal by shortening the back porch
+ * and front porch within permissible limits.
+ */
+ if (lspcon->active && lspcon->hdr_supported &&
+ mode->clock > 570000) {
+ mode->clock = 570000;
+ mode->htotal -= 180;
+ mode->hsync_start -= 72;
+ mode->hsync_end -= 72;
+ }
+
max_link_clock = intel_dp_max_link_rate(intel_dp);
max_lanes = intel_dp_max_lane_count(intel_dp);
--
2.26.2
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^ permalink raw reply related [flat|nested] 31+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable HDR on MCA LSPCON based Gen9 devices (rev6)
2020-09-14 21:00 [Intel-gfx] [v6 00/11] Enable HDR on MCA LSPCON based Gen9 devices Uma Shankar
` (10 preceding siblings ...)
2020-09-14 21:00 ` [Intel-gfx] [v6 11/11] drm/i915/display: [NOT FOR MERGE] Reduce blanking to support 4k60@10bpp for LSPCON Uma Shankar
@ 2020-09-14 21:39 ` Patchwork
2020-09-14 22:02 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-09-15 7:10 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
13 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2020-09-14 21:39 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-gfx
== Series Details ==
Series: Enable HDR on MCA LSPCON based Gen9 devices (rev6)
URL : https://patchwork.freedesktop.org/series/68081/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_reset.c:1311:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Enable HDR on MCA LSPCON based Gen9 devices (rev6)
2020-09-14 21:00 [Intel-gfx] [v6 00/11] Enable HDR on MCA LSPCON based Gen9 devices Uma Shankar
` (11 preceding siblings ...)
2020-09-14 21:39 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable HDR on MCA LSPCON based Gen9 devices (rev6) Patchwork
@ 2020-09-14 22:02 ` Patchwork
2020-09-15 7:10 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
13 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2020-09-14 22:02 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 9829 bytes --]
== Series Details ==
Series: Enable HDR on MCA LSPCON based Gen9 devices (rev6)
URL : https://patchwork.freedesktop.org/series/68081/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9008 -> Patchwork_18495
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/index.html
Known issues
------------
Here are the changes found in Patchwork_18495 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@execlists:
- fi-icl-y: [PASS][1] -> [INCOMPLETE][2] ([i915#2276])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/fi-icl-y/igt@i915_selftest@live@execlists.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/fi-icl-y/igt@i915_selftest@live@execlists.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7500u: [PASS][3] -> [DMESG-WARN][4] ([i915#2203])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-bsw-n3050: [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
- fi-bsw-kefka: [PASS][7] -> [DMESG-WARN][8] ([i915#1982])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-legacy:
- fi-icl-u2: [PASS][9] -> [DMESG-WARN][10] ([i915#1982])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cursor-legacy.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cursor-legacy.html
* igt@prime_vgem@basic-read:
- fi-tgl-y: [PASS][11] -> [DMESG-WARN][12] ([i915#402]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/fi-tgl-y/igt@prime_vgem@basic-read.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/fi-tgl-y/igt@prime_vgem@basic-read.html
#### Possible fixes ####
* {igt@core_hotunplug@unbind-rebind}:
- {fi-tgl-dsi}: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/fi-tgl-dsi/igt@core_hotunplug@unbind-rebind.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/fi-tgl-dsi/igt@core_hotunplug@unbind-rebind.html
* igt@gem_flink_basic@double-flink:
- fi-tgl-y: [DMESG-WARN][15] ([i915#402]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/fi-tgl-y/igt@gem_flink_basic@double-flink.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/fi-tgl-y/igt@gem_flink_basic@double-flink.html
* igt@i915_module_load@reload:
- fi-byt-j1900: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/fi-byt-j1900/igt@i915_module_load@reload.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/fi-byt-j1900/igt@i915_module_load@reload.html
- fi-tgl-u2: [DMESG-WARN][19] ([i915#1982] / [k.org#205379]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/fi-tgl-u2/igt@i915_module_load@reload.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/fi-tgl-u2/igt@i915_module_load@reload.html
* igt@kms_busy@basic@flip:
- fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/fi-kbl-x1275/igt@kms_busy@basic@flip.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/fi-kbl-x1275/igt@kms_busy@basic@flip.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-atomic:
- fi-icl-u2: [DMESG-WARN][23] ([i915#1982]) -> [PASS][24] +1 similar issue
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html
* igt@vgem_basic@unload:
- fi-skl-guc: [DMESG-WARN][25] ([i915#2203]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/fi-skl-guc/igt@vgem_basic@unload.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/fi-skl-guc/igt@vgem_basic@unload.html
- fi-kbl-x1275: [DMESG-WARN][27] ([i915#62] / [i915#92]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/fi-kbl-x1275/igt@vgem_basic@unload.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/fi-kbl-x1275/igt@vgem_basic@unload.html
#### Warnings ####
* igt@i915_pm_rpm@module-reload:
- fi-tgl-y: [DMESG-WARN][29] ([i915#1982] / [i915#2411]) -> [DMESG-WARN][30] ([i915#2411])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/fi-tgl-y/igt@i915_pm_rpm@module-reload.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/fi-tgl-y/igt@i915_pm_rpm@module-reload.html
- fi-kbl-x1275: [DMESG-FAIL][31] ([i915#62]) -> [SKIP][32] ([fdo#109271])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html
* igt@kms_force_connector_basic@force-connector-state:
- fi-kbl-x1275: [DMESG-WARN][33] ([i915#62] / [i915#92]) -> [DMESG-WARN][34] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/fi-kbl-x1275/igt@kms_force_connector_basic@force-connector-state.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/fi-kbl-x1275/igt@kms_force_connector_basic@force-connector-state.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- fi-kbl-x1275: [DMESG-WARN][35] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][36] ([i915#62] / [i915#92]) +6 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/fi-kbl-x1275/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/fi-kbl-x1275/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-kbl-x1275: [DMESG-WARN][37] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][38] ([i915#1982] / [i915#62] / [i915#92])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/fi-kbl-x1275/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/fi-kbl-x1275/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
[i915#2276]: https://gitlab.freedesktop.org/drm/intel/issues/2276
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
[k.org#205379]: https://bugzilla.kernel.org/show_bug.cgi?id=205379
Participating hosts (45 -> 39)
------------------------------
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_9008 -> Patchwork_18495
CI-20190529: 20190529
CI_DRM_9008: 14dc141acc195be5b1d0ffb563c5c0a277569715 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5784: 265f1d4a5a14998b98f963ee04d695cf3f3c2d3a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18495: 96a7b3e3f9cff60cd864c6c31deeb397a8499924 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
96a7b3e3f9cf drm/i915/display: [NOT FOR MERGE] Reduce blanking to support 4k60@10bpp for LSPCON
b8982b1dac67 drm/i915/lspcon: Do not send DRM infoframes to non-HDMI sinks
5d152c3103f9 drm/i915/lspcon: Do not send infoframes to non-HDMI sinks
70b72195dee1 drm/i915/lspcon: Create separate infoframe_enabled helper
013ce8f3b132 drm/i915/display: Implement DRM infoframe read for LSPCON
4de1b718b255 drm/i915/display: Implement infoframes readback for LSPCON
10b8afc89e50 drm/i915/display: Enable HDR for Parade based lspcon
8ebfeff403de drm/i915/display: Enable BT2020 for HDR on LSPCON devices
53accb8bdc37 drm/i915/display: Attach HDR property for capable Gen9 devices
dc9d043ad86b drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon
a7dffc50cee7 drm/i915/display: Add HDR Capability detection for LSPCON
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/index.html
[-- Attachment #1.2: Type: text/html, Size: 12830 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for Enable HDR on MCA LSPCON based Gen9 devices (rev6)
2020-09-14 21:00 [Intel-gfx] [v6 00/11] Enable HDR on MCA LSPCON based Gen9 devices Uma Shankar
` (12 preceding siblings ...)
2020-09-14 22:02 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-09-15 7:10 ` Patchwork
13 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2020-09-15 7:10 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 15147 bytes --]
== Series Details ==
Series: Enable HDR on MCA LSPCON based Gen9 devices (rev6)
URL : https://patchwork.freedesktop.org/series/68081/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9008_full -> Patchwork_18495_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_18495_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@core_hotunplug@hotrebind-lateclose}:
- shard-tglb: [DMESG-FAIL][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/shard-tglb5/igt@core_hotunplug@hotrebind-lateclose.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/shard-tglb6/igt@core_hotunplug@hotrebind-lateclose.html
Known issues
------------
Here are the changes found in Patchwork_18495_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_persistence@engines-mixed-process@rcs0:
- shard-apl: [PASS][3] -> [FAIL][4] ([i915#1635] / [i915#2374])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/shard-apl3/igt@gem_ctx_persistence@engines-mixed-process@rcs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/shard-apl7/igt@gem_ctx_persistence@engines-mixed-process@rcs0.html
* igt@gem_exec_reloc@basic-many-active@vecs0:
- shard-glk: [PASS][5] -> [FAIL][6] ([i915#2389])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/shard-glk8/igt@gem_exec_reloc@basic-many-active@vecs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/shard-glk1/igt@gem_exec_reloc@basic-many-active@vecs0.html
* igt@gem_exec_whisper@basic-fds-forked-all:
- shard-glk: [PASS][7] -> [DMESG-WARN][8] ([i915#118] / [i915#95])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/shard-glk5/igt@gem_exec_whisper@basic-fds-forked-all.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/shard-glk4/igt@gem_exec_whisper@basic-fds-forked-all.html
* igt@gem_mmap_offset@blt-coherency:
- shard-apl: [PASS][9] -> [FAIL][10] ([i915#1635])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/shard-apl1/igt@gem_mmap_offset@blt-coherency.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/shard-apl4/igt@gem_mmap_offset@blt-coherency.html
* igt@gem_workarounds@suspend-resume:
- shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([i915#180])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/shard-kbl1/igt@gem_workarounds@suspend-resume.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/shard-kbl7/igt@gem_workarounds@suspend-resume.html
* igt@kms_big_fb@x-tiled-8bpp-rotate-0:
- shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#1982])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/shard-kbl7/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/shard-kbl7/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html
* igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1:
- shard-skl: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) +9 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/shard-skl10/igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/shard-skl10/igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-skl: [PASS][17] -> [FAIL][18] ([i915#79])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/shard-skl8/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [PASS][19] -> [INCOMPLETE][20] ([i915#155] / [i915#180]) +2 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/shard-kbl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip@plain-flip-fb-recreate@c-edp1:
- shard-skl: [PASS][21] -> [FAIL][22] ([i915#2122])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/shard-skl4/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/shard-skl9/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html
* igt@kms_frontbuffer_tracking@fbc-stridechange:
- shard-iclb: [PASS][23] -> [DMESG-WARN][24] ([i915#1982])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-stridechange.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-stridechange.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-onoff:
- shard-tglb: [PASS][25] -> [DMESG-WARN][26] ([i915#1982]) +2 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-onoff.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-onoff.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][27] -> [DMESG-FAIL][28] ([fdo#108145] / [i915#1982])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][29] -> [FAIL][30] ([fdo#108145] / [i915#265])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_basic:
- shard-iclb: [PASS][31] -> [SKIP][32] ([fdo#109441]) +2 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/shard-iclb2/igt@kms_psr@psr2_basic.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/shard-iclb8/igt@kms_psr@psr2_basic.html
#### Possible fixes ####
* igt@gem_exec_schedule@semaphore-resolve:
- shard-skl: [DMESG-WARN][33] ([i915#1982]) -> [PASS][34] +7 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/shard-skl9/igt@gem_exec_schedule@semaphore-resolve.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/shard-skl8/igt@gem_exec_schedule@semaphore-resolve.html
* igt@gem_exec_suspend@basic-s3:
- shard-kbl: [INCOMPLETE][35] ([i915#155]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/shard-kbl6/igt@gem_exec_suspend@basic-s3.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/shard-kbl7/igt@gem_exec_suspend@basic-s3.html
* igt@gem_userptr_blits@sync-unmap-cycles:
- shard-skl: [TIMEOUT][37] ([i915#1958] / [i915#2424]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/shard-skl3/igt@gem_userptr_blits@sync-unmap-cycles.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/shard-skl7/igt@gem_userptr_blits@sync-unmap-cycles.html
* igt@gem_userptr_blits@unsync-unmap-cycles:
- shard-skl: [TIMEOUT][39] ([i915#1958]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/shard-skl6/igt@gem_userptr_blits@unsync-unmap-cycles.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/shard-skl1/igt@gem_userptr_blits@unsync-unmap-cycles.html
* igt@i915_pm_dc@dc5-psr:
- shard-skl: [INCOMPLETE][41] ([i915#198]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/shard-skl8/igt@i915_pm_dc@dc5-psr.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/shard-skl6/igt@i915_pm_dc@dc5-psr.html
* igt@i915_pm_sseu@full-enable:
- shard-glk: [FAIL][43] -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/shard-glk8/igt@i915_pm_sseu@full-enable.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/shard-glk3/igt@i915_pm_sseu@full-enable.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-0:
- shard-iclb: [DMESG-WARN][45] ([i915#1982]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/shard-iclb3/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/shard-iclb6/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic:
- shard-skl: [FAIL][47] ([i915#2346]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/shard-skl5/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/shard-skl8/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
* igt@kms_flip@2x-dpms-vs-vblank-race@ab-hdmi-a1-hdmi-a2:
- shard-glk: [DMESG-WARN][49] ([i915#1982]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/shard-glk6/igt@kms_flip@2x-dpms-vs-vblank-race@ab-hdmi-a1-hdmi-a2.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/shard-glk6/igt@kms_flip@2x-dpms-vs-vblank-race@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1:
- shard-skl: [FAIL][51] ([i915#2122]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/shard-skl3/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/shard-skl7/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
* igt@kms_flip@plain-flip-ts-check-interruptible@a-dp1:
- shard-kbl: [DMESG-WARN][53] ([i915#1982]) -> [PASS][54] +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/shard-kbl7/igt@kms_flip@plain-flip-ts-check-interruptible@a-dp1.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/shard-kbl6/igt@kms_flip@plain-flip-ts-check-interruptible@a-dp1.html
* igt@kms_frontbuffer_tracking@fbcpsr-shrfb-scaledprimary:
- shard-tglb: [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] +2 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-shrfb-scaledprimary.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-shrfb-scaledprimary.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-kbl: [DMESG-WARN][57] ([i915#180]) -> [PASS][58] +2 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/shard-kbl2/igt@kms_hdr@bpc-switch-suspend.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/shard-kbl3/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence:
- shard-skl: [FAIL][59] ([i915#53]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/shard-skl5/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/shard-skl1/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [FAIL][61] ([fdo#108145] / [i915#265]) -> [PASS][62] +2 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [SKIP][63] ([fdo#109441]) -> [PASS][64] +2 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/shard-iclb6/igt@kms_psr@psr2_cursor_mmap_cpu.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@perf@blocking:
- shard-skl: [FAIL][65] ([i915#1542]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9008/shard-skl9/igt@perf@blocking.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/shard-skl8/igt@perf@blocking.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2374]: https://gitlab.freedesktop.org/drm/intel/issues/2374
[i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389
[i915#2424]: https://gitlab.freedesktop.org/drm/intel/issues/2424
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#53]: https://gitlab.freedesktop.org/drm/intel/issues/53
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_9008 -> Patchwork_18495
CI-20190529: 20190529
CI_DRM_9008: 14dc141acc195be5b1d0ffb563c5c0a277569715 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5784: 265f1d4a5a14998b98f963ee04d695cf3f3c2d3a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18495: 96a7b3e3f9cff60cd864c6c31deeb397a8499924 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18495/index.html
[-- Attachment #1.2: Type: text/html, Size: 17843 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] [v6 02/11] drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon
2020-09-14 21:00 ` [Intel-gfx] [v6 02/11] drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon Uma Shankar
@ 2020-09-29 16:12 ` Ville Syrjälä
2020-10-05 21:25 ` Shankar, Uma
0 siblings, 1 reply; 31+ messages in thread
From: Ville Syrjälä @ 2020-09-29 16:12 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-gfx
On Tue, Sep 15, 2020 at 02:30:38AM +0530, Uma Shankar wrote:
> Gen9 hardware supports HDMI2.0 through LSPCON chips.
> Extending HDR support for MCA LSPCON based GEN9 devices.
>
> SOC will drive LSPCON as DP and send HDR metadata as standard
> DP SDP packets. LSPCON will be set to operate in PCON mode,
> will receive the metadata and create Dynamic Range and
> Mastering Infoframe (DRM packets) and send it to HDR capable
> HDMI sink devices.
>
> v2: Re-used hsw infoframe write implementation for HDR metadata
> for LSPCON as per Ville's suggestion.
>
> v3: Addressed Jani Nikula's review comments.
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_hdmi.c | 10 ++++++
> drivers/gpu/drm/i915/display/intel_lspcon.c | 37 +++++++++++++++------
> drivers/gpu/drm/i915/display/intel_lspcon.h | 5 ++-
> 3 files changed, 40 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 0978b0d8f4c6..1e40ed473fb9 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -590,6 +590,16 @@ static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
> return val & mask;
> }
>
> +void lspcon_drm_write_infoframe(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state,
> + unsigned int type,
> + const void *frame, ssize_t len)
> +{
> + drm_dbg_kms(encoder->base.dev, "Update HDR metadata for lspcon\n");
> + /* It uses the legacy hsw implementation for the same */
> + hsw_write_infoframe(encoder, crtc_state, type, frame, len);
> +}
This wrapper seems quite pointless.
> +
> static const u8 infoframe_type_to_idx[] = {
> HDMI_PACKET_TYPE_GENERAL_CONTROL,
> HDMI_PACKET_TYPE_GAMUT_METADATA,
> diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c
> index 8e8c7a02ab51..5e2d7ca1d20f 100644
> --- a/drivers/gpu/drm/i915/display/intel_lspcon.c
> +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
> @@ -461,27 +461,42 @@ void lspcon_write_infoframe(struct intel_encoder *encoder,
> unsigned int type,
> const void *frame, ssize_t len)
> {
> - bool ret;
> + bool ret = true;
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder);
>
> - /* LSPCON only needs AVI IF */
> - if (type != HDMI_INFOFRAME_TYPE_AVI)
> + /*
> + * Supporting HDR on MCA LSPCON
> + * Todo: Add support for Parade later
> + */
> + if (type == HDMI_PACKET_TYPE_GAMUT_METADATA &&
> + lspcon->vendor != LSPCON_VENDOR_MCA)
> return;
We shouldn't have the infoframe flagged as enabled if we
don't support it. So this check seems pointless, or there's
a bug somewhere else.
>
> - if (lspcon->vendor == LSPCON_VENDOR_MCA)
> - ret = _lspcon_write_avi_infoframe_mca(&intel_dp->aux,
> - frame, len);
> - else
> - ret = _lspcon_write_avi_infoframe_parade(&intel_dp->aux,
> - frame, len);
> + switch (type) {
> + case HDMI_INFOFRAME_TYPE_AVI:
> + if (lspcon->vendor == LSPCON_VENDOR_MCA)
> + ret = _lspcon_write_avi_infoframe_mca(&intel_dp->aux,
> + frame, len);
> + else
> + ret = _lspcon_write_avi_infoframe_parade(&intel_dp->aux,
> + frame, len);
> + break;
> + case HDMI_PACKET_TYPE_GAMUT_METADATA:
> + lspcon_drm_write_infoframe(encoder, crtc_state,
> + HDMI_PACKET_TYPE_GAMUT_METADATA,
> + frame, VIDEO_DIP_DATA_SIZE);
Why are we hardocoding the parameters here? Just pass them through?
> + break;
> + default:
> + return;
> + }
>
> if (!ret) {
> - DRM_ERROR("Failed to write AVI infoframes\n");
> + DRM_ERROR("Failed to write infoframes\n");
> return;
> }
>
> - DRM_DEBUG_DRIVER("AVI infoframes updated successfully\n");
> + DRM_DEBUG_DRIVER("Infoframes updated successfully\n");
That pointless debug should probably be just nuked.
> }
>
> void lspcon_read_infoframe(struct intel_encoder *encoder,
> diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h b/drivers/gpu/drm/i915/display/intel_lspcon.h
> index 1cffe8a42a08..3fac05535731 100644
> --- a/drivers/gpu/drm/i915/display/intel_lspcon.h
> +++ b/drivers/gpu/drm/i915/display/intel_lspcon.h
> @@ -34,5 +34,8 @@ u32 lspcon_infoframes_enabled(struct intel_encoder *encoder,
> const struct intel_crtc_state *pipe_config);
> void lspcon_ycbcr420_config(struct drm_connector *connector,
> struct intel_crtc_state *crtc_state);
> -
> +void lspcon_drm_write_infoframe(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state,
> + unsigned int type,
> + const void *frame, ssize_t len);
I think we ususally leave a blank line here.
> #endif /* __INTEL_LSPCON_H__ */
> --
> 2.26.2
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] [v6 03/11] drm/i915/display: Attach HDR property for capable Gen9 devices
2020-09-14 21:00 ` [Intel-gfx] [v6 03/11] drm/i915/display: Attach HDR property for capable Gen9 devices Uma Shankar
@ 2020-09-29 16:14 ` Ville Syrjälä
2020-10-05 21:32 ` Shankar, Uma
0 siblings, 1 reply; 31+ messages in thread
From: Ville Syrjälä @ 2020-09-29 16:14 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-gfx
On Tue, Sep 15, 2020 at 02:30:39AM +0530, Uma Shankar wrote:
> Attach HDR property for Gen9 devices with MCA LSPCON
> chips.
>
> v2: Cleaned HDR property attachment logic based on capability
> as per Jani Nikula's suggestion.
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_lspcon.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c
> index 5e2d7ca1d20f..fd05210f4405 100644
> --- a/drivers/gpu/drm/i915/display/intel_lspcon.c
> +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
> @@ -626,6 +626,11 @@ bool lspcon_init(struct intel_digital_port *dig_port)
>
> lspcon_detect_hdr_capability(lspcon);
>
> + if (lspcon->hdr_supported)
> + drm_object_attach_property(&connector->base,
> + connector->dev->mode_config.hdr_output_metadata_property,
> + 0);
Hmm. This hdr capability detection is going to cause us extra grief
when looking at Kai-Heng's patch to defer lspcon detection until
hotplug time. Not quite sure what to do about that though.
> +
> connector->ycbcr_420_allowed = true;
> lspcon->active = true;
> DRM_DEBUG_KMS("Success: LSPCON init\n");
> --
> 2.26.2
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] [v6 04/11] drm/i915/display: Enable BT2020 for HDR on LSPCON devices
2020-09-14 21:00 ` [Intel-gfx] [v6 04/11] drm/i915/display: Enable BT2020 for HDR on LSPCON devices Uma Shankar
@ 2020-09-29 16:18 ` Ville Syrjälä
2020-10-05 21:33 ` Shankar, Uma
0 siblings, 1 reply; 31+ messages in thread
From: Ville Syrjälä @ 2020-09-29 16:18 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-gfx
On Tue, Sep 15, 2020 at 02:30:40AM +0530, Uma Shankar wrote:
> Enable Colorspace as BT2020 if driving HDR content.Sending Colorimetry
> data for HDR using AVI infoframe. LSPCON firmware expects this and though
> SOC drives DP, for HDMI panel AVI infoframe is sent to the LSPCON device
> which transfers the same to HDMI sink.
>
> v2: Dropped state managed in drm core as per Jani Nikula's suggestion.
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_lspcon.c | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c
> index fd05210f4405..b0ca494f1110 100644
> --- a/drivers/gpu/drm/i915/display/intel_lspcon.c
> +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
> @@ -507,6 +507,11 @@ void lspcon_read_infoframe(struct intel_encoder *encoder,
> /* FIXME implement this */
> }
>
> +/* HDMI HDR Colorspace Spec Definitions */
> +#define NORMAL_COLORIMETRY_MASK 0x3
> +#define EXTENDED_COLORIMETRY_MASK 0x7
> +#define HDMI_COLORIMETRY_BT2020_YCC ((3 << 0) | (6 << 2) | (0 << 5))
> +
> void lspcon_set_infoframes(struct intel_encoder *encoder,
> bool enable,
> const struct intel_crtc_state *crtc_state,
> @@ -551,6 +556,19 @@ void lspcon_set_infoframes(struct intel_encoder *encoder,
> HDMI_QUANTIZATION_RANGE_LIMITED :
> HDMI_QUANTIZATION_RANGE_FULL);
>
> + /*
> + * Set BT2020 colorspace if driving HDR data
> + * ToDo: Make this generic and expose all colorspaces for lspcon
> + */
> + if (lspcon->active && lspcon->hdr_supported) {
> + frame.avi.colorimetry =
> + HDMI_COLORIMETRY_BT2020_YCC &
> + NORMAL_COLORIMETRY_MASK;
> + frame.avi.extended_colorimetry =
> + (HDMI_COLORIMETRY_BT2020_YCC >> 2) &
> + EXTENDED_COLORIMETRY_MASK;
> + }
drm_hdmi_avi_infoframe_colorspace().
Also pls try to match intel_hdmi_compute_avi_infoframe() as
closesly as possible if we can't just outright reuse it. That
will make it easier to spot differences between the two.
> +
> ret = hdmi_infoframe_pack(&frame, buf, sizeof(buf));
> if (ret < 0) {
> DRM_ERROR("Failed to pack AVI IF\n");
> --
> 2.26.2
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] [v6 05/11] drm/i915/display: Enable HDR for Parade based lspcon
2020-09-14 21:00 ` [Intel-gfx] [v6 05/11] drm/i915/display: Enable HDR for Parade based lspcon Uma Shankar
@ 2020-09-29 16:19 ` Ville Syrjälä
2020-10-05 21:33 ` Shankar, Uma
0 siblings, 1 reply; 31+ messages in thread
From: Ville Syrjälä @ 2020-09-29 16:19 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-gfx, Vipin Anand
On Tue, Sep 15, 2020 at 02:30:41AM +0530, Uma Shankar wrote:
> Enable HDR for LSPCON based on Parade along with MCA.
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Vipin Anand <vipin.anand@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_lspcon.c | 19 ++++++++-----------
> 1 file changed, 8 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c
> index b0ca494f1110..60863b825cc5 100644
> --- a/drivers/gpu/drm/i915/display/intel_lspcon.c
> +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
> @@ -36,6 +36,7 @@
> #define LSPCON_VENDOR_MCA_OUI 0x0060AD
>
> #define DPCD_MCA_LSPCON_HDR_STATUS 0x70003
> +#define DPCD_PARADE_LSPCON_HDR_STATUS 0x00511
>
> /* AUX addresses to write MCA AVI IF */
> #define LSPCON_MCA_AVI_IF_WRITE_OFFSET 0x5C0
> @@ -112,16 +113,20 @@ static void lspcon_detect_hdr_capability(struct intel_lspcon *lspcon)
> container_of(lspcon, struct intel_digital_port, lspcon);
> struct drm_device *dev = intel_dig_port->base.base.dev;
> struct intel_dp *dp = lspcon_to_intel_dp(lspcon);
> + u32 lspcon_hdr_status_reg;
> u8 hdr_caps;
> int ret;
>
> - /* Enable HDR for MCA based LSPCON devices */
> if (lspcon->vendor == LSPCON_VENDOR_MCA)
> - ret = drm_dp_dpcd_read(&dp->aux, DPCD_MCA_LSPCON_HDR_STATUS,
> - &hdr_caps, 1);
> + lspcon_hdr_status_reg = DPCD_MCA_LSPCON_HDR_STATUS;
> + else if (lspcon->vendor == LSPCON_VENDOR_PARADE)
> + lspcon_hdr_status_reg = DPCD_PARADE_LSPCON_HDR_STATUS;
> else
> return;
That could be small helper function.
>
> + ret = drm_dp_dpcd_read(&dp->aux, lspcon_hdr_status_reg,
> + &hdr_caps, 1);
> +
> if (ret < 0) {
> drm_dbg_kms(dev, "hdr capability detection failed\n");
> lspcon->hdr_supported = false;
> @@ -465,14 +470,6 @@ void lspcon_write_infoframe(struct intel_encoder *encoder,
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder);
>
> - /*
> - * Supporting HDR on MCA LSPCON
> - * Todo: Add support for Parade later
> - */
> - if (type == HDMI_PACKET_TYPE_GAMUT_METADATA &&
> - lspcon->vendor != LSPCON_VENDOR_MCA)
> - return;
> -
> switch (type) {
> case HDMI_INFOFRAME_TYPE_AVI:
> if (lspcon->vendor == LSPCON_VENDOR_MCA)
> --
> 2.26.2
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] [v6 06/11] drm/i915/display: Implement infoframes readback for LSPCON
2020-09-14 21:00 ` [Intel-gfx] [v6 06/11] drm/i915/display: Implement infoframes readback for LSPCON Uma Shankar
@ 2020-09-29 16:20 ` Ville Syrjälä
2020-10-05 21:36 ` Shankar, Uma
0 siblings, 1 reply; 31+ messages in thread
From: Ville Syrjälä @ 2020-09-29 16:20 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-gfx
On Tue, Sep 15, 2020 at 02:30:42AM +0530, Uma Shankar wrote:
> Implemented Infoframes enabled readback for LSPCON devices.
> This will help align the implementation with state readback
> infrastructure.
>
> v2: Added proper bitmask of enabled infoframes as per Ville's
> recommendation.
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_lspcon.c | 57 ++++++++++++++++++++-
> 1 file changed, 55 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c
> index 60863b825cc5..565913b8e656 100644
> --- a/drivers/gpu/drm/i915/display/intel_lspcon.c
> +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
> @@ -576,11 +576,64 @@ void lspcon_set_infoframes(struct intel_encoder *encoder,
> buf, ret);
> }
>
> +static bool _lspcon_read_avi_infoframe_enabled_mca(struct drm_dp_aux *aux)
> +{
> + int ret;
> + u32 val = 0;
> + u16 reg = LSPCON_MCA_AVI_IF_CTRL;
> +
> + ret = drm_dp_dpcd_read(aux, reg, &val, 1);
> + if (ret < 0) {
> + DRM_ERROR("DPCD read failed, address 0x%x\n", reg);
> + return false;
> + }
> +
> + return val & LSPCON_MCA_AVI_IF_KICKOFF;
> +}
> +
> +static bool _lspcon_read_avi_infoframe_enabled_parade(struct drm_dp_aux *aux)
> +{
> + int ret;
> + u32 val = 0;
> + u16 reg = LSPCON_PARADE_AVI_IF_CTRL;
> +
> + ret = drm_dp_dpcd_read(aux, reg, &val, 1);
> + if (ret < 0) {
> + DRM_ERROR("DPCD read failed, address 0x%x\n", reg);
> + return false;
> + }
> +
> + return val & LSPCON_PARADE_AVI_IF_KICKOFF;
> +}
> +
> u32 lspcon_infoframes_enabled(struct intel_encoder *encoder,
> const struct intel_crtc_state *pipe_config)
> {
> - /* FIXME actually read this from the hw */
> - return 0;
> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> + struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder);
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + bool infoframes_enabled;
> + u32 val = 0;
> + u32 mask, tmp;
> +
> + if (lspcon->vendor == LSPCON_VENDOR_MCA)
> + infoframes_enabled = _lspcon_read_avi_infoframe_enabled_mca(&intel_dp->aux);
> + else
> + infoframes_enabled = _lspcon_read_avi_infoframe_enabled_parade(&intel_dp->aux);
> +
> + if (infoframes_enabled)
> + val |= VIDEO_DIP_ENABLE_AVI_HSW;
Still not a fan of abusing the HSW specific reg values here.
> +
> + if (lspcon->hdr_supported) {
> + tmp = intel_de_read(dev_priv,
> + HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
> + mask = VIDEO_DIP_ENABLE_GMP_HSW;
> +
> + if (tmp & mask)
> + val |= mask;
> + }
> +
> + return val;
> }
>
> void lspcon_resume(struct intel_lspcon *lspcon)
> --
> 2.26.2
--
Ville Syrjälä
Intel
_______________________________________________
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^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] [v6 07/11] drm/i915/display: Implement DRM infoframe read for LSPCON
2020-09-14 21:00 ` [Intel-gfx] [v6 07/11] drm/i915/display: Implement DRM infoframe read " Uma Shankar
@ 2020-09-29 16:22 ` Ville Syrjälä
2020-10-05 21:37 ` Shankar, Uma
0 siblings, 1 reply; 31+ messages in thread
From: Ville Syrjälä @ 2020-09-29 16:22 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-gfx
On Tue, Sep 15, 2020 at 02:30:43AM +0530, Uma Shankar wrote:
> Implement Read back of HDR metadata infoframes i.e Dynamic Range
> and Mastering Infoframe for LSPCON devices.
>
> v2: Added proper bitmask of enabled infoframes as per Ville's
> recommendation.
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_hdmi.c | 10 ++++++++++
> drivers/gpu/drm/i915/display/intel_lspcon.c | 6 +++++-
> drivers/gpu/drm/i915/display/intel_lspcon.h | 4 ++++
> 3 files changed, 19 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 1e40ed473fb9..02b0b5921bed 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -600,6 +600,16 @@ void lspcon_drm_write_infoframe(struct intel_encoder *encoder,
> hsw_write_infoframe(encoder, crtc_state, type, frame, len);
> }
>
> +void lspcon_drm_read_infoframe(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state,
> + unsigned int type,
> + void *frame, ssize_t len)
> +{
> + drm_dbg_kms(encoder->base.dev, "Read HDR metadata for lspcon\n");
> + /* It uses the legacy hsw implementation for the same */
> + hsw_read_infoframe(encoder, crtc_state, type, frame, len);
> +}
Another pointless wrapper.
> +
> static const u8 infoframe_type_to_idx[] = {
> HDMI_PACKET_TYPE_GENERAL_CONTROL,
> HDMI_PACKET_TYPE_GAMUT_METADATA,
> diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c
> index 565913b8e656..ee77a5381cb5 100644
> --- a/drivers/gpu/drm/i915/display/intel_lspcon.c
> +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
> @@ -501,7 +501,11 @@ void lspcon_read_infoframe(struct intel_encoder *encoder,
> unsigned int type,
> void *frame, ssize_t len)
> {
> - /* FIXME implement this */
> + /* FIXME implement for AVI Infoframe as well */
> + if (type == HDMI_PACKET_TYPE_GAMUT_METADATA)
> + lspcon_drm_read_infoframe(encoder, crtc_state,
> + HDMI_PACKET_TYPE_GAMUT_METADATA,
> + frame, VIDEO_DIP_DATA_SIZE);
Again I'd just pass the params through.
> }
>
> /* HDMI HDR Colorspace Spec Definitions */
> diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h b/drivers/gpu/drm/i915/display/intel_lspcon.h
> index 3fac05535731..1b9fb531128e 100644
> --- a/drivers/gpu/drm/i915/display/intel_lspcon.h
> +++ b/drivers/gpu/drm/i915/display/intel_lspcon.h
> @@ -38,4 +38,8 @@ void lspcon_drm_write_infoframe(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state,
> unsigned int type,
> const void *frame, ssize_t len);
> +void lspcon_drm_read_infoframe(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state,
> + unsigned int type,
> + void *frame, ssize_t len);
> #endif /* __INTEL_LSPCON_H__ */
> --
> 2.26.2
--
Ville Syrjälä
Intel
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^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] [v6 02/11] drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon
2020-09-29 16:12 ` Ville Syrjälä
@ 2020-10-05 21:25 ` Shankar, Uma
0 siblings, 0 replies; 31+ messages in thread
From: Shankar, Uma @ 2020-10-05 21:25 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Tuesday, September 29, 2020 9:42 PM
> To: Shankar, Uma <uma.shankar@intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [v6 02/11] drm/i915/display: Enable HDR on gen9 devices with MCA
> Lspcon
>
> On Tue, Sep 15, 2020 at 02:30:38AM +0530, Uma Shankar wrote:
> > Gen9 hardware supports HDMI2.0 through LSPCON chips.
> > Extending HDR support for MCA LSPCON based GEN9 devices.
> >
> > SOC will drive LSPCON as DP and send HDR metadata as standard DP SDP
> > packets. LSPCON will be set to operate in PCON mode, will receive the
> > metadata and create Dynamic Range and Mastering Infoframe (DRM
> > packets) and send it to HDR capable HDMI sink devices.
> >
> > v2: Re-used hsw infoframe write implementation for HDR metadata for
> > LSPCON as per Ville's suggestion.
> >
> > v3: Addressed Jani Nikula's review comments.
> >
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_hdmi.c | 10 ++++++
> > drivers/gpu/drm/i915/display/intel_lspcon.c | 37
> > +++++++++++++++------ drivers/gpu/drm/i915/display/intel_lspcon.h |
> > 5 ++-
> > 3 files changed, 40 insertions(+), 12 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> > b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > index 0978b0d8f4c6..1e40ed473fb9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > @@ -590,6 +590,16 @@ static u32 hsw_infoframes_enabled(struct
> intel_encoder *encoder,
> > return val & mask;
> > }
> >
> > +void lspcon_drm_write_infoframe(struct intel_encoder *encoder,
> > + const struct intel_crtc_state *crtc_state,
> > + unsigned int type,
> > + const void *frame, ssize_t len)
> > +{
> > + drm_dbg_kms(encoder->base.dev, "Update HDR metadata for lspcon\n");
> > + /* It uses the legacy hsw implementation for the same */
> > + hsw_write_infoframe(encoder, crtc_state, type, frame, len); }
>
> This wrapper seems quite pointless.
Hmm yeah, will drop this.
> > +
> > static const u8 infoframe_type_to_idx[] = {
> > HDMI_PACKET_TYPE_GENERAL_CONTROL,
> > HDMI_PACKET_TYPE_GAMUT_METADATA,
> > diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c
> > b/drivers/gpu/drm/i915/display/intel_lspcon.c
> > index 8e8c7a02ab51..5e2d7ca1d20f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lspcon.c
> > +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
> > @@ -461,27 +461,42 @@ void lspcon_write_infoframe(struct intel_encoder
> *encoder,
> > unsigned int type,
> > const void *frame, ssize_t len) {
> > - bool ret;
> > + bool ret = true;
> > struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder);
> >
> > - /* LSPCON only needs AVI IF */
> > - if (type != HDMI_INFOFRAME_TYPE_AVI)
> > + /*
> > + * Supporting HDR on MCA LSPCON
> > + * Todo: Add support for Parade later
> > + */
> > + if (type == HDMI_PACKET_TYPE_GAMUT_METADATA &&
> > + lspcon->vendor != LSPCON_VENDOR_MCA)
> > return;
>
> We shouldn't have the infoframe flagged as enabled if we don't support it. So
> this check seems pointless, or there's a bug somewhere else.
Sure, will drop this check. It's not required.
> >
> > - if (lspcon->vendor == LSPCON_VENDOR_MCA)
> > - ret = _lspcon_write_avi_infoframe_mca(&intel_dp->aux,
> > - frame, len);
> > - else
> > - ret = _lspcon_write_avi_infoframe_parade(&intel_dp->aux,
> > - frame, len);
> > + switch (type) {
> > + case HDMI_INFOFRAME_TYPE_AVI:
> > + if (lspcon->vendor == LSPCON_VENDOR_MCA)
> > + ret = _lspcon_write_avi_infoframe_mca(&intel_dp->aux,
> > + frame, len);
> > + else
> > + ret = _lspcon_write_avi_infoframe_parade(&intel_dp-
> >aux,
> > + frame, len);
> > + break;
> > + case HDMI_PACKET_TYPE_GAMUT_METADATA:
> > + lspcon_drm_write_infoframe(encoder, crtc_state,
> > +
> HDMI_PACKET_TYPE_GAMUT_METADATA,
> > + frame, VIDEO_DIP_DATA_SIZE);
>
> Why are we hardocoding the parameters here? Just pass them through?
Ok, will rectify this.
> > + break;
> > + default:
> > + return;
> > + }
> >
> > if (!ret) {
> > - DRM_ERROR("Failed to write AVI infoframes\n");
> > + DRM_ERROR("Failed to write infoframes\n");
> > return;
> > }
> >
> > - DRM_DEBUG_DRIVER("AVI infoframes updated successfully\n");
> > + DRM_DEBUG_DRIVER("Infoframes updated successfully\n");
>
> That pointless debug should probably be just nuked.
Ok, will drop it.
> > }
> >
> > void lspcon_read_infoframe(struct intel_encoder *encoder, diff --git
> > a/drivers/gpu/drm/i915/display/intel_lspcon.h
> > b/drivers/gpu/drm/i915/display/intel_lspcon.h
> > index 1cffe8a42a08..3fac05535731 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lspcon.h
> > +++ b/drivers/gpu/drm/i915/display/intel_lspcon.h
> > @@ -34,5 +34,8 @@ u32 lspcon_infoframes_enabled(struct intel_encoder
> *encoder,
> > const struct intel_crtc_state *pipe_config); void
> > lspcon_ycbcr420_config(struct drm_connector *connector,
> > struct intel_crtc_state *crtc_state);
> > -
> > +void lspcon_drm_write_infoframe(struct intel_encoder *encoder,
> > + const struct intel_crtc_state *crtc_state,
> > + unsigned int type,
> > + const void *frame, ssize_t len);
>
> I think we ususally leave a blank line here.
Will do it.
> > #endif /* __INTEL_LSPCON_H__ */
> > --
> > 2.26.2
>
> --
> Ville Syrjälä
> Intel
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^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] [v6 03/11] drm/i915/display: Attach HDR property for capable Gen9 devices
2020-09-29 16:14 ` Ville Syrjälä
@ 2020-10-05 21:32 ` Shankar, Uma
2020-10-06 9:06 ` Ville Syrjälä
0 siblings, 1 reply; 31+ messages in thread
From: Shankar, Uma @ 2020-10-05 21:32 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Tuesday, September 29, 2020 9:44 PM
> To: Shankar, Uma <uma.shankar@intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [v6 03/11] drm/i915/display: Attach HDR property for capable Gen9
> devices
>
> On Tue, Sep 15, 2020 at 02:30:39AM +0530, Uma Shankar wrote:
> > Attach HDR property for Gen9 devices with MCA LSPCON chips.
> >
> > v2: Cleaned HDR property attachment logic based on capability as per
> > Jani Nikula's suggestion.
> >
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_lspcon.c | 5 +++++
> > 1 file changed, 5 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c
> > b/drivers/gpu/drm/i915/display/intel_lspcon.c
> > index 5e2d7ca1d20f..fd05210f4405 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lspcon.c
> > +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
> > @@ -626,6 +626,11 @@ bool lspcon_init(struct intel_digital_port
> > *dig_port)
> >
> > lspcon_detect_hdr_capability(lspcon);
> >
> > + if (lspcon->hdr_supported)
> > + drm_object_attach_property(&connector->base,
> > + connector->dev-
> >mode_config.hdr_output_metadata_property,
> > + 0);
>
> Hmm. This hdr capability detection is going to cause us extra grief when looking
> at Kai-Heng's patch to defer lspcon detection until hotplug time. Not quite sure
> what to do about that though.
Yeah Ville, saw your comments and with Kai's change merge, I am thinking how to attach
this dynamically.
Can we just assume that Lspcon will support HDR as is the case in Gen9. We can just attach this
unconditionally at init if Lspcon is exposed from VBT. Will this be acceptable or Any better ideas ?
> > +
> > connector->ycbcr_420_allowed = true;
> > lspcon->active = true;
> > DRM_DEBUG_KMS("Success: LSPCON init\n");
> > --
> > 2.26.2
>
> --
> Ville Syrjälä
> Intel
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^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] [v6 04/11] drm/i915/display: Enable BT2020 for HDR on LSPCON devices
2020-09-29 16:18 ` Ville Syrjälä
@ 2020-10-05 21:33 ` Shankar, Uma
0 siblings, 0 replies; 31+ messages in thread
From: Shankar, Uma @ 2020-10-05 21:33 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Tuesday, September 29, 2020 9:48 PM
> To: Shankar, Uma <uma.shankar@intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [v6 04/11] drm/i915/display: Enable BT2020 for HDR on LSPCON
> devices
>
> On Tue, Sep 15, 2020 at 02:30:40AM +0530, Uma Shankar wrote:
> > Enable Colorspace as BT2020 if driving HDR content.Sending Colorimetry
> > data for HDR using AVI infoframe. LSPCON firmware expects this and
> > though SOC drives DP, for HDMI panel AVI infoframe is sent to the
> > LSPCON device which transfers the same to HDMI sink.
> >
> > v2: Dropped state managed in drm core as per Jani Nikula's suggestion.
> >
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_lspcon.c | 18 ++++++++++++++++++
> > 1 file changed, 18 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c
> > b/drivers/gpu/drm/i915/display/intel_lspcon.c
> > index fd05210f4405..b0ca494f1110 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lspcon.c
> > +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
> > @@ -507,6 +507,11 @@ void lspcon_read_infoframe(struct intel_encoder
> *encoder,
> > /* FIXME implement this */
> > }
> >
> > +/* HDMI HDR Colorspace Spec Definitions */
> > +#define NORMAL_COLORIMETRY_MASK 0x3
> > +#define EXTENDED_COLORIMETRY_MASK 0x7
> > +#define HDMI_COLORIMETRY_BT2020_YCC ((3 << 0) | (6 << 2) | (0 << 5))
> > +
> > void lspcon_set_infoframes(struct intel_encoder *encoder,
> > bool enable,
> > const struct intel_crtc_state *crtc_state, @@ -551,6
> +556,19 @@
> > void lspcon_set_infoframes(struct intel_encoder *encoder,
> > HDMI_QUANTIZATION_RANGE_LIMITED
> :
> > HDMI_QUANTIZATION_RANGE_FULL);
> >
> > + /*
> > + * Set BT2020 colorspace if driving HDR data
> > + * ToDo: Make this generic and expose all colorspaces for lspcon
> > + */
> > + if (lspcon->active && lspcon->hdr_supported) {
> > + frame.avi.colorimetry =
> > + HDMI_COLORIMETRY_BT2020_YCC &
> > + NORMAL_COLORIMETRY_MASK;
> > + frame.avi.extended_colorimetry =
> > + (HDMI_COLORIMETRY_BT2020_YCC >> 2) &
> > + EXTENDED_COLORIMETRY_MASK;
> > + }
>
> drm_hdmi_avi_infoframe_colorspace().
>
> Also pls try to match intel_hdmi_compute_avi_infoframe() as closesly as possible
> if we can't just outright reuse it. That will make it easier to spot differences
> between the two.
Sure, will rectify it.
> > +
> > ret = hdmi_infoframe_pack(&frame, buf, sizeof(buf));
> > if (ret < 0) {
> > DRM_ERROR("Failed to pack AVI IF\n");
> > --
> > 2.26.2
>
> --
> Ville Syrjälä
> Intel
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^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] [v6 05/11] drm/i915/display: Enable HDR for Parade based lspcon
2020-09-29 16:19 ` Ville Syrjälä
@ 2020-10-05 21:33 ` Shankar, Uma
0 siblings, 0 replies; 31+ messages in thread
From: Shankar, Uma @ 2020-10-05 21:33 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, Anand, Vipin
> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Tuesday, September 29, 2020 9:49 PM
> To: Shankar, Uma <uma.shankar@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Anand, Vipin <vipin.anand@intel.com>
> Subject: Re: [v6 05/11] drm/i915/display: Enable HDR for Parade based lspcon
>
> On Tue, Sep 15, 2020 at 02:30:41AM +0530, Uma Shankar wrote:
> > Enable HDR for LSPCON based on Parade along with MCA.
> >
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > Signed-off-by: Vipin Anand <vipin.anand@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_lspcon.c | 19 ++++++++-----------
> > 1 file changed, 8 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c
> > b/drivers/gpu/drm/i915/display/intel_lspcon.c
> > index b0ca494f1110..60863b825cc5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lspcon.c
> > +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
> > @@ -36,6 +36,7 @@
> > #define LSPCON_VENDOR_MCA_OUI 0x0060AD
> >
> > #define DPCD_MCA_LSPCON_HDR_STATUS 0x70003
> > +#define DPCD_PARADE_LSPCON_HDR_STATUS 0x00511
> >
> > /* AUX addresses to write MCA AVI IF */ #define
> > LSPCON_MCA_AVI_IF_WRITE_OFFSET 0x5C0 @@ -112,16 +113,20 @@ static
> void
> > lspcon_detect_hdr_capability(struct intel_lspcon *lspcon)
> > container_of(lspcon, struct intel_digital_port, lspcon);
> > struct drm_device *dev = intel_dig_port->base.base.dev;
> > struct intel_dp *dp = lspcon_to_intel_dp(lspcon);
> > + u32 lspcon_hdr_status_reg;
> > u8 hdr_caps;
> > int ret;
> >
> > - /* Enable HDR for MCA based LSPCON devices */
> > if (lspcon->vendor == LSPCON_VENDOR_MCA)
> > - ret = drm_dp_dpcd_read(&dp->aux,
> DPCD_MCA_LSPCON_HDR_STATUS,
> > - &hdr_caps, 1);
> > + lspcon_hdr_status_reg = DPCD_MCA_LSPCON_HDR_STATUS;
> > + else if (lspcon->vendor == LSPCON_VENDOR_PARADE)
> > + lspcon_hdr_status_reg = DPCD_PARADE_LSPCON_HDR_STATUS;
> > else
> > return;
>
> That could be small helper function.
Ok, will add the same.
> >
> > + ret = drm_dp_dpcd_read(&dp->aux, lspcon_hdr_status_reg,
> > + &hdr_caps, 1);
> > +
> > if (ret < 0) {
> > drm_dbg_kms(dev, "hdr capability detection failed\n");
> > lspcon->hdr_supported = false;
> > @@ -465,14 +470,6 @@ void lspcon_write_infoframe(struct intel_encoder
> *encoder,
> > struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder);
> >
> > - /*
> > - * Supporting HDR on MCA LSPCON
> > - * Todo: Add support for Parade later
> > - */
> > - if (type == HDMI_PACKET_TYPE_GAMUT_METADATA &&
> > - lspcon->vendor != LSPCON_VENDOR_MCA)
> > - return;
> > -
> > switch (type) {
> > case HDMI_INFOFRAME_TYPE_AVI:
> > if (lspcon->vendor == LSPCON_VENDOR_MCA)
> > --
> > 2.26.2
>
> --
> Ville Syrjälä
> Intel
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] [v6 06/11] drm/i915/display: Implement infoframes readback for LSPCON
2020-09-29 16:20 ` Ville Syrjälä
@ 2020-10-05 21:36 ` Shankar, Uma
2020-10-06 9:09 ` Ville Syrjälä
0 siblings, 1 reply; 31+ messages in thread
From: Shankar, Uma @ 2020-10-05 21:36 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Tuesday, September 29, 2020 9:51 PM
> To: Shankar, Uma <uma.shankar@intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [v6 06/11] drm/i915/display: Implement infoframes readback for
> LSPCON
>
> On Tue, Sep 15, 2020 at 02:30:42AM +0530, Uma Shankar wrote:
> > Implemented Infoframes enabled readback for LSPCON devices.
> > This will help align the implementation with state readback
> > infrastructure.
> >
> > v2: Added proper bitmask of enabled infoframes as per Ville's
> > recommendation.
> >
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_lspcon.c | 57
> > ++++++++++++++++++++-
> > 1 file changed, 55 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c
> > b/drivers/gpu/drm/i915/display/intel_lspcon.c
> > index 60863b825cc5..565913b8e656 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lspcon.c
> > +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
> > @@ -576,11 +576,64 @@ void lspcon_set_infoframes(struct intel_encoder
> *encoder,
> > buf, ret);
> > }
> >
> > +static bool _lspcon_read_avi_infoframe_enabled_mca(struct drm_dp_aux
> > +*aux) {
> > + int ret;
> > + u32 val = 0;
> > + u16 reg = LSPCON_MCA_AVI_IF_CTRL;
> > +
> > + ret = drm_dp_dpcd_read(aux, reg, &val, 1);
> > + if (ret < 0) {
> > + DRM_ERROR("DPCD read failed, address 0x%x\n", reg);
> > + return false;
> > + }
> > +
> > + return val & LSPCON_MCA_AVI_IF_KICKOFF; }
> > +
> > +static bool _lspcon_read_avi_infoframe_enabled_parade(struct
> > +drm_dp_aux *aux) {
> > + int ret;
> > + u32 val = 0;
> > + u16 reg = LSPCON_PARADE_AVI_IF_CTRL;
> > +
> > + ret = drm_dp_dpcd_read(aux, reg, &val, 1);
> > + if (ret < 0) {
> > + DRM_ERROR("DPCD read failed, address 0x%x\n", reg);
> > + return false;
> > + }
> > +
> > + return val & LSPCON_PARADE_AVI_IF_KICKOFF; }
> > +
> > u32 lspcon_infoframes_enabled(struct intel_encoder *encoder,
> > const struct intel_crtc_state *pipe_config) {
> > - /* FIXME actually read this from the hw */
> > - return 0;
> > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > + struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder);
> > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > + bool infoframes_enabled;
> > + u32 val = 0;
> > + u32 mask, tmp;
> > +
> > + if (lspcon->vendor == LSPCON_VENDOR_MCA)
> > + infoframes_enabled =
> _lspcon_read_avi_infoframe_enabled_mca(&intel_dp->aux);
> > + else
> > + infoframes_enabled =
> > +_lspcon_read_avi_infoframe_enabled_parade(&intel_dp->aux);
> > +
> > + if (infoframes_enabled)
> > + val |= VIDEO_DIP_ENABLE_AVI_HSW;
>
> Still not a fan of abusing the HSW specific reg values here.
I just kept it so that rest of the infrastructure can be re-used easily. So the AVI and GMP
bit fields will get re-used and will not require any separate handling.
> > +
> > + if (lspcon->hdr_supported) {
> > + tmp = intel_de_read(dev_priv,
> > + HSW_TVIDEO_DIP_CTL(pipe_config-
> >cpu_transcoder));
> > + mask = VIDEO_DIP_ENABLE_GMP_HSW;
> > +
> > + if (tmp & mask)
> > + val |= mask;
> > + }
> > +
> > + return val;
> > }
> >
> > void lspcon_resume(struct intel_lspcon *lspcon)
> > --
> > 2.26.2
>
> --
> Ville Syrjälä
> Intel
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] [v6 07/11] drm/i915/display: Implement DRM infoframe read for LSPCON
2020-09-29 16:22 ` Ville Syrjälä
@ 2020-10-05 21:37 ` Shankar, Uma
0 siblings, 0 replies; 31+ messages in thread
From: Shankar, Uma @ 2020-10-05 21:37 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Tuesday, September 29, 2020 9:53 PM
> To: Shankar, Uma <uma.shankar@intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [v6 07/11] drm/i915/display: Implement DRM infoframe read for
> LSPCON
>
> On Tue, Sep 15, 2020 at 02:30:43AM +0530, Uma Shankar wrote:
> > Implement Read back of HDR metadata infoframes i.e Dynamic Range and
> > Mastering Infoframe for LSPCON devices.
> >
> > v2: Added proper bitmask of enabled infoframes as per Ville's
> > recommendation.
> >
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_hdmi.c | 10 ++++++++++
> > drivers/gpu/drm/i915/display/intel_lspcon.c | 6 +++++-
> > drivers/gpu/drm/i915/display/intel_lspcon.h | 4 ++++
> > 3 files changed, 19 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> > b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > index 1e40ed473fb9..02b0b5921bed 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > @@ -600,6 +600,16 @@ void lspcon_drm_write_infoframe(struct
> intel_encoder *encoder,
> > hsw_write_infoframe(encoder, crtc_state, type, frame, len); }
> >
> > +void lspcon_drm_read_infoframe(struct intel_encoder *encoder,
> > + const struct intel_crtc_state *crtc_state,
> > + unsigned int type,
> > + void *frame, ssize_t len)
> > +{
> > + drm_dbg_kms(encoder->base.dev, "Read HDR metadata for lspcon\n");
> > + /* It uses the legacy hsw implementation for the same */
> > + hsw_read_infoframe(encoder, crtc_state, type, frame, len); }
>
> Another pointless wrapper.
Sure, will drop this.
> > +
> > static const u8 infoframe_type_to_idx[] = {
> > HDMI_PACKET_TYPE_GENERAL_CONTROL,
> > HDMI_PACKET_TYPE_GAMUT_METADATA,
> > diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c
> > b/drivers/gpu/drm/i915/display/intel_lspcon.c
> > index 565913b8e656..ee77a5381cb5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lspcon.c
> > +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
> > @@ -501,7 +501,11 @@ void lspcon_read_infoframe(struct intel_encoder
> *encoder,
> > unsigned int type,
> > void *frame, ssize_t len)
> > {
> > - /* FIXME implement this */
> > + /* FIXME implement for AVI Infoframe as well */
> > + if (type == HDMI_PACKET_TYPE_GAMUT_METADATA)
> > + lspcon_drm_read_infoframe(encoder, crtc_state,
> > +
> HDMI_PACKET_TYPE_GAMUT_METADATA,
> > + frame, VIDEO_DIP_DATA_SIZE);
>
> Again I'd just pass the params through.
Will do the same.
> > }
> >
> > /* HDMI HDR Colorspace Spec Definitions */ diff --git
> > a/drivers/gpu/drm/i915/display/intel_lspcon.h
> > b/drivers/gpu/drm/i915/display/intel_lspcon.h
> > index 3fac05535731..1b9fb531128e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lspcon.h
> > +++ b/drivers/gpu/drm/i915/display/intel_lspcon.h
> > @@ -38,4 +38,8 @@ void lspcon_drm_write_infoframe(struct intel_encoder
> *encoder,
> > const struct intel_crtc_state *crtc_state,
> > unsigned int type,
> > const void *frame, ssize_t len);
> > +void lspcon_drm_read_infoframe(struct intel_encoder *encoder,
> > + const struct intel_crtc_state *crtc_state,
> > + unsigned int type,
> > + void *frame, ssize_t len);
> > #endif /* __INTEL_LSPCON_H__ */
> > --
> > 2.26.2
>
> --
> Ville Syrjälä
> Intel
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] [v6 03/11] drm/i915/display: Attach HDR property for capable Gen9 devices
2020-10-05 21:32 ` Shankar, Uma
@ 2020-10-06 9:06 ` Ville Syrjälä
2020-10-06 12:26 ` Shankar, Uma
0 siblings, 1 reply; 31+ messages in thread
From: Ville Syrjälä @ 2020-10-06 9:06 UTC (permalink / raw)
To: Shankar, Uma; +Cc: intel-gfx
On Mon, Oct 05, 2020 at 09:32:22PM +0000, Shankar, Uma wrote:
>
>
> > -----Original Message-----
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Sent: Tuesday, September 29, 2020 9:44 PM
> > To: Shankar, Uma <uma.shankar@intel.com>
> > Cc: intel-gfx@lists.freedesktop.org
> > Subject: Re: [v6 03/11] drm/i915/display: Attach HDR property for capable Gen9
> > devices
> >
> > On Tue, Sep 15, 2020 at 02:30:39AM +0530, Uma Shankar wrote:
> > > Attach HDR property for Gen9 devices with MCA LSPCON chips.
> > >
> > > v2: Cleaned HDR property attachment logic based on capability as per
> > > Jani Nikula's suggestion.
> > >
> > > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_lspcon.c | 5 +++++
> > > 1 file changed, 5 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c
> > > b/drivers/gpu/drm/i915/display/intel_lspcon.c
> > > index 5e2d7ca1d20f..fd05210f4405 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_lspcon.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
> > > @@ -626,6 +626,11 @@ bool lspcon_init(struct intel_digital_port
> > > *dig_port)
> > >
> > > lspcon_detect_hdr_capability(lspcon);
> > >
> > > + if (lspcon->hdr_supported)
> > > + drm_object_attach_property(&connector->base,
> > > + connector->dev-
> > >mode_config.hdr_output_metadata_property,
> > > + 0);
> >
> > Hmm. This hdr capability detection is going to cause us extra grief when looking
> > at Kai-Heng's patch to defer lspcon detection until hotplug time. Not quite sure
> > what to do about that though.
>
> Yeah Ville, saw your comments and with Kai's change merge, I am thinking how to attach
> this dynamically.
Not allowed.
>
> Can we just assume that Lspcon will support HDR as is the case in Gen9. We can just attach this
> unconditionally at init if Lspcon is exposed from VBT. Will this be acceptable or Any better ideas ?
I have no idea what these lspcon chips supports since -ENODOCS.
The only idea I have is to attempt an early probe for this, and if it
fails on some chips due to hpd not being asserted so be it.
>
> > > +
> > > connector->ycbcr_420_allowed = true;
> > > lspcon->active = true;
> > > DRM_DEBUG_KMS("Success: LSPCON init\n");
> > > --
> > > 2.26.2
> >
> > --
> > Ville Syrjälä
> > Intel
--
Ville Syrjälä
Intel
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^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] [v6 06/11] drm/i915/display: Implement infoframes readback for LSPCON
2020-10-05 21:36 ` Shankar, Uma
@ 2020-10-06 9:09 ` Ville Syrjälä
2020-10-06 12:27 ` Shankar, Uma
0 siblings, 1 reply; 31+ messages in thread
From: Ville Syrjälä @ 2020-10-06 9:09 UTC (permalink / raw)
To: Shankar, Uma; +Cc: intel-gfx
On Mon, Oct 05, 2020 at 09:36:35PM +0000, Shankar, Uma wrote:
>
>
> > -----Original Message-----
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Sent: Tuesday, September 29, 2020 9:51 PM
> > To: Shankar, Uma <uma.shankar@intel.com>
> > Cc: intel-gfx@lists.freedesktop.org
> > Subject: Re: [v6 06/11] drm/i915/display: Implement infoframes readback for
> > LSPCON
> >
> > On Tue, Sep 15, 2020 at 02:30:42AM +0530, Uma Shankar wrote:
> > > Implemented Infoframes enabled readback for LSPCON devices.
> > > This will help align the implementation with state readback
> > > infrastructure.
> > >
> > > v2: Added proper bitmask of enabled infoframes as per Ville's
> > > recommendation.
> > >
> > > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_lspcon.c | 57
> > > ++++++++++++++++++++-
> > > 1 file changed, 55 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c
> > > b/drivers/gpu/drm/i915/display/intel_lspcon.c
> > > index 60863b825cc5..565913b8e656 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_lspcon.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
> > > @@ -576,11 +576,64 @@ void lspcon_set_infoframes(struct intel_encoder
> > *encoder,
> > > buf, ret);
> > > }
> > >
> > > +static bool _lspcon_read_avi_infoframe_enabled_mca(struct drm_dp_aux
> > > +*aux) {
> > > + int ret;
> > > + u32 val = 0;
> > > + u16 reg = LSPCON_MCA_AVI_IF_CTRL;
> > > +
> > > + ret = drm_dp_dpcd_read(aux, reg, &val, 1);
> > > + if (ret < 0) {
> > > + DRM_ERROR("DPCD read failed, address 0x%x\n", reg);
> > > + return false;
> > > + }
> > > +
> > > + return val & LSPCON_MCA_AVI_IF_KICKOFF; }
> > > +
> > > +static bool _lspcon_read_avi_infoframe_enabled_parade(struct
> > > +drm_dp_aux *aux) {
> > > + int ret;
> > > + u32 val = 0;
> > > + u16 reg = LSPCON_PARADE_AVI_IF_CTRL;
> > > +
> > > + ret = drm_dp_dpcd_read(aux, reg, &val, 1);
> > > + if (ret < 0) {
> > > + DRM_ERROR("DPCD read failed, address 0x%x\n", reg);
> > > + return false;
> > > + }
> > > +
> > > + return val & LSPCON_PARADE_AVI_IF_KICKOFF; }
> > > +
> > > u32 lspcon_infoframes_enabled(struct intel_encoder *encoder,
> > > const struct intel_crtc_state *pipe_config) {
> > > - /* FIXME actually read this from the hw */
> > > - return 0;
> > > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > > + struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder);
> > > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > > + bool infoframes_enabled;
> > > + u32 val = 0;
> > > + u32 mask, tmp;
> > > +
> > > + if (lspcon->vendor == LSPCON_VENDOR_MCA)
> > > + infoframes_enabled =
> > _lspcon_read_avi_infoframe_enabled_mca(&intel_dp->aux);
> > > + else
> > > + infoframes_enabled =
> > > +_lspcon_read_avi_infoframe_enabled_parade(&intel_dp->aux);
> > > +
> > > + if (infoframes_enabled)
> > > + val |= VIDEO_DIP_ENABLE_AVI_HSW;
> >
> > Still not a fan of abusing the HSW specific reg values here.
>
> I just kept it so that rest of the infrastructure can be re-used easily. So the AVI and GMP
> bit fields will get re-used and will not require any separate handling.
Using the abstract infoframe types wouldn't prevent that.
>
> > > +
> > > + if (lspcon->hdr_supported) {
> > > + tmp = intel_de_read(dev_priv,
> > > + HSW_TVIDEO_DIP_CTL(pipe_config-
> > >cpu_transcoder));
> > > + mask = VIDEO_DIP_ENABLE_GMP_HSW;
> > > +
> > > + if (tmp & mask)
> > > + val |= mask;
> > > + }
> > > +
> > > + return val;
> > > }
> > >
> > > void lspcon_resume(struct intel_lspcon *lspcon)
> > > --
> > > 2.26.2
> >
> > --
> > Ville Syrjälä
> > Intel
--
Ville Syrjälä
Intel
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^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] [v6 03/11] drm/i915/display: Attach HDR property for capable Gen9 devices
2020-10-06 9:06 ` Ville Syrjälä
@ 2020-10-06 12:26 ` Shankar, Uma
0 siblings, 0 replies; 31+ messages in thread
From: Shankar, Uma @ 2020-10-06 12:26 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Tuesday, October 6, 2020 2:36 PM
> To: Shankar, Uma <uma.shankar@intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [v6 03/11] drm/i915/display: Attach HDR property for capable Gen9
> devices
>
> On Mon, Oct 05, 2020 at 09:32:22PM +0000, Shankar, Uma wrote:
> >
> >
> > > -----Original Message-----
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Sent: Tuesday, September 29, 2020 9:44 PM
> > > To: Shankar, Uma <uma.shankar@intel.com>
> > > Cc: intel-gfx@lists.freedesktop.org
> > > Subject: Re: [v6 03/11] drm/i915/display: Attach HDR property for
> > > capable Gen9 devices
> > >
> > > On Tue, Sep 15, 2020 at 02:30:39AM +0530, Uma Shankar wrote:
> > > > Attach HDR property for Gen9 devices with MCA LSPCON chips.
> > > >
> > > > v2: Cleaned HDR property attachment logic based on capability as
> > > > per Jani Nikula's suggestion.
> > > >
> > > > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_lspcon.c | 5 +++++
> > > > 1 file changed, 5 insertions(+)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c
> > > > b/drivers/gpu/drm/i915/display/intel_lspcon.c
> > > > index 5e2d7ca1d20f..fd05210f4405 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_lspcon.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
> > > > @@ -626,6 +626,11 @@ bool lspcon_init(struct intel_digital_port
> > > > *dig_port)
> > > >
> > > > lspcon_detect_hdr_capability(lspcon);
> > > >
> > > > + if (lspcon->hdr_supported)
> > > > + drm_object_attach_property(&connector->base,
> > > > + connector->dev-
> > > >mode_config.hdr_output_metadata_property,
> > > > + 0);
> > >
> > > Hmm. This hdr capability detection is going to cause us extra grief
> > > when looking at Kai-Heng's patch to defer lspcon detection until
> > > hotplug time. Not quite sure what to do about that though.
> >
> > Yeah Ville, saw your comments and with Kai's change merge, I am
> > thinking how to attach this dynamically.
>
> Not allowed.
>
> >
> > Can we just assume that Lspcon will support HDR as is the case in
> > Gen9. We can just attach this unconditionally at init if Lspcon is exposed from
> VBT. Will this be acceptable or Any better ideas ?
>
> I have no idea what these lspcon chips supports since -ENODOCS.
>
> The only idea I have is to attempt an early probe for this, and if it fails on some
> chips due to hpd not being asserted so be it.
Hmm, may be we can check for detection here and based on that enable HDR. If its
not detected on any particular chip, let it not get enabled. I feel this can be a good
WA as most of the devices seem to detect it fine. I will float the next version with this
approach.
Thanks Ville.
> >
> > > > +
> > > > connector->ycbcr_420_allowed = true;
> > > > lspcon->active = true;
> > > > DRM_DEBUG_KMS("Success: LSPCON init\n");
> > > > --
> > > > 2.26.2
> > >
> > > --
> > > Ville Syrjälä
> > > Intel
>
> --
> Ville Syrjälä
> Intel
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Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] [v6 06/11] drm/i915/display: Implement infoframes readback for LSPCON
2020-10-06 9:09 ` Ville Syrjälä
@ 2020-10-06 12:27 ` Shankar, Uma
0 siblings, 0 replies; 31+ messages in thread
From: Shankar, Uma @ 2020-10-06 12:27 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Tuesday, October 6, 2020 2:39 PM
> To: Shankar, Uma <uma.shankar@intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [v6 06/11] drm/i915/display: Implement infoframes readback for
> LSPCON
>
> On Mon, Oct 05, 2020 at 09:36:35PM +0000, Shankar, Uma wrote:
> >
> >
> > > -----Original Message-----
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Sent: Tuesday, September 29, 2020 9:51 PM
> > > To: Shankar, Uma <uma.shankar@intel.com>
> > > Cc: intel-gfx@lists.freedesktop.org
> > > Subject: Re: [v6 06/11] drm/i915/display: Implement infoframes
> > > readback for LSPCON
> > >
> > > On Tue, Sep 15, 2020 at 02:30:42AM +0530, Uma Shankar wrote:
> > > > Implemented Infoframes enabled readback for LSPCON devices.
> > > > This will help align the implementation with state readback
> > > > infrastructure.
> > > >
> > > > v2: Added proper bitmask of enabled infoframes as per Ville's
> > > > recommendation.
> > > >
> > > > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_lspcon.c | 57
> > > > ++++++++++++++++++++-
> > > > 1 file changed, 55 insertions(+), 2 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c
> > > > b/drivers/gpu/drm/i915/display/intel_lspcon.c
> > > > index 60863b825cc5..565913b8e656 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_lspcon.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
> > > > @@ -576,11 +576,64 @@ void lspcon_set_infoframes(struct
> > > > intel_encoder
> > > *encoder,
> > > > buf, ret);
> > > > }
> > > >
> > > > +static bool _lspcon_read_avi_infoframe_enabled_mca(struct
> > > > +drm_dp_aux
> > > > +*aux) {
> > > > + int ret;
> > > > + u32 val = 0;
> > > > + u16 reg = LSPCON_MCA_AVI_IF_CTRL;
> > > > +
> > > > + ret = drm_dp_dpcd_read(aux, reg, &val, 1);
> > > > + if (ret < 0) {
> > > > + DRM_ERROR("DPCD read failed, address 0x%x\n", reg);
> > > > + return false;
> > > > + }
> > > > +
> > > > + return val & LSPCON_MCA_AVI_IF_KICKOFF; }
> > > > +
> > > > +static bool _lspcon_read_avi_infoframe_enabled_parade(struct
> > > > +drm_dp_aux *aux) {
> > > > + int ret;
> > > > + u32 val = 0;
> > > > + u16 reg = LSPCON_PARADE_AVI_IF_CTRL;
> > > > +
> > > > + ret = drm_dp_dpcd_read(aux, reg, &val, 1);
> > > > + if (ret < 0) {
> > > > + DRM_ERROR("DPCD read failed, address 0x%x\n", reg);
> > > > + return false;
> > > > + }
> > > > +
> > > > + return val & LSPCON_PARADE_AVI_IF_KICKOFF; }
> > > > +
> > > > u32 lspcon_infoframes_enabled(struct intel_encoder *encoder,
> > > > const struct intel_crtc_state *pipe_config) {
> > > > - /* FIXME actually read this from the hw */
> > > > - return 0;
> > > > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > > > + struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder);
> > > > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > > > + bool infoframes_enabled;
> > > > + u32 val = 0;
> > > > + u32 mask, tmp;
> > > > +
> > > > + if (lspcon->vendor == LSPCON_VENDOR_MCA)
> > > > + infoframes_enabled =
> > > _lspcon_read_avi_infoframe_enabled_mca(&intel_dp->aux);
> > > > + else
> > > > + infoframes_enabled =
> > > > +_lspcon_read_avi_infoframe_enabled_parade(&intel_dp->aux);
> > > > +
> > > > + if (infoframes_enabled)
> > > > + val |= VIDEO_DIP_ENABLE_AVI_HSW;
> > >
> > > Still not a fan of abusing the HSW specific reg values here.
> >
> > I just kept it so that rest of the infrastructure can be re-used
> > easily. So the AVI and GMP bit fields will get re-used and will not require any
> separate handling.
>
> Using the abstract infoframe types wouldn't prevent that.
Ok, would remove the HSW specific bits.
> >
> > > > +
> > > > + if (lspcon->hdr_supported) {
> > > > + tmp = intel_de_read(dev_priv,
> > > > + HSW_TVIDEO_DIP_CTL(pipe_config-
> > > >cpu_transcoder));
> > > > + mask = VIDEO_DIP_ENABLE_GMP_HSW;
> > > > +
> > > > + if (tmp & mask)
> > > > + val |= mask;
> > > > + }
> > > > +
> > > > + return val;
> > > > }
> > > >
> > > > void lspcon_resume(struct intel_lspcon *lspcon)
> > > > --
> > > > 2.26.2
> > >
> > > --
> > > Ville Syrjälä
> > > Intel
>
> --
> Ville Syrjälä
> Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
end of thread, other threads:[~2020-10-06 12:27 UTC | newest]
Thread overview: 31+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-09-14 21:00 [Intel-gfx] [v6 00/11] Enable HDR on MCA LSPCON based Gen9 devices Uma Shankar
2020-09-14 21:00 ` [Intel-gfx] [v6 01/11] drm/i915/display: Add HDR Capability detection for LSPCON Uma Shankar
2020-09-14 21:00 ` [Intel-gfx] [v6 02/11] drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon Uma Shankar
2020-09-29 16:12 ` Ville Syrjälä
2020-10-05 21:25 ` Shankar, Uma
2020-09-14 21:00 ` [Intel-gfx] [v6 03/11] drm/i915/display: Attach HDR property for capable Gen9 devices Uma Shankar
2020-09-29 16:14 ` Ville Syrjälä
2020-10-05 21:32 ` Shankar, Uma
2020-10-06 9:06 ` Ville Syrjälä
2020-10-06 12:26 ` Shankar, Uma
2020-09-14 21:00 ` [Intel-gfx] [v6 04/11] drm/i915/display: Enable BT2020 for HDR on LSPCON devices Uma Shankar
2020-09-29 16:18 ` Ville Syrjälä
2020-10-05 21:33 ` Shankar, Uma
2020-09-14 21:00 ` [Intel-gfx] [v6 05/11] drm/i915/display: Enable HDR for Parade based lspcon Uma Shankar
2020-09-29 16:19 ` Ville Syrjälä
2020-10-05 21:33 ` Shankar, Uma
2020-09-14 21:00 ` [Intel-gfx] [v6 06/11] drm/i915/display: Implement infoframes readback for LSPCON Uma Shankar
2020-09-29 16:20 ` Ville Syrjälä
2020-10-05 21:36 ` Shankar, Uma
2020-10-06 9:09 ` Ville Syrjälä
2020-10-06 12:27 ` Shankar, Uma
2020-09-14 21:00 ` [Intel-gfx] [v6 07/11] drm/i915/display: Implement DRM infoframe read " Uma Shankar
2020-09-29 16:22 ` Ville Syrjälä
2020-10-05 21:37 ` Shankar, Uma
2020-09-14 21:00 ` [Intel-gfx] [v6 08/11] drm/i915/lspcon: Create separate infoframe_enabled helper Uma Shankar
2020-09-14 21:00 ` [Intel-gfx] [v6 09/11] drm/i915/lspcon: Do not send infoframes to non-HDMI sinks Uma Shankar
2020-09-14 21:00 ` [Intel-gfx] [v6 10/11] drm/i915/lspcon: Do not send DRM " Uma Shankar
2020-09-14 21:00 ` [Intel-gfx] [v6 11/11] drm/i915/display: [NOT FOR MERGE] Reduce blanking to support 4k60@10bpp for LSPCON Uma Shankar
2020-09-14 21:39 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable HDR on MCA LSPCON based Gen9 devices (rev6) Patchwork
2020-09-14 22:02 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-09-15 7:10 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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