[PATCH] KVM: arm64: Do not flush memslot if FWB is supported

[PATCH] KVM: arm64: Do not flush memslot if FWB is supported

[Alexandru Elisei]

As a result of a KVM_SET_USER_MEMORY_REGION ioctl, KVM flushes the
dcache for the memslot being changed to ensure a consistent view of memory
between the host and the guest: the host runs with caches enabled, and
it is possible for the data written by the hypervisor to still be in the
caches, but the guest is running with stage 1 disabled, meaning data
accesses are to Device-nGnRnE memory, bypassing the caches entirely.

Flushing the dcache is not necessary when KVM enables FWB, because it
forces the guest to uses cacheable memory accesses.

The current behaviour does not change, as the dcache flush helpers execute
the cache operation only if FWB is not enabled, but walking the stage 2
table is avoided.

Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
---
 arch/arm64/kvm/mmu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c
index 9a636b8064f1..c29105c6e975 100644
--- a/arch/arm64/kvm/mmu.c
+++ b/arch/arm64/kvm/mmu.c
@@ -2537,7 +2537,7 @@ int kvm_arch_prepare_memory_region(struct kvm *kvm,
 	spin_lock(&kvm->mmu_lock);
 	if (ret)
 		unmap_stage2_range(&kvm->arch.mmu, mem->guest_phys_addr, mem->memory_size);
-	else
+	else if (!cpus_have_final_cap(ARM64_HAS_STAGE2_FWB))
 		stage2_flush_memslot(kvm, memslot);
 	spin_unlock(&kvm->mmu_lock);
 out:
-- 
2.28.0

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[PATCH] KVM: arm64: Do not flush memslot if FWB is supported

[Alexandru Elisei]

As a result of a KVM_SET_USER_MEMORY_REGION ioctl, KVM flushes the
dcache for the memslot being changed to ensure a consistent view of memory
between the host and the guest: the host runs with caches enabled, and
it is possible for the data written by the hypervisor to still be in the
caches, but the guest is running with stage 1 disabled, meaning data
accesses are to Device-nGnRnE memory, bypassing the caches entirely.

Flushing the dcache is not necessary when KVM enables FWB, because it
forces the guest to uses cacheable memory accesses.

The current behaviour does not change, as the dcache flush helpers execute
the cache operation only if FWB is not enabled, but walking the stage 2
table is avoided.

Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
---
 arch/arm64/kvm/mmu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c
index 9a636b8064f1..c29105c6e975 100644
--- a/arch/arm64/kvm/mmu.c
+++ b/arch/arm64/kvm/mmu.c
@@ -2537,7 +2537,7 @@ int kvm_arch_prepare_memory_region(struct kvm *kvm,
 	spin_lock(&kvm->mmu_lock);
 	if (ret)
 		unmap_stage2_range(&kvm->arch.mmu, mem->guest_phys_addr, mem->memory_size);
-	else
+	else if (!cpus_have_final_cap(ARM64_HAS_STAGE2_FWB))
 		stage2_flush_memslot(kvm, memslot);
 	spin_unlock(&kvm->mmu_lock);
 out:
-- 
2.28.0


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Re: [PATCH] KVM: arm64: Do not flush memslot if FWB is supported

[Marc Zyngier]

On Tue, 15 Sep 2020 18:04:42 +0100, Alexandru Elisei wrote:
> As a result of a KVM_SET_USER_MEMORY_REGION ioctl, KVM flushes the
> dcache for the memslot being changed to ensure a consistent view of memory
> between the host and the guest: the host runs with caches enabled, and
> it is possible for the data written by the hypervisor to still be in the
> caches, but the guest is running with stage 1 disabled, meaning data
> accesses are to Device-nGnRnE memory, bypassing the caches entirely.
> 
> [...]

Applied to next, thanks!

[1/1] KVM: arm64: Do not flush memslot if FWB is supported
      commit: ada329e6b5b406f33fae665e62caff7814409906

Cheers,

	M.
-- 
Without deviation from the norm, progress is not possible.


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kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm

Re: [PATCH] KVM: arm64: Do not flush memslot if FWB is supported

[Marc Zyngier]

On Tue, 15 Sep 2020 18:04:42 +0100, Alexandru Elisei wrote:
> As a result of a KVM_SET_USER_MEMORY_REGION ioctl, KVM flushes the
> dcache for the memslot being changed to ensure a consistent view of memory
> between the host and the guest: the host runs with caches enabled, and
> it is possible for the data written by the hypervisor to still be in the
> caches, but the guest is running with stage 1 disabled, meaning data
> accesses are to Device-nGnRnE memory, bypassing the caches entirely.
> 
> [...]

Applied to next, thanks!

[1/1] KVM: arm64: Do not flush memslot if FWB is supported
      commit: ada329e6b5b406f33fae665e62caff7814409906

Cheers,

	M.
-- 
Without deviation from the norm, progress is not possible.



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