* [Intel-gfx] [PATCH 1/2] drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch
@ 2020-09-16 2:44 José Roberto de Souza
2020-09-16 2:44 ` [Intel-gfx] [PATCH 2/2] drm/i915/display: Check PSR parameter and flag only in state compute phase José Roberto de Souza
2020-09-16 3:25 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch Patchwork
0 siblings, 2 replies; 4+ messages in thread
From: José Roberto de Souza @ 2020-09-16 2:44 UTC (permalink / raw)
To: intel-gfx
For platforms without selective fetch this register is reserved so
do not write 0 to it.
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 8a9d0bdde1bf..4e09ae61d4aa 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -942,7 +942,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
intel_de_write(dev_priv, EXITLINE(cpu_transcoder), val);
}
- if (HAS_PSR_HW_TRACKING(dev_priv))
+ if (HAS_PSR_HW_TRACKING(dev_priv) && HAS_PSR2_SEL_FETCH(dev_priv))
intel_de_rmw(dev_priv, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING,
dev_priv->psr.psr2_sel_fetch_enabled ?
IGNORE_PSR2_HW_TRACKING : 0);
--
2.28.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [Intel-gfx] [PATCH 2/2] drm/i915/display: Check PSR parameter and flag only in state compute phase
2020-09-16 2:44 [Intel-gfx] [PATCH 1/2] drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch José Roberto de Souza
@ 2020-09-16 2:44 ` José Roberto de Souza
2020-09-17 12:27 ` Ville Syrjälä
2020-09-16 3:25 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch Patchwork
1 sibling, 1 reply; 4+ messages in thread
From: José Roberto de Souza @ 2020-09-16 2:44 UTC (permalink / raw)
To: intel-gfx
Due to the debugfs flag, has_psr2 in CRTC state could have a different
value than psr.psr2_enabled and it was causing PSR2 subfeatures(DC3CO
and selective fetch) to be set to not a expected state.
So here only taking in consideration the parameter and debugfs flag
when computing PSR state, this way the CRTC state will also have
the correct state.
intel_psr_fastset_force() was already broken as
intel_psr_compute_config() was already only enabling PSR when
psr_global_enabled() and all other PSR requirements are met.
So some changes was required in this function, now it iterates over
all connectors, if it is a eDP connector and is active force a modeset
in the CRTC driving this connector, what will cause the new PSR state
to be set based on the debugfs flag.
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 65 ++++++++++++++----------
1 file changed, 37 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 4e09ae61d4aa..383b66d9f2f2 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -91,19 +91,14 @@ static bool psr_global_enabled(struct drm_i915_private *i915)
}
}
-static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
- const struct intel_crtc_state *crtc_state)
+static bool psr2_global_enabled(struct drm_i915_private *dev_priv)
{
- /* Cannot enable DSC and PSR2 simultaneously */
- drm_WARN_ON(&dev_priv->drm, crtc_state->dsc.compression_enable &&
- crtc_state->has_psr2);
-
switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
case I915_PSR_DEBUG_DISABLE:
case I915_PSR_DEBUG_FORCE_PSR1:
return false;
default:
- return crtc_state->has_psr2;
+ return true;
}
}
@@ -729,6 +724,11 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
return false;
}
+ if (!psr2_global_enabled(dev_priv)) {
+ drm_dbg_kms(&dev_priv->drm, "PSR2 disabled by flag\n");
+ return false;
+ }
+
/*
* DSC and PSR2 cannot be enabled simultaneously. If a requested
* resolution requires DSC to be enabled, priority is given to DSC
@@ -817,8 +817,11 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
if (intel_dp != dev_priv->psr.dp)
return;
- if (!psr_global_enabled(dev_priv))
+ if (!psr_global_enabled(dev_priv)) {
+ drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n");
return;
+ }
+
/*
* HSW spec explicitly says PSR is tied to port A.
* BDW+ platforms have a instance of PSR registers per transcoder but
@@ -959,7 +962,7 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
drm_WARN_ON(&dev_priv->drm, dev_priv->psr.enabled);
- dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state);
+ dev_priv->psr.psr2_enabled = crtc_state->has_psr2;
dev_priv->psr.busy_frontbuffer_bits = 0;
dev_priv->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
dev_priv->psr.dc3co_enabled = !!crtc_state->dc3co_exitline;
@@ -1029,15 +1032,7 @@ void intel_psr_enable(struct intel_dp *intel_dp,
drm_WARN_ON(&dev_priv->drm, dev_priv->drrs.dp);
mutex_lock(&dev_priv->psr.lock);
-
- if (!psr_global_enabled(dev_priv)) {
- drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n");
- goto unlock;
- }
-
intel_psr_enable_locked(dev_priv, crtc_state, conn_state);
-
-unlock:
mutex_unlock(&dev_priv->psr.lock);
}
@@ -1222,8 +1217,8 @@ void intel_psr_update(struct intel_dp *intel_dp,
mutex_lock(&dev_priv->psr.lock);
- enable = crtc_state->has_psr && psr_global_enabled(dev_priv);
- psr2_enable = intel_psr2_enabled(dev_priv, crtc_state);
+ enable = crtc_state->has_psr;
+ psr2_enable = crtc_state->has_psr2;
if (enable == psr->enabled && psr2_enable == psr->psr2_enabled) {
/* Force a PSR exit when enabling CRC to avoid CRC timeouts */
@@ -1320,10 +1315,11 @@ static bool __psr_wait_for_idle_locked(struct drm_i915_private *dev_priv)
static int intel_psr_fastset_force(struct drm_i915_private *dev_priv)
{
+ struct drm_connector_list_iter conn_iter;
struct drm_device *dev = &dev_priv->drm;
struct drm_modeset_acquire_ctx ctx;
struct drm_atomic_state *state;
- struct intel_crtc *crtc;
+ struct drm_connector *conn;
int err;
state = drm_atomic_state_alloc(dev);
@@ -1334,21 +1330,34 @@ static int intel_psr_fastset_force(struct drm_i915_private *dev_priv)
state->acquire_ctx = &ctx;
retry:
- for_each_intel_crtc(dev, crtc) {
- struct intel_crtc_state *crtc_state =
- intel_atomic_get_crtc_state(state, crtc);
+ drm_connector_list_iter_begin(dev, &conn_iter);
+ drm_for_each_connector_iter(conn, &conn_iter) {
+ struct drm_connector_state *conn_state;
+ struct drm_crtc_state *crtc_state;
+
+ if (conn->connector_type != DRM_MODE_CONNECTOR_eDP)
+ continue;
+
+ conn_state = drm_atomic_get_connector_state(state, conn);
+ if (IS_ERR(conn_state)) {
+ err = PTR_ERR(conn_state);
+ goto error;
+ }
+
+ if (!conn_state->crtc)
+ continue;
+
+ crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc);
if (IS_ERR(crtc_state)) {
err = PTR_ERR(crtc_state);
goto error;
}
- if (crtc_state->hw.active && crtc_state->has_psr) {
- /* Mark mode as changed to trigger a pipe->update() */
- crtc_state->uapi.mode_changed = true;
- break;
- }
+ /* Mark mode as changed to trigger a pipe->update() */
+ crtc_state->mode_changed = true;
}
+ drm_connector_list_iter_end(&conn_iter);
err = drm_atomic_commit(state);
--
2.28.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch
2020-09-16 2:44 [Intel-gfx] [PATCH 1/2] drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch José Roberto de Souza
2020-09-16 2:44 ` [Intel-gfx] [PATCH 2/2] drm/i915/display: Check PSR parameter and flag only in state compute phase José Roberto de Souza
@ 2020-09-16 3:25 ` Patchwork
1 sibling, 0 replies; 4+ messages in thread
From: Patchwork @ 2020-09-16 3:25 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 6699 bytes --]
== Series Details ==
Series: series starting with [1/2] drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch
URL : https://patchwork.freedesktop.org/series/81718/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9016 -> Patchwork_18506
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_18506 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18506, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18506/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_18506:
### IGT changes ###
#### Possible regressions ####
* igt@kms_psr@sprite_plane_onoff:
- fi-kbl-r: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9016/fi-kbl-r/igt@kms_psr@sprite_plane_onoff.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18506/fi-kbl-r/igt@kms_psr@sprite_plane_onoff.html
Known issues
------------
Here are the changes found in Patchwork_18506 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_flink_basic@double-flink:
- fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#402])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9016/fi-tgl-y/igt@gem_flink_basic@double-flink.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18506/fi-tgl-y/igt@gem_flink_basic@double-flink.html
* igt@i915_module_load@reload:
- fi-byt-j1900: [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9016/fi-byt-j1900/igt@i915_module_load@reload.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18506/fi-byt-j1900/igt@i915_module_load@reload.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7500u: [PASS][7] -> [DMESG-WARN][8] ([i915#2203])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9016/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18506/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
- fi-icl-u2: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9016/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18506/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
#### Possible fixes ####
* igt@gem_sync@basic-each:
- fi-tgl-y: [DMESG-WARN][11] ([i915#402]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9016/fi-tgl-y/igt@gem_sync@basic-each.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18506/fi-tgl-y/igt@gem_sync@basic-each.html
* igt@i915_module_load@reload:
- fi-tgl-y: [DMESG-WARN][13] ([i915#1982] / [k.org#205379]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9016/fi-tgl-y/igt@i915_module_load@reload.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18506/fi-tgl-y/igt@i915_module_load@reload.html
* igt@kms_busy@basic@flip:
- fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9016/fi-kbl-x1275/igt@kms_busy@basic@flip.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18506/fi-kbl-x1275/igt@kms_busy@basic@flip.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] +2 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9016/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18506/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
#### Warnings ####
* igt@i915_pm_rpm@basic-rte:
- fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][20] ([i915#62] / [i915#92])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9016/fi-kbl-x1275/igt@i915_pm_rpm@basic-rte.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18506/fi-kbl-x1275/igt@i915_pm_rpm@basic-rte.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92]) -> [DMESG-WARN][22] ([i915#62] / [i915#92] / [i915#95]) +6 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9016/fi-kbl-x1275/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18506/fi-kbl-x1275/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
[k.org#205379]: https://bugzilla.kernel.org/show_bug.cgi?id=205379
Participating hosts (47 -> 40)
------------------------------
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_9016 -> Patchwork_18506
CI-20190529: 20190529
CI_DRM_9016: bb9b5e0a638ce6c8cb3645d875fc65dfacfe5f16 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5785: ee01acab0b6cee7be5cc4278e5d7527ec3e358ba @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18506: f9ae100f868bf9344ee885abbd969fbe6737d41e @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f9ae100f868b drm/i915/display: Check PSR parameter and flag only in state compute phase
d3e8065b6555 drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18506/index.html
[-- Attachment #1.2: Type: text/html, Size: 8438 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/display: Check PSR parameter and flag only in state compute phase
2020-09-16 2:44 ` [Intel-gfx] [PATCH 2/2] drm/i915/display: Check PSR parameter and flag only in state compute phase José Roberto de Souza
@ 2020-09-17 12:27 ` Ville Syrjälä
0 siblings, 0 replies; 4+ messages in thread
From: Ville Syrjälä @ 2020-09-17 12:27 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
On Tue, Sep 15, 2020 at 07:44:10PM -0700, José Roberto de Souza wrote:
> Due to the debugfs flag, has_psr2 in CRTC state could have a different
> value than psr.psr2_enabled and it was causing PSR2 subfeatures(DC3CO
> and selective fetch) to be set to not a expected state.
>
> So here only taking in consideration the parameter and debugfs flag
> when computing PSR state, this way the CRTC state will also have
> the correct state.
>
> intel_psr_fastset_force() was already broken as
> intel_psr_compute_config() was already only enabling PSR when
> psr_global_enabled() and all other PSR requirements are met.
> So some changes was required in this function, now it iterates over
> all connectors, if it is a eDP connector and is active force a modeset
> in the CRTC driving this connector, what will cause the new PSR state
> to be set based on the debugfs flag.
>
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Looks sensible.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 65 ++++++++++++++----------
> 1 file changed, 37 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 4e09ae61d4aa..383b66d9f2f2 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -91,19 +91,14 @@ static bool psr_global_enabled(struct drm_i915_private *i915)
> }
> }
>
> -static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
> - const struct intel_crtc_state *crtc_state)
> +static bool psr2_global_enabled(struct drm_i915_private *dev_priv)
> {
> - /* Cannot enable DSC and PSR2 simultaneously */
> - drm_WARN_ON(&dev_priv->drm, crtc_state->dsc.compression_enable &&
> - crtc_state->has_psr2);
> -
> switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
> case I915_PSR_DEBUG_DISABLE:
> case I915_PSR_DEBUG_FORCE_PSR1:
> return false;
> default:
> - return crtc_state->has_psr2;
> + return true;
> }
> }
>
> @@ -729,6 +724,11 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
> return false;
> }
>
> + if (!psr2_global_enabled(dev_priv)) {
> + drm_dbg_kms(&dev_priv->drm, "PSR2 disabled by flag\n");
> + return false;
> + }
> +
> /*
> * DSC and PSR2 cannot be enabled simultaneously. If a requested
> * resolution requires DSC to be enabled, priority is given to DSC
> @@ -817,8 +817,11 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
> if (intel_dp != dev_priv->psr.dp)
> return;
>
> - if (!psr_global_enabled(dev_priv))
> + if (!psr_global_enabled(dev_priv)) {
> + drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n");
> return;
> + }
> +
> /*
> * HSW spec explicitly says PSR is tied to port A.
> * BDW+ platforms have a instance of PSR registers per transcoder but
> @@ -959,7 +962,7 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
>
> drm_WARN_ON(&dev_priv->drm, dev_priv->psr.enabled);
>
> - dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state);
> + dev_priv->psr.psr2_enabled = crtc_state->has_psr2;
> dev_priv->psr.busy_frontbuffer_bits = 0;
> dev_priv->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
> dev_priv->psr.dc3co_enabled = !!crtc_state->dc3co_exitline;
> @@ -1029,15 +1032,7 @@ void intel_psr_enable(struct intel_dp *intel_dp,
> drm_WARN_ON(&dev_priv->drm, dev_priv->drrs.dp);
>
> mutex_lock(&dev_priv->psr.lock);
> -
> - if (!psr_global_enabled(dev_priv)) {
> - drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n");
> - goto unlock;
> - }
> -
> intel_psr_enable_locked(dev_priv, crtc_state, conn_state);
> -
> -unlock:
> mutex_unlock(&dev_priv->psr.lock);
> }
>
> @@ -1222,8 +1217,8 @@ void intel_psr_update(struct intel_dp *intel_dp,
>
> mutex_lock(&dev_priv->psr.lock);
>
> - enable = crtc_state->has_psr && psr_global_enabled(dev_priv);
> - psr2_enable = intel_psr2_enabled(dev_priv, crtc_state);
> + enable = crtc_state->has_psr;
> + psr2_enable = crtc_state->has_psr2;
>
> if (enable == psr->enabled && psr2_enable == psr->psr2_enabled) {
> /* Force a PSR exit when enabling CRC to avoid CRC timeouts */
> @@ -1320,10 +1315,11 @@ static bool __psr_wait_for_idle_locked(struct drm_i915_private *dev_priv)
>
> static int intel_psr_fastset_force(struct drm_i915_private *dev_priv)
> {
> + struct drm_connector_list_iter conn_iter;
> struct drm_device *dev = &dev_priv->drm;
> struct drm_modeset_acquire_ctx ctx;
> struct drm_atomic_state *state;
> - struct intel_crtc *crtc;
> + struct drm_connector *conn;
> int err;
>
> state = drm_atomic_state_alloc(dev);
> @@ -1334,21 +1330,34 @@ static int intel_psr_fastset_force(struct drm_i915_private *dev_priv)
> state->acquire_ctx = &ctx;
>
> retry:
> - for_each_intel_crtc(dev, crtc) {
> - struct intel_crtc_state *crtc_state =
> - intel_atomic_get_crtc_state(state, crtc);
>
> + drm_connector_list_iter_begin(dev, &conn_iter);
> + drm_for_each_connector_iter(conn, &conn_iter) {
> + struct drm_connector_state *conn_state;
> + struct drm_crtc_state *crtc_state;
> +
> + if (conn->connector_type != DRM_MODE_CONNECTOR_eDP)
> + continue;
> +
> + conn_state = drm_atomic_get_connector_state(state, conn);
> + if (IS_ERR(conn_state)) {
> + err = PTR_ERR(conn_state);
> + goto error;
> + }
> +
> + if (!conn_state->crtc)
> + continue;
> +
> + crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc);
> if (IS_ERR(crtc_state)) {
> err = PTR_ERR(crtc_state);
> goto error;
> }
>
> - if (crtc_state->hw.active && crtc_state->has_psr) {
> - /* Mark mode as changed to trigger a pipe->update() */
> - crtc_state->uapi.mode_changed = true;
> - break;
> - }
> + /* Mark mode as changed to trigger a pipe->update() */
> + crtc_state->mode_changed = true;
> }
> + drm_connector_list_iter_end(&conn_iter);
>
> err = drm_atomic_commit(state);
>
> --
> 2.28.0
--
Ville Syrjälä
Intel
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^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2020-09-17 12:27 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-09-16 2:44 [Intel-gfx] [PATCH 1/2] drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch José Roberto de Souza
2020-09-16 2:44 ` [Intel-gfx] [PATCH 2/2] drm/i915/display: Check PSR parameter and flag only in state compute phase José Roberto de Souza
2020-09-17 12:27 ` Ville Syrjälä
2020-09-16 3:25 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch Patchwork
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