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From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: gregkh@linuxfoundation.org
Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH 11/16] coresight: etm4x: Fix issues on trcseqevr access
Date: Wed, 16 Sep 2020 13:17:32 -0600	[thread overview]
Message-ID: <20200916191737.4001561-12-mathieu.poirier@linaro.org> (raw)
In-Reply-To: <20200916191737.4001561-1-mathieu.poirier@linaro.org>

From: Jonathan Zhou <jonathan.zhouwen@huawei.com>

The TRCSEQEVR(3) is reserved, using '@nrseqstate - 1' instead to avoid
accessing the reserved register.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>
Cc: lizixian@hisilicon.com
Fixes: f188b5e76aae ("coresight: etm4x: Save/restore state across CPU low power states")
Signed-off-by: Jonathan Zhou <jonathan.zhouwen@huawei.com>
[Fixed capital letter in title]
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 drivers/hwtracing/coresight/coresight-etm4x.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
index 63cb1e0d5953..b29ad4f7fac2 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x.c
@@ -1193,7 +1193,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
 	state->trcvdsacctlr = readl(drvdata->base + TRCVDSACCTLR);
 	state->trcvdarcctlr = readl(drvdata->base + TRCVDARCCTLR);
 
-	for (i = 0; i < drvdata->nrseqstate; i++)
+	for (i = 0; i < drvdata->nrseqstate - 1; i++)
 		state->trcseqevr[i] = readl(drvdata->base + TRCSEQEVRn(i));
 
 	state->trcseqrstevr = readl(drvdata->base + TRCSEQRSTEVR);
@@ -1298,7 +1298,7 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
 	writel_relaxed(state->trcvdsacctlr, drvdata->base + TRCVDSACCTLR);
 	writel_relaxed(state->trcvdarcctlr, drvdata->base + TRCVDARCCTLR);
 
-	for (i = 0; i < drvdata->nrseqstate; i++)
+	for (i = 0; i < drvdata->nrseqstate - 1; i++)
 		writel_relaxed(state->trcseqevr[i],
 			       drvdata->base + TRCSEQEVRn(i));
 
-- 
2.25.1


WARNING: multiple messages have this Message-ID (diff)
From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: gregkh@linuxfoundation.org
Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH 11/16] coresight: etm4x: Fix issues on trcseqevr access
Date: Wed, 16 Sep 2020 13:17:32 -0600	[thread overview]
Message-ID: <20200916191737.4001561-12-mathieu.poirier@linaro.org> (raw)
In-Reply-To: <20200916191737.4001561-1-mathieu.poirier@linaro.org>

From: Jonathan Zhou <jonathan.zhouwen@huawei.com>

The TRCSEQEVR(3) is reserved, using '@nrseqstate - 1' instead to avoid
accessing the reserved register.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>
Cc: lizixian@hisilicon.com
Fixes: f188b5e76aae ("coresight: etm4x: Save/restore state across CPU low power states")
Signed-off-by: Jonathan Zhou <jonathan.zhouwen@huawei.com>
[Fixed capital letter in title]
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 drivers/hwtracing/coresight/coresight-etm4x.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
index 63cb1e0d5953..b29ad4f7fac2 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x.c
@@ -1193,7 +1193,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
 	state->trcvdsacctlr = readl(drvdata->base + TRCVDSACCTLR);
 	state->trcvdarcctlr = readl(drvdata->base + TRCVDARCCTLR);
 
-	for (i = 0; i < drvdata->nrseqstate; i++)
+	for (i = 0; i < drvdata->nrseqstate - 1; i++)
 		state->trcseqevr[i] = readl(drvdata->base + TRCSEQEVRn(i));
 
 	state->trcseqrstevr = readl(drvdata->base + TRCSEQRSTEVR);
@@ -1298,7 +1298,7 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
 	writel_relaxed(state->trcvdsacctlr, drvdata->base + TRCVDSACCTLR);
 	writel_relaxed(state->trcvdarcctlr, drvdata->base + TRCVDARCCTLR);
 
-	for (i = 0; i < drvdata->nrseqstate; i++)
+	for (i = 0; i < drvdata->nrseqstate - 1; i++)
 		writel_relaxed(state->trcseqevr[i],
 			       drvdata->base + TRCSEQEVRn(i));
 
-- 
2.25.1


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  parent reply	other threads:[~2020-09-16 19:21 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-16 19:17 [PATCH 00/16] coresight: next v5.9-rc5 Mathieu Poirier
2020-09-16 19:17 ` Mathieu Poirier
2020-09-16 19:17 ` [PATCH 01/16] coresight: etm4x: Fix etm4_count race by moving cpuhp callbacks to init Mathieu Poirier
2020-09-16 19:17   ` Mathieu Poirier
2020-09-16 19:17 ` [PATCH 02/16] coresight: stm: Support marked packet Mathieu Poirier
2020-09-16 19:17   ` Mathieu Poirier
2020-09-16 19:17 ` [PATCH 03/16] coresight: fix offset by one error in counting ports Mathieu Poirier
2020-09-16 19:17   ` Mathieu Poirier
2020-09-16 19:17 ` [PATCH 04/16] coresight: etm4x: Add Support for HiSilicon ETM device Mathieu Poirier
2020-09-16 19:17   ` Mathieu Poirier
2020-09-16 19:17 ` [PATCH 05/16] coresight: cti: disclaim device only when it's claimed Mathieu Poirier
2020-09-16 19:17   ` Mathieu Poirier
2020-09-16 19:17 ` [PATCH 06/16] coresight: cti: remove pm_runtime_get_sync() from CPU hotplug Mathieu Poirier
2020-09-16 19:17   ` Mathieu Poirier
2020-09-16 19:17 ` [PATCH 07/16] coresight: etm4x: Ensure default perf settings filter user/kernel Mathieu Poirier
2020-09-16 19:17   ` Mathieu Poirier
2020-09-16 19:17 ` [PATCH 08/16] coresight: etm4x: Fix issues within reset interface of sysfs Mathieu Poirier
2020-09-16 19:17   ` Mathieu Poirier
2020-09-16 19:17 ` [PATCH 09/16] coresight: cti: Write regsiters directly in cti_enable_hw() Mathieu Poirier
2020-09-16 19:17   ` Mathieu Poirier
2020-09-16 19:17 ` [PATCH 10/16] coresight: etm4x: Handle unreachable sink in perf mode Mathieu Poirier
2020-09-16 19:17   ` Mathieu Poirier
2020-09-16 19:17 ` Mathieu Poirier [this message]
2020-09-16 19:17   ` [PATCH 11/16] coresight: etm4x: Fix issues on trcseqevr access Mathieu Poirier
2020-09-16 19:17 ` [PATCH 12/16] MAINTAINERS: Add CoreSight mailing list Mathieu Poirier
2020-09-16 19:17   ` Mathieu Poirier
2020-09-16 19:17 ` [PATCH 13/16] coresight: etm: perf: Sink selection using sysfs is deprecated Mathieu Poirier
2020-09-16 19:17   ` Mathieu Poirier
2020-09-16 19:17 ` [PATCH 14/16] coresight: Make sysfs functional on topologies with per core sink Mathieu Poirier
2020-09-16 19:17   ` Mathieu Poirier
2020-09-16 19:17 ` [PATCH 15/16] coresight: etm4x: Fix mis-usage of nr_resource in sysfs interface Mathieu Poirier
2020-09-16 19:17   ` Mathieu Poirier
2020-09-16 19:17 ` [PATCH 16/16] coresight: etm4x: Fix number of resources check for ETM 4.3 and above Mathieu Poirier
2020-09-16 19:17   ` Mathieu Poirier
2020-09-17  9:08 ` [PATCH 00/16] coresight: next v5.9-rc5 Greg KH
2020-09-17  9:08   ` Greg KH
2020-09-17 14:35   ` Mathieu Poirier
2020-09-17 14:35     ` Mathieu Poirier

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