[PATCH 00/15] DC Patches September 21, 2020

[PATCH 00/15] DC Patches September 21, 2020

[Qingqing Zhuo]

This DC patchset brings improvements in multiple areas. In summary, we have:

* DC version 3.2.104.
* DMUB Firmware release 0.0.34.
* Improve on HDMI fallback mechanism.
* Enable DP YCbCr420 mode support for DCN10 ASICs.
* Bug fixes for backlight, ODM, eDP and others.

------

Anthony Koo (2):
  drm/amd/display: [FW Promotion] Release 0.0.33
  drm/amd/display: [FW Promotion] Release 0.0.34

Aric Cyr (2):
  drm/amd/display: 3.2.103
  drm/amd/display: 3.2.104

Chris Park (1):
  drm/amd/display: TMDS Fallback transition

David Galiffi (1):
  drm/amd/display: Fix incorrect backlight register offset for DCN

Gary Li (1):
  drm/amd/display: Enable DP YCbCr420 mode support for DCN10

Peikang Zhang (2):
  drm/amd/display: Bug in dce_is_panel_backlight_on()
  drm/amd/display: eDP intermittent black screen during PnP

Taimur Hassan (1):
  drm/amd/display: Check for flip pending before locking pipes.

Wenjing Liu (1):
  drm/amd/display: allow DP RX to use more cr aux rd interval delay

Wesley Chalmers (2):
  drm/amd/display: Fix ODM policy implementation
  drm/amd/display: Increase timeout for DP Disable

Wyatt Wood (1):
  drm/amd/display: Implement PSR wait for enable/disable

jinlong zhang (1):
  drm/amd/display: Replace msleep with udelay while read edid return
    defer.

 .../display/amdgpu_dm/amdgpu_dm_mst_types.c   | 13 +++++++++
 drivers/gpu/drm/amd/display/dc/core/dc.c      | 11 ++------
 drivers/gpu/drm/amd/display/dc/core/dc_link.c |  2 +-
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 19 ++++++++++++-
 .../drm/amd/display/dc/core/dc_link_hwss.c    |  2 ++
 .../gpu/drm/amd/display/dc/core/dc_resource.c | 11 ++++----
 drivers/gpu/drm/amd/display/dc/dc.h           |  2 +-
 drivers/gpu/drm/amd/display/dc/dc_link.h      |  2 ++
 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c  |  2 +-
 .../drm/amd/display/dc/dce/dce_panel_cntl.c   | 10 ++++---
 .../drm/amd/display/dc/dce/dce_panel_cntl.h   |  6 ++++-
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 27 ++++++++++++++++++-
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h |  2 +-
 .../display/dc/dce110/dce110_hw_sequencer.c   |  1 +
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 12 +++++++--
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.h |  2 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_init.c |  1 +
 .../drm/amd/display/dc/dcn10/dcn10_resource.c |  2 +-
 .../display/dc/dcn10/dcn10_stream_encoder.c   |  4 +--
 .../gpu/drm/amd/display/dc/dcn20/dcn20_init.c |  1 +
 .../gpu/drm/amd/display/dc/dcn21/dcn21_init.c |  1 +
 .../gpu/drm/amd/display/dc/dcn30/dcn30_init.c |  1 +
 .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |  2 +-
 .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   | 11 +++++---
 24 files changed, 113 insertions(+), 34 deletions(-)

-- 
2.17.1

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[PATCH 01/15] drm/amd/display: Fix incorrect backlight register offset for DCN

[Qingqing Zhuo]

From: David Galiffi <David.Galiffi@amd.com>

[Why]
Typo in backlight refactor introduced wrong register offset.

[How]
SR(BIOS_SCRATCH_2) to NBIO_SR(BIOS_SCRATCH_2).

Signed-off-by: David Galiffi <David.Galiffi@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Cc: <stable@vger.kernel.org>
---
 drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h b/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h
index 99c68ca9c7e0..967d04d75b98 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h
@@ -54,7 +54,7 @@
 	SR(BL_PWM_CNTL2), \
 	SR(BL_PWM_PERIOD_CNTL), \
 	SR(BL_PWM_GRP1_REG_LOCK), \
-	SR(BIOS_SCRATCH_2)
+	NBIO_SR(BIOS_SCRATCH_2)
 
 #define DCE_PANEL_CNTL_SF(reg_name, field_name, post_fix)\
 	.field_name = reg_name ## __ ## field_name ## post_fix
-- 
2.17.1

[PATCH 01/15] drm/amd/display: Fix incorrect backlight register offset for DCN

[Qingqing Zhuo]

From: David Galiffi <David.Galiffi@amd.com>

[Why]
Typo in backlight refactor introduced wrong register offset.

[How]
SR(BIOS_SCRATCH_2) to NBIO_SR(BIOS_SCRATCH_2).

Signed-off-by: David Galiffi <David.Galiffi@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Cc: <stable@vger.kernel.org>
---
 drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h b/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h
index 99c68ca9c7e0..967d04d75b98 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h
@@ -54,7 +54,7 @@
 	SR(BL_PWM_CNTL2), \
 	SR(BL_PWM_PERIOD_CNTL), \
 	SR(BL_PWM_GRP1_REG_LOCK), \
-	SR(BIOS_SCRATCH_2)
+	NBIO_SR(BIOS_SCRATCH_2)
 
 #define DCE_PANEL_CNTL_SF(reg_name, field_name, post_fix)\
 	.field_name = reg_name ## __ ## field_name ## post_fix
-- 
2.17.1

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[PATCH 02/15] drm/amd/display: [FW Promotion] Release 0.0.33

[Qingqing Zhuo]

From: Anthony Koo <Anthony.Koo@amd.com>

Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
---
 drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index a0bd502dc7d7..f20d6df6def1 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -36,10 +36,10 @@
 
 /* Firmware versioning. */
 #ifdef DMUB_EXPOSE_VERSION
-#define DMUB_FW_VERSION_GIT_HASH 0x82f998da6
+#define DMUB_FW_VERSION_GIT_HASH 0xd0772ca1b
 #define DMUB_FW_VERSION_MAJOR 0
 #define DMUB_FW_VERSION_MINOR 0
-#define DMUB_FW_VERSION_REVISION 32
+#define DMUB_FW_VERSION_REVISION 33
 #define DMUB_FW_VERSION_TEST 0
 #define DMUB_FW_VERSION_VBIOS 0
 #define DMUB_FW_VERSION_HOTFIX 0
-- 
2.17.1

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[PATCH 03/15] drm/amd/display: 3.2.103

[Qingqing Zhuo]

From: Aric Cyr <aric.cyr@amd.com>

Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index d9b22d6a985a..d65483483d05 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -42,7 +42,7 @@
 #include "inc/hw/dmcu.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.2.102"
+#define DC_VER "3.2.103"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
-- 
2.17.1

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[PATCH 04/15] drm/amd/display: Replace msleep with udelay while read edid return defer.

[Qingqing Zhuo]

From: jinlong zhang <jinlong.zhang@amd.com>

[why]
while read edid return defer, then it enter to msleep,
but it actually took more time during msleep,
this will cause remaining edid read fail.

[how]
Replacing msleep with udelay, it will not take any extra time, edid return pass finally.

Signed-off-by: jinlong zhang <jinlong.zhang@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
index 743042d5905a..cdcad82765e0 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
@@ -653,7 +653,7 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
 					if ((*payload->reply == AUX_TRANSACTION_REPLY_AUX_DEFER) ||
 						(*payload->reply == AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER)) {
 						if (payload->defer_delay > 0)
-							msleep(payload->defer_delay);
+							udelay(payload->defer_delay * 1000);
 					}
 				}
 				break;
-- 
2.17.1

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[PATCH 05/15] drm/amd/display: Bug in dce_is_panel_backlight_on()

[Qingqing Zhuo]

From: Peikang Zhang <peikang.zhang@amd.com>

[Why]
dce_is_panel_backlight_on() will return wrong value if
LVTMA_BLON_OVRD is 0

[How]
When LVTMA_BLON_OVRD is 0, read
LVTMA_PWRSEQ_TARGET_STATE instead

Signed-off-by: Peikang Zhang <peikang.zhang@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c | 10 +++++++---
 drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h |  4 ++++
 2 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c b/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c
index df7f826eebd8..74f7619d4154 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c
@@ -159,11 +159,15 @@ static uint32_t dce_panel_cntl_hw_init(struct panel_cntl *panel_cntl)
 static bool dce_is_panel_backlight_on(struct panel_cntl *panel_cntl)
 {
 	struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(panel_cntl);
-	uint32_t value;
+	uint32_t blon, blon_ovrd, pwrseq_target_state;
 
-	REG_GET(PWRSEQ_CNTL, LVTMA_BLON, &value);
+	REG_GET_2(PWRSEQ_CNTL, LVTMA_BLON, &blon, LVTMA_BLON_OVRD, &blon_ovrd);
+	REG_GET(PWRSEQ_CNTL, LVTMA_PWRSEQ_TARGET_STATE, &pwrseq_target_state);
 
-	return value;
+	if (blon_ovrd)
+		return blon;
+	else
+		return pwrseq_target_state;
 }
 
 static bool dce_is_panel_powered_on(struct panel_cntl *panel_cntl)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h b/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h
index 967d04d75b98..6bd1196083a3 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h
@@ -61,8 +61,10 @@
 
 #define DCE_PANEL_CNTL_MASK_SH_LIST(mask_sh) \
 	DCE_PANEL_CNTL_SF(LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\
+	DCE_PANEL_CNTL_SF(LVTMA_PWRSEQ_CNTL, LVTMA_BLON_OVRD, mask_sh),\
 	DCE_PANEL_CNTL_SF(LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, mask_sh),\
 	DCE_PANEL_CNTL_SF(LVTMA_PWRSEQ_CNTL, LVTMA_DIGON_OVRD, mask_sh),\
+	DCE_PANEL_CNTL_SF(LVTMA_PWRSEQ_CNTL, LVTMA_PWRSEQ_TARGET_STATE, mask_sh), \
 	DCE_PANEL_CNTL_SF(LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh), \
 	DCE_PANEL_CNTL_SF(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV, mask_sh), \
 	DCE_PANEL_CNTL_SF(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, mask_sh), \
@@ -76,8 +78,10 @@
 
 #define DCE_PANEL_CNTL_REG_FIELD_LIST(type) \
 	type LVTMA_BLON;\
+	type LVTMA_BLON_OVRD;\
 	type LVTMA_DIGON;\
 	type LVTMA_DIGON_OVRD;\
+	type LVTMA_PWRSEQ_TARGET_STATE; \
 	type LVTMA_PWRSEQ_TARGET_STATE_R; \
 	type BL_PWM_REF_DIV; \
 	type BL_PWM_EN; \
-- 
2.17.1

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[PATCH 06/15] drm/amd/display: eDP intermittent black screen during PnP

[Qingqing Zhuo]

From: Peikang Zhang <peikang.zhang@amd.com>

[Why]
We dont's turn off backlight before power off eDP (VDD),
which is a violation of eDP specs.

[How]
Power off eDP backlight before power off eDP

Signed-off-by: Peikang Zhang <peikang.zhang@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c          | 2 ++
 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 1 +
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c           | 1 +
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c           | 1 +
 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c           | 1 +
 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c           | 1 +
 6 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index 81c026319ccd..dba338c88256 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -229,6 +229,8 @@ void dp_disable_link_phy(struct dc_link *link, enum signal_type signal)
 		dp_receiver_power_ctrl(link, false);
 
 	if (signal == SIGNAL_TYPE_EDP) {
+		if (link->dc->hwss.edp_backlight_control)
+			link->dc->hwss.edp_backlight_control(link, false);
 		link->link_enc->funcs->disable_output(link->link_enc, signal);
 		link->dc->hwss.edp_power_control(link, false);
 	} else {
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 1002ce9979dc..27a1262a20f6 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -2890,6 +2890,7 @@ static const struct hw_sequencer_funcs dce110_funcs = {
 	.setup_stereo = NULL,
 	.set_avmute = dce110_set_avmute,
 	.wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect,
+	.edp_backlight_control = dce110_edp_backlight_control,
 	.edp_power_control = dce110_edp_power_control,
 	.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
 	.set_cursor_position = dce110_set_cursor_position,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
index a1d1559bb5d7..b24c8ae8b1ec 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
@@ -66,6 +66,7 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
 	.get_hw_state = dcn10_get_hw_state,
 	.clear_status_bits = dcn10_clear_status_bits,
 	.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
+	.edp_backlight_control = dce110_edp_backlight_control,
 	.edp_power_control = dce110_edp_power_control,
 	.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
 	.set_cursor_position = dcn10_set_cursor_position,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
index 966e1790b9bf..072193c5ffe6 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
@@ -68,6 +68,7 @@ static const struct hw_sequencer_funcs dcn20_funcs = {
 	.get_hw_state = dcn10_get_hw_state,
 	.clear_status_bits = dcn10_clear_status_bits,
 	.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
+	.edp_backlight_control = dce110_edp_backlight_control,
 	.edp_power_control = dce110_edp_power_control,
 	.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
 	.set_cursor_position = dcn10_set_cursor_position,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
index 2ba880c3943c..2b7396c9fcb4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
@@ -69,6 +69,7 @@ static const struct hw_sequencer_funcs dcn21_funcs = {
 	.get_hw_state = dcn10_get_hw_state,
 	.clear_status_bits = dcn10_clear_status_bits,
 	.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
+	.edp_backlight_control = dce110_edp_backlight_control,
 	.edp_power_control = dce110_edp_power_control,
 	.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
 	.set_cursor_position = dcn10_set_cursor_position,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
index 19daa456e3bf..7c90c2222506 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
@@ -69,6 +69,7 @@ static const struct hw_sequencer_funcs dcn30_funcs = {
 	.get_hw_state = dcn10_get_hw_state,
 	.clear_status_bits = dcn10_clear_status_bits,
 	.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
+	.edp_backlight_control = dce110_edp_backlight_control,
 	.edp_power_control = dce110_edp_power_control,
 	.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
 	.set_cursor_position = dcn10_set_cursor_position,
-- 
2.17.1

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[PATCH 07/15] drm/amd/display: Fix ODM policy implementation

[Qingqing Zhuo]

From: Wesley Chalmers <Wesley.Chalmers@amd.com>

[WHY]
Only the leftmost ODM pipe should be offset when scaling. A previous
code change was intended to implement this policy, but a section of code
was overlooked.

Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Cc: <stable@vger.kernel.org>
---
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 4cea9344d8aa..e430148e47cf 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -785,14 +785,15 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx)
 	/*
 	 * Only the leftmost ODM pipe should be offset by a nonzero distance
 	 */
-	if (!pipe_ctx->prev_odm_pipe)
+	if (!pipe_ctx->prev_odm_pipe) {
 		data->recout.x = stream->dst.x;
-	else
-		data->recout.x = 0;
-	if (stream->src.x < surf_clip.x)
-		data->recout.x += (surf_clip.x - stream->src.x) * stream->dst.width
+		if (stream->src.x < surf_clip.x)
+			data->recout.x += (surf_clip.x - stream->src.x) * stream->dst.width
 						/ stream->src.width;
 
+	} else
+		data->recout.x = 0;
+
 	data->recout.width = surf_clip.width * stream->dst.width / stream->src.width;
 	if (data->recout.width + data->recout.x > stream->dst.x + stream->dst.width)
 		data->recout.width = stream->dst.x + stream->dst.width - data->recout.x;
-- 
2.17.1

[PATCH 07/15] drm/amd/display: Fix ODM policy implementation

[Qingqing Zhuo]

From: Wesley Chalmers <Wesley.Chalmers@amd.com>

[WHY]
Only the leftmost ODM pipe should be offset when scaling. A previous
code change was intended to implement this policy, but a section of code
was overlooked.

Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Cc: <stable@vger.kernel.org>
---
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 4cea9344d8aa..e430148e47cf 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -785,14 +785,15 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx)
 	/*
 	 * Only the leftmost ODM pipe should be offset by a nonzero distance
 	 */
-	if (!pipe_ctx->prev_odm_pipe)
+	if (!pipe_ctx->prev_odm_pipe) {
 		data->recout.x = stream->dst.x;
-	else
-		data->recout.x = 0;
-	if (stream->src.x < surf_clip.x)
-		data->recout.x += (surf_clip.x - stream->src.x) * stream->dst.width
+		if (stream->src.x < surf_clip.x)
+			data->recout.x += (surf_clip.x - stream->src.x) * stream->dst.width
 						/ stream->src.width;
 
+	} else
+		data->recout.x = 0;
+
 	data->recout.width = surf_clip.width * stream->dst.width / stream->src.width;
 	if (data->recout.width + data->recout.x > stream->dst.x + stream->dst.width)
 		data->recout.width = stream->dst.x + stream->dst.width - data->recout.x;
-- 
2.17.1

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[PATCH 08/15] drm/amd/display: Increase timeout for DP Disable

[Qingqing Zhuo]

From: Wesley Chalmers <Wesley.Chalmers@amd.com>

[WHY]
When disabling DP video, the current REG_WAIT timeout
of 50ms is too low for certain cases with very high
VSYNC intervals.

[HOW]
Increase the timeout to 102ms, so that
refresh rates as low as 10Hz can be handled properly.

Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Cc: <stable@vger.kernel.org>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
index 9cf139be3f40..f70fcadf1ee5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
@@ -896,10 +896,10 @@ void enc1_stream_encoder_dp_blank(
 	 */
 	REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2);
 	/* Larger delay to wait until VBLANK - use max retry of
-	 * 10us*5000=50ms. This covers 41.7ms of minimum 24 Hz mode +
+	 * 10us*10200=102ms. This covers 100.0ms of minimum 10 Hz mode +
 	 * a little more because we may not trust delay accuracy.
 	 */
-	max_retries = DP_BLANK_MAX_RETRY * 250;
+	max_retries = DP_BLANK_MAX_RETRY * 501;
 
 	/* disable DP stream */
 	REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
-- 
2.17.1

[PATCH 08/15] drm/amd/display: Increase timeout for DP Disable

[Qingqing Zhuo]

From: Wesley Chalmers <Wesley.Chalmers@amd.com>

[WHY]
When disabling DP video, the current REG_WAIT timeout
of 50ms is too low for certain cases with very high
VSYNC intervals.

[HOW]
Increase the timeout to 102ms, so that
refresh rates as low as 10Hz can be handled properly.

Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Cc: <stable@vger.kernel.org>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
index 9cf139be3f40..f70fcadf1ee5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
@@ -896,10 +896,10 @@ void enc1_stream_encoder_dp_blank(
 	 */
 	REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2);
 	/* Larger delay to wait until VBLANK - use max retry of
-	 * 10us*5000=50ms. This covers 41.7ms of minimum 24 Hz mode +
+	 * 10us*10200=102ms. This covers 100.0ms of minimum 10 Hz mode +
 	 * a little more because we may not trust delay accuracy.
 	 */
-	max_retries = DP_BLANK_MAX_RETRY * 250;
+	max_retries = DP_BLANK_MAX_RETRY * 501;
 
 	/* disable DP stream */
 	REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
-- 
2.17.1

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[PATCH 09/15] drm/amd/display: Enable DP YCbCr420 mode support for DCN10

[Qingqing Zhuo]

From: Gary Li <gary.li@amd.com>

[WHY]
In DCN10 when a panel with YCbCr420 capability is connected via
USB-C to HDMI active dongle, no YCbCr420 option is listed in
Radeon settings.

[HOW]
Enable DP YCbCr420 mode support for DCN10

Signed-off-by: Gary Li <gary.li@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 1abd81e17f09..a78712caf124 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -798,7 +798,7 @@ static const struct encoder_feature_support link_enc_feature = {
 		.max_hdmi_deep_color = COLOR_DEPTH_121212,
 		.max_hdmi_pixel_clock = 600000,
 		.hdmi_ycbcr420_supported = true,
-		.dp_ycbcr420_supported = false,
+		.dp_ycbcr420_supported = true,
 		.flags.bits.IS_HBR2_CAPABLE = true,
 		.flags.bits.IS_HBR3_CAPABLE = true,
 		.flags.bits.IS_TPS3_CAPABLE = true,
-- 
2.17.1

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[PATCH 10/15] drm/amd/display: allow DP RX to use more cr aux rd interval delay

[Qingqing Zhuo]

From: Wenjing Liu <wenjing.liu@amd.com>

[why]
Regression is caused by previous change with attempt to correct the
extended cr aux rd interval delay due to mis interpretation of the DP specs.
I4b4f508e30e5218ffeb7e40cc19e6dc54357361e
The change turns out not working well with certain RXs.
So we decided to keep the cr aux rd interval logic as before.

Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Reviewed-by: George Shen <George.Shen@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
---
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 47fb09f41bfb..232d77721ad9 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -49,6 +49,23 @@ static struct dc_link_settings get_common_supported_link_settings(
 		struct dc_link_settings link_setting_a,
 		struct dc_link_settings link_setting_b);
 
+static uint32_t get_cr_training_aux_rd_interval(struct dc_link *link,
+		const struct dc_link_settings *link_settings)
+{
+	union training_aux_rd_interval training_rd_interval;
+	uint32_t wait_in_micro_secs = 100;
+
+	memset(&training_rd_interval, 0, sizeof(training_rd_interval));
+	core_link_read_dpcd(
+			link,
+			DP_TRAINING_AUX_RD_INTERVAL,
+			(uint8_t *)&training_rd_interval,
+			sizeof(training_rd_interval));
+	if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
+		wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
+	return wait_in_micro_secs;
+}
+
 static uint32_t get_eq_training_aux_rd_interval(
 	struct dc_link *link,
 	const struct dc_link_settings *link_settings)
@@ -1251,7 +1268,7 @@ static void initialize_training_settings(
 	if (overrides->cr_pattern_time != NULL)
 		lt_settings->cr_pattern_time = *overrides->cr_pattern_time;
 	else
-		lt_settings->cr_pattern_time = 100;
+		lt_settings->cr_pattern_time = get_cr_training_aux_rd_interval(link, link_setting);
 
 	if (overrides->eq_pattern_time != NULL)
 		lt_settings->eq_pattern_time = *overrides->eq_pattern_time;
-- 
2.17.1

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[PATCH 11/15] drm/amd/display: Implement PSR wait for enable/disable

[Qingqing Zhuo]

From: Wyatt Wood <wyatt.wood@amd.com>

[Why]
For DMUB implementation of PSR, the 'wait' parameter,
used to determine if driver should wait for PSR enable/disable,
is not implemented correctly.

[How]
Implement wait for PSR enable/disable.

Signed-off-by: Wyatt Wood <wyatt.wood@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c |  2 +-
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 27 ++++++++++++++++++-
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h |  2 +-
 3 files changed, 28 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 1871ff6119ae..f13396254b5d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2566,7 +2566,7 @@ bool dc_link_set_psr_allow_active(struct dc_link *link, bool allow_active, bool
 	link->psr_settings.psr_allow_active = allow_active;
 
 	if (psr != NULL && link->psr_settings.psr_feature_enabled)
-		psr->funcs->psr_enable(psr, allow_active);
+		psr->funcs->psr_enable(psr, allow_active, wait);
 	else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) && link->psr_settings.psr_feature_enabled)
 		dmcu->funcs->set_psr_enable(dmcu, allow_active, wait);
 	else
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index 5167d6b8a48d..bf24f1029547 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -119,10 +119,11 @@ static bool dmub_psr_set_version(struct dmub_psr *dmub, struct dc_stream_state *
 /**
  * Enable/Disable PSR.
  */
-static void dmub_psr_enable(struct dmub_psr *dmub, bool enable)
+static void dmub_psr_enable(struct dmub_psr *dmub, bool enable, bool wait)
 {
 	union dmub_rb_cmd cmd;
 	struct dc_context *dc = dmub->ctx;
+	uint32_t retry_count, psr_state = 0;
 
 	cmd.psr_enable.header.type = DMUB_CMD__PSR;
 
@@ -136,6 +137,30 @@ static void dmub_psr_enable(struct dmub_psr *dmub, bool enable)
 	dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
 	dc_dmub_srv_cmd_execute(dc->dmub_srv);
 	dc_dmub_srv_wait_idle(dc->dmub_srv);
+
+	/* Below loops 1000 x 500us = 500 ms.
+	 *  Exit PSR may need to wait 1-2 frames to power up. Timeout after at
+	 *  least a few frames. Should never hit the max retry assert below.
+	 */
+	if (wait) {
+		for (retry_count = 0; retry_count <= 1000; retry_count++) {
+			dmub_psr_get_state(dmub, &psr_state);
+
+			if (enable) {
+				if (psr_state != 0)
+					break;
+			} else {
+				if (psr_state == 0)
+					break;
+			}
+
+			udelay(500);
+		}
+
+		/* assert if max retry hit */
+		if (retry_count >= 1000)
+			ASSERT(0);
+	}
 }
 
 /**
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h
index f404fecd6410..dc121ed92d2e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h
@@ -36,7 +36,7 @@ struct dmub_psr {
 
 struct dmub_psr_funcs {
 	bool (*psr_copy_settings)(struct dmub_psr *dmub, struct dc_link *link, struct psr_context *psr_context);
-	void (*psr_enable)(struct dmub_psr *dmub, bool enable);
+	void (*psr_enable)(struct dmub_psr *dmub, bool enable, bool wait);
 	void (*psr_get_state)(struct dmub_psr *dmub, uint32_t *psr_state);
 	void (*psr_set_level)(struct dmub_psr *dmub, uint16_t psr_level);
 };
-- 
2.17.1

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[PATCH 12/15] drm/amd/display: Check for flip pending before locking pipes.

[Qingqing Zhuo]

From: Taimur Hassan <syed.hassan@amd.com>

[Why]
When running a game/benchmark with v-sync disabled, disabling a plane
(which is v-sync) can cause an underflow. This is due to flips that are
pending before pipe locking being applied after locks are released and
pipes have been re-arranged or disconnected. This can potentially apply
a flip on the incorrect pipe.

[How]
Check that any pending flips are cleared before locking any pipes to
ensure flips are applied on the correct pipes.

Signed-off-by: Taimur Hassan <syed.hassan@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c             | 11 ++---------
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c    | 12 ++++++++++--
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h    |  2 +-
 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h    |  2 +-
 4 files changed, 14 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 83ce55edb3aa..1efc823c2a14 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2324,7 +2324,6 @@ static void commit_planes_for_stream(struct dc *dc,
 		enum surface_update_type update_type,
 		struct dc_state *context)
 {
-	bool mpcc_disconnected = false;
 	int i, j;
 	struct pipe_ctx *top_pipe_to_program = NULL;
 
@@ -2355,14 +2354,8 @@ static void commit_planes_for_stream(struct dc *dc,
 		context_clock_trace(dc, context);
 	}
 
-	if (update_type != UPDATE_TYPE_FAST && dc->hwss.interdependent_update_lock &&
-		dc->hwss.disconnect_pipes && dc->hwss.wait_for_pending_cleared){
-		dc->hwss.interdependent_update_lock(dc, context, true);
-		mpcc_disconnected = dc->hwss.disconnect_pipes(dc, context);
-		dc->hwss.interdependent_update_lock(dc, context, false);
-		if (mpcc_disconnected)
-			dc->hwss.wait_for_pending_cleared(dc, context);
-	}
+	if (update_type != UPDATE_TYPE_FAST && dc->hwss.interdependent_update_lock && dc->hwss.wait_for_pending_cleared)
+		dc->hwss.disconnect_pipes(dc, context);
 
 	for (j = 0; j < dc->res_pool->pipe_count; j++) {
 		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index d0f3bf953d02..79fe9571cf5d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2761,7 +2761,7 @@ static struct pipe_ctx *dcn10_find_top_pipe_for_stream(
 	return NULL;
 }
 
-bool dcn10_disconnect_pipes(
+void dcn10_disconnect_pipes(
 		struct dc *dc,
 		struct dc_state *context)
 {
@@ -2772,6 +2772,10 @@ bool dcn10_disconnect_pipes(
 		bool mpcc_disconnected = false;
 		struct pipe_ctx *old_pipe;
 		struct pipe_ctx *new_pipe;
+
+		dc->hwss.wait_for_pending_cleared(dc, context);
+		dc->hwss.interdependent_update_lock(dc, context, true);
+
 		DC_LOGGER_INIT(dc->ctx->logger);
 
 		/* Set pipe update flags and lock pipes */
@@ -2874,7 +2878,11 @@ bool dcn10_disconnect_pipes(
 				}
 			}
 		}
-	return mpcc_disconnected;
+
+		dc->hwss.interdependent_update_lock(dc, context, false);
+
+		if (mpcc_disconnected)
+			dc->hwss.wait_for_pending_cleared(dc, context);
 }
 
 void dcn10_wait_for_pending_cleared(struct dc *dc,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
index e5691e499023..9a0f7a8a85cd 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
@@ -194,7 +194,7 @@ void dcn10_get_surface_visual_confirm_color(
 void dcn10_get_hdr_visual_confirm_color(
 		struct pipe_ctx *pipe_ctx,
 		struct tg_color *color);
-bool dcn10_disconnect_pipes(
+void dcn10_disconnect_pipes(
 		struct dc *dc,
 		struct dc_state *context);
 
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 64c1be818b0e..f48ee24d42f9 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -67,7 +67,7 @@ struct hw_sequencer_funcs {
 			int num_planes, struct dc_state *context);
 	void (*program_front_end_for_ctx)(struct dc *dc,
 			struct dc_state *context);
-	bool (*disconnect_pipes)(struct dc *dc,
+	void (*disconnect_pipes)(struct dc *dc,
 			struct dc_state *context);
 	void (*wait_for_pending_cleared)(struct dc *dc,
 			struct dc_state *context);
-- 
2.17.1

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[PATCH 13/15] drm/amd/display: TMDS Fallback transition

[Qingqing Zhuo]

From: Chris Park <Chris.Park@amd.com>

[Why]
HDMI requires fallback to TMDS by redetection
in order to switch PHY settings.
This avoids black out when link training fail
during mode setting, link quality update,
disable driver sequence.

[How]
Allow driver to redetect HDMI displays
based on retraining or fallback mechanism.

Signed-off-by: Chris Park <Chris.Park@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
---
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 13 +++++++++++++
 drivers/gpu/drm/amd/display/dc/dc_link.h            |  2 ++
 2 files changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 0b9a4fc642ae..98b4d5e2e336 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -158,7 +158,20 @@ static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnecto
 	u8 dsc_caps[16] = { 0 };
 
 	aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port);
+#if defined(CONFIG_HP_HOOK_WORKAROUND)
+	/*
+	 * drm_dp_mst_dsc_aux_for_port() will return NULL for certain configs
+	 * because it only check the dsc/fec caps of the "port variable" and not the dock
+	 *
+	 * This case will return NULL: DSC capabe MST dock connected to a non fec/dsc capable display
+	 *
+	 * Workaround: explicitly check the use case above and use the mst dock's aux as dsc_aux
+	 *
+	 */
 
+	if (!aconnector->dsc_aux && !port->parent->port_parent)
+		aconnector->dsc_aux = &aconnector->mst_port->dm_dp_aux.aux;
+#endif
 	if (!aconnector->dsc_aux)
 		return false;
 
diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
index e002ef706e1d..266b93a705d5 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -237,6 +237,8 @@ enum dc_detect_reason {
 	DETECT_REASON_BOOT,
 	DETECT_REASON_HPD,
 	DETECT_REASON_HPDRX,
+	DETECT_REASON_FALLBACK,
+	DETECT_REASON_RETRAIN
 };
 
 bool dc_link_detect(struct dc_link *dc_link, enum dc_detect_reason reason);
-- 
2.17.1

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[PATCH 14/15] drm/amd/display: [FW Promotion] Release 0.0.34

[Qingqing Zhuo]

From: Anthony Koo <Anthony.Koo@amd.com>

[Header Changes]
       - Add new SCRATCH0 status bits for detecting restore state

Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
---
 drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index f20d6df6def1..137613a60419 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -36,10 +36,10 @@
 
 /* Firmware versioning. */
 #ifdef DMUB_EXPOSE_VERSION
-#define DMUB_FW_VERSION_GIT_HASH 0xd0772ca1b
+#define DMUB_FW_VERSION_GIT_HASH 0xf547f0b9d
 #define DMUB_FW_VERSION_MAJOR 0
 #define DMUB_FW_VERSION_MINOR 0
-#define DMUB_FW_VERSION_REVISION 33
+#define DMUB_FW_VERSION_REVISION 34
 #define DMUB_FW_VERSION_TEST 0
 #define DMUB_FW_VERSION_VBIOS 0
 #define DMUB_FW_VERSION_HOTFIX 0
@@ -170,7 +170,7 @@ union dmub_fw_boot_status {
 		uint32_t dal_fw : 1;
 		uint32_t mailbox_rdy : 1;
 		uint32_t optimized_init_done : 1;
-		uint32_t reserved : 29;
+		uint32_t restore_required : 1;
 	} bits;
 	uint32_t all;
 };
@@ -179,6 +179,7 @@ enum dmub_fw_boot_status_bit {
 	DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0),
 	DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1),
 	DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2),
+	DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3),
 };
 
 /* Register bit definition for SCRATCH15 */
@@ -301,6 +302,10 @@ enum dmub_cmd_type {
 	DMUB_CMD__VBIOS = 128,
 };
 
+enum dmub_out_cmd_type {
+	DMUB_OUT_CMD__NULL = 0,
+};
+
 #pragma pack(push, 1)
 
 struct dmub_cmd_header {
-- 
2.17.1

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[PATCH 15/15] drm/amd/display: 3.2.104

[Qingqing Zhuo]

From: Aric Cyr <aric.cyr@amd.com>

Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index d65483483d05..061ca15660ac 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -42,7 +42,7 @@
 #include "inc/hw/dmcu.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.2.103"
+#define DC_VER "3.2.104"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
-- 
2.17.1

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Re: [PATCH 04/15] drm/amd/display: Replace msleep with udelay while read edid return defer.

[Alex Deucher]

On Wed, Sep 16, 2020 at 3:42 PM Qingqing Zhuo <qingqing.zhuo@amd.com> wrote:
>
> From: jinlong zhang <jinlong.zhang@amd.com>
>
> [why]
> while read edid return defer, then it enter to msleep,
> but it actually took more time during msleep,
> this will cause remaining edid read fail.
>
> [how]
> Replacing msleep with udelay, it will not take any extra time, edid return pass finally.

How long of a delay are we talking about here?  Some platforms don't
support long udelays and someone will send a patch to change this to
msleep.

Alex

>
> Signed-off-by: jinlong zhang <jinlong.zhang@amd.com>
> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
> ---
>  drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> index 743042d5905a..cdcad82765e0 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> @@ -653,7 +653,7 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
>                                         if ((*payload->reply == AUX_TRANSACTION_REPLY_AUX_DEFER) ||
>                                                 (*payload->reply == AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER)) {
>                                                 if (payload->defer_delay > 0)
> -                                                       msleep(payload->defer_delay);
> +                                                       udelay(payload->defer_delay * 1000);
>                                         }
>                                 }
>                                 break;
> --
> 2.17.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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RE: [PATCH 04/15] drm/amd/display: Replace msleep with udelay while read edid return defer.

[Zhuo, Qingqing]

[AMD Official Use Only - Internal Distribution Only]

On Wed, Sep 16, 2020 at 3:42 PM Qingqing Zhuo <qingqing.zhuo@amd.com> wrote:
>
> From: jinlong zhang <jinlong.zhang@amd.com>
>
> [why]
> while read edid return defer, then it enter to msleep, but it actually 
> took more time during msleep, this will cause remaining edid read 
> fail.
>
> [how]
> Replacing msleep with udelay, it will not take any extra time, edid return pass finally.

How long of a delay are we talking about here?  Some platforms don't support long udelays and someone will send a patch to change this to msleep.

Alex

---------------------

Hi Alex,

It's between 0-5ms for generic cases, though there exist some dongle workaround cases where we will do 70ms. Would this be a concern?  

Thank you,
Lillian


>
> Signed-off-by: jinlong zhang <jinlong.zhang@amd.com>
> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
> ---
>  drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 
> b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> index 743042d5905a..cdcad82765e0 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> @@ -653,7 +653,7 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
>                                         if ((*payload->reply == AUX_TRANSACTION_REPLY_AUX_DEFER) ||
>                                                 (*payload->reply == AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER)) {
>                                                 if (payload->defer_delay > 0)
> -                                                       msleep(payload->defer_delay);
> +                                                       
> + udelay(payload->defer_delay * 1000);
>                                         }
>                                 }
>                                 break;
> --
> 2.17.1
>
> _______________________________________________
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> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
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> ngqing.zhuo%40amd.com%7C36c3bee68c28448769fa08d85a884619%7C3dd8961fe48
> 84e608e11a82d994e183d%7C0%7C0%7C637358888627498307&amp;sdata=mynpHpiup
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Re: [PATCH 04/15] drm/amd/display: Replace msleep with udelay while read edid return defer.

[Alex Deucher]

On Wed, Sep 16, 2020 at 6:16 PM Zhuo, Qingqing <Qingqing.Zhuo@amd.com> wrote:
>
> [AMD Official Use Only - Internal Distribution Only]
>
> On Wed, Sep 16, 2020 at 3:42 PM Qingqing Zhuo <qingqing.zhuo@amd.com> wrote:
> >
> > From: jinlong zhang <jinlong.zhang@amd.com>
> >
> > [why]
> > while read edid return defer, then it enter to msleep, but it actually
> > took more time during msleep, this will cause remaining edid read
> > fail.
> >
> > [how]
> > Replacing msleep with udelay, it will not take any extra time, edid return pass finally.
>
> How long of a delay are we talking about here?  Some platforms don't support long udelays and someone will send a patch to change this to msleep.
>
> Alex
>
> ---------------------
>
> Hi Alex,
>
> It's between 0-5ms for generic cases, though there exist some dongle workaround cases where we will do 70ms. Would this be a concern?

I think ARM has a limit of 2ms for udelay.

Alex

>
> Thank you,
> Lillian
>
>
> >
> > Signed-off-by: jinlong zhang <jinlong.zhang@amd.com>
> > Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
> > Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
> > ---
> >  drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> > b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> > index 743042d5905a..cdcad82765e0 100644
> > --- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> > +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> > @@ -653,7 +653,7 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
> >                                         if ((*payload->reply == AUX_TRANSACTION_REPLY_AUX_DEFER) ||
> >                                                 (*payload->reply == AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER)) {
> >                                                 if (payload->defer_delay > 0)
> > -                                                       msleep(payload->defer_delay);
> > +
> > + udelay(payload->defer_delay * 1000);
> >                                         }
> >                                 }
> >                                 break;
> > --
> > 2.17.1
> >
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
> > s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=02%7C01%7Cqi
> > ngqing.zhuo%40amd.com%7C36c3bee68c28448769fa08d85a884619%7C3dd8961fe48
> > 84e608e11a82d994e183d%7C0%7C0%7C637358888627498307&amp;sdata=mynpHpiup
> > J%2FU2o5gZNW%2Bft%2Fg2beFY86%2BzMRWoTZCghQ%3D&amp;reserved=0
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Re: [PATCH 04/15] drm/amd/display: Replace msleep with udelay while read edid return defer.

[Christian König]

Am 17.09.20 um 00:18 schrieb Alex Deucher:
> On Wed, Sep 16, 2020 at 6:16 PM Zhuo, Qingqing <Qingqing.Zhuo@amd.com> wrote:
>> [AMD Official Use Only - Internal Distribution Only]
>>
>> On Wed, Sep 16, 2020 at 3:42 PM Qingqing Zhuo <qingqing.zhuo@amd.com> wrote:
>>> From: jinlong zhang <jinlong.zhang@amd.com>
>>>
>>> [why]
>>> while read edid return defer, then it enter to msleep, but it actually
>>> took more time during msleep, this will cause remaining edid read
>>> fail.
>>>
>>> [how]
>>> Replacing msleep with udelay, it will not take any extra time, edid return pass finally.
>> How long of a delay are we talking about here?  Some platforms don't support long udelays and someone will send a patch to change this to msleep.
>>
>> Alex
>>
>> ---------------------
>>
>> Hi Alex,
>>
>> It's between 0-5ms for generic cases, though there exist some dongle workaround cases where we will do 70ms. Would this be a concern?
> I think ARM has a limit of 2ms for udelay.

Yeah, there is even a define somewhere for this.

If you need a delay which is longer than this but still more precise 
than msleep() then there is the high precision timer sleep as alternative.

I've forgotten the function name to use here, but there was a LWN 
article about this a few years ago. You just need to google a bit.

Regards,
Christian.

>
> Alex
>
>> Thank you,
>> Lillian
>>
>>
>>> Signed-off-by: jinlong zhang <jinlong.zhang@amd.com>
>>> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
>>> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
>>> ---
>>>   drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 2 +-
>>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
>>> b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
>>> index 743042d5905a..cdcad82765e0 100644
>>> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
>>> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
>>> @@ -653,7 +653,7 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
>>>                                          if ((*payload->reply == AUX_TRANSACTION_REPLY_AUX_DEFER) ||
>>>                                                  (*payload->reply == AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER)) {
>>>                                                  if (payload->defer_delay > 0)
>>> -                                                       msleep(payload->defer_delay);
>>> +
>>> + udelay(payload->defer_delay * 1000);
>>>                                          }
>>>                                  }
>>>                                  break;
>>> --
>>> 2.17.1
>>>
>>> _______________________________________________
>>> amd-gfx mailing list
>>> amd-gfx@lists.freedesktop.org
>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
>>> s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=02%7C01%7Cqi
>>> ngqing.zhuo%40amd.com%7C36c3bee68c28448769fa08d85a884619%7C3dd8961fe48
>>> 84e608e11a82d994e183d%7C0%7C0%7C637358888627498307&amp;sdata=mynpHpiup
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Re: [PATCH 04/15] drm/amd/display: Replace msleep with udelay while read edid return defer.

[Alex Deucher]

On Thu, Sep 17, 2020 at 4:26 AM Christian König
<ckoenig.leichtzumerken@gmail.com> wrote:
>
> Am 17.09.20 um 00:18 schrieb Alex Deucher:
> > On Wed, Sep 16, 2020 at 6:16 PM Zhuo, Qingqing <Qingqing.Zhuo@amd.com> wrote:
> >> [AMD Official Use Only - Internal Distribution Only]
> >>
> >> On Wed, Sep 16, 2020 at 3:42 PM Qingqing Zhuo <qingqing.zhuo@amd.com> wrote:
> >>> From: jinlong zhang <jinlong.zhang@amd.com>
> >>>
> >>> [why]
> >>> while read edid return defer, then it enter to msleep, but it actually
> >>> took more time during msleep, this will cause remaining edid read
> >>> fail.
> >>>
> >>> [how]
> >>> Replacing msleep with udelay, it will not take any extra time, edid return pass finally.
> >> How long of a delay are we talking about here?  Some platforms don't support long udelays and someone will send a patch to change this to msleep.
> >>
> >> Alex
> >>
> >> ---------------------
> >>
> >> Hi Alex,
> >>
> >> It's between 0-5ms for generic cases, though there exist some dongle workaround cases where we will do 70ms. Would this be a concern?
> > I think ARM has a limit of 2ms for udelay.
>
> Yeah, there is even a define somewhere for this.
>
> If you need a delay which is longer than this but still more precise
> than msleep() then there is the high precision timer sleep as alternative.
>
> I've forgotten the function name to use here, but there was a LWN
> article about this a few years ago. You just need to google a bit.

I think usleep_range() is what you want.

Alex

>
> Regards,
> Christian.
>
> >
> > Alex
> >
> >> Thank you,
> >> Lillian
> >>
> >>
> >>> Signed-off-by: jinlong zhang <jinlong.zhang@amd.com>
> >>> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
> >>> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
> >>> ---
> >>>   drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 2 +-
> >>>   1 file changed, 1 insertion(+), 1 deletion(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> >>> b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> >>> index 743042d5905a..cdcad82765e0 100644
> >>> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> >>> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> >>> @@ -653,7 +653,7 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
> >>>                                          if ((*payload->reply == AUX_TRANSACTION_REPLY_AUX_DEFER) ||
> >>>                                                  (*payload->reply == AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER)) {
> >>>                                                  if (payload->defer_delay > 0)
> >>> -                                                       msleep(payload->defer_delay);
> >>> +
> >>> + udelay(payload->defer_delay * 1000);
> >>>                                          }
> >>>                                  }
> >>>                                  break;
> >>> --
> >>> 2.17.1
> >>>
> >>> _______________________________________________
> >>> amd-gfx mailing list
> >>> amd-gfx@lists.freedesktop.org
> >>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
> >>> s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=02%7C01%7Cqi
> >>> ngqing.zhuo%40amd.com%7C36c3bee68c28448769fa08d85a884619%7C3dd8961fe48
> >>> 84e608e11a82d994e183d%7C0%7C0%7C637358888627498307&amp;sdata=mynpHpiup
> >>> J%2FU2o5gZNW%2Bft%2Fg2beFY86%2BzMRWoTZCghQ%3D&amp;reserved=0
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
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RE: [PATCH 04/15] drm/amd/display: Replace msleep with udelay while read edid return defer.

[Zhuo, Qingqing]

[AMD Official Use Only - Internal Distribution Only]

Am 17.09.20 um 00:18 schrieb Alex Deucher:
>> On Wed, Sep 16, 2020 at 6:16 PM Zhuo, Qingqing <Qingqing.Zhuo@amd.com> wrote:
>>> [AMD Official Use Only - Internal Distribution Only]
>>>
>>>On Wed, Sep 16, 2020 at 3:42 PM Qingqing Zhuo <qingqing.zhuo@amd.com> wrote:
>>>> From: jinlong zhang <jinlong.zhang@amd.com>
>>>>
>>> >[why]
>>>>while read edid return defer, then it enter to msleep, but it 
>>>>actually took more time during msleep, this will cause remaining 
>>>>edid read fail.
>>>>
>>>> [how]
>>>> Replacing msleep with udelay, it will not take any extra time, edid return pass finally.
>>> How long of a delay are we talking about here?  Some platforms don't support long udelays and someone will send a patch to change this to msleep.
>>>
>>> Alex
>>>
>>> ---------------------
>>>
>>> Hi Alex,
>>>
>>> It's between 0-5ms for generic cases, though there exist some dongle workaround cases where we will do 70ms. Would this be a concern?
>> I think ARM has a limit of 2ms for udelay.

> Yeah, there is even a define somewhere for this.

> If you need a delay which is longer than this but still more precise than msleep() then there is the high precision timer sleep as alternative.

> I've forgotten the function name to use here, but there was a LWN article about this a few years ago. You just need to google a bit.

Hi Alex and Christian,

Thanks a lot for the input! Given what's been discussed, I will drop this patch for now.

Regards,
Lillian

>
> Regards,
> Christian.
>>
>> Alex
>>
>>> Thank you,
>>> Lillian
>>>
>>>
>>>> Signed-off-by: jinlong zhang <jinlong.zhang@amd.com>
>>>> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
>>>> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
>>>> ---
>>>> drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 2 +-
>>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
>>>> b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
>>>> index 743042d5905a..cdcad82765e0 100644
>>>> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
>>>> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
>>>> @@ -653,7 +653,7 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
>>>>                                          if ((*payload->reply == AUX_TRANSACTION_REPLY_AUX_DEFER) ||
>>>>                                                  (*payload->reply == AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER)) {
>>>>                                                  if (payload->defer_delay > 0)
>>>> -                                                       msleep(payload->defer_delay);
>>>> +
>>>> + udelay(payload->defer_delay * 1000);
>>>>                                          }
>>>>                                  }
>>>>                                  break;
>>>> --
>>>> 2.17.1
>>>>
>>>> _______________________________________________
>>>> amd-gfx mailing list
>>>> amd-gfx@lists.freedesktop.org
>>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fli
>>>> st 
>>>> s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=02%7C01%7C
>>>> qi
>>>> ngqing.zhuo%40amd.com%7C36c3bee68c28448769fa08d85a884619%7C3dd8961fe
>>>> 48 
>>>> 84e608e11a82d994e183d%7C0%7C0%7C637358888627498307&amp;sdata=mynpHpi
>>>> up
>>>> J%2FU2o5gZNW%2Bft%2Fg2beFY86%2BzMRWoTZCghQ%3D&amp;reserved=0
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
>> s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=02%7C01%7CQi
>> ngqing.Zhuo%40amd.com%7Cd4acd0d5e65c49a7270f08d85ae37036%7C3dd8961fe48
>> 84e608e11a82d994e183d%7C0%7C0%7C637359280197936127&amp;sdata=ahcoCqG91
>> EDMNlHNSk4Eimh1azMtRWSX%2BKyHCdpFq1Q%3D&amp;reserved=0
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH 04/15] drm/amd/display: Replace msleep with udelay while read edid return defer.

[Zhang, Jinlong]

HI Christian
While #include <linux/delay.h>, it prompt ..\..\..\..\..\dc\dce\dce_aux.c(31): fatal error C1083: Cannot open include file: 'linux/delay.h': No such file or directory
Could you help to check how to include the header of void usleep_range(unsigned long min, unsigned long max);

-----Original Message-----
From: Zhuo, Qingqing <Qingqing.Zhuo@amd.com> 
Sent: Thursday, September 17, 2020 9:02 PM
To: Koenig, Christian <Christian.Koenig@amd.com>; Alex Deucher <alexdeucher@gmail.com>
Cc: Brol, Eryk <Eryk.Brol@amd.com>; Li, Sun peng (Leo) <Sunpeng.Li@amd.com>; Lakha, Bhawanpreet <Bhawanpreet.Lakha@amd.com>; Siqueira, Rodrigo <Rodrigo.Siqueira@amd.com>; amd-gfx list <amd-gfx@lists.freedesktop.org>; Zhang, Jinlong <Jinlong.Zhang@amd.com>; Wentland, Harry <Harry.Wentland@amd.com>
Subject: RE: [PATCH 04/15] drm/amd/display: Replace msleep with udelay while read edid return defer.

[AMD Official Use Only - Internal Distribution Only]

Am 17.09.20 um 00:18 schrieb Alex Deucher:
>> On Wed, Sep 16, 2020 at 6:16 PM Zhuo, Qingqing <Qingqing.Zhuo@amd.com> wrote:
>>> [AMD Official Use Only - Internal Distribution Only]
>>>
>>>On Wed, Sep 16, 2020 at 3:42 PM Qingqing Zhuo <qingqing.zhuo@amd.com> wrote:
>>>> From: jinlong zhang <jinlong.zhang@amd.com>
>>>>
>>> >[why]
>>>>while read edid return defer, then it enter to msleep, but it 
>>>>actually took more time during msleep, this will cause remaining 
>>>>edid read fail.
>>>>
>>>> [how]
>>>> Replacing msleep with udelay, it will not take any extra time, edid return pass finally.
>>> How long of a delay are we talking about here?  Some platforms don't support long udelays and someone will send a patch to change this to msleep.
>>>
>>> Alex
>>>
>>> ---------------------
>>>
>>> Hi Alex,
>>>
>>> It's between 0-5ms for generic cases, though there exist some dongle workaround cases where we will do 70ms. Would this be a concern?
>> I think ARM has a limit of 2ms for udelay.

> Yeah, there is even a define somewhere for this.

> If you need a delay which is longer than this but still more precise than msleep() then there is the high precision timer sleep as alternative.

> I've forgotten the function name to use here, but there was a LWN article about this a few years ago. You just need to google a bit.

Hi Alex and Christian,

Thanks a lot for the input! Given what's been discussed, I will drop this patch for now.

Regards,
Lillian

>
> Regards,
> Christian.
>>
>> Alex
>>
>>> Thank you,
>>> Lillian
>>>
>>>
>>>> Signed-off-by: jinlong zhang <jinlong.zhang@amd.com>
>>>> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
>>>> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
>>>> ---
>>>> drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 2 +-
>>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
>>>> b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
>>>> index 743042d5905a..cdcad82765e0 100644
>>>> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
>>>> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
>>>> @@ -653,7 +653,7 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
>>>>                                          if ((*payload->reply == AUX_TRANSACTION_REPLY_AUX_DEFER) ||
>>>>                                                  (*payload->reply == AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER)) {
>>>>                                                  if (payload->defer_delay > 0)
>>>> -                                                       msleep(payload->defer_delay);
>>>> +
>>>> + udelay(payload->defer_delay * 1000);
>>>>                                          }
>>>>                                  }
>>>>                                  break;
>>>> --
>>>> 2.17.1
>>>>
>>>> _______________________________________________
>>>> amd-gfx mailing list
>>>> amd-gfx@lists.freedesktop.org
>>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fl
>>>> i
>>>> st
>>>> s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=02%7C01%7
>>>> C
>>>> qi
>>>> ngqing.zhuo%40amd.com%7C36c3bee68c28448769fa08d85a884619%7C3dd8961f
>>>> e
>>>> 48
>>>> 84e608e11a82d994e183d%7C0%7C0%7C637358888627498307&amp;sdata=mynpHp
>>>> i
>>>> up
>>>> J%2FU2o5gZNW%2Bft%2Fg2beFY86%2BzMRWoTZCghQ%3D&amp;reserved=0
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flis
>> t 
>> s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=02%7C01%7CQ
>> i
>> ngqing.Zhuo%40amd.com%7Cd4acd0d5e65c49a7270f08d85ae37036%7C3dd8961fe4
>> 8
>> 84e608e11a82d994e183d%7C0%7C0%7C637359280197936127&amp;sdata=ahcoCqG9
>> 1
>> EDMNlHNSk4Eimh1azMtRWSX%2BKyHCdpFq1Q%3D&amp;reserved=0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 04/15] drm/amd/display: Replace msleep with udelay while read edid return defer.

[Christian König]

No idea what that is. I can include delay.h just fine in the rest of the 
driver.

Must be something DC specific.

Regards,
Christian.

Am 17.09.20 um 16:39 schrieb Zhang, Jinlong:
> HI Christian
> While #include <linux/delay.h>, it prompt ..\..\..\..\..\dc\dce\dce_aux.c(31): fatal error C1083: Cannot open include file: 'linux/delay.h': No such file or directory
> Could you help to check how to include the header of void usleep_range(unsigned long min, unsigned long max);
>
> -----Original Message-----
> From: Zhuo, Qingqing <Qingqing.Zhuo@amd.com>
> Sent: Thursday, September 17, 2020 9:02 PM
> To: Koenig, Christian <Christian.Koenig@amd.com>; Alex Deucher <alexdeucher@gmail.com>
> Cc: Brol, Eryk <Eryk.Brol@amd.com>; Li, Sun peng (Leo) <Sunpeng.Li@amd.com>; Lakha, Bhawanpreet <Bhawanpreet.Lakha@amd.com>; Siqueira, Rodrigo <Rodrigo.Siqueira@amd.com>; amd-gfx list <amd-gfx@lists.freedesktop.org>; Zhang, Jinlong <Jinlong.Zhang@amd.com>; Wentland, Harry <Harry.Wentland@amd.com>
> Subject: RE: [PATCH 04/15] drm/amd/display: Replace msleep with udelay while read edid return defer.
>
> [AMD Official Use Only - Internal Distribution Only]
>
> Am 17.09.20 um 00:18 schrieb Alex Deucher:
>>> On Wed, Sep 16, 2020 at 6:16 PM Zhuo, Qingqing <Qingqing.Zhuo@amd.com> wrote:
>>>> [AMD Official Use Only - Internal Distribution Only]
>>>>
>>>> On Wed, Sep 16, 2020 at 3:42 PM Qingqing Zhuo <qingqing.zhuo@amd.com> wrote:
>>>>> From: jinlong zhang <jinlong.zhang@amd.com>
>>>>>
>>>>> [why]
>>>>> while read edid return defer, then it enter to msleep, but it
>>>>> actually took more time during msleep, this will cause remaining
>>>>> edid read fail.
>>>>>
>>>>> [how]
>>>>> Replacing msleep with udelay, it will not take any extra time, edid return pass finally.
>>>> How long of a delay are we talking about here?  Some platforms don't support long udelays and someone will send a patch to change this to msleep.
>>>>
>>>> Alex
>>>>
>>>> ---------------------
>>>>
>>>> Hi Alex,
>>>>
>>>> It's between 0-5ms for generic cases, though there exist some dongle workaround cases where we will do 70ms. Would this be a concern?
>>> I think ARM has a limit of 2ms for udelay.
>> Yeah, there is even a define somewhere for this.
>> If you need a delay which is longer than this but still more precise than msleep() then there is the high precision timer sleep as alternative.
>> I've forgotten the function name to use here, but there was a LWN article about this a few years ago. You just need to google a bit.
> Hi Alex and Christian,
>
> Thanks a lot for the input! Given what's been discussed, I will drop this patch for now.
>
> Regards,
> Lillian
>
>> Regards,
>> Christian.
>>> Alex
>>>
>>>> Thank you,
>>>> Lillian
>>>>
>>>>
>>>>> Signed-off-by: jinlong zhang <jinlong.zhang@amd.com>
>>>>> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
>>>>> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
>>>>> ---
>>>>> drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 2 +-
>>>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
>>>>> b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
>>>>> index 743042d5905a..cdcad82765e0 100644
>>>>> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
>>>>> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
>>>>> @@ -653,7 +653,7 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
>>>>>                                           if ((*payload->reply == AUX_TRANSACTION_REPLY_AUX_DEFER) ||
>>>>>                                                   (*payload->reply == AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER)) {
>>>>>                                                   if (payload->defer_delay > 0)
>>>>> -                                                       msleep(payload->defer_delay);
>>>>> +
>>>>> + udelay(payload->defer_delay * 1000);
>>>>>                                           }
>>>>>                                   }
>>>>>                                   break;
>>>>> --
>>>>> 2.17.1
>>>>>
>>>>> _______________________________________________
>>>>> amd-gfx mailing list
>>>>> amd-gfx@lists.freedesktop.org
>>>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fl
>>>>> i
>>>>> st
>>>>> s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=02%7C01%7
>>>>> C
>>>>> qi
>>>>> ngqing.zhuo%40amd.com%7C36c3bee68c28448769fa08d85a884619%7C3dd8961f
>>>>> e
>>>>> 48
>>>>> 84e608e11a82d994e183d%7C0%7C0%7C637358888627498307&amp;sdata=mynpHp
>>>>> i
>>>>> up
>>>>> J%2FU2o5gZNW%2Bft%2Fg2beFY86%2BzMRWoTZCghQ%3D&amp;reserved=0
>>> _______________________________________________
>>> amd-gfx mailing list
>>> amd-gfx@lists.freedesktop.org
>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flis
>>> t
>>> s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=02%7C01%7CQ
>>> i
>>> ngqing.Zhuo%40amd.com%7Cd4acd0d5e65c49a7270f08d85ae37036%7C3dd8961fe4
>>> 8
>>> 84e608e11a82d994e183d%7C0%7C0%7C637359280197936127&amp;sdata=ahcoCqG9
>>> 1
>>> EDMNlHNSk4Eimh1azMtRWSX%2BKyHCdpFq1Q%3D&amp;reserved=0

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 04/15] drm/amd/display: Replace msleep with udelay while read edid return defer.

[Alex Deucher]

On Thu, Sep 17, 2020 at 10:39 AM Zhang, Jinlong <Jinlong.Zhang@amd.com> wrote:
>
> HI Christian
> While #include <linux/delay.h>, it prompt ..\..\..\..\..\dc\dce\dce_aux.c(31): fatal error C1083: Cannot open include file: 'linux/delay.h': No such file or directory
> Could you help to check how to include the header of void usleep_range(unsigned long min, unsigned long max);

That should do it.  DC code has #include <linux/delay.h> in a bunch of
other files.

Alex

>
> -----Original Message-----
> From: Zhuo, Qingqing <Qingqing.Zhuo@amd.com>
> Sent: Thursday, September 17, 2020 9:02 PM
> To: Koenig, Christian <Christian.Koenig@amd.com>; Alex Deucher <alexdeucher@gmail.com>
> Cc: Brol, Eryk <Eryk.Brol@amd.com>; Li, Sun peng (Leo) <Sunpeng.Li@amd.com>; Lakha, Bhawanpreet <Bhawanpreet.Lakha@amd.com>; Siqueira, Rodrigo <Rodrigo.Siqueira@amd.com>; amd-gfx list <amd-gfx@lists.freedesktop.org>; Zhang, Jinlong <Jinlong.Zhang@amd.com>; Wentland, Harry <Harry.Wentland@amd.com>
> Subject: RE: [PATCH 04/15] drm/amd/display: Replace msleep with udelay while read edid return defer.
>
> [AMD Official Use Only - Internal Distribution Only]
>
> Am 17.09.20 um 00:18 schrieb Alex Deucher:
> >> On Wed, Sep 16, 2020 at 6:16 PM Zhuo, Qingqing <Qingqing.Zhuo@amd.com> wrote:
> >>> [AMD Official Use Only - Internal Distribution Only]
> >>>
> >>>On Wed, Sep 16, 2020 at 3:42 PM Qingqing Zhuo <qingqing.zhuo@amd.com> wrote:
> >>>> From: jinlong zhang <jinlong.zhang@amd.com>
> >>>>
> >>> >[why]
> >>>>while read edid return defer, then it enter to msleep, but it
> >>>>actually took more time during msleep, this will cause remaining
> >>>>edid read fail.
> >>>>
> >>>> [how]
> >>>> Replacing msleep with udelay, it will not take any extra time, edid return pass finally.
> >>> How long of a delay are we talking about here?  Some platforms don't support long udelays and someone will send a patch to change this to msleep.
> >>>
> >>> Alex
> >>>
> >>> ---------------------
> >>>
> >>> Hi Alex,
> >>>
> >>> It's between 0-5ms for generic cases, though there exist some dongle workaround cases where we will do 70ms. Would this be a concern?
> >> I think ARM has a limit of 2ms for udelay.
>
> > Yeah, there is even a define somewhere for this.
>
> > If you need a delay which is longer than this but still more precise than msleep() then there is the high precision timer sleep as alternative.
>
> > I've forgotten the function name to use here, but there was a LWN article about this a few years ago. You just need to google a bit.
>
> Hi Alex and Christian,
>
> Thanks a lot for the input! Given what's been discussed, I will drop this patch for now.
>
> Regards,
> Lillian
>
> >
> > Regards,
> > Christian.
> >>
> >> Alex
> >>
> >>> Thank you,
> >>> Lillian
> >>>
> >>>
> >>>> Signed-off-by: jinlong zhang <jinlong.zhang@amd.com>
> >>>> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
> >>>> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
> >>>> ---
> >>>> drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 2 +-
> >>>> 1 file changed, 1 insertion(+), 1 deletion(-)
> >>>>
> >>>> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> >>>> b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> >>>> index 743042d5905a..cdcad82765e0 100644
> >>>> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> >>>> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> >>>> @@ -653,7 +653,7 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
> >>>>                                          if ((*payload->reply == AUX_TRANSACTION_REPLY_AUX_DEFER) ||
> >>>>                                                  (*payload->reply == AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER)) {
> >>>>                                                  if (payload->defer_delay > 0)
> >>>> -                                                       msleep(payload->defer_delay);
> >>>> +
> >>>> + udelay(payload->defer_delay * 1000);
> >>>>                                          }
> >>>>                                  }
> >>>>                                  break;
> >>>> --
> >>>> 2.17.1
> >>>>
> >>>> _______________________________________________
> >>>> amd-gfx mailing list
> >>>> amd-gfx@lists.freedesktop.org
> >>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fl
> >>>> i
> >>>> st
> >>>> s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=02%7C01%7
> >>>> C
> >>>> qi
> >>>> ngqing.zhuo%40amd.com%7C36c3bee68c28448769fa08d85a884619%7C3dd8961f
> >>>> e
> >>>> 48
> >>>> 84e608e11a82d994e183d%7C0%7C0%7C637358888627498307&amp;sdata=mynpHp
> >>>> i
> >>>> up
> >>>> J%2FU2o5gZNW%2Bft%2Fg2beFY86%2BzMRWoTZCghQ%3D&amp;reserved=0
> >> _______________________________________________
> >> amd-gfx mailing list
> >> amd-gfx@lists.freedesktop.org
> >> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flis
> >> t
> >> s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=02%7C01%7CQ
> >> i
> >> ngqing.Zhuo%40amd.com%7Cd4acd0d5e65c49a7270f08d85ae37036%7C3dd8961fe4
> >> 8
> >> 84e608e11a82d994e183d%7C0%7C0%7C637359280197936127&amp;sdata=ahcoCqG9
> >> 1
> >> EDMNlHNSk4Eimh1azMtRWSX%2BKyHCdpFq1Q%3D&amp;reserved=0
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH 04/15] drm/amd/display: Replace msleep with udelay while read edid return defer.

[Zhuo, Qingqing]

[AMD Official Use Only - Internal Distribution Only]

Hi Jinlong,

This is a public thread for upstream review purpose mainly. Let's sync internally for your issue.

Thanks,
Lillian

-----Original Message-----
From: Koenig, Christian <Christian.Koenig@amd.com> 
Sent: Thursday, September 17, 2020 10:46 AM
To: Zhang, Jinlong <Jinlong.Zhang@amd.com>; Zhuo, Qingqing <Qingqing.Zhuo@amd.com>; Alex Deucher <alexdeucher@gmail.com>
Cc: Brol, Eryk <Eryk.Brol@amd.com>; Li, Sun peng (Leo) <Sunpeng.Li@amd.com>; Lakha, Bhawanpreet <Bhawanpreet.Lakha@amd.com>; Siqueira, Rodrigo <Rodrigo.Siqueira@amd.com>; amd-gfx list <amd-gfx@lists.freedesktop.org>; Wentland, Harry <Harry.Wentland@amd.com>
Subject: Re: [PATCH 04/15] drm/amd/display: Replace msleep with udelay while read edid return defer.

No idea what that is. I can include delay.h just fine in the rest of the driver.

Must be something DC specific.

Regards,
Christian.

Am 17.09.20 um 16:39 schrieb Zhang, Jinlong:
> HI Christian
> While #include <linux/delay.h>, it prompt 
> ..\..\..\..\..\dc\dce\dce_aux.c(31): fatal error C1083: Cannot open 
> include file: 'linux/delay.h': No such file or directory Could you 
> help to check how to include the header of void usleep_range(unsigned 
> long min, unsigned long max);
>
> -----Original Message-----
> From: Zhuo, Qingqing <Qingqing.Zhuo@amd.com>
> Sent: Thursday, September 17, 2020 9:02 PM
> To: Koenig, Christian <Christian.Koenig@amd.com>; Alex Deucher 
> <alexdeucher@gmail.com>
> Cc: Brol, Eryk <Eryk.Brol@amd.com>; Li, Sun peng (Leo) 
> <Sunpeng.Li@amd.com>; Lakha, Bhawanpreet <Bhawanpreet.Lakha@amd.com>; 
> Siqueira, Rodrigo <Rodrigo.Siqueira@amd.com>; amd-gfx list 
> <amd-gfx@lists.freedesktop.org>; Zhang, Jinlong 
> <Jinlong.Zhang@amd.com>; Wentland, Harry <Harry.Wentland@amd.com>
> Subject: RE: [PATCH 04/15] drm/amd/display: Replace msleep with udelay while read edid return defer.
>
> [AMD Official Use Only - Internal Distribution Only]
>
> Am 17.09.20 um 00:18 schrieb Alex Deucher:
>>> On Wed, Sep 16, 2020 at 6:16 PM Zhuo, Qingqing <Qingqing.Zhuo@amd.com> wrote:
>>>> [AMD Official Use Only - Internal Distribution Only]
>>>>
>>>> On Wed, Sep 16, 2020 at 3:42 PM Qingqing Zhuo <qingqing.zhuo@amd.com> wrote:
>>>>> From: jinlong zhang <jinlong.zhang@amd.com>
>>>>>
>>>>> [why]
>>>>> while read edid return defer, then it enter to msleep, but it 
>>>>> actually took more time during msleep, this will cause remaining 
>>>>> edid read fail.
>>>>>
>>>>> [how]
>>>>> Replacing msleep with udelay, it will not take any extra time, edid return pass finally.
>>>> How long of a delay are we talking about here?  Some platforms don't support long udelays and someone will send a patch to change this to msleep.
>>>>
>>>> Alex
>>>>
>>>> ---------------------
>>>>
>>>> Hi Alex,
>>>>
>>>> It's between 0-5ms for generic cases, though there exist some dongle workaround cases where we will do 70ms. Would this be a concern?
>>> I think ARM has a limit of 2ms for udelay.
>> Yeah, there is even a define somewhere for this.
>> If you need a delay which is longer than this but still more precise than msleep() then there is the high precision timer sleep as alternative.
>> I've forgotten the function name to use here, but there was a LWN article about this a few years ago. You just need to google a bit.
> Hi Alex and Christian,
>
> Thanks a lot for the input! Given what's been discussed, I will drop this patch for now.
>
> Regards,
> Lillian
>
>> Regards,
>> Christian.
>>> Alex
>>>
>>>> Thank you,
>>>> Lillian
>>>>
>>>>
>>>>> Signed-off-by: jinlong zhang <jinlong.zhang@amd.com>
>>>>> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
>>>>> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
>>>>> ---
>>>>> drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 2 +-
>>>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
>>>>> b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
>>>>> index 743042d5905a..cdcad82765e0 100644
>>>>> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
>>>>> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
>>>>> @@ -653,7 +653,7 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
>>>>>                                           if ((*payload->reply == AUX_TRANSACTION_REPLY_AUX_DEFER) ||
>>>>>                                                   (*payload->reply == AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER)) {
>>>>>                                                   if (payload->defer_delay > 0)
>>>>> -                                                       msleep(payload->defer_delay);
>>>>> +
>>>>> + udelay(payload->defer_delay * 1000);
>>>>>                                           }
>>>>>                                   }
>>>>>                                   break;
>>>>> --
>>>>> 2.17.1
>>>>>
>>>>> _______________________________________________
>>>>> amd-gfx mailing list
>>>>> amd-gfx@lists.freedesktop.org
>>>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2F
>>>>> l
>>>>> i
>>>>> st
>>>>> s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=02%7C01%
>>>>> 7
>>>>> C
>>>>> qi
>>>>> ngqing.zhuo%40amd.com%7C36c3bee68c28448769fa08d85a884619%7C3dd8961
>>>>> f
>>>>> e
>>>>> 48
>>>>> 84e608e11a82d994e183d%7C0%7C0%7C637358888627498307&amp;sdata=mynpH
>>>>> p
>>>>> i
>>>>> up
>>>>> J%2FU2o5gZNW%2Bft%2Fg2beFY86%2BzMRWoTZCghQ%3D&amp;reserved=0
>>> _______________________________________________
>>> amd-gfx mailing list
>>> amd-gfx@lists.freedesktop.org
>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fli
>>> s
>>> t
>>> s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=02%7C01%7C
>>> Q
>>> i
>>> ngqing.Zhuo%40amd.com%7Cd4acd0d5e65c49a7270f08d85ae37036%7C3dd8961fe
>>> 4
>>> 8
>>> 84e608e11a82d994e183d%7C0%7C0%7C637359280197936127&amp;sdata=ahcoCqG
>>> 9
>>> 1
>>> EDMNlHNSk4Eimh1azMtRWSX%2BKyHCdpFq1Q%3D&amp;reserved=0
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Re: [PATCH 08/15] drm/amd/display: Increase timeout for DP Disable

[Sasha Levin]

Hi

[This is an automated email]

This commit has been processed because it contains a -stable tag.
The stable tag indicates that it's relevant for the following trees: all

The bot has tested the following trees: v5.8.10, v5.4.66, v4.19.146, v4.14.198, v4.9.236, v4.4.236.

v5.8.10: Build OK!
v5.4.66: Build OK!
v4.19.146: Failed to apply! Possible dependencies:
    3af91bb15093 ("drm/amd/display: Increase DP blank timeout from 30 ms to 50 ms")

v4.14.198: Failed to apply! Possible dependencies:
    0c41891c81c0 ("drm/amd/display: Refactor stream encoder for HW review")
    1b0c0f9dc5ca ("drm/amdgpu: move userptr BOs to CPU domain during CS v2")
    3fe89771cb0a ("drm/amdgpu: stop reserving the BO in the MMU callback v3")
    4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
    587cdfe9463e ("drm/amd/display: Rename trasnform to dpp for dcn's")
    5aff86c1b325 ("drm/amd/display: Implement input gamma LUT")
    60de1c1740f3 ("drm/amdgpu: use a rw_semaphore for MMU notifiers")
    70ccab604049 ("drm/amdgpu/display: Add core dc support for DCN")
    9a18999640fa ("drm/amdgpu: move MMU notifier related defines to amdgpu_mn.h")
    9a70eba7f2c6 ("drm/amd/display: consolidate dce8-11.2 display clock code")
    9cca0b8e5df0 ("drm/amdgpu: move amdgpu_cs_sysvm_access_required into find_mapping")
    a216ab09955d ("drm/amdgpu: fix userptr put_page handling")
    b1a4eb992c17 ("drm/amd/display: enable diags compilation")
    b51adc77e220 ("drm/amd/display: Only blank DCN when we have set_blank implementation")
    b72cf4fca2bb ("drm/amdgpu: move taking mmap_sem into get_user_pages v2")
    ca666a3c298f ("drm/amdgpu: stop using BO status for user pages")

v4.9.236: Failed to apply! Possible dependencies:
    0c41891c81c0 ("drm/amd/display: Refactor stream encoder for HW review")
    1cec20f0ea0e ("dma-buf: Restart reservation_object_wait_timeout_rcu() after writes")
    248a1d6f1ac4 ("drm/amd: fix include notation and remove -Iinclude/drm flag")
    4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
    587cdfe9463e ("drm/amd/display: Rename trasnform to dpp for dcn's")
    5aff86c1b325 ("drm/amd/display: Implement input gamma LUT")
    70ccab604049 ("drm/amdgpu/display: Add core dc support for DCN")
    78010cd9736e ("dma-buf/fence: add an lockdep_assert_held()")
    9a70eba7f2c6 ("drm/amd/display: consolidate dce8-11.2 display clock code")
    b1a4eb992c17 ("drm/amd/display: enable diags compilation")
    b51adc77e220 ("drm/amd/display: Only blank DCN when we have set_blank implementation")
    f54d1867005c ("dma-buf: Rename struct fence to dma_fence")
    fedf54132d24 ("dma-buf: Restart reservation_object_get_fences_rcu() after writes")

v4.4.236: Failed to apply! Possible dependencies:
    0c41891c81c0 ("drm/amd/display: Refactor stream encoder for HW review")
    0f477c6dea70 ("staging/android/sync: add sync_fence_create_dma")
    1f7371b2a5fa ("drm/amd/powerplay: add basic powerplay framework")
    248a1d6f1ac4 ("drm/amd: fix include notation and remove -Iinclude/drm flag")
    288912cb95d1 ("drm/amdgpu: use $(src) in Makefile (v2)")
    375fb53ec1be ("staging: android: replace explicit NULL comparison")
    395dec6f6bc5 ("Documentation: add doc for sync_file_get_fence()")
    4325198180e5 ("drm/amdgpu: remove GART page addr array")
    4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
    587cdfe9463e ("drm/amd/display: Rename trasnform to dpp for dcn's")
    5aff86c1b325 ("drm/amd/display: Implement input gamma LUT")
    62304fb1fc08 ("dma-buf/sync_file: de-stage sync_file")
    70ccab604049 ("drm/amdgpu/display: Add core dc support for DCN")
    9a70eba7f2c6 ("drm/amd/display: consolidate dce8-11.2 display clock code")
    a1d29476d666 ("drm/amdgpu: optionally enable GART debugfs file")
    a8fe58cec351 ("drm/amd: add ACP driver support")
    b1a4eb992c17 ("drm/amd/display: enable diags compilation")
    b51adc77e220 ("drm/amd/display: Only blank DCN when we have set_blank implementation")
    b70f014d58b9 ("drm/amdgpu: change default sched jobs to 32")
    c784c82a3fd6 ("Documentation: add Sync File doc")
    d4cab38e153d ("staging/android: prepare sync_file for de-staging")
    d7fdb0ae9d11 ("staging/android: rename sync_fence to sync_file")
    f54d1867005c ("dma-buf: Rename struct fence to dma_fence")
    fac8434dab96 ("Documentation: Fix some grammar mistakes in sync_file.txt")
    fdba11f4079e ("drm/amdgpu: move all Kconfig options to amdgpu/Kconfig")


NOTE: The patch will not be queued to stable trees until it is upstream.

How should we proceed with this patch?

-- 
Thanks
Sasha

Re: [PATCH 08/15] drm/amd/display: Increase timeout for DP Disable

[Sasha Levin]

Hi

[This is an automated email]

This commit has been processed because it contains a -stable tag.
The stable tag indicates that it's relevant for the following trees: all

The bot has tested the following trees: v5.8.10, v5.4.66, v4.19.146, v4.14.198, v4.9.236, v4.4.236.

v5.8.10: Build OK!
v5.4.66: Build OK!
v4.19.146: Failed to apply! Possible dependencies:
    3af91bb15093 ("drm/amd/display: Increase DP blank timeout from 30 ms to 50 ms")

v4.14.198: Failed to apply! Possible dependencies:
    0c41891c81c0 ("drm/amd/display: Refactor stream encoder for HW review")
    1b0c0f9dc5ca ("drm/amdgpu: move userptr BOs to CPU domain during CS v2")
    3fe89771cb0a ("drm/amdgpu: stop reserving the BO in the MMU callback v3")
    4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
    587cdfe9463e ("drm/amd/display: Rename trasnform to dpp for dcn's")
    5aff86c1b325 ("drm/amd/display: Implement input gamma LUT")
    60de1c1740f3 ("drm/amdgpu: use a rw_semaphore for MMU notifiers")
    70ccab604049 ("drm/amdgpu/display: Add core dc support for DCN")
    9a18999640fa ("drm/amdgpu: move MMU notifier related defines to amdgpu_mn.h")
    9a70eba7f2c6 ("drm/amd/display: consolidate dce8-11.2 display clock code")
    9cca0b8e5df0 ("drm/amdgpu: move amdgpu_cs_sysvm_access_required into find_mapping")
    a216ab09955d ("drm/amdgpu: fix userptr put_page handling")
    b1a4eb992c17 ("drm/amd/display: enable diags compilation")
    b51adc77e220 ("drm/amd/display: Only blank DCN when we have set_blank implementation")
    b72cf4fca2bb ("drm/amdgpu: move taking mmap_sem into get_user_pages v2")
    ca666a3c298f ("drm/amdgpu: stop using BO status for user pages")

v4.9.236: Failed to apply! Possible dependencies:
    0c41891c81c0 ("drm/amd/display: Refactor stream encoder for HW review")
    1cec20f0ea0e ("dma-buf: Restart reservation_object_wait_timeout_rcu() after writes")
    248a1d6f1ac4 ("drm/amd: fix include notation and remove -Iinclude/drm flag")
    4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
    587cdfe9463e ("drm/amd/display: Rename trasnform to dpp for dcn's")
    5aff86c1b325 ("drm/amd/display: Implement input gamma LUT")
    70ccab604049 ("drm/amdgpu/display: Add core dc support for DCN")
    78010cd9736e ("dma-buf/fence: add an lockdep_assert_held()")
    9a70eba7f2c6 ("drm/amd/display: consolidate dce8-11.2 display clock code")
    b1a4eb992c17 ("drm/amd/display: enable diags compilation")
    b51adc77e220 ("drm/amd/display: Only blank DCN when we have set_blank implementation")
    f54d1867005c ("dma-buf: Rename struct fence to dma_fence")
    fedf54132d24 ("dma-buf: Restart reservation_object_get_fences_rcu() after writes")

v4.4.236: Failed to apply! Possible dependencies:
    0c41891c81c0 ("drm/amd/display: Refactor stream encoder for HW review")
    0f477c6dea70 ("staging/android/sync: add sync_fence_create_dma")
    1f7371b2a5fa ("drm/amd/powerplay: add basic powerplay framework")
    248a1d6f1ac4 ("drm/amd: fix include notation and remove -Iinclude/drm flag")
    288912cb95d1 ("drm/amdgpu: use $(src) in Makefile (v2)")
    375fb53ec1be ("staging: android: replace explicit NULL comparison")
    395dec6f6bc5 ("Documentation: add doc for sync_file_get_fence()")
    4325198180e5 ("drm/amdgpu: remove GART page addr array")
    4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
    587cdfe9463e ("drm/amd/display: Rename trasnform to dpp for dcn's")
    5aff86c1b325 ("drm/amd/display: Implement input gamma LUT")
    62304fb1fc08 ("dma-buf/sync_file: de-stage sync_file")
    70ccab604049 ("drm/amdgpu/display: Add core dc support for DCN")
    9a70eba7f2c6 ("drm/amd/display: consolidate dce8-11.2 display clock code")
    a1d29476d666 ("drm/amdgpu: optionally enable GART debugfs file")
    a8fe58cec351 ("drm/amd: add ACP driver support")
    b1a4eb992c17 ("drm/amd/display: enable diags compilation")
    b51adc77e220 ("drm/amd/display: Only blank DCN when we have set_blank implementation")
    b70f014d58b9 ("drm/amdgpu: change default sched jobs to 32")
    c784c82a3fd6 ("Documentation: add Sync File doc")
    d4cab38e153d ("staging/android: prepare sync_file for de-staging")
    d7fdb0ae9d11 ("staging/android: rename sync_fence to sync_file")
    f54d1867005c ("dma-buf: Rename struct fence to dma_fence")
    fac8434dab96 ("Documentation: Fix some grammar mistakes in sync_file.txt")
    fdba11f4079e ("drm/amdgpu: move all Kconfig options to amdgpu/Kconfig")


NOTE: The patch will not be queued to stable trees until it is upstream.

How should we proceed with this patch?

-- 
Thanks
Sasha
_______________________________________________
amd-gfx mailing list
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Re: [PATCH 01/15] drm/amd/display: Fix incorrect backlight register offset for DCN

[Sasha Levin]

Hi

[This is an automated email]

This commit has been processed because it contains a -stable tag.
The stable tag indicates that it's relevant for the following trees: all

The bot has tested the following trees: v5.8.10, v5.4.66, v4.19.146, v4.14.198, v4.9.236, v4.4.236.

v5.4.66: Failed to apply! Possible dependencies:
    2b77dcc5e5aa ("drm/amd/display: rename core_dc to dc")
    48af9b91b129 ("drm/amd/display: Don't allocate payloads if link lost")
    4c1a1335dfe0 ("drm/amd/display: Driverside changes to support PSR in DMCUB")
    7f7652ee8c8c ("drm/amd/display: enable single dp seamless boot")
    904fb6e0f4e8 ("drm/amd/display: move panel power seq to new panel struct")
    9ae1b27f31d0 ("drm/amd/display: fix hotplug during display off")
    9dac88d8792a ("drm/amd/display: Add driver support for enabling PSR on DMCUB")
    ab4a4072f260 ("drm/amd/display: exit PSR during detection")
    d4252eee1f7c ("drm/amd/display: Add debugfs entry to force YUV420 output")
    d462fcf5012b ("drm/amd/display: Update hdcp display config")
    e0d08a40a63b ("drm/amd/display: Add debugfs entry for reading psr state")
    e78a312f81c8 ("drm/amd/display: use requested_dispclk_khz instead of clk")
    ef5a7d266e82 ("drm/amd/display: skip enable stream on disconnected display")

v4.19.146: Failed to apply! Possible dependencies:
    1f6010a96273 ("drm/amd/display: Improve spelling, grammar, and formatting of amdgpu_dm.c comments")
    813d20dccf93 ("drm/amd/display: Fix multi-thread writing to 1 state")
    8c3db1284a01 ("drm/amdgpu: fill in amdgpu_dm_remove_sink_from_freesync_module")
    904fb6e0f4e8 ("drm/amd/display: move panel power seq to new panel struct")
    98e6436d3af5 ("drm/amd/display: Refactor FreeSync module")
    a87fa9938749 ("drm/amd/display: Build stream update and plane updates in dm")
    a94d5569b232 ("drm/amd: Add DM DMCU support")
    b8592b48450b ("drm/amd/display: Initial documentation for AMDgpu DC")
    dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
    eb3dc8978596 ("drm/amd/display: Use private obj helpers for dm_atomic_state")

v4.14.198: Failed to apply! Possible dependencies:
    1296423bf23c ("drm/amd/display: define DC_LOGGER for logger")
    1b0c0f9dc5ca ("drm/amdgpu: move userptr BOs to CPU domain during CS v2")
    3fe89771cb0a ("drm/amdgpu: stop reserving the BO in the MMU callback v3")
    4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
    60de1c1740f3 ("drm/amdgpu: use a rw_semaphore for MMU notifiers")
    74c49c7ac14f ("drm/amdgpu/display: Add calcs code for DCN")
    904fb6e0f4e8 ("drm/amd/display: move panel power seq to new panel struct")
    9a18999640fa ("drm/amdgpu: move MMU notifier related defines to amdgpu_mn.h")
    9cca0b8e5df0 ("drm/amdgpu: move amdgpu_cs_sysvm_access_required into find_mapping")
    a216ab09955d ("drm/amdgpu: fix userptr put_page handling")
    b72cf4fca2bb ("drm/amdgpu: move taking mmap_sem into get_user_pages v2")
    ca666a3c298f ("drm/amdgpu: stop using BO status for user pages")
    dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
    f3efec54ed6a ("drm/amd/display: Allow option to use worst-case watermark")

v4.9.236: Failed to apply! Possible dependencies:
    1296423bf23c ("drm/amd/display: define DC_LOGGER for logger")
    1cec20f0ea0e ("dma-buf: Restart reservation_object_wait_timeout_rcu() after writes")
    248a1d6f1ac4 ("drm/amd: fix include notation and remove -Iinclude/drm flag")
    4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
    74c49c7ac14f ("drm/amdgpu/display: Add calcs code for DCN")
    78010cd9736e ("dma-buf/fence: add an lockdep_assert_held()")
    904fb6e0f4e8 ("drm/amd/display: move panel power seq to new panel struct")
    dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
    f3efec54ed6a ("drm/amd/display: Allow option to use worst-case watermark")
    f54d1867005c ("dma-buf: Rename struct fence to dma_fence")
    fedf54132d24 ("dma-buf: Restart reservation_object_get_fences_rcu() after writes")

v4.4.236: Failed to apply! Possible dependencies:
    0f477c6dea70 ("staging/android/sync: add sync_fence_create_dma")
    1296423bf23c ("drm/amd/display: define DC_LOGGER for logger")
    1f7371b2a5fa ("drm/amd/powerplay: add basic powerplay framework")
    248a1d6f1ac4 ("drm/amd: fix include notation and remove -Iinclude/drm flag")
    288912cb95d1 ("drm/amdgpu: use $(src) in Makefile (v2)")
    375fb53ec1be ("staging: android: replace explicit NULL comparison")
    395dec6f6bc5 ("Documentation: add doc for sync_file_get_fence()")
    4325198180e5 ("drm/amdgpu: remove GART page addr array")
    4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
    62304fb1fc08 ("dma-buf/sync_file: de-stage sync_file")
    74c49c7ac14f ("drm/amdgpu/display: Add calcs code for DCN")
    904fb6e0f4e8 ("drm/amd/display: move panel power seq to new panel struct")
    a1d29476d666 ("drm/amdgpu: optionally enable GART debugfs file")
    a8fe58cec351 ("drm/amd: add ACP driver support")
    b70f014d58b9 ("drm/amdgpu: change default sched jobs to 32")
    c784c82a3fd6 ("Documentation: add Sync File doc")
    d4cab38e153d ("staging/android: prepare sync_file for de-staging")
    d7fdb0ae9d11 ("staging/android: rename sync_fence to sync_file")
    dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
    f3efec54ed6a ("drm/amd/display: Allow option to use worst-case watermark")
    f54d1867005c ("dma-buf: Rename struct fence to dma_fence")
    fac8434dab96 ("Documentation: Fix some grammar mistakes in sync_file.txt")
    fdba11f4079e ("drm/amdgpu: move all Kconfig options to amdgpu/Kconfig")


NOTE: The patch will not be queued to stable trees until it is upstream.

How should we proceed with this patch?

-- 
Thanks
Sasha

Re: [PATCH 01/15] drm/amd/display: Fix incorrect backlight register offset for DCN

[Sasha Levin]

Hi

[This is an automated email]

This commit has been processed because it contains a -stable tag.
The stable tag indicates that it's relevant for the following trees: all

The bot has tested the following trees: v5.8.10, v5.4.66, v4.19.146, v4.14.198, v4.9.236, v4.4.236.

v5.4.66: Failed to apply! Possible dependencies:
    2b77dcc5e5aa ("drm/amd/display: rename core_dc to dc")
    48af9b91b129 ("drm/amd/display: Don't allocate payloads if link lost")
    4c1a1335dfe0 ("drm/amd/display: Driverside changes to support PSR in DMCUB")
    7f7652ee8c8c ("drm/amd/display: enable single dp seamless boot")
    904fb6e0f4e8 ("drm/amd/display: move panel power seq to new panel struct")
    9ae1b27f31d0 ("drm/amd/display: fix hotplug during display off")
    9dac88d8792a ("drm/amd/display: Add driver support for enabling PSR on DMCUB")
    ab4a4072f260 ("drm/amd/display: exit PSR during detection")
    d4252eee1f7c ("drm/amd/display: Add debugfs entry to force YUV420 output")
    d462fcf5012b ("drm/amd/display: Update hdcp display config")
    e0d08a40a63b ("drm/amd/display: Add debugfs entry for reading psr state")
    e78a312f81c8 ("drm/amd/display: use requested_dispclk_khz instead of clk")
    ef5a7d266e82 ("drm/amd/display: skip enable stream on disconnected display")

v4.19.146: Failed to apply! Possible dependencies:
    1f6010a96273 ("drm/amd/display: Improve spelling, grammar, and formatting of amdgpu_dm.c comments")
    813d20dccf93 ("drm/amd/display: Fix multi-thread writing to 1 state")
    8c3db1284a01 ("drm/amdgpu: fill in amdgpu_dm_remove_sink_from_freesync_module")
    904fb6e0f4e8 ("drm/amd/display: move panel power seq to new panel struct")
    98e6436d3af5 ("drm/amd/display: Refactor FreeSync module")
    a87fa9938749 ("drm/amd/display: Build stream update and plane updates in dm")
    a94d5569b232 ("drm/amd: Add DM DMCU support")
    b8592b48450b ("drm/amd/display: Initial documentation for AMDgpu DC")
    dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
    eb3dc8978596 ("drm/amd/display: Use private obj helpers for dm_atomic_state")

v4.14.198: Failed to apply! Possible dependencies:
    1296423bf23c ("drm/amd/display: define DC_LOGGER for logger")
    1b0c0f9dc5ca ("drm/amdgpu: move userptr BOs to CPU domain during CS v2")
    3fe89771cb0a ("drm/amdgpu: stop reserving the BO in the MMU callback v3")
    4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
    60de1c1740f3 ("drm/amdgpu: use a rw_semaphore for MMU notifiers")
    74c49c7ac14f ("drm/amdgpu/display: Add calcs code for DCN")
    904fb6e0f4e8 ("drm/amd/display: move panel power seq to new panel struct")
    9a18999640fa ("drm/amdgpu: move MMU notifier related defines to amdgpu_mn.h")
    9cca0b8e5df0 ("drm/amdgpu: move amdgpu_cs_sysvm_access_required into find_mapping")
    a216ab09955d ("drm/amdgpu: fix userptr put_page handling")
    b72cf4fca2bb ("drm/amdgpu: move taking mmap_sem into get_user_pages v2")
    ca666a3c298f ("drm/amdgpu: stop using BO status for user pages")
    dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
    f3efec54ed6a ("drm/amd/display: Allow option to use worst-case watermark")

v4.9.236: Failed to apply! Possible dependencies:
    1296423bf23c ("drm/amd/display: define DC_LOGGER for logger")
    1cec20f0ea0e ("dma-buf: Restart reservation_object_wait_timeout_rcu() after writes")
    248a1d6f1ac4 ("drm/amd: fix include notation and remove -Iinclude/drm flag")
    4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
    74c49c7ac14f ("drm/amdgpu/display: Add calcs code for DCN")
    78010cd9736e ("dma-buf/fence: add an lockdep_assert_held()")
    904fb6e0f4e8 ("drm/amd/display: move panel power seq to new panel struct")
    dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
    f3efec54ed6a ("drm/amd/display: Allow option to use worst-case watermark")
    f54d1867005c ("dma-buf: Rename struct fence to dma_fence")
    fedf54132d24 ("dma-buf: Restart reservation_object_get_fences_rcu() after writes")

v4.4.236: Failed to apply! Possible dependencies:
    0f477c6dea70 ("staging/android/sync: add sync_fence_create_dma")
    1296423bf23c ("drm/amd/display: define DC_LOGGER for logger")
    1f7371b2a5fa ("drm/amd/powerplay: add basic powerplay framework")
    248a1d6f1ac4 ("drm/amd: fix include notation and remove -Iinclude/drm flag")
    288912cb95d1 ("drm/amdgpu: use $(src) in Makefile (v2)")
    375fb53ec1be ("staging: android: replace explicit NULL comparison")
    395dec6f6bc5 ("Documentation: add doc for sync_file_get_fence()")
    4325198180e5 ("drm/amdgpu: remove GART page addr array")
    4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
    62304fb1fc08 ("dma-buf/sync_file: de-stage sync_file")
    74c49c7ac14f ("drm/amdgpu/display: Add calcs code for DCN")
    904fb6e0f4e8 ("drm/amd/display: move panel power seq to new panel struct")
    a1d29476d666 ("drm/amdgpu: optionally enable GART debugfs file")
    a8fe58cec351 ("drm/amd: add ACP driver support")
    b70f014d58b9 ("drm/amdgpu: change default sched jobs to 32")
    c784c82a3fd6 ("Documentation: add Sync File doc")
    d4cab38e153d ("staging/android: prepare sync_file for de-staging")
    d7fdb0ae9d11 ("staging/android: rename sync_fence to sync_file")
    dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
    f3efec54ed6a ("drm/amd/display: Allow option to use worst-case watermark")
    f54d1867005c ("dma-buf: Rename struct fence to dma_fence")
    fac8434dab96 ("Documentation: Fix some grammar mistakes in sync_file.txt")
    fdba11f4079e ("drm/amdgpu: move all Kconfig options to amdgpu/Kconfig")


NOTE: The patch will not be queued to stable trees until it is upstream.

How should we proceed with this patch?

-- 
Thanks
Sasha
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 07/15] drm/amd/display: Fix ODM policy implementation

[Sasha Levin]

Hi

[This is an automated email]

This commit has been processed because it contains a -stable tag.
The stable tag indicates that it's relevant for the following trees: all

The bot has tested the following trees: v5.8.10, v5.4.66, v4.19.146, v4.14.198, v4.9.236, v4.4.236.

v5.4.66: Failed to apply! Possible dependencies:
    2b77dcc5e5aa ("drm/amd/display: rename core_dc to dc")
    48af9b91b129 ("drm/amd/display: Don't allocate payloads if link lost")
    4c1a1335dfe0 ("drm/amd/display: Driverside changes to support PSR in DMCUB")
    7f7652ee8c8c ("drm/amd/display: enable single dp seamless boot")
    904fb6e0f4e8 ("drm/amd/display: move panel power seq to new panel struct")
    9ae1b27f31d0 ("drm/amd/display: fix hotplug during display off")
    9dac88d8792a ("drm/amd/display: Add driver support for enabling PSR on DMCUB")
    ab4a4072f260 ("drm/amd/display: exit PSR during detection")
    b739ab3a4fe6 ("drm/amd/display: Fix incorrect backlight register offset for DCN")
    d4252eee1f7c ("drm/amd/display: Add debugfs entry to force YUV420 output")
    d462fcf5012b ("drm/amd/display: Update hdcp display config")
    e0d08a40a63b ("drm/amd/display: Add debugfs entry for reading psr state")
    e78a312f81c8 ("drm/amd/display: use requested_dispclk_khz instead of clk")
    ef5a7d266e82 ("drm/amd/display: skip enable stream on disconnected display")

v4.19.146: Failed to apply! Possible dependencies:
    1f6010a96273 ("drm/amd/display: Improve spelling, grammar, and formatting of amdgpu_dm.c comments")
    813d20dccf93 ("drm/amd/display: Fix multi-thread writing to 1 state")
    8c3db1284a01 ("drm/amdgpu: fill in amdgpu_dm_remove_sink_from_freesync_module")
    904fb6e0f4e8 ("drm/amd/display: move panel power seq to new panel struct")
    98e6436d3af5 ("drm/amd/display: Refactor FreeSync module")
    a87fa9938749 ("drm/amd/display: Build stream update and plane updates in dm")
    a94d5569b232 ("drm/amd: Add DM DMCU support")
    b739ab3a4fe6 ("drm/amd/display: Fix incorrect backlight register offset for DCN")
    b8592b48450b ("drm/amd/display: Initial documentation for AMDgpu DC")
    dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
    eb3dc8978596 ("drm/amd/display: Use private obj helpers for dm_atomic_state")

v4.14.198: Failed to apply! Possible dependencies:
    1296423bf23c ("drm/amd/display: define DC_LOGGER for logger")
    1b0c0f9dc5ca ("drm/amdgpu: move userptr BOs to CPU domain during CS v2")
    3fe89771cb0a ("drm/amdgpu: stop reserving the BO in the MMU callback v3")
    4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
    60de1c1740f3 ("drm/amdgpu: use a rw_semaphore for MMU notifiers")
    74c49c7ac14f ("drm/amdgpu/display: Add calcs code for DCN")
    904fb6e0f4e8 ("drm/amd/display: move panel power seq to new panel struct")
    9a18999640fa ("drm/amdgpu: move MMU notifier related defines to amdgpu_mn.h")
    9cca0b8e5df0 ("drm/amdgpu: move amdgpu_cs_sysvm_access_required into find_mapping")
    a216ab09955d ("drm/amdgpu: fix userptr put_page handling")
    b72cf4fca2bb ("drm/amdgpu: move taking mmap_sem into get_user_pages v2")
    b739ab3a4fe6 ("drm/amd/display: Fix incorrect backlight register offset for DCN")
    ca666a3c298f ("drm/amdgpu: stop using BO status for user pages")
    dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
    f3efec54ed6a ("drm/amd/display: Allow option to use worst-case watermark")

v4.9.236: Failed to apply! Possible dependencies:
    1296423bf23c ("drm/amd/display: define DC_LOGGER for logger")
    1cec20f0ea0e ("dma-buf: Restart reservation_object_wait_timeout_rcu() after writes")
    248a1d6f1ac4 ("drm/amd: fix include notation and remove -Iinclude/drm flag")
    4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
    74c49c7ac14f ("drm/amdgpu/display: Add calcs code for DCN")
    78010cd9736e ("dma-buf/fence: add an lockdep_assert_held()")
    904fb6e0f4e8 ("drm/amd/display: move panel power seq to new panel struct")
    b739ab3a4fe6 ("drm/amd/display: Fix incorrect backlight register offset for DCN")
    dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
    f3efec54ed6a ("drm/amd/display: Allow option to use worst-case watermark")
    f54d1867005c ("dma-buf: Rename struct fence to dma_fence")
    fedf54132d24 ("dma-buf: Restart reservation_object_get_fences_rcu() after writes")

v4.4.236: Failed to apply! Possible dependencies:
    0f477c6dea70 ("staging/android/sync: add sync_fence_create_dma")
    1296423bf23c ("drm/amd/display: define DC_LOGGER for logger")
    1f7371b2a5fa ("drm/amd/powerplay: add basic powerplay framework")
    248a1d6f1ac4 ("drm/amd: fix include notation and remove -Iinclude/drm flag")
    288912cb95d1 ("drm/amdgpu: use $(src) in Makefile (v2)")
    375fb53ec1be ("staging: android: replace explicit NULL comparison")
    395dec6f6bc5 ("Documentation: add doc for sync_file_get_fence()")
    4325198180e5 ("drm/amdgpu: remove GART page addr array")
    4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
    62304fb1fc08 ("dma-buf/sync_file: de-stage sync_file")
    74c49c7ac14f ("drm/amdgpu/display: Add calcs code for DCN")
    904fb6e0f4e8 ("drm/amd/display: move panel power seq to new panel struct")
    a1d29476d666 ("drm/amdgpu: optionally enable GART debugfs file")
    a8fe58cec351 ("drm/amd: add ACP driver support")
    b70f014d58b9 ("drm/amdgpu: change default sched jobs to 32")
    b739ab3a4fe6 ("drm/amd/display: Fix incorrect backlight register offset for DCN")
    c784c82a3fd6 ("Documentation: add Sync File doc")
    d4cab38e153d ("staging/android: prepare sync_file for de-staging")
    d7fdb0ae9d11 ("staging/android: rename sync_fence to sync_file")
    dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
    f3efec54ed6a ("drm/amd/display: Allow option to use worst-case watermark")
    f54d1867005c ("dma-buf: Rename struct fence to dma_fence")
    fac8434dab96 ("Documentation: Fix some grammar mistakes in sync_file.txt")
    fdba11f4079e ("drm/amdgpu: move all Kconfig options to amdgpu/Kconfig")


NOTE: The patch will not be queued to stable trees until it is upstream.

How should we proceed with this patch?

-- 
Thanks
Sasha

Re: [PATCH 07/15] drm/amd/display: Fix ODM policy implementation

[Sasha Levin]

Hi

[This is an automated email]

This commit has been processed because it contains a -stable tag.
The stable tag indicates that it's relevant for the following trees: all

The bot has tested the following trees: v5.8.10, v5.4.66, v4.19.146, v4.14.198, v4.9.236, v4.4.236.

v5.4.66: Failed to apply! Possible dependencies:
    2b77dcc5e5aa ("drm/amd/display: rename core_dc to dc")
    48af9b91b129 ("drm/amd/display: Don't allocate payloads if link lost")
    4c1a1335dfe0 ("drm/amd/display: Driverside changes to support PSR in DMCUB")
    7f7652ee8c8c ("drm/amd/display: enable single dp seamless boot")
    904fb6e0f4e8 ("drm/amd/display: move panel power seq to new panel struct")
    9ae1b27f31d0 ("drm/amd/display: fix hotplug during display off")
    9dac88d8792a ("drm/amd/display: Add driver support for enabling PSR on DMCUB")
    ab4a4072f260 ("drm/amd/display: exit PSR during detection")
    b739ab3a4fe6 ("drm/amd/display: Fix incorrect backlight register offset for DCN")
    d4252eee1f7c ("drm/amd/display: Add debugfs entry to force YUV420 output")
    d462fcf5012b ("drm/amd/display: Update hdcp display config")
    e0d08a40a63b ("drm/amd/display: Add debugfs entry for reading psr state")
    e78a312f81c8 ("drm/amd/display: use requested_dispclk_khz instead of clk")
    ef5a7d266e82 ("drm/amd/display: skip enable stream on disconnected display")

v4.19.146: Failed to apply! Possible dependencies:
    1f6010a96273 ("drm/amd/display: Improve spelling, grammar, and formatting of amdgpu_dm.c comments")
    813d20dccf93 ("drm/amd/display: Fix multi-thread writing to 1 state")
    8c3db1284a01 ("drm/amdgpu: fill in amdgpu_dm_remove_sink_from_freesync_module")
    904fb6e0f4e8 ("drm/amd/display: move panel power seq to new panel struct")
    98e6436d3af5 ("drm/amd/display: Refactor FreeSync module")
    a87fa9938749 ("drm/amd/display: Build stream update and plane updates in dm")
    a94d5569b232 ("drm/amd: Add DM DMCU support")
    b739ab3a4fe6 ("drm/amd/display: Fix incorrect backlight register offset for DCN")
    b8592b48450b ("drm/amd/display: Initial documentation for AMDgpu DC")
    dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
    eb3dc8978596 ("drm/amd/display: Use private obj helpers for dm_atomic_state")

v4.14.198: Failed to apply! Possible dependencies:
    1296423bf23c ("drm/amd/display: define DC_LOGGER for logger")
    1b0c0f9dc5ca ("drm/amdgpu: move userptr BOs to CPU domain during CS v2")
    3fe89771cb0a ("drm/amdgpu: stop reserving the BO in the MMU callback v3")
    4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
    60de1c1740f3 ("drm/amdgpu: use a rw_semaphore for MMU notifiers")
    74c49c7ac14f ("drm/amdgpu/display: Add calcs code for DCN")
    904fb6e0f4e8 ("drm/amd/display: move panel power seq to new panel struct")
    9a18999640fa ("drm/amdgpu: move MMU notifier related defines to amdgpu_mn.h")
    9cca0b8e5df0 ("drm/amdgpu: move amdgpu_cs_sysvm_access_required into find_mapping")
    a216ab09955d ("drm/amdgpu: fix userptr put_page handling")
    b72cf4fca2bb ("drm/amdgpu: move taking mmap_sem into get_user_pages v2")
    b739ab3a4fe6 ("drm/amd/display: Fix incorrect backlight register offset for DCN")
    ca666a3c298f ("drm/amdgpu: stop using BO status for user pages")
    dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
    f3efec54ed6a ("drm/amd/display: Allow option to use worst-case watermark")

v4.9.236: Failed to apply! Possible dependencies:
    1296423bf23c ("drm/amd/display: define DC_LOGGER for logger")
    1cec20f0ea0e ("dma-buf: Restart reservation_object_wait_timeout_rcu() after writes")
    248a1d6f1ac4 ("drm/amd: fix include notation and remove -Iinclude/drm flag")
    4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
    74c49c7ac14f ("drm/amdgpu/display: Add calcs code for DCN")
    78010cd9736e ("dma-buf/fence: add an lockdep_assert_held()")
    904fb6e0f4e8 ("drm/amd/display: move panel power seq to new panel struct")
    b739ab3a4fe6 ("drm/amd/display: Fix incorrect backlight register offset for DCN")
    dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
    f3efec54ed6a ("drm/amd/display: Allow option to use worst-case watermark")
    f54d1867005c ("dma-buf: Rename struct fence to dma_fence")
    fedf54132d24 ("dma-buf: Restart reservation_object_get_fences_rcu() after writes")

v4.4.236: Failed to apply! Possible dependencies:
    0f477c6dea70 ("staging/android/sync: add sync_fence_create_dma")
    1296423bf23c ("drm/amd/display: define DC_LOGGER for logger")
    1f7371b2a5fa ("drm/amd/powerplay: add basic powerplay framework")
    248a1d6f1ac4 ("drm/amd: fix include notation and remove -Iinclude/drm flag")
    288912cb95d1 ("drm/amdgpu: use $(src) in Makefile (v2)")
    375fb53ec1be ("staging: android: replace explicit NULL comparison")
    395dec6f6bc5 ("Documentation: add doc for sync_file_get_fence()")
    4325198180e5 ("drm/amdgpu: remove GART page addr array")
    4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
    62304fb1fc08 ("dma-buf/sync_file: de-stage sync_file")
    74c49c7ac14f ("drm/amdgpu/display: Add calcs code for DCN")
    904fb6e0f4e8 ("drm/amd/display: move panel power seq to new panel struct")
    a1d29476d666 ("drm/amdgpu: optionally enable GART debugfs file")
    a8fe58cec351 ("drm/amd: add ACP driver support")
    b70f014d58b9 ("drm/amdgpu: change default sched jobs to 32")
    b739ab3a4fe6 ("drm/amd/display: Fix incorrect backlight register offset for DCN")
    c784c82a3fd6 ("Documentation: add Sync File doc")
    d4cab38e153d ("staging/android: prepare sync_file for de-staging")
    d7fdb0ae9d11 ("staging/android: rename sync_fence to sync_file")
    dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
    f3efec54ed6a ("drm/amd/display: Allow option to use worst-case watermark")
    f54d1867005c ("dma-buf: Rename struct fence to dma_fence")
    fac8434dab96 ("Documentation: Fix some grammar mistakes in sync_file.txt")
    fdba11f4079e ("drm/amdgpu: move all Kconfig options to amdgpu/Kconfig")


NOTE: The patch will not be queued to stable trees until it is upstream.

How should we proceed with this patch?

-- 
Thanks
Sasha
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx