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* [Intel-gfx] [PATCH 1/3] drm/i915: Extract intel_dp_output_format()
@ 2020-09-17 21:43 Ville Syrjala
  2020-09-17 21:43 ` [Intel-gfx] [PATCH 2/3] drm/i915: Decouple intel_dp_{min, output}_bpp() from crtc_state Ville Syrjala
                   ` (6 more replies)
  0 siblings, 7 replies; 14+ messages in thread
From: Ville Syrjala @ 2020-09-17 21:43 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Refactor the output_format calculation into a helper so that
we can reuse it for mode validation as well.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 32 +++++++++++++++----------
 1 file changed, 20 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index bf1e9cf1c0f3..ad9b8b16fadb 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -592,6 +592,22 @@ static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
 	return 0;
 }
 
+static enum intel_output_format
+intel_dp_output_format(struct drm_connector *connector,
+		       const struct drm_display_mode *mode)
+{
+	struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
+	const struct drm_display_info *info = &connector->display_info;
+
+	if (!drm_mode_is_420_only(info, mode))
+		return INTEL_OUTPUT_FORMAT_RGB;
+
+	if (intel_dp->dfp.ycbcr_444_to_420)
+		return INTEL_OUTPUT_FORMAT_YCBCR444;
+	else
+		return INTEL_OUTPUT_FORMAT_YCBCR420;
+}
+
 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
 				  int hdisplay)
 {
@@ -2430,27 +2446,20 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
 }
 
 static int
-intel_dp_ycbcr420_config(struct intel_dp *intel_dp,
-			 struct intel_crtc_state *crtc_state,
+intel_dp_ycbcr420_config(struct intel_crtc_state *crtc_state,
 			 const struct drm_connector_state *conn_state)
 {
 	struct drm_connector *connector = conn_state->connector;
-	const struct drm_display_info *info = &connector->display_info;
 	const struct drm_display_mode *adjusted_mode =
 		&crtc_state->hw.adjusted_mode;
 
 	if (!connector->ycbcr_420_allowed)
 		return 0;
 
-	if (!drm_mode_is_420_only(info, adjusted_mode))
-		return 0;
+	crtc_state->output_format = intel_dp_output_format(connector, adjusted_mode);
 
-	if (intel_dp->dfp.ycbcr_444_to_420) {
-		crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
+	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_YCBCR420)
 		return 0;
-	}
-
-	crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
 
 	return intel_pch_panel_fitting(crtc_state, conn_state);
 }
@@ -2710,8 +2719,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	if (lspcon->active)
 		lspcon_ycbcr420_config(&intel_connector->base, pipe_config);
 	else
-		ret = intel_dp_ycbcr420_config(intel_dp, pipe_config,
-					       conn_state);
+		ret = intel_dp_ycbcr420_config(pipe_config, conn_state);
 	if (ret)
 		return ret;
 
-- 
2.26.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 14+ messages in thread

* [Intel-gfx] [PATCH 2/3] drm/i915: Decouple intel_dp_{min, output}_bpp() from crtc_state
  2020-09-17 21:43 [Intel-gfx] [PATCH 1/3] drm/i915: Extract intel_dp_output_format() Ville Syrjala
@ 2020-09-17 21:43 ` Ville Syrjala
  2020-09-17 23:59   ` Navare, Manasi
  2020-09-18  5:01   ` Kulkarni, Vandita
  2020-09-17 21:43 ` [Intel-gfx] [PATCH 3/3] drm/i915: Use the correct bpp when validating "4:2:0 only" modes Ville Syrjala
                   ` (5 subsequent siblings)
  6 siblings, 2 replies; 14+ messages in thread
From: Ville Syrjala @ 2020-09-17 21:43 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Pass the output_format directly to intel_dp_{min,output}_bpp()
rather than passing in the crtc_state and digging out the
output_format inside the functions. This will allow us to reuse
the functions for mode validation purposes.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c     | 15 ++++++++-------
 drivers/gpu/drm/i915/display/intel_dp.h     |  3 ++-
 drivers/gpu/drm/i915/display/intel_dp_mst.c |  2 +-
 3 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index ad9b8b16fadb..aa4801a8123d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2111,14 +2111,14 @@ intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
 	}
 }
 
-static int intel_dp_output_bpp(const struct intel_crtc_state *crtc_state, int bpp)
+static int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
 {
 	/*
 	 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
 	 * format of the number of bytes per pixel will be half the number
 	 * of bytes of RGB pixel.
 	 */
-	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+	if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 		bpp /= 2;
 
 	return bpp;
@@ -2135,7 +2135,7 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
 	int mode_rate, link_clock, link_avail;
 
 	for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
-		int output_bpp = intel_dp_output_bpp(pipe_config, bpp);
+		int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
 
 		mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
 						   output_bpp);
@@ -2346,9 +2346,9 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 	return 0;
 }
 
-int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state)
+int intel_dp_min_bpp(enum intel_output_format output_format)
 {
-	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
+	if (output_format == INTEL_OUTPUT_FORMAT_RGB)
 		return 6 * 3;
 	else
 		return 8 * 3;
@@ -2379,7 +2379,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
 	limits.min_lane_count = 1;
 	limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
 
-	limits.min_bpp = intel_dp_min_bpp(pipe_config);
+	limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
 	limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config);
 
 	if (intel_dp_is_edp(intel_dp)) {
@@ -2765,7 +2765,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	if (pipe_config->dsc.compression_enable)
 		output_bpp = pipe_config->dsc.compressed_bpp;
 	else
-		output_bpp = intel_dp_output_bpp(pipe_config, pipe_config->pipe_bpp);
+		output_bpp = intel_dp_output_bpp(pipe_config->output_format,
+						 pipe_config->pipe_bpp);
 
 	intel_link_compute_m_n(output_bpp,
 			       pipe_config->lane_count,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 08a1c0aa8b94..a9580d1df35b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -10,6 +10,7 @@
 
 #include "i915_reg.h"
 
+enum intel_output_format;
 enum pipe;
 enum port;
 struct drm_connector_state;
@@ -35,7 +36,7 @@ void intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
 				       struct link_config_limits *limits);
 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
 				  const struct drm_connector_state *conn_state);
-int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state);
+int intel_dp_min_bpp(enum intel_output_format output_format);
 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
 			   i915_reg_t dp_reg, enum port port,
 			   enum pipe *pipe);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 64d885539e94..6a874b779b1f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -130,7 +130,7 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
 	limits.min_lane_count =
 	limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
 
-	limits.min_bpp = intel_dp_min_bpp(pipe_config);
+	limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
 	/*
 	 * FIXME: If all the streams can't fit into the link with
 	 * their current pipe_bpp we should reduce pipe_bpp across
-- 
2.26.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 14+ messages in thread

* [Intel-gfx] [PATCH 3/3] drm/i915: Use the correct bpp when validating "4:2:0 only" modes
  2020-09-17 21:43 [Intel-gfx] [PATCH 1/3] drm/i915: Extract intel_dp_output_format() Ville Syrjala
  2020-09-17 21:43 ` [Intel-gfx] [PATCH 2/3] drm/i915: Decouple intel_dp_{min, output}_bpp() from crtc_state Ville Syrjala
@ 2020-09-17 21:43 ` Ville Syrjala
  2020-09-18  0:01   ` Navare, Manasi
  2020-09-18  5:02   ` Kulkarni, Vandita
  2020-09-17 21:53 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/3] drm/i915: Extract intel_dp_output_format() Patchwork
                   ` (4 subsequent siblings)
  6 siblings, 2 replies; 14+ messages in thread
From: Ville Syrjala @ 2020-09-17 21:43 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

When validating a "YCbCr 4:2:0 only" mode we must take into
account the fact that we're going to be outputting YCbCr
4:2:0 or 4:4:4 (when a DP->HDMI protocol converter is doing
the 4:2:0 downsampling). For YCbCr 4:4:4 the minimum output
bpc is 8, for YCbCr 4:2:0 it'll be half that. The currently
hardcoded 6bpc is only correct for RGB 4:4:4, which we will
never use with these kinds of modes. Figure out what we're
going to output and use the correct min bpp value to validate
whether the link has sufficient bandwidth.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 55 +++++++++++++++----------
 1 file changed, 33 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index aa4801a8123d..54a4b81ea3ff 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -608,6 +608,37 @@ intel_dp_output_format(struct drm_connector *connector,
 		return INTEL_OUTPUT_FORMAT_YCBCR420;
 }
 
+int intel_dp_min_bpp(enum intel_output_format output_format)
+{
+	if (output_format == INTEL_OUTPUT_FORMAT_RGB)
+		return 6 * 3;
+	else
+		return 8 * 3;
+}
+
+static int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
+{
+	/*
+	 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
+	 * format of the number of bytes per pixel will be half the number
+	 * of bytes of RGB pixel.
+	 */
+	if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+		bpp /= 2;
+
+	return bpp;
+}
+
+static int
+intel_dp_mode_min_output_bpp(struct drm_connector *connector,
+			     const struct drm_display_mode *mode)
+{
+	enum intel_output_format output_format =
+		intel_dp_output_format(connector, mode);
+
+	return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
+}
+
 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
 				  int hdisplay)
 {
@@ -687,7 +718,8 @@ intel_dp_mode_valid(struct drm_connector *connector,
 	max_lanes = intel_dp_max_lane_count(intel_dp);
 
 	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
-	mode_rate = intel_dp_link_required(target_clock, 18);
+	mode_rate = intel_dp_link_required(target_clock,
+					   intel_dp_mode_min_output_bpp(connector, mode));
 
 	if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
 		return MODE_H_ILLEGAL;
@@ -2111,19 +2143,6 @@ intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
 	}
 }
 
-static int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
-{
-	/*
-	 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
-	 * format of the number of bytes per pixel will be half the number
-	 * of bytes of RGB pixel.
-	 */
-	if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
-		bpp /= 2;
-
-	return bpp;
-}
-
 /* Optimize link config in order: max bpp, min clock, min lanes */
 static int
 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
@@ -2346,14 +2365,6 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 	return 0;
 }
 
-int intel_dp_min_bpp(enum intel_output_format output_format)
-{
-	if (output_format == INTEL_OUTPUT_FORMAT_RGB)
-		return 6 * 3;
-	else
-		return 8 * 3;
-}
-
 static int
 intel_dp_compute_link_config(struct intel_encoder *encoder,
 			     struct intel_crtc_state *pipe_config,
-- 
2.26.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 14+ messages in thread

* [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/3] drm/i915: Extract intel_dp_output_format()
  2020-09-17 21:43 [Intel-gfx] [PATCH 1/3] drm/i915: Extract intel_dp_output_format() Ville Syrjala
  2020-09-17 21:43 ` [Intel-gfx] [PATCH 2/3] drm/i915: Decouple intel_dp_{min, output}_bpp() from crtc_state Ville Syrjala
  2020-09-17 21:43 ` [Intel-gfx] [PATCH 3/3] drm/i915: Use the correct bpp when validating "4:2:0 only" modes Ville Syrjala
@ 2020-09-17 21:53 ` Patchwork
  2020-09-17 23:57 ` [Intel-gfx] [PATCH 1/3] " Navare, Manasi
                   ` (3 subsequent siblings)
  6 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2020-09-17 21:53 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

== Series Details ==

Series: series starting with [1/3] drm/i915: Extract intel_dp_output_format()
URL   : https://patchwork.freedesktop.org/series/81815/
State : failure

== Summary ==

Applying: drm/i915: Extract intel_dp_output_format()
error: sha1 information is lacking or useless (drivers/gpu/drm/i915/display/intel_dp.c).
error: could not build fake ancestor
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0001 drm/i915: Extract intel_dp_output_format()
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".


_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [Intel-gfx] [PATCH 1/3] drm/i915: Extract intel_dp_output_format()
  2020-09-17 21:43 [Intel-gfx] [PATCH 1/3] drm/i915: Extract intel_dp_output_format() Ville Syrjala
                   ` (2 preceding siblings ...)
  2020-09-17 21:53 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/3] drm/i915: Extract intel_dp_output_format() Patchwork
@ 2020-09-17 23:57 ` Navare, Manasi
  2020-09-18 10:39   ` Ville Syrjälä
  2020-09-18  5:00 ` Kulkarni, Vandita
                   ` (2 subsequent siblings)
  6 siblings, 1 reply; 14+ messages in thread
From: Navare, Manasi @ 2020-09-17 23:57 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

On Fri, Sep 18, 2020 at 12:43:33AM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Refactor the output_format calculation into a helper so that
> we can reuse it for mode validation as well.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 32 +++++++++++++++----------
>  1 file changed, 20 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index bf1e9cf1c0f3..ad9b8b16fadb 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -592,6 +592,22 @@ static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
>  	return 0;
>  }
>  
> +static enum intel_output_format
> +intel_dp_output_format(struct drm_connector *connector,
> +		       const struct drm_display_mode *mode)
> +{
> +	struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
> +	const struct drm_display_info *info = &connector->display_info;
> +
> +	if (!drm_mode_is_420_only(info, mode))
> +		return INTEL_OUTPUT_FORMAT_RGB;
> +
> +	if (intel_dp->dfp.ycbcr_444_to_420)
> +		return INTEL_OUTPUT_FORMAT_YCBCR444;
> +	else
> +		return INTEL_OUTPUT_FORMAT_YCBCR420;
> +}
> +
>  static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
>  				  int hdisplay)
>  {
> @@ -2430,27 +2446,20 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
>  }
>  
>  static int
> -intel_dp_ycbcr420_config(struct intel_dp *intel_dp,
> -			 struct intel_crtc_state *crtc_state,
> +intel_dp_ycbcr420_config(struct intel_crtc_state *crtc_state,
>  			 const struct drm_connector_state *conn_state)
>  {
>  	struct drm_connector *connector = conn_state->connector;
> -	const struct drm_display_info *info = &connector->display_info;
>  	const struct drm_display_mode *adjusted_mode =
>  		&crtc_state->hw.adjusted_mode;
>  
>  	if (!connector->ycbcr_420_allowed)
>  		return 0;
>  
> -	if (!drm_mode_is_420_only(info, adjusted_mode))
> -		return 0;
> +	crtc_state->output_format = intel_dp_output_format(connector, adjusted_mode);

So by default if its not 420_only then we set it to RGB?

Manasi

>  
> -	if (intel_dp->dfp.ycbcr_444_to_420) {
> -		crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
> +	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_YCBCR420)
>  		return 0;
> -	}
> -
> -	crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
>  
>  	return intel_pch_panel_fitting(crtc_state, conn_state);
>  }
> @@ -2710,8 +2719,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>  	if (lspcon->active)
>  		lspcon_ycbcr420_config(&intel_connector->base, pipe_config);
>  	else
> -		ret = intel_dp_ycbcr420_config(intel_dp, pipe_config,
> -					       conn_state);
> +		ret = intel_dp_ycbcr420_config(pipe_config, conn_state);
>  	if (ret)
>  		return ret;
>  
> -- 
> 2.26.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [Intel-gfx] [PATCH 2/3] drm/i915: Decouple intel_dp_{min, output}_bpp() from crtc_state
  2020-09-17 21:43 ` [Intel-gfx] [PATCH 2/3] drm/i915: Decouple intel_dp_{min, output}_bpp() from crtc_state Ville Syrjala
@ 2020-09-17 23:59   ` Navare, Manasi
  2020-09-18  5:01   ` Kulkarni, Vandita
  1 sibling, 0 replies; 14+ messages in thread
From: Navare, Manasi @ 2020-09-17 23:59 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

On Fri, Sep 18, 2020 at 12:43:34AM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Pass the output_format directly to intel_dp_{min,output}_bpp()
> rather than passing in the crtc_state and digging out the
> output_format inside the functions. This will allow us to reuse
> the functions for mode validation purposes.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Looks good

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

Manasi

> ---
>  drivers/gpu/drm/i915/display/intel_dp.c     | 15 ++++++++-------
>  drivers/gpu/drm/i915/display/intel_dp.h     |  3 ++-
>  drivers/gpu/drm/i915/display/intel_dp_mst.c |  2 +-
>  3 files changed, 11 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index ad9b8b16fadb..aa4801a8123d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2111,14 +2111,14 @@ intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
>  	}
>  }
>  
> -static int intel_dp_output_bpp(const struct intel_crtc_state *crtc_state, int bpp)
> +static int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
>  {
>  	/*
>  	 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
>  	 * format of the number of bytes per pixel will be half the number
>  	 * of bytes of RGB pixel.
>  	 */
> -	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
> +	if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
>  		bpp /= 2;
>  
>  	return bpp;
> @@ -2135,7 +2135,7 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
>  	int mode_rate, link_clock, link_avail;
>  
>  	for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
> -		int output_bpp = intel_dp_output_bpp(pipe_config, bpp);
> +		int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
>  
>  		mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
>  						   output_bpp);
> @@ -2346,9 +2346,9 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
>  	return 0;
>  }
>  
> -int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state)
> +int intel_dp_min_bpp(enum intel_output_format output_format)
>  {
> -	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
> +	if (output_format == INTEL_OUTPUT_FORMAT_RGB)
>  		return 6 * 3;
>  	else
>  		return 8 * 3;
> @@ -2379,7 +2379,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
>  	limits.min_lane_count = 1;
>  	limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
>  
> -	limits.min_bpp = intel_dp_min_bpp(pipe_config);
> +	limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
>  	limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config);
>  
>  	if (intel_dp_is_edp(intel_dp)) {
> @@ -2765,7 +2765,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>  	if (pipe_config->dsc.compression_enable)
>  		output_bpp = pipe_config->dsc.compressed_bpp;
>  	else
> -		output_bpp = intel_dp_output_bpp(pipe_config, pipe_config->pipe_bpp);
> +		output_bpp = intel_dp_output_bpp(pipe_config->output_format,
> +						 pipe_config->pipe_bpp);
>  
>  	intel_link_compute_m_n(output_bpp,
>  			       pipe_config->lane_count,
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index 08a1c0aa8b94..a9580d1df35b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -10,6 +10,7 @@
>  
>  #include "i915_reg.h"
>  
> +enum intel_output_format;
>  enum pipe;
>  enum port;
>  struct drm_connector_state;
> @@ -35,7 +36,7 @@ void intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
>  				       struct link_config_limits *limits);
>  bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
>  				  const struct drm_connector_state *conn_state);
> -int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state);
> +int intel_dp_min_bpp(enum intel_output_format output_format);
>  bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
>  			   i915_reg_t dp_reg, enum port port,
>  			   enum pipe *pipe);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 64d885539e94..6a874b779b1f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -130,7 +130,7 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
>  	limits.min_lane_count =
>  	limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
>  
> -	limits.min_bpp = intel_dp_min_bpp(pipe_config);
> +	limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
>  	/*
>  	 * FIXME: If all the streams can't fit into the link with
>  	 * their current pipe_bpp we should reduce pipe_bpp across
> -- 
> 2.26.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [Intel-gfx] [PATCH 3/3] drm/i915: Use the correct bpp when validating "4:2:0 only" modes
  2020-09-17 21:43 ` [Intel-gfx] [PATCH 3/3] drm/i915: Use the correct bpp when validating "4:2:0 only" modes Ville Syrjala
@ 2020-09-18  0:01   ` Navare, Manasi
  2020-09-18  5:02   ` Kulkarni, Vandita
  1 sibling, 0 replies; 14+ messages in thread
From: Navare, Manasi @ 2020-09-18  0:01 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

On Fri, Sep 18, 2020 at 12:43:35AM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> When validating a "YCbCr 4:2:0 only" mode we must take into
> account the fact that we're going to be outputting YCbCr
> 4:2:0 or 4:4:4 (when a DP->HDMI protocol converter is doing
> the 4:2:0 downsampling). For YCbCr 4:4:4 the minimum output
> bpc is 8, for YCbCr 4:2:0 it'll be half that. The currently
> hardcoded 6bpc is only correct for RGB 4:4:4, which we will
> never use with these kinds of modes. Figure out what we're
> going to output and use the correct min bpp value to validate
> whether the link has sufficient bandwidth.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

Manasi

> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 55 +++++++++++++++----------
>  1 file changed, 33 insertions(+), 22 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index aa4801a8123d..54a4b81ea3ff 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -608,6 +608,37 @@ intel_dp_output_format(struct drm_connector *connector,
>  		return INTEL_OUTPUT_FORMAT_YCBCR420;
>  }
>  
> +int intel_dp_min_bpp(enum intel_output_format output_format)
> +{
> +	if (output_format == INTEL_OUTPUT_FORMAT_RGB)
> +		return 6 * 3;
> +	else
> +		return 8 * 3;
> +}
> +
> +static int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
> +{
> +	/*
> +	 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
> +	 * format of the number of bytes per pixel will be half the number
> +	 * of bytes of RGB pixel.
> +	 */
> +	if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
> +		bpp /= 2;
> +
> +	return bpp;
> +}
> +
> +static int
> +intel_dp_mode_min_output_bpp(struct drm_connector *connector,
> +			     const struct drm_display_mode *mode)
> +{
> +	enum intel_output_format output_format =
> +		intel_dp_output_format(connector, mode);
> +
> +	return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
> +}
> +
>  static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
>  				  int hdisplay)
>  {
> @@ -687,7 +718,8 @@ intel_dp_mode_valid(struct drm_connector *connector,
>  	max_lanes = intel_dp_max_lane_count(intel_dp);
>  
>  	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
> -	mode_rate = intel_dp_link_required(target_clock, 18);
> +	mode_rate = intel_dp_link_required(target_clock,
> +					   intel_dp_mode_min_output_bpp(connector, mode));
>  
>  	if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
>  		return MODE_H_ILLEGAL;
> @@ -2111,19 +2143,6 @@ intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
>  	}
>  }
>  
> -static int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
> -{
> -	/*
> -	 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
> -	 * format of the number of bytes per pixel will be half the number
> -	 * of bytes of RGB pixel.
> -	 */
> -	if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
> -		bpp /= 2;
> -
> -	return bpp;
> -}
> -
>  /* Optimize link config in order: max bpp, min clock, min lanes */
>  static int
>  intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
> @@ -2346,14 +2365,6 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
>  	return 0;
>  }
>  
> -int intel_dp_min_bpp(enum intel_output_format output_format)
> -{
> -	if (output_format == INTEL_OUTPUT_FORMAT_RGB)
> -		return 6 * 3;
> -	else
> -		return 8 * 3;
> -}
> -
>  static int
>  intel_dp_compute_link_config(struct intel_encoder *encoder,
>  			     struct intel_crtc_state *pipe_config,
> -- 
> 2.26.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [Intel-gfx] [PATCH 1/3] drm/i915: Extract intel_dp_output_format()
  2020-09-17 21:43 [Intel-gfx] [PATCH 1/3] drm/i915: Extract intel_dp_output_format() Ville Syrjala
                   ` (3 preceding siblings ...)
  2020-09-17 23:57 ` [Intel-gfx] [PATCH 1/3] " Navare, Manasi
@ 2020-09-18  5:00 ` Kulkarni, Vandita
  2020-09-18 14:27 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Extract intel_dp_output_format() (rev2) Patchwork
  2020-09-18 17:15 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
  6 siblings, 0 replies; 14+ messages in thread
From: Kulkarni, Vandita @ 2020-09-18  5:00 UTC (permalink / raw)
  To: Ville Syrjala, intel-gfx

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Friday, September 18, 2020 3:14 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 1/3] drm/i915: Extract intel_dp_output_format()
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Refactor the output_format calculation into a helper so that we can reuse it
> for mode validation as well.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Looks good to me.
Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>

Thanks,
Vandita
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 32 +++++++++++++++----------
>  1 file changed, 20 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index bf1e9cf1c0f3..ad9b8b16fadb 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -592,6 +592,22 @@ static u8 intel_dp_dsc_get_slice_count(struct
> intel_dp *intel_dp,
>  	return 0;
>  }
> 
> +static enum intel_output_format
> +intel_dp_output_format(struct drm_connector *connector,
> +		       const struct drm_display_mode *mode) {
> +	struct intel_dp *intel_dp =
> intel_attached_dp(to_intel_connector(connector));
> +	const struct drm_display_info *info = &connector->display_info;
> +
> +	if (!drm_mode_is_420_only(info, mode))
> +		return INTEL_OUTPUT_FORMAT_RGB;
> +
> +	if (intel_dp->dfp.ycbcr_444_to_420)
> +		return INTEL_OUTPUT_FORMAT_YCBCR444;
> +	else
> +		return INTEL_OUTPUT_FORMAT_YCBCR420;
> +}
> +
>  static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
>  				  int hdisplay)
>  {
> @@ -2430,27 +2446,20 @@ intel_dp_compute_link_config(struct
> intel_encoder *encoder,  }
> 
>  static int
> -intel_dp_ycbcr420_config(struct intel_dp *intel_dp,
> -			 struct intel_crtc_state *crtc_state,
> +intel_dp_ycbcr420_config(struct intel_crtc_state *crtc_state,
>  			 const struct drm_connector_state *conn_state)  {
>  	struct drm_connector *connector = conn_state->connector;
> -	const struct drm_display_info *info = &connector->display_info;
>  	const struct drm_display_mode *adjusted_mode =
>  		&crtc_state->hw.adjusted_mode;
> 
>  	if (!connector->ycbcr_420_allowed)
>  		return 0;
> 
> -	if (!drm_mode_is_420_only(info, adjusted_mode))
> -		return 0;
> +	crtc_state->output_format = intel_dp_output_format(connector,
> +adjusted_mode);
> 
> -	if (intel_dp->dfp.ycbcr_444_to_420) {
> -		crtc_state->output_format =
> INTEL_OUTPUT_FORMAT_YCBCR444;
> +	if (crtc_state->output_format !=
> INTEL_OUTPUT_FORMAT_YCBCR420)
>  		return 0;
> -	}
> -
> -	crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
> 
>  	return intel_pch_panel_fitting(crtc_state, conn_state);  } @@ -
> 2710,8 +2719,7 @@ intel_dp_compute_config(struct intel_encoder
> *encoder,
>  	if (lspcon->active)
>  		lspcon_ycbcr420_config(&intel_connector->base,
> pipe_config);
>  	else
> -		ret = intel_dp_ycbcr420_config(intel_dp, pipe_config,
> -					       conn_state);
> +		ret = intel_dp_ycbcr420_config(pipe_config, conn_state);
>  	if (ret)
>  		return ret;
> 
> --
> 2.26.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [Intel-gfx] [PATCH 2/3] drm/i915: Decouple intel_dp_{min, output}_bpp() from crtc_state
  2020-09-17 21:43 ` [Intel-gfx] [PATCH 2/3] drm/i915: Decouple intel_dp_{min, output}_bpp() from crtc_state Ville Syrjala
  2020-09-17 23:59   ` Navare, Manasi
@ 2020-09-18  5:01   ` Kulkarni, Vandita
  1 sibling, 0 replies; 14+ messages in thread
From: Kulkarni, Vandita @ 2020-09-18  5:01 UTC (permalink / raw)
  To: Ville Syrjala, intel-gfx

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Friday, September 18, 2020 3:14 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 2/3] drm/i915: Decouple intel_dp_{min,
> output}_bpp() from crtc_state
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Pass the output_format directly to intel_dp_{min,output}_bpp() rather than
> passing in the crtc_state and digging out the output_format inside the
> functions. This will allow us to reuse the functions for mode validation
> purposes.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Looks good to me.
Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>

Thanks,
Vandita
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c     | 15 ++++++++-------
>  drivers/gpu/drm/i915/display/intel_dp.h     |  3 ++-
>  drivers/gpu/drm/i915/display/intel_dp_mst.c |  2 +-
>  3 files changed, 11 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index ad9b8b16fadb..aa4801a8123d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2111,14 +2111,14 @@ intel_dp_adjust_compliance_config(struct
> intel_dp *intel_dp,
>  	}
>  }
> 
> -static int intel_dp_output_bpp(const struct intel_crtc_state *crtc_state, int
> bpp)
> +static int intel_dp_output_bpp(enum intel_output_format output_format,
> +int bpp)
>  {
>  	/*
>  	 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
>  	 * format of the number of bytes per pixel will be half the number
>  	 * of bytes of RGB pixel.
>  	 */
> -	if (crtc_state->output_format ==
> INTEL_OUTPUT_FORMAT_YCBCR420)
> +	if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
>  		bpp /= 2;
> 
>  	return bpp;
> @@ -2135,7 +2135,7 @@ intel_dp_compute_link_config_wide(struct
> intel_dp *intel_dp,
>  	int mode_rate, link_clock, link_avail;
> 
>  	for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
> -		int output_bpp = intel_dp_output_bpp(pipe_config, bpp);
> +		int output_bpp = intel_dp_output_bpp(pipe_config-
> >output_format,
> +bpp);
> 
>  		mode_rate = intel_dp_link_required(adjusted_mode-
> >crtc_clock,
>  						   output_bpp);
> @@ -2346,9 +2346,9 @@ static int intel_dp_dsc_compute_config(struct
> intel_dp *intel_dp,
>  	return 0;
>  }
> 
> -int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state)
> +int intel_dp_min_bpp(enum intel_output_format output_format)
>  {
> -	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
> +	if (output_format == INTEL_OUTPUT_FORMAT_RGB)
>  		return 6 * 3;
>  	else
>  		return 8 * 3;
> @@ -2379,7 +2379,7 @@ intel_dp_compute_link_config(struct
> intel_encoder *encoder,
>  	limits.min_lane_count = 1;
>  	limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
> 
> -	limits.min_bpp = intel_dp_min_bpp(pipe_config);
> +	limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
>  	limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config);
> 
>  	if (intel_dp_is_edp(intel_dp)) {
> @@ -2765,7 +2765,8 @@ intel_dp_compute_config(struct intel_encoder
> *encoder,
>  	if (pipe_config->dsc.compression_enable)
>  		output_bpp = pipe_config->dsc.compressed_bpp;
>  	else
> -		output_bpp = intel_dp_output_bpp(pipe_config,
> pipe_config->pipe_bpp);
> +		output_bpp = intel_dp_output_bpp(pipe_config-
> >output_format,
> +						 pipe_config->pipe_bpp);
> 
>  	intel_link_compute_m_n(output_bpp,
>  			       pipe_config->lane_count,
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
> b/drivers/gpu/drm/i915/display/intel_dp.h
> index 08a1c0aa8b94..a9580d1df35b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -10,6 +10,7 @@
> 
>  #include "i915_reg.h"
> 
> +enum intel_output_format;
>  enum pipe;
>  enum port;
>  struct drm_connector_state;
> @@ -35,7 +36,7 @@ void intel_dp_adjust_compliance_config(struct intel_dp
> *intel_dp,
>  				       struct link_config_limits *limits);  bool
> intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
>  				  const struct drm_connector_state
> *conn_state); -int intel_dp_min_bpp(const struct intel_crtc_state
> *crtc_state);
> +int intel_dp_min_bpp(enum intel_output_format output_format);
>  bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
>  			   i915_reg_t dp_reg, enum port port,
>  			   enum pipe *pipe);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 64d885539e94..6a874b779b1f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -130,7 +130,7 @@ static int intel_dp_mst_compute_config(struct
> intel_encoder *encoder,
>  	limits.min_lane_count =
>  	limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
> 
> -	limits.min_bpp = intel_dp_min_bpp(pipe_config);
> +	limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
>  	/*
>  	 * FIXME: If all the streams can't fit into the link with
>  	 * their current pipe_bpp we should reduce pipe_bpp across
> --
> 2.26.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [Intel-gfx] [PATCH 3/3] drm/i915: Use the correct bpp when validating "4:2:0 only" modes
  2020-09-17 21:43 ` [Intel-gfx] [PATCH 3/3] drm/i915: Use the correct bpp when validating "4:2:0 only" modes Ville Syrjala
  2020-09-18  0:01   ` Navare, Manasi
@ 2020-09-18  5:02   ` Kulkarni, Vandita
  1 sibling, 0 replies; 14+ messages in thread
From: Kulkarni, Vandita @ 2020-09-18  5:02 UTC (permalink / raw)
  To: Ville Syrjala, intel-gfx

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Friday, September 18, 2020 3:14 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 3/3] drm/i915: Use the correct bpp when
> validating "4:2:0 only" modes
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> When validating a "YCbCr 4:2:0 only" mode we must take into account the
> fact that we're going to be outputting YCbCr
> 4:2:0 or 4:4:4 (when a DP->HDMI protocol converter is doing the 4:2:0
> downsampling). For YCbCr 4:4:4 the minimum output bpc is 8, for YCbCr 4:2:0
> it'll be half that. The currently hardcoded 6bpc is only correct for RGB 4:4:4,
> which we will never use with these kinds of modes. Figure out what we're
> going to output and use the correct min bpp value to validate whether the
> link has sufficient bandwidth.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Looks good to me.
Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>

Thanks,
Vandita
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 55 +++++++++++++++----------
>  1 file changed, 33 insertions(+), 22 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index aa4801a8123d..54a4b81ea3ff 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -608,6 +608,37 @@ intel_dp_output_format(struct drm_connector
> *connector,
>  		return INTEL_OUTPUT_FORMAT_YCBCR420;
>  }
> 
> +int intel_dp_min_bpp(enum intel_output_format output_format) {
> +	if (output_format == INTEL_OUTPUT_FORMAT_RGB)
> +		return 6 * 3;
> +	else
> +		return 8 * 3;
> +}
> +
> +static int intel_dp_output_bpp(enum intel_output_format output_format,
> +int bpp) {
> +	/*
> +	 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
> +	 * format of the number of bytes per pixel will be half the number
> +	 * of bytes of RGB pixel.
> +	 */
> +	if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
> +		bpp /= 2;
> +
> +	return bpp;
> +}
> +
> +static int
> +intel_dp_mode_min_output_bpp(struct drm_connector *connector,
> +			     const struct drm_display_mode *mode) {
> +	enum intel_output_format output_format =
> +		intel_dp_output_format(connector, mode);
> +
> +	return intel_dp_output_bpp(output_format,
> +intel_dp_min_bpp(output_format)); }
> +
>  static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
>  				  int hdisplay)
>  {
> @@ -687,7 +718,8 @@ intel_dp_mode_valid(struct drm_connector
> *connector,
>  	max_lanes = intel_dp_max_lane_count(intel_dp);
> 
>  	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
> -	mode_rate = intel_dp_link_required(target_clock, 18);
> +	mode_rate = intel_dp_link_required(target_clock,
> +
> intel_dp_mode_min_output_bpp(connector, mode));
> 
>  	if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
>  		return MODE_H_ILLEGAL;
> @@ -2111,19 +2143,6 @@ intel_dp_adjust_compliance_config(struct
> intel_dp *intel_dp,
>  	}
>  }
> 
> -static int intel_dp_output_bpp(enum intel_output_format output_format,
> int bpp) -{
> -	/*
> -	 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
> -	 * format of the number of bytes per pixel will be half the number
> -	 * of bytes of RGB pixel.
> -	 */
> -	if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
> -		bpp /= 2;
> -
> -	return bpp;
> -}
> -
>  /* Optimize link config in order: max bpp, min clock, min lanes */  static int
> intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, @@ -2346,14
> +2365,6 @@ static int intel_dp_dsc_compute_config(struct intel_dp
> *intel_dp,
>  	return 0;
>  }
> 
> -int intel_dp_min_bpp(enum intel_output_format output_format) -{
> -	if (output_format == INTEL_OUTPUT_FORMAT_RGB)
> -		return 6 * 3;
> -	else
> -		return 8 * 3;
> -}
> -
>  static int
>  intel_dp_compute_link_config(struct intel_encoder *encoder,
>  			     struct intel_crtc_state *pipe_config,
> --
> 2.26.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [Intel-gfx] [PATCH 1/3] drm/i915: Extract intel_dp_output_format()
  2020-09-17 23:57 ` [Intel-gfx] [PATCH 1/3] " Navare, Manasi
@ 2020-09-18 10:39   ` Ville Syrjälä
  2020-09-18 18:49     ` Navare, Manasi
  0 siblings, 1 reply; 14+ messages in thread
From: Ville Syrjälä @ 2020-09-18 10:39 UTC (permalink / raw)
  To: Navare, Manasi; +Cc: intel-gfx

On Thu, Sep 17, 2020 at 04:57:09PM -0700, Navare, Manasi wrote:
> On Fri, Sep 18, 2020 at 12:43:33AM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Refactor the output_format calculation into a helper so that
> > we can reuse it for mode validation as well.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_dp.c | 32 +++++++++++++++----------
> >  1 file changed, 20 insertions(+), 12 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > index bf1e9cf1c0f3..ad9b8b16fadb 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -592,6 +592,22 @@ static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
> >  	return 0;
> >  }
> >  
> > +static enum intel_output_format
> > +intel_dp_output_format(struct drm_connector *connector,
> > +		       const struct drm_display_mode *mode)
> > +{
> > +	struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
> > +	const struct drm_display_info *info = &connector->display_info;
> > +
> > +	if (!drm_mode_is_420_only(info, mode))
> > +		return INTEL_OUTPUT_FORMAT_RGB;
> > +
> > +	if (intel_dp->dfp.ycbcr_444_to_420)
> > +		return INTEL_OUTPUT_FORMAT_YCBCR444;
> > +	else
> > +		return INTEL_OUTPUT_FORMAT_YCBCR420;
> > +}
> > +
> >  static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
> >  				  int hdisplay)
> >  {
> > @@ -2430,27 +2446,20 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
> >  }
> >  
> >  static int
> > -intel_dp_ycbcr420_config(struct intel_dp *intel_dp,
> > -			 struct intel_crtc_state *crtc_state,
> > +intel_dp_ycbcr420_config(struct intel_crtc_state *crtc_state,
> >  			 const struct drm_connector_state *conn_state)
> >  {
> >  	struct drm_connector *connector = conn_state->connector;
> > -	const struct drm_display_info *info = &connector->display_info;
> >  	const struct drm_display_mode *adjusted_mode =
> >  		&crtc_state->hw.adjusted_mode;
> >  
> >  	if (!connector->ycbcr_420_allowed)
> >  		return 0;
> >  
> > -	if (!drm_mode_is_420_only(info, adjusted_mode))
> > -		return 0;
> > +	crtc_state->output_format = intel_dp_output_format(connector, adjusted_mode);
> 
> So by default if its not 420_only then we set it to RGB?

Yes. The code is still a bit messy because we have three places where
we set this. Probably will try to unify it a bit more, and try to get
the lspcon stuff looking more like any other protocol converter.

Actually IIRC I noticed that some lspcon chips seem to have some
of the 1.3 protocol converter registers even though they only
advertise DPCD 1.2. Not yet sure how to handle that in the
cleanest way possible...

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 14+ messages in thread

* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Extract intel_dp_output_format() (rev2)
  2020-09-17 21:43 [Intel-gfx] [PATCH 1/3] drm/i915: Extract intel_dp_output_format() Ville Syrjala
                   ` (4 preceding siblings ...)
  2020-09-18  5:00 ` Kulkarni, Vandita
@ 2020-09-18 14:27 ` Patchwork
  2020-09-18 17:15 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
  6 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2020-09-18 14:27 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx


[-- Attachment #1.1: Type: text/plain, Size: 8976 bytes --]

== Series Details ==

Series: series starting with [1/3] drm/i915: Extract intel_dp_output_format() (rev2)
URL   : https://patchwork.freedesktop.org/series/81815/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9025 -> Patchwork_18530
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/index.html

Known issues
------------

  Here are the changes found in Patchwork_18530 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_flink_basic@double-flink:
    - fi-tgl-y:           [PASS][1] -> [DMESG-WARN][2] ([i915#402])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/fi-tgl-y/igt@gem_flink_basic@double-flink.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/fi-tgl-y/igt@gem_flink_basic@double-flink.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - fi-bsw-kefka:       [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) +1 similar issue
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_flip@basic-flip-vs-wf_vblank@b-edp1:
    - fi-icl-u2:          [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vblank@b-edp1.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vblank@b-edp1.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
    - fi-tgl-y:           [PASS][7] -> [DMESG-WARN][8] ([i915#1982])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/fi-tgl-y/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/fi-tgl-y/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html

  * igt@vgem_basic@unload:
    - fi-kbl-x1275:       [PASS][9] -> [DMESG-WARN][10] ([i915#62] / [i915#92])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/fi-kbl-x1275/igt@vgem_basic@unload.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/fi-kbl-x1275/igt@vgem_basic@unload.html

  
#### Possible fixes ####

  * {igt@core_hotunplug@unbind-rebind}:
    - fi-kbl-x1275:       [DMESG-WARN][11] ([i915#62] / [i915#92]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/fi-kbl-x1275/igt@core_hotunplug@unbind-rebind.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/fi-kbl-x1275/igt@core_hotunplug@unbind-rebind.html

  * igt@gem_tiled_fence_blits@basic:
    - fi-tgl-y:           [DMESG-WARN][13] ([i915#402]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/fi-tgl-y/igt@gem_tiled_fence_blits@basic.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/fi-tgl-y/igt@gem_tiled_fence_blits@basic.html

  * igt@i915_module_load@reload:
    - fi-apl-guc:         [DMESG-WARN][15] ([i915#1635] / [i915#1982]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/fi-apl-guc/igt@i915_module_load@reload.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/fi-apl-guc/igt@i915_module_load@reload.html

  * igt@kms_busy@basic@flip:
    - fi-kbl-x1275:       [DMESG-WARN][17] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/fi-kbl-x1275/igt@kms_busy@basic@flip.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/fi-kbl-x1275/igt@kms_busy@basic@flip.html

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-kbl-7500u:       [DMESG-WARN][19] ([i915#2203]) -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - fi-icl-u2:          [DMESG-WARN][21] ([i915#1982]) -> [PASS][22] +2 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_flip@basic-flip-vs-dpms@d-dsi1:
    - {fi-tgl-dsi}:       [DMESG-WARN][23] ([i915#1982]) -> [PASS][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/fi-tgl-dsi/igt@kms_flip@basic-flip-vs-dpms@d-dsi1.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/fi-tgl-dsi/igt@kms_flip@basic-flip-vs-dpms@d-dsi1.html

  * igt@kms_flip@basic-flip-vs-wf_vblank@c-hdmi-a2:
    - fi-skl-guc:         [DMESG-WARN][25] ([i915#2203]) -> [PASS][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/fi-skl-guc/igt@kms_flip@basic-flip-vs-wf_vblank@c-hdmi-a2.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/fi-skl-guc/igt@kms_flip@basic-flip-vs-wf_vblank@c-hdmi-a2.html

  
#### Warnings ####

  * igt@gem_exec_suspend@basic-s0:
    - fi-kbl-x1275:       [DMESG-WARN][27] ([i915#1982] / [i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][28] ([i915#62] / [i915#92])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html

  * igt@gem_exec_suspend@basic-s3:
    - fi-tgl-y:           [DMESG-WARN][29] ([i915#2411]) -> [DMESG-WARN][30] ([i915#2411] / [i915#402])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/fi-tgl-y/igt@gem_exec_suspend@basic-s3.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/fi-tgl-y/igt@gem_exec_suspend@basic-s3.html

  * igt@i915_pm_rpm@module-reload:
    - fi-tgl-y:           [DMESG-WARN][31] ([i915#1982] / [i915#2411]) -> [DMESG-WARN][32] ([i915#2411]) +1 similar issue
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/fi-tgl-y/igt@i915_pm_rpm@module-reload.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/fi-tgl-y/igt@i915_pm_rpm@module-reload.html

  * igt@kms_force_connector_basic@force-edid:
    - fi-kbl-x1275:       [DMESG-WARN][33] ([i915#62] / [i915#92]) -> [DMESG-WARN][34] ([i915#62] / [i915#92] / [i915#95]) +5 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/fi-kbl-x1275/igt@kms_force_connector_basic@force-edid.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/fi-kbl-x1275/igt@kms_force_connector_basic@force-edid.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
    - fi-kbl-x1275:       [DMESG-WARN][35] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][36] ([i915#62] / [i915#92]) +2 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/fi-kbl-x1275/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/fi-kbl-x1275/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
  [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
  [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
  [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95


Participating hosts (45 -> 40)
------------------------------

  Missing    (5): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_9025 -> Patchwork_18530

  CI-20190529: 20190529
  CI_DRM_9025: 955d04e2ed0cf4bb4679f594a852cc2eebe8266b @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5787: 0ec962017c8131de14e0cb038f7f76b1f17ed637 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_18530: 1cc6a0e5fdd2889b65894521bce5aea74d9e661e @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

1cc6a0e5fdd2 drm/i915: Use the correct bpp when validating "4:2:0 only" modes
bcac59993165 drm/i915: Decouple intel_dp_{min, output}_bpp() from crtc_state
7aff500c0fe7 drm/i915: Extract intel_dp_output_format()

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/index.html

[-- Attachment #1.2: Type: text/html, Size: 12127 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 14+ messages in thread

* [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/3] drm/i915: Extract intel_dp_output_format() (rev2)
  2020-09-17 21:43 [Intel-gfx] [PATCH 1/3] drm/i915: Extract intel_dp_output_format() Ville Syrjala
                   ` (5 preceding siblings ...)
  2020-09-18 14:27 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Extract intel_dp_output_format() (rev2) Patchwork
@ 2020-09-18 17:15 ` Patchwork
  6 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2020-09-18 17:15 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx


[-- Attachment #1.1: Type: text/plain, Size: 14772 bytes --]

== Series Details ==

Series: series starting with [1/3] drm/i915: Extract intel_dp_output_format() (rev2)
URL   : https://patchwork.freedesktop.org/series/81815/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9025_full -> Patchwork_18530_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_18530_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_18530_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_18530_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_flip@2x-nonexisting-fb-interruptible@ac-vga1-hdmi-a1:
    - shard-hsw:          NOTRUN -> [INCOMPLETE][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/shard-hsw7/igt@kms_flip@2x-nonexisting-fb-interruptible@ac-vga1-hdmi-a1.html

  
Known issues
------------

  Here are the changes found in Patchwork_18530_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - shard-skl:          [PASS][2] -> [DMESG-WARN][3] ([i915#1982]) +6 similar issues
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-skl7/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/shard-skl7/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_draw_crc@draw-method-rgb565-pwrite-untiled:
    - shard-skl:          [PASS][4] -> [FAIL][5] ([i915#177] / [i915#52] / [i915#54])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-skl5/igt@kms_draw_crc@draw-method-rgb565-pwrite-untiled.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/shard-skl6/igt@kms_draw_crc@draw-method-rgb565-pwrite-untiled.html

  * igt@kms_flip@2x-flip-vs-blocking-wf-vblank@ab-vga1-hdmi-a1:
    - shard-hsw:          [PASS][6] -> [DMESG-WARN][7] ([i915#1982])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-hsw7/igt@kms_flip@2x-flip-vs-blocking-wf-vblank@ab-vga1-hdmi-a1.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/shard-hsw6/igt@kms_flip@2x-flip-vs-blocking-wf-vblank@ab-vga1-hdmi-a1.html

  * igt@kms_flip@plain-flip-fb-recreate@c-edp1:
    - shard-skl:          [PASS][8] -> [FAIL][9] ([i915#2122])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-skl3/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/shard-skl3/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html

  * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite:
    - shard-kbl:          [PASS][10] -> [DMESG-WARN][11] ([i915#1982])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-kbl4/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/shard-kbl1/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-skl:          [PASS][12] -> [FAIL][13] ([i915#49]) +1 similar issue
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-skl5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-wc.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/shard-skl6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-skl:          [PASS][14] -> [FAIL][15] ([i915#1188]) +1 similar issue
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-skl2/igt@kms_hdr@bpc-switch-suspend.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/shard-skl9/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
    - shard-skl:          [PASS][16] -> [FAIL][17] ([fdo#108145] / [i915#265]) +2 similar issues
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-skl4/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/shard-skl6/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html

  * igt@kms_psr@psr2_cursor_render:
    - shard-iclb:         [PASS][18] -> [SKIP][19] ([fdo#109441]) +3 similar issues
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/shard-iclb4/igt@kms_psr@psr2_cursor_render.html

  * igt@kms_universal_plane@universal-plane-gen9-features-pipe-b:
    - shard-tglb:         [PASS][20] -> [DMESG-WARN][21] ([i915#1982])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-tglb6/igt@kms_universal_plane@universal-plane-gen9-features-pipe-b.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/shard-tglb8/igt@kms_universal_plane@universal-plane-gen9-features-pipe-b.html

  * igt@kms_vblank@pipe-a-ts-continuation-suspend:
    - shard-kbl:          [PASS][22] -> [DMESG-WARN][23] ([i915#180])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-kbl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/shard-kbl3/igt@kms_vblank@pipe-a-ts-continuation-suspend.html

  * igt@kms_vblank@pipe-c-wait-forked-hang:
    - shard-apl:          [PASS][24] -> [DMESG-WARN][25] ([i915#1635] / [i915#1982])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-apl2/igt@kms_vblank@pipe-c-wait-forked-hang.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/shard-apl3/igt@kms_vblank@pipe-c-wait-forked-hang.html

  * igt@perf@polling-small-buf:
    - shard-iclb:         [PASS][26] -> [FAIL][27] ([i915#1722])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-iclb6/igt@perf@polling-small-buf.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/shard-iclb3/igt@perf@polling-small-buf.html

  
#### Possible fixes ####

  * igt@gem_eio@suspend:
    - shard-iclb:         [INCOMPLETE][28] -> [PASS][29]
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-iclb3/igt@gem_eio@suspend.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/shard-iclb4/igt@gem_eio@suspend.html

  * igt@gem_userptr_blits@sync-unmap-cycles:
    - shard-skl:          [TIMEOUT][30] ([i915#1958] / [i915#2424]) -> [PASS][31]
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-skl8/igt@gem_userptr_blits@sync-unmap-cycles.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/shard-skl2/igt@gem_userptr_blits@sync-unmap-cycles.html

  * igt@gem_userptr_blits@unsync-unmap-cycles:
    - shard-skl:          [TIMEOUT][32] ([i915#1958]) -> [PASS][33]
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-skl7/igt@gem_userptr_blits@unsync-unmap-cycles.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/shard-skl10/igt@gem_userptr_blits@unsync-unmap-cycles.html

  * igt@gen9_exec_parse@allowed-single:
    - shard-skl:          [DMESG-WARN][34] ([i915#1436] / [i915#716]) -> [PASS][35]
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-skl1/igt@gen9_exec_parse@allowed-single.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/shard-skl8/igt@gen9_exec_parse@allowed-single.html

  * igt@i915_selftest@mock@contexts:
    - shard-apl:          [INCOMPLETE][36] ([i915#1635] / [i915#2278]) -> [PASS][37]
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-apl2/igt@i915_selftest@mock@contexts.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/shard-apl3/igt@i915_selftest@mock@contexts.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
    - shard-glk:          [FAIL][38] ([i915#72]) -> [PASS][39]
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-glk5/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/shard-glk1/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html

  * igt@kms_flip@2x-dpms-vs-vblank-race@ab-vga1-hdmi-a1:
    - shard-hsw:          [DMESG-WARN][40] ([i915#1982]) -> [PASS][41]
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-hsw6/igt@kms_flip@2x-dpms-vs-vblank-race@ab-vga1-hdmi-a1.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/shard-hsw8/igt@kms_flip@2x-dpms-vs-vblank-race@ab-vga1-hdmi-a1.html

  * igt@kms_flip@2x-flip-vs-suspend-interruptible@bc-vga1-hdmi-a1:
    - shard-hsw:          [INCOMPLETE][42] ([i915#2055]) -> [PASS][43]
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-hsw8/igt@kms_flip@2x-flip-vs-suspend-interruptible@bc-vga1-hdmi-a1.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/shard-hsw7/igt@kms_flip@2x-flip-vs-suspend-interruptible@bc-vga1-hdmi-a1.html

  * igt@kms_flip@flip-vs-suspend@c-dp1:
    - shard-kbl:          [DMESG-WARN][44] ([i915#180]) -> [PASS][45] +3 similar issues
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-kbl7/igt@kms_flip@flip-vs-suspend@c-dp1.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/shard-kbl6/igt@kms_flip@flip-vs-suspend@c-dp1.html

  * igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1:
    - shard-skl:          [FAIL][46] ([i915#2122]) -> [PASS][47]
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-skl1/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/shard-skl8/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw:
    - shard-iclb:         [DMESG-WARN][48] ([i915#1982]) -> [PASS][49]
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-skl:          [FAIL][50] ([i915#1188]) -> [PASS][51]
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-skl10/igt@kms_hdr@bpc-switch-dpms.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/shard-skl4/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_plane_scaling@pipe-c-plane-scaling:
    - shard-skl:          [DMESG-WARN][52] ([i915#1982]) -> [PASS][53] +2 similar issues
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-skl6/igt@kms_plane_scaling@pipe-c-plane-scaling.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/shard-skl5/igt@kms_plane_scaling@pipe-c-plane-scaling.html

  * igt@kms_psr@psr2_sprite_mmap_gtt:
    - shard-iclb:         [SKIP][54] ([fdo#109441]) -> [PASS][55] +1 similar issue
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-iclb7/igt@kms_psr@psr2_sprite_mmap_gtt.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html

  * igt@kms_vblank@pipe-b-query-busy:
    - shard-apl:          [DMESG-WARN][56] ([i915#1635] / [i915#1982]) -> [PASS][57] +2 similar issues
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-apl7/igt@kms_vblank@pipe-b-query-busy.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/shard-apl6/igt@kms_vblank@pipe-b-query-busy.html

  
#### Warnings ####

  * igt@kms_flip@flip-vs-suspend@a-edp1:
    - shard-skl:          [INCOMPLETE][58] ([i915#198] / [i915#1982]) -> [DMESG-WARN][59] ([i915#1982])
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-skl2/igt@kms_flip@flip-vs-suspend@a-edp1.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/shard-skl10/igt@kms_flip@flip-vs-suspend@a-edp1.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [DMESG-WARN][60] ([i915#1982]) -> [DMESG-FAIL][61] ([fdo#108145] / [i915#1982])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
  [i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
  [i915#177]: https://gitlab.freedesktop.org/drm/intel/issues/177
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958
  [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2055]: https://gitlab.freedesktop.org/drm/intel/issues/2055
  [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
  [i915#2278]: https://gitlab.freedesktop.org/drm/intel/issues/2278
  [i915#2424]: https://gitlab.freedesktop.org/drm/intel/issues/2424
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
  [i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52
  [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
  [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
  [i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72


Participating hosts (11 -> 10)
------------------------------

  Missing    (1): pig-icl-1065g7 


Build changes
-------------

  * Linux: CI_DRM_9025 -> Patchwork_18530

  CI-20190529: 20190529
  CI_DRM_9025: 955d04e2ed0cf4bb4679f594a852cc2eebe8266b @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5787: 0ec962017c8131de14e0cb038f7f76b1f17ed637 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_18530: 1cc6a0e5fdd2889b65894521bce5aea74d9e661e @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18530/index.html

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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [Intel-gfx] [PATCH 1/3] drm/i915: Extract intel_dp_output_format()
  2020-09-18 10:39   ` Ville Syrjälä
@ 2020-09-18 18:49     ` Navare, Manasi
  0 siblings, 0 replies; 14+ messages in thread
From: Navare, Manasi @ 2020-09-18 18:49 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx

On Fri, Sep 18, 2020 at 01:39:45PM +0300, Ville Syrjälä wrote:
> On Thu, Sep 17, 2020 at 04:57:09PM -0700, Navare, Manasi wrote:
> > On Fri, Sep 18, 2020 at 12:43:33AM +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > Refactor the output_format calculation into a helper so that
> > > we can reuse it for mode validation as well.
> > > 
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_dp.c | 32 +++++++++++++++----------
> > >  1 file changed, 20 insertions(+), 12 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > > index bf1e9cf1c0f3..ad9b8b16fadb 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > @@ -592,6 +592,22 @@ static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
> > >  	return 0;
> > >  }
> > >  
> > > +static enum intel_output_format
> > > +intel_dp_output_format(struct drm_connector *connector,
> > > +		       const struct drm_display_mode *mode)
> > > +{
> > > +	struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
> > > +	const struct drm_display_info *info = &connector->display_info;
> > > +
> > > +	if (!drm_mode_is_420_only(info, mode))
> > > +		return INTEL_OUTPUT_FORMAT_RGB;
> > > +
> > > +	if (intel_dp->dfp.ycbcr_444_to_420)
> > > +		return INTEL_OUTPUT_FORMAT_YCBCR444;
> > > +	else
> > > +		return INTEL_OUTPUT_FORMAT_YCBCR420;
> > > +}
> > > +
> > >  static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
> > >  				  int hdisplay)
> > >  {
> > > @@ -2430,27 +2446,20 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
> > >  }
> > >  
> > >  static int
> > > -intel_dp_ycbcr420_config(struct intel_dp *intel_dp,
> > > -			 struct intel_crtc_state *crtc_state,
> > > +intel_dp_ycbcr420_config(struct intel_crtc_state *crtc_state,
> > >  			 const struct drm_connector_state *conn_state)
> > >  {
> > >  	struct drm_connector *connector = conn_state->connector;
> > > -	const struct drm_display_info *info = &connector->display_info;
> > >  	const struct drm_display_mode *adjusted_mode =
> > >  		&crtc_state->hw.adjusted_mode;
> > >  
> > >  	if (!connector->ycbcr_420_allowed)
> > >  		return 0;
> > >  
> > > -	if (!drm_mode_is_420_only(info, adjusted_mode))
> > > -		return 0;
> > > +	crtc_state->output_format = intel_dp_output_format(connector, adjusted_mode);
> > 
> > So by default if its not 420_only then we set it to RGB?
> 
> Yes. The code is still a bit messy because we have three places where
> we set this. Probably will try to unify it a bit more, and try to get
> the lspcon stuff looking more like any other protocol converter.
> 
> Actually IIRC I noticed that some lspcon chips seem to have some
> of the 1.3 protocol converter registers even though they only
> advertise DPCD 1.2. Not yet sure how to handle that in the
> cleanest way possible...

But if DPCD says only 1.2 then we shouldnt be reading 1.3 specific registers
and support it as 1.2 IMO

Manasi
> 
> -- 
> Ville Syrjälä
> Intel
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^ permalink raw reply	[flat|nested] 14+ messages in thread

end of thread, other threads:[~2020-09-18 18:49 UTC | newest]

Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-09-17 21:43 [Intel-gfx] [PATCH 1/3] drm/i915: Extract intel_dp_output_format() Ville Syrjala
2020-09-17 21:43 ` [Intel-gfx] [PATCH 2/3] drm/i915: Decouple intel_dp_{min, output}_bpp() from crtc_state Ville Syrjala
2020-09-17 23:59   ` Navare, Manasi
2020-09-18  5:01   ` Kulkarni, Vandita
2020-09-17 21:43 ` [Intel-gfx] [PATCH 3/3] drm/i915: Use the correct bpp when validating "4:2:0 only" modes Ville Syrjala
2020-09-18  0:01   ` Navare, Manasi
2020-09-18  5:02   ` Kulkarni, Vandita
2020-09-17 21:53 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/3] drm/i915: Extract intel_dp_output_format() Patchwork
2020-09-17 23:57 ` [Intel-gfx] [PATCH 1/3] " Navare, Manasi
2020-09-18 10:39   ` Ville Syrjälä
2020-09-18 18:49     ` Navare, Manasi
2020-09-18  5:00 ` Kulkarni, Vandita
2020-09-18 14:27 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Extract intel_dp_output_format() (rev2) Patchwork
2020-09-18 17:15 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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