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From: Joel Stanley <joel@jms.id.au>
To: Rob Herring <robh+dt@kernel.org>, Andrew Jeffery <andrew@aj.id.au>
Cc: linux-aspeed@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 3/3] ARM: dts: aspeed: Add silicon id node
Date: Mon, 21 Sep 2020 18:46:44 +0930	[thread overview]
Message-ID: <20200921091644.133107-4-joel@jms.id.au> (raw)
In-Reply-To: <20200921091644.133107-1-joel@jms.id.au>

This register describes the silicon id and chip unique id. It varies
between CPU revisions, but is always part of the SCU.

Signed-off-by: Joel Stanley <joel@jms.id.au>
---
v2: Fix whitespace
---
 arch/arm/boot/dts/aspeed-g4.dtsi | 5 +++++
 arch/arm/boot/dts/aspeed-g5.dtsi | 5 +++++
 arch/arm/boot/dts/aspeed-g6.dtsi | 5 +++++
 3 files changed, 15 insertions(+)

diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index 82f0213e3a3c..b3dafbc8caca 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -192,6 +192,11 @@ p2a: p2a-control@2c {
 					status = "disabled";
 				};
 
+				silicon-id@7c {
+					compatible = "aspeed,ast2400-silicon-id", "aspeed,silicon-id";
+					reg = <0x7c 0x4>;
+				};
+
 				pinctrl: pinctrl@80 {
 					reg = <0x80 0x18>, <0xa0 0x10>;
 					compatible = "aspeed,ast2400-pinctrl";
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 9c91afb2b404..c6862182313a 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -239,6 +239,11 @@ p2a: p2a-control@2c {
 					status = "disabled";
 				};
 
+				silicon-id@7c {
+					compatible = "aspeed,ast2500-silicon-id", "aspeed,silicon-id";
+					reg = <0x7c 0x4 0x150 0x8>;
+				};
+
 				pinctrl: pinctrl@80 {
 					compatible = "aspeed,ast2500-pinctrl";
 					reg = <0x80 0x18>, <0xa0 0x10>;
diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
index b58220a49cbd..1ce3a1f06f7f 100644
--- a/arch/arm/boot/dts/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed-g6.dtsi
@@ -311,6 +311,11 @@ pinctrl: pinctrl {
 					compatible = "aspeed,ast2600-pinctrl";
 				};
 
+				silicon-id@14 {
+					compatible = "aspeed,ast2600-silicon-id", "aspeed,silicon-id";
+					reg = <0x14 0x4 0x5b0 0x8>;
+				};
+
 				smp-memram@180 {
 					compatible = "aspeed,ast2600-smpmem";
 					reg = <0x180 0x40>;
-- 
2.28.0


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  parent reply	other threads:[~2020-09-21  9:18 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-21  9:16 [PATCH v3 0/3] ARM: aspeed: Add socinfo driver Joel Stanley
2020-09-21  9:16 ` [PATCH v3 1/3] dt-bindings: aspeed: Add silicon id node to SCU Joel Stanley
2020-09-24  6:46   ` Andrew Jeffery
2020-09-21  9:16 ` [PATCH v3 2/3] soc: aspeed: Add soc info driver Joel Stanley
2020-09-24  6:56   ` Andrew Jeffery
2020-09-21  9:16 ` Joel Stanley [this message]
2020-09-24  6:57   ` [PATCH v3 3/3] ARM: dts: aspeed: Add silicon id node Andrew Jeffery

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