From: "Andrew Jeffery" <andrew@aj.id.au>
To: "Joel Stanley" <joel@jms.id.au>, "Rob Herring" <robh+dt@kernel.org>
Cc: linux-aspeed@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v3 3/3] ARM: dts: aspeed: Add silicon id node
Date: Thu, 24 Sep 2020 16:27:43 +0930 [thread overview]
Message-ID: <53bc663a-6788-43b2-bd4f-8336f3dd4a3b@www.fastmail.com> (raw)
In-Reply-To: <20200921091644.133107-4-joel@jms.id.au>
On Mon, 21 Sep 2020, at 18:46, Joel Stanley wrote:
> This register describes the silicon id and chip unique id. It varies
> between CPU revisions, but is always part of the SCU.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
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prev parent reply other threads:[~2020-09-24 7:00 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-21 9:16 [PATCH v3 0/3] ARM: aspeed: Add socinfo driver Joel Stanley
2020-09-21 9:16 ` [PATCH v3 1/3] dt-bindings: aspeed: Add silicon id node to SCU Joel Stanley
2020-09-24 6:46 ` Andrew Jeffery
2020-09-21 9:16 ` [PATCH v3 2/3] soc: aspeed: Add soc info driver Joel Stanley
2020-09-24 6:56 ` Andrew Jeffery
2020-09-21 9:16 ` [PATCH v3 3/3] ARM: dts: aspeed: Add silicon id node Joel Stanley
2020-09-24 6:57 ` Andrew Jeffery [this message]
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