[igt-dev] [PATCH i-g-t v4 00/25] tests/benchmarks: Libdrm removal

[igt-dev] [PATCH i-g-t v4 00/25] tests/benchmarks: Libdrm removal

[Dominik Grzegorzek]

This removes libdrm using intel_bb from bunch of tests.
Due to lackage of hardware prime_* was not tested. 

v2: gem_tiled_blits.c: device instead of cpu map in object creation
v3: added control over fencing to enable parrallel execution using one ibb,
    added HAX commit with is NOT FOR REVIEW!
    gem_tiled_blits.c: back to cpu mapping
    gem_set_tiling_vs_blit.c: disable fencing in first workload
v4: added blit_copy wrapper for the whole intel_buf
    gem_set_tiling_vs_blit.c: swap x and y in src bo in busy_buf blit
    			      enforce relocs
    gem_pipe_control_store_loop: intel_bb_sync() added
    
Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>

Dominik Grzegorzek (23):
  lib/intel_batchbuffer: add intel_bb_blit_copy wrapper
  Remove unused intel_bufmgr.h headers
  i915/gem_pwrite_snooped: Remove libdrm dependency
  i915/gem_pipe_control_store_loop.c: Remove libdrm dependency
  i915/gem_pread_after_blit.c: Remove libdrm dependency
  i915/gem_threaded_access_tiled.c: Remove libdrm dependency
  i915/gem_tiled_blits: Remove libdrm dependency
  i915/gem_unfence_active_buffers.c: Remove librdm dependency
  i915/gem_unref_active_buffers.c: Remove libdrm dependency
  i915/gem_tiled_partial_pwrite_pread: Remove libdrm dependency
  i915/gem_set_tiling_vs_blit.c: Remove libdrm dependency
  tests/kms_fence_pin_leak.c: Remove libdrm dependency
  tests/kms_flip.c: Remove libdrm dependency
  tests/kms_psr2_su.c: Get rid of unused bufmgr
  benchmarks: Remove libdrm dependency
  tests/prime_mmap_coherency.c: Remove libdrm dependency
  tools/intel_perf_counters: Remove libdrm dependency
  tests/prime_udl: Remove libdrm dependency
  tests/prime_nv_pcopy.c: Remove libdrm dependency
  tests/prime_nv_api.c: Remove libdrm dependency
  tests/prime_nv_test.c: Remove libdrm dependency
  tests/i915/gem_ppgtt: make copying more readable
  HAX: run changed tests in BAT only.

Zbigniew Kempczyński (1):
  lib/intel_batchbuffer: Add control over fencing in intel_bb

 benchmarks/gem_userptr_benchmark.c          |   1 -
 benchmarks/intel_upload_blit_large.c        |  69 +++---
 benchmarks/intel_upload_blit_large_gtt.c    |  72 ++++---
 benchmarks/intel_upload_blit_large_map.c    |  74 +++----
 benchmarks/intel_upload_blit_small.c        |  68 +++---
 lib/intel_batchbuffer.c                     |  70 ++++++-
 lib/intel_batchbuffer.h                     |   5 +
 lib/media_fill.c                            |   1 -
 tests/i915/gem_create.c                     |   1 -
 tests/i915/gem_flink_race.c                 |   2 -
 tests/i915/gem_mmap.c                       |  25 ++-
 tests/i915/gem_mmap_wc.c                    |  26 ++-
 tests/i915/gem_pipe_control_store_loop.c    | 143 ++++++-------
 tests/i915/gem_ppgtt.c                      |  16 +-
 tests/i915/gem_pread_after_blit.c           | 135 ++++++------
 tests/i915/gem_pwrite_snooped.c             |  66 +++---
 tests/i915/gem_request_retire.c             |   1 -
 tests/i915/gem_set_tiling_vs_blt.c          | 219 ++++++++++----------
 tests/i915/gem_threaded_access_tiled.c      |  38 ++--
 tests/i915/gem_tiled_blits.c                |  75 +++----
 tests/i915/gem_tiled_partial_pwrite_pread.c | 123 ++++++-----
 tests/i915/gem_unfence_active_buffers.c     | 134 ++++++------
 tests/i915/gem_unref_active_buffers.c       |  56 +++--
 tests/i915/gem_userptr_blits.c              |   1 -
 tests/i915/i915_getparams_basic.c           |   1 -
 tests/intel-ci/fast-feedback.testlist       |  10 +
 tests/kms_fence_pin_leak.c                  |  83 ++++----
 tests/kms_flip.c                            |  22 +-
 tests/kms_psr2_su.c                         |   7 -
 tests/kms_sequence.c                        |   2 -
 tests/kms_setmode.c                         |   1 -
 tests/kms_vblank.c                          |   2 -
 tests/prime_mmap_coherency.c                | 105 +++++-----
 tests/prime_nv_api.c                        | 203 ++++++++++--------
 tests/prime_nv_pcopy.c                      | 103 +++++----
 tests/prime_nv_test.c                       | 189 +++++++++--------
 tests/prime_udl.c                           |  44 ++--
 tools/intel_perf_counters.c                 | 109 +++++-----
 38 files changed, 1201 insertions(+), 1101 deletions(-)

-- 
2.20.1

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[igt-dev] [PATCH i-g-t v4 01/25] i915/gem_mmap: Modified offset in subtest "bad-size"

[Dominik Grzegorzek]

From: Apoorva Singh <apoorva1.singh@intel.com>

Subtest "bad-size" should keep valid/good offset
corresponding to buffer object being mapped.
Currently, subtest will pass for any value of size
provided as the offset value itself will not allow
to map any size of memory which defies the purpose
of this subtest.

The subtest should not pass due to bad offset value
while it should pass only due to bad size provided.

v2: Added new offset. Updated the same changes in
"bad-size" subtest of gem_mmap_wc too.

Signed-off-by: Apoorva Singh <apoorva1.singh@intel.com>
Cc: Melkaveri, Arjun <arjun.melkaveri@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 tests/i915/gem_mmap.c    | 25 ++++++++++++++++---------
 tests/i915/gem_mmap_wc.c | 26 ++++++++++++++++----------
 2 files changed, 32 insertions(+), 19 deletions(-)

diff --git a/tests/i915/gem_mmap.c b/tests/i915/gem_mmap.c
index f8cf052e..8bad9b14 100644
--- a/tests/i915/gem_mmap.c
+++ b/tests/i915/gem_mmap.c
@@ -214,18 +214,25 @@ igt_main
 			2 * 4096,
 			~0,
 		};
+		uint64_t offset[] = {
+			4096,
+			0
+		};
 
-		for (int i = 0; i < ARRAY_SIZE(bad_size); i++) {
-			struct drm_i915_gem_mmap arg = {
-				.handle = gem_create(fd, 4096),
-				.offset = 4096,
-				.size = bad_size[i],
-			};
+		for(int i = 0; i < ARRAY_SIZE(offset); i++) {
+			for (int j = 0; j < ARRAY_SIZE(bad_size); j++) {
+				struct drm_i915_gem_mmap arg = {
+					.handle = gem_create(fd, 4096),
+					.offset = offset[i],
+					.size = bad_size[j],
+				};
 
-			igt_debug("Trying to mmap bad size; size: %'"PRIu64"\n", bad_size[i]);
-			igt_assert_eq(mmap_ioctl(fd, &arg), -EINVAL);
+				igt_debug("Trying to mmap bad size; size: %'"PRIu64", offset: %'"PRIu64"\n",
+						bad_size[j], offset[i]);
+				igt_assert_eq(mmap_ioctl(fd, &arg), -EINVAL);
 
-			gem_close(fd, arg.handle);
+				gem_close(fd, arg.handle);
+			}
 		}
 	}
 
diff --git a/tests/i915/gem_mmap_wc.c b/tests/i915/gem_mmap_wc.c
index f44b406d..fe1283e5 100644
--- a/tests/i915/gem_mmap_wc.c
+++ b/tests/i915/gem_mmap_wc.c
@@ -563,17 +563,23 @@ igt_main
 			2 * 4096,
 			~0,
 		};
+		uint64_t offset[] = {
+			4096,
+			0
+		};
 
-		for (int i = 0; i < ARRAY_SIZE(bad_size); i++) {
-			struct drm_i915_gem_mmap arg = {
-				.handle = gem_create(fd, 4096),
-				.offset = 4096,
-				.size = bad_size[i],
-				.flags = I915_MMAP_WC,
-			};
-
-			igt_assert_eq(mmap_ioctl(fd, &arg), -EINVAL);
-			gem_close(fd, arg.handle);
+		for(int i = 0; i < ARRAY_SIZE(offset); i++) {
+			for (int j = 0; j < ARRAY_SIZE(bad_size); j++) {
+				struct drm_i915_gem_mmap arg = {
+					.handle = gem_create(fd, 4096),
+					.offset = offset[i],
+					.size = bad_size[j],
+					.flags = I915_MMAP_WC,
+				};
+
+				igt_assert_eq(mmap_ioctl(fd, &arg), -EINVAL);
+				gem_close(fd, arg.handle);
+			}
 		}
 	}
 
-- 
2.20.1

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[igt-dev] [PATCH i-g-t v4 02/25] lib/intel_batchbuffer: Add control over fencing in intel_bb

[Dominik Grzegorzek]

From: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

From default intel_bb uses fencing to track subsequent execs.
It is required to properly sync intel_bb. Unfortunately this
also has some drawback, when we want to use same intel_bb to
schedule some time consuming job then run something else. Fencing
as turned on from default will serialize such execs. To avoid that
add possibility to turn on / off fencing in the intel_bb.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 lib/intel_batchbuffer.c | 47 ++++++++++++++++++++++++++++++++---------
 lib/intel_batchbuffer.h |  2 ++
 2 files changed, 39 insertions(+), 10 deletions(-)

diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index be764646..079d6389 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -1266,6 +1266,7 @@ __intel_bb_create(int i915, uint32_t size, bool do_relocs)
 	ibb->ptr = ibb->batch;
 	ibb->prng = (uint32_t) to_user_pointer(ibb);
 	ibb->fence = -1;
+	ibb->use_fences = true;
 
 	gtt_size = gem_aperture_size(i915);
 	if (!gem_uses_full_ppgtt(i915))
@@ -1513,6 +1514,26 @@ void intel_bb_set_debug(struct intel_bb *ibb, bool debug)
 	ibb->debug = debug;
 }
 
+/**
+ * intel_bb_set_fencing:
+ * @ibb: pointer to intel_bb
+ * @use_fences: true / false
+ *
+ * Sets using fences to true / false.
+ */
+void intel_bb_set_fencing(struct intel_bb *ibb, bool use_fences)
+{
+	if (use_fences == ibb->use_fences)
+		return;
+
+	if (use_fences == false && ibb->fence >= 0) {
+		close(ibb->fence);
+		ibb->fence = -1;
+	}
+
+	ibb->use_fences = use_fences;
+}
+
 /**
  * intel_bb_set_dump_base64:
  * @ibb: pointer to intel_bb
@@ -2058,7 +2079,11 @@ int __intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
 	execbuf.buffer_count = ibb->num_objects;
 	execbuf.batch_len = end_offset;
 	execbuf.rsvd1 = ibb->ctx = ctx;
-	execbuf.flags = flags | I915_EXEC_BATCH_FIRST | I915_EXEC_FENCE_OUT;
+	execbuf.flags = flags | I915_EXEC_BATCH_FIRST;
+
+	if (ibb->use_fences)
+		execbuf.flags |= I915_EXEC_FENCE_OUT;
+
 	if (ibb->enforce_relocs)
 		execbuf.flags &= ~I915_EXEC_NO_RELOC;
 	execbuf.rsvd2 = 0;
@@ -2077,15 +2102,17 @@ int __intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
 	update_offsets(ibb, objects);
 
 	/* Save/merge fences */
-	fence = execbuf.rsvd2 >> 32;
-
-	if (ibb->fence < 0) {
-		ibb->fence = fence;
-	} else {
-		new_fence = sync_fence_merge(ibb->fence, fence);
-		close(ibb->fence);
-		close(fence);
-		ibb->fence = new_fence;
+	if (ibb->use_fences) {
+		fence = execbuf.rsvd2 >> 32;
+
+		if (ibb->fence < 0) {
+			ibb->fence = fence;
+		} else {
+			new_fence = sync_fence_merge(ibb->fence, fence);
+			close(ibb->fence);
+			close(fence);
+			ibb->fence = new_fence;
+		}
 	}
 
 	if (sync || ibb->debug)
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index 8b9c1ed9..cbfbe25f 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -446,6 +446,7 @@ struct intel_bb {
 	uint32_t *ptr;
 	uint64_t alignment;
 	int fence;
+	bool use_fences;
 
 	uint32_t prng;
 	uint64_t gtt_size;
@@ -497,6 +498,7 @@ int intel_bb_sync(struct intel_bb *ibb);
 void intel_bb_print(struct intel_bb *ibb);
 void intel_bb_dump(struct intel_bb *ibb, const char *filename);
 void intel_bb_set_debug(struct intel_bb *ibb, bool debug);
+void intel_bb_set_fencing(struct intel_bb *ibb, bool use_fences);
 void intel_bb_set_dump_base64(struct intel_bb *ibb, bool dump);
 
 static inline uint64_t
-- 
2.20.1

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[igt-dev] [PATCH i-g-t v4 03/25] lib/intel_batchbuffer: add intel_bb_blit_copy wrapper

[Dominik Grzegorzek]

This patch adds intel_bb_copy_intel_buf to make copying a whole
intel_buf easier and more readable.

Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 lib/intel_batchbuffer.c | 23 +++++++++++++++++++++++
 lib/intel_batchbuffer.h |  3 +++
 2 files changed, 26 insertions(+)

diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index 079d6389..259b15c5 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -2545,6 +2545,29 @@ void intel_bb_blt_copy(struct intel_bb *ibb,
 	intel_bb_flush_blit(ibb);
 }
 
+/**
+ * intel_bb_copy_intel_buf:
+ * @batch: batchbuffer object
+ * @src: source buffer (intel_buf)
+ * @dst: destination libdrm buffer object
+ * @size: size of the copy range in bytes
+ *
+ * Tmits a copy operation using blitter commands into the supplied batch
+ * buffer object. A total of @size bytes from the start of @src is copied
+ * over to @dst. Note that @size must be page-aligned.
+ */
+void intel_bb_copy_intel_buf(struct intel_bb *ibb,
+			     struct intel_buf *dst, struct intel_buf *src,
+			     long int size)
+{
+	igt_assert(size % 4096 == 0);
+
+	intel_bb_blt_copy(ibb,
+		       src, 0, 0, 4096,
+		       dst, 0, 0, 4096,
+		       4096/4, size/4096, 32);
+}
+
 /**
  * igt_get_huc_copyfunc:
  * @devid: pci device id
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index cbfbe25f..a23ba9af 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -654,6 +654,9 @@ void intel_bb_blt_copy(struct intel_bb *ibb,
 		       struct intel_buf *dst,
 		       int dst_x1, int dst_y1, int dst_pitch,
 		       int width, int height, int bpp);
+void intel_bb_copy_intel_buf(struct intel_bb *ibb,
+			     struct intel_buf *dst, struct intel_buf *src,
+			     long int size);
 
 /**
  * igt_huc_copyfunc_t:
-- 
2.20.1

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[igt-dev] [PATCH i-g-t v4 04/25] Remove unused intel_bufmgr.h headers

[Dominik Grzegorzek]

Delete intel_bufmgr include where it is not necessary.

Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 benchmarks/gem_userptr_benchmark.c | 1 -
 lib/media_fill.c                   | 1 -
 tests/i915/gem_create.c            | 1 -
 tests/i915/gem_flink_race.c        | 2 --
 tests/i915/gem_request_retire.c    | 1 -
 tests/i915/gem_userptr_blits.c     | 1 -
 tests/i915/i915_getparams_basic.c  | 1 -
 tests/kms_sequence.c               | 2 --
 tests/kms_setmode.c                | 1 -
 tests/kms_vblank.c                 | 2 --
 10 files changed, 13 deletions(-)

diff --git a/benchmarks/gem_userptr_benchmark.c b/benchmarks/gem_userptr_benchmark.c
index eccc65be..d7a49520 100644
--- a/benchmarks/gem_userptr_benchmark.c
+++ b/benchmarks/gem_userptr_benchmark.c
@@ -48,7 +48,6 @@
 #include "i915_drm.h"
 
 #include "drmtest.h"
-#include "intel_bufmgr.h"
 #include "intel_batchbuffer.h"
 #include "intel_chipset.h"
 #include "ioctl_wrappers.h"
diff --git a/lib/media_fill.c b/lib/media_fill.c
index c21de54b..c4883874 100644
--- a/lib/media_fill.c
+++ b/lib/media_fill.c
@@ -22,7 +22,6 @@
  *
  */
 
-#include <intel_bufmgr.h>
 #include <i915_drm.h>
 
 #include "media_fill.h"
diff --git a/tests/i915/gem_create.c b/tests/i915/gem_create.c
index c7444d55..dc945ab6 100644
--- a/tests/i915/gem_create.c
+++ b/tests/i915/gem_create.c
@@ -47,7 +47,6 @@
 #include "drm.h"
 #include "drmtest.h"
 #include "ioctl_wrappers.h"
-#include "intel_bufmgr.h"
 #include "intel_batchbuffer.h"
 #include "intel_io.h"
 #include "intel_chipset.h"
diff --git a/tests/i915/gem_flink_race.c b/tests/i915/gem_flink_race.c
index c1f5d5d5..de64443d 100644
--- a/tests/i915/gem_flink_race.c
+++ b/tests/i915/gem_flink_race.c
@@ -33,8 +33,6 @@
 #include <pthread.h>
 #include <errno.h>
 
-#include "intel_bufmgr.h"
-
 IGT_TEST_DESCRIPTION("Check for flink/open vs. gem close races.");
 
 /* Testcase: check for flink/open vs. gem close races
diff --git a/tests/i915/gem_request_retire.c b/tests/i915/gem_request_retire.c
index 4a1ec115..31fb4198 100644
--- a/tests/i915/gem_request_retire.c
+++ b/tests/i915/gem_request_retire.c
@@ -48,7 +48,6 @@
 
 #include "i915/gem.h"
 #include "igt.h"
-#include "intel_bufmgr.h"
 
 IGT_TEST_DESCRIPTION("Collection of tests targeting request retirement code"
 		     " paths.");
diff --git a/tests/i915/gem_userptr_blits.c b/tests/i915/gem_userptr_blits.c
index 268423dc..65272c1b 100644
--- a/tests/i915/gem_userptr_blits.c
+++ b/tests/i915/gem_userptr_blits.c
@@ -62,7 +62,6 @@
 
 #include "i915/gem.h"
 #include "igt.h"
-#include "intel_bufmgr.h"
 #include "sw_sync.h"
 
 #include "eviction_common.c"
diff --git a/tests/i915/i915_getparams_basic.c b/tests/i915/i915_getparams_basic.c
index 7cb210df..e1b4634f 100644
--- a/tests/i915/i915_getparams_basic.c
+++ b/tests/i915/i915_getparams_basic.c
@@ -30,7 +30,6 @@
 #include <errno.h>
 #include <xf86drm.h>
 #include <i915_drm.h>
-#include "intel_bufmgr.h"
 
 IGT_TEST_DESCRIPTION("Tests the export of parameters via DRM_IOCTL_I915_GETPARAM\n");
 
diff --git a/tests/kms_sequence.c b/tests/kms_sequence.c
index a21ab55c..081bd9d7 100644
--- a/tests/kms_sequence.c
+++ b/tests/kms_sequence.c
@@ -42,8 +42,6 @@
 
 #include <drm.h>
 
-#include "intel_bufmgr.h"
-
 IGT_TEST_DESCRIPTION("Test CrtcGetSequence and CrtcQueueSequence.");
 
 typedef struct {
diff --git a/tests/kms_setmode.c b/tests/kms_setmode.c
index 92f3ead2..00dfedd5 100644
--- a/tests/kms_setmode.c
+++ b/tests/kms_setmode.c
@@ -30,7 +30,6 @@
 #include <string.h>
 #include <sys/time.h>
 #include <math.h>
-#include "intel_bufmgr.h"
 
 #define MAX_CONNECTORS  10
 #define MAX_CRTCS       6
diff --git a/tests/kms_vblank.c b/tests/kms_vblank.c
index be001312..b00ebec5 100644
--- a/tests/kms_vblank.c
+++ b/tests/kms_vblank.c
@@ -41,8 +41,6 @@
 
 #include <drm.h>
 
-#include "intel_bufmgr.h"
-
 IGT_TEST_DESCRIPTION("Test speed of WaitVblank.");
 
 typedef struct {
-- 
2.20.1

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[igt-dev] [PATCH i-g-t v4 05/25] i915/gem_pwrite_snooped: Remove libdrm dependency

[Dominik Grzegorzek]

Use intel_bb / intel_buf to remove libdrm dependency.

Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 tests/i915/gem_pwrite_snooped.c | 66 ++++++++++++++++-----------------
 1 file changed, 33 insertions(+), 33 deletions(-)

diff --git a/tests/i915/gem_pwrite_snooped.c b/tests/i915/gem_pwrite_snooped.c
index 4a339524..52ebaec2 100644
--- a/tests/i915/gem_pwrite_snooped.c
+++ b/tests/i915/gem_pwrite_snooped.c
@@ -42,40 +42,38 @@ IGT_TEST_DESCRIPTION(
    "pwrite to a snooped bo then make it uncached and check that the GPU sees the data.");
 
 static int fd;
-static uint32_t devid;
-static drm_intel_bufmgr *bufmgr;
+static struct buf_ops *bops;
 
-static void blit(drm_intel_bo *dst, drm_intel_bo *src,
+static void blit(struct intel_buf *dst, struct intel_buf *src,
 		 unsigned int width, unsigned int height,
 		 unsigned int dst_pitch, unsigned int src_pitch)
 {
-	struct intel_batchbuffer *batch;
+	struct intel_bb *ibb;
 
-	batch = intel_batchbuffer_alloc(bufmgr, devid);
-	igt_assert(batch);
-
-	BLIT_COPY_BATCH_START(0);
-	OUT_BATCH((3 << 24) | /* 32 bits */
+	ibb = intel_bb_create(fd, 4096);
+	intel_bb_add_intel_buf(ibb, dst, true);
+	intel_bb_add_intel_buf(ibb, src, false);
+	intel_bb_blit_start(ibb, 0);
+	intel_bb_out(ibb, (3 << 24) | /* 32 bits */
 		  (0xcc << 16) | /* copy ROP */
 		  dst_pitch);
-	OUT_BATCH(0 << 16 | 0);
-	OUT_BATCH(height << 16 | width);
-	OUT_RELOC_FENCED(dst, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
-	OUT_BATCH(0 << 16 | 0);
-	OUT_BATCH(src_pitch);
-	OUT_RELOC_FENCED(src, I915_GEM_DOMAIN_RENDER, 0, 0);
-	ADVANCE_BATCH();
-
-	if (batch->gen >= 6) {
-		BEGIN_BATCH(3, 0);
-		OUT_BATCH(XY_SETUP_CLIP_BLT_CMD);
-		OUT_BATCH(0);
-		OUT_BATCH(0);
-		ADVANCE_BATCH();
+	intel_bb_out(ibb, 0 << 16 | 0);
+	intel_bb_out(ibb, height << 16 | width);
+	intel_bb_emit_reloc_fenced(ibb, dst->handle, I915_GEM_DOMAIN_RENDER,
+				   I915_GEM_DOMAIN_RENDER, 0, dst->addr.offset);
+	intel_bb_out(ibb, 0 << 16 | 0);
+	intel_bb_out(ibb, src_pitch);
+	intel_bb_emit_reloc_fenced(ibb, src->handle, I915_GEM_DOMAIN_RENDER,
+				   0, 0, src->addr.offset);
+
+	if (ibb->gen >= 6) {
+		intel_bb_out(ibb, XY_SETUP_CLIP_BLT_CMD);
+		intel_bb_out(ibb, 0);
+		intel_bb_out(ibb, 0);
 	}
 
-	intel_batchbuffer_flush(batch);
-	intel_batchbuffer_free(batch);
+	intel_bb_flush_blit(ibb);
+	intel_bb_destroy(ibb);
 }
 
 static void *memchr_inv(const void *s, int c, size_t n)
@@ -98,13 +96,13 @@ static void *memchr_inv(const void *s, int c, size_t n)
 static void test(int w, int h)
 {
 	int object_size = w * h * 4;
-	drm_intel_bo *src, *dst;
+	struct intel_buf *src, *dst;
 	void *buf;
 
-	src = drm_intel_bo_alloc(bufmgr, "src", object_size, 4096);
-	igt_assert(src);
-	dst = drm_intel_bo_alloc(bufmgr, "dst", object_size, 4096);
-	igt_assert(dst);
+	src = intel_buf_create(bops, w, h, 32, 0, I915_TILING_NONE,
+			       I915_COMPRESSION_NONE);
+	dst = intel_buf_create(bops, w, h, 32, 0, I915_TILING_NONE,
+			       I915_COMPRESSION_NONE);
 
 	buf = malloc(object_size);
 	igt_assert(buf);
@@ -125,6 +123,9 @@ static void test(int w, int h)
 	gem_read(fd, dst->handle, 0, buf, object_size);
 
 	igt_assert(memchr_inv(buf, 0xff, object_size) == NULL);
+
+	intel_buf_destroy(src);
+	intel_buf_destroy(dst);
 }
 
 igt_simple_main
@@ -133,11 +134,10 @@ igt_simple_main
 	igt_require_gem(fd);
 	gem_require_blitter(fd);
 
-	devid = intel_get_drm_devid(fd);
-	bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
+	bops = buf_ops_create(fd);
 
 	test(256, 256);
 
-	drm_intel_bufmgr_destroy(bufmgr);
+	buf_ops_destroy(bops);
 	close(fd);
 }
-- 
2.20.1

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[igt-dev] [PATCH i-g-t v4 06/25] i915/gem_pipe_control_store_loop.c: Remove libdrm dependency

[Dominik Grzegorzek]

Use intel_bb / intel_buf to remove libdrm dependency.

Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 tests/i915/gem_pipe_control_store_loop.c | 143 +++++++++++------------
 1 file changed, 69 insertions(+), 74 deletions(-)

diff --git a/tests/i915/gem_pipe_control_store_loop.c b/tests/i915/gem_pipe_control_store_loop.c
index 863a4871..d508ea29 100644
--- a/tests/i915/gem_pipe_control_store_loop.c
+++ b/tests/i915/gem_pipe_control_store_loop.c
@@ -43,13 +43,11 @@
 #include "drm.h"
 #include "i915/gem.h"
 #include "igt.h"
-#include "intel_bufmgr.h"
 
 IGT_TEST_DESCRIPTION("Test (TLB-)Coherency of pipe_control QW writes.");
 
-static drm_intel_bufmgr *bufmgr;
-struct intel_batchbuffer *batch;
-uint32_t devid;
+static struct buf_ops *bops;
+static struct intel_bb *ibb;
 
 #define GFX_OP_PIPE_CONTROL	((0x3<<29)|(0x3<<27)|(0x2<<24)|2)
 #define   PIPE_CONTROL_WRITE_IMMEDIATE	(1<<14)
@@ -68,96 +66,102 @@ store_pipe_control_loop(bool preuse_buffer, int timeout)
 {
 	int val = 0;
 	uint32_t *buf;
-	drm_intel_bo *target_bo;
+	struct intel_buf *target_buf;
 
 	igt_until_timeout(timeout) {
 		/* we want to check tlb consistency of the pipe_control target,
 		 * so get a new buffer every time around */
-		target_bo = drm_intel_bo_alloc(bufmgr, "target bo", 4096, 4096);
-		igt_assert(target_bo);
+		target_buf = intel_buf_create(bops, 32, 32, 32, 4096,
+					      I915_TILING_NONE,
+					      I915_COMPRESSION_NONE);
+		intel_bb_add_intel_buf(ibb, target_buf, true);
 
 		if (preuse_buffer) {
-			COLOR_BLIT_COPY_BATCH_START(0);
-			OUT_BATCH((3 << 24) | (0xf0 << 16) | 64);
-			OUT_BATCH(0);
-			OUT_BATCH(1 << 16 | 1);
+			intel_bb_out(ibb, XY_COLOR_BLT_CMD_NOLEN |
+				     COLOR_BLT_WRITE_ALPHA |
+				     XY_COLOR_BLT_WRITE_RGB |
+				     (4 + (ibb->gen >= 8)));
+
+			intel_bb_out(ibb, (3 << 24) | (0xf0 << 16) | 64);
+			intel_bb_out(ibb, 0);
+			intel_bb_out(ibb, 1 << 16 | 1);
 
 			/*
 			 * IMPORTANT: We need to preuse the buffer in a
 			 * different domain than what the pipe control write
 			 * (and kernel wa) uses!
 			 */
-			OUT_RELOC_FENCED(target_bo,
-			     I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
-			     0);
-			OUT_BATCH(0xdeadbeef);
-			ADVANCE_BATCH();
+			intel_bb_emit_reloc_fenced(ibb, target_buf->handle,
+						   I915_GEM_DOMAIN_RENDER,
+						   I915_GEM_DOMAIN_RENDER,
+						   0, target_buf->addr.offset);
+			intel_bb_out(ibb, 0xdeadbeef);
 
-			intel_batchbuffer_flush(batch);
+			intel_bb_flush_blit(ibb);
 		}
 
 		/* gem_storedw_batches_loop.c is a bit overenthusiastic with
 		 * creating new batchbuffers - with buffer reuse disabled, the
 		 * support code will do that for us. */
-		if (batch->gen >= 8) {
-			BEGIN_BATCH(4, 1);
-			OUT_BATCH(GFX_OP_PIPE_CONTROL + 1);
-			OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
-			OUT_RELOC_FENCED(target_bo,
-			     I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
-			     PIPE_CONTROL_GLOBAL_GTT);
-			OUT_BATCH(val); /* write data */
-			ADVANCE_BATCH();
-
-		} else if (batch->gen >= 6) {
+		if (ibb->gen >= 8) {
+			intel_bb_out(ibb, GFX_OP_PIPE_CONTROL + 1);
+			intel_bb_out(ibb, PIPE_CONTROL_WRITE_IMMEDIATE);
+			intel_bb_emit_reloc_fenced(ibb, target_buf->handle,
+						   I915_GEM_DOMAIN_INSTRUCTION,
+						   I915_GEM_DOMAIN_INSTRUCTION,
+						   PIPE_CONTROL_GLOBAL_GTT,
+						   target_buf->addr.offset);
+			intel_bb_out(ibb, val); /* write data */
+		} else if (ibb->gen >= 6) {
 			/* work-around hw issue, see intel_emit_post_sync_nonzero_flush
 			 * in mesa sources. */
-			BEGIN_BATCH(4, 1);
-			OUT_BATCH(GFX_OP_PIPE_CONTROL);
-			OUT_BATCH(PIPE_CONTROL_CS_STALL |
-			     PIPE_CONTROL_STALL_AT_SCOREBOARD);
-			OUT_BATCH(0); /* address */
-			OUT_BATCH(0); /* write data */
-			ADVANCE_BATCH();
-
-			BEGIN_BATCH(4, 1);
-			OUT_BATCH(GFX_OP_PIPE_CONTROL);
-			OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
-			OUT_RELOC(target_bo,
-			     I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 
-			     PIPE_CONTROL_GLOBAL_GTT);
-			OUT_BATCH(val); /* write data */
-			ADVANCE_BATCH();
-		} else if (batch->gen >= 4) {
-			BEGIN_BATCH(4, 1);
-			OUT_BATCH(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_WC_FLUSH |
-					PIPE_CONTROL_TC_FLUSH |
-					PIPE_CONTROL_WRITE_IMMEDIATE | 2);
-			OUT_RELOC(target_bo,
-				I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
-				PIPE_CONTROL_GLOBAL_GTT);
-			OUT_BATCH(val);
-			OUT_BATCH(0xdeadbeef);
-			ADVANCE_BATCH();
+			intel_bb_out(ibb, GFX_OP_PIPE_CONTROL);
+			intel_bb_out(ibb, PIPE_CONTROL_CS_STALL |
+				     PIPE_CONTROL_STALL_AT_SCOREBOARD);
+			intel_bb_out(ibb, 0); /* address */
+			intel_bb_out(ibb, 0); /* write data */
+
+			intel_bb_out(ibb, GFX_OP_PIPE_CONTROL);
+			intel_bb_out(ibb, PIPE_CONTROL_WRITE_IMMEDIATE);
+			intel_bb_emit_reloc(ibb, target_buf->handle,
+					    I915_GEM_DOMAIN_INSTRUCTION,
+					    I915_GEM_DOMAIN_INSTRUCTION,
+					    PIPE_CONTROL_GLOBAL_GTT,
+					    target_buf->addr.offset);
+			intel_bb_out(ibb, val); /* write data */
+		} else if (ibb->gen >= 4) {
+			intel_bb_out(ibb, GFX_OP_PIPE_CONTROL |
+				     PIPE_CONTROL_WC_FLUSH |
+				     PIPE_CONTROL_TC_FLUSH |
+				     PIPE_CONTROL_WRITE_IMMEDIATE | 2);
+			intel_bb_emit_reloc(ibb, target_buf->handle,
+					    I915_GEM_DOMAIN_INSTRUCTION,
+					    I915_GEM_DOMAIN_INSTRUCTION,
+					    PIPE_CONTROL_GLOBAL_GTT,
+					    target_buf->addr.offset);
+			intel_bb_out(ibb, val);
+			intel_bb_out(ibb, 0xdeadbeef);
 		}
 
-		intel_batchbuffer_flush_on_ring(batch, 0);
+		intel_bb_flush(ibb, ibb->ctx, 0);
+		intel_bb_sync(ibb);
 
-		drm_intel_bo_map(target_bo, 1);
+		intel_buf_cpu_map(target_buf, 0);
 
-		buf = target_bo->virtual;
+		buf = target_buf->ptr;
 		igt_assert(buf[0] == val);
 
-		drm_intel_bo_unmap(target_bo);
+		intel_buf_unmap(target_buf);
 		/* Make doublesure that this buffer won't get reused. */
-		drm_intel_bo_disable_reuse(target_bo);
-		drm_intel_bo_unreference(target_bo);
+		intel_bb_reset(ibb, true);
 
+		intel_buf_destroy(target_buf);
 		val++;
 	}
 }
 
 int fd;
+uint32_t devid;
 
 igt_main
 {
@@ -167,20 +171,12 @@ igt_main
 		gem_require_blitter(fd);
 
 		devid = intel_get_drm_devid(fd);
-
-		bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
-		igt_assert(bufmgr);
+		bops = buf_ops_create(fd);
 
 		igt_skip_on(IS_GEN2(devid) || IS_GEN3(devid));
 		igt_skip_on(devid == PCI_CHIP_I965_G); /* has totally broken pipe control */
 
-		/* IMPORTANT: No call to
-		 * drm_intel_bufmgr_gem_enable_reuse(bufmgr);
-		 * here because we wan't to have fresh buffers (to trash the tlb)
-		 * every time! */
-
-		batch = intel_batchbuffer_alloc(bufmgr, devid);
-		igt_assert(batch);
+		ibb = intel_bb_create(fd, 4096);
 	}
 
 	igt_subtest("fresh-buffer")
@@ -190,9 +186,8 @@ igt_main
 		store_pipe_control_loop(true, 2);
 
 	igt_fixture {
-		intel_batchbuffer_free(batch);
-		drm_intel_bufmgr_destroy(bufmgr);
-
+		intel_bb_destroy(ibb);
+		buf_ops_destroy(bops);
 		close(fd);
 	}
 }
-- 
2.20.1

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[igt-dev] [PATCH i-g-t v4 07/25] i915/gem_pread_after_blit.c: Remove libdrm dependency

[Dominik Grzegorzek]

Use intel_bb / intel_buf to remove libdrm dependency.

Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 tests/i915/gem_pread_after_blit.c | 135 +++++++++++++++---------------
 1 file changed, 68 insertions(+), 67 deletions(-)

diff --git a/tests/i915/gem_pread_after_blit.c b/tests/i915/gem_pread_after_blit.c
index 81454c93..5919011c 100644
--- a/tests/i915/gem_pread_after_blit.c
+++ b/tests/i915/gem_pread_after_blit.c
@@ -50,70 +50,69 @@
 
 IGT_TEST_DESCRIPTION("Test pread behavior when getting values out of"
 		     " just-drawn-to buffers.");
-
-static drm_intel_bufmgr *bufmgr;
-struct intel_batchbuffer *batch;
+static struct intel_bb *ibb;
 static const int width = 512, height = 512;
 static const int size = 1024 * 1024;
 
 #define PAGE_SIZE 4096
 
-static drm_intel_bo *
-create_bo(uint32_t val)
+static struct intel_buf *
+create_bo(struct buf_ops *bops, uint32_t val)
 {
-	drm_intel_bo *bo;
+	struct intel_buf *buf;
 	uint32_t *vaddr;
 	int i;
 
-	bo = drm_intel_bo_alloc(bufmgr, "src bo", size, 4096);
+	buf = intel_buf_create(bops, width, height, 32, 0, I915_TILING_NONE,
+			       I915_COMPRESSION_NONE);
 
 	/* Fill the BO with dwords starting at start_val */
-	drm_intel_bo_map(bo, 1);
-	vaddr = bo->virtual;
+	intel_buf_cpu_map(buf, 1);
+	vaddr = buf->ptr;
 
 	for (i = 0; i < 1024 * 1024 / 4; i++)
 		vaddr[i] = val++;
 
-	drm_intel_bo_unmap(bo);
+	intel_buf_unmap(buf);
 
-	return bo;
+	return buf;
 }
 
 static void
-verify_large_read(drm_intel_bo *bo, uint32_t val)
+verify_large_read(int fd, struct intel_buf *buf, uint32_t val)
 {
-	uint32_t buf[size / 4];
+	uint32_t tmp[size / 4];
 	int i;
 
-	drm_intel_bo_get_subdata(bo, 0, size, buf);
+	gem_read(fd, buf->handle, 0, tmp, size);
 
 	for (i = 0; i < size / 4; i++) {
-		igt_assert_f(buf[i] == val,
+		igt_assert_f(tmp[i] == val,
 			     "Unexpected value 0x%08x instead of "
 			     "0x%08x at offset 0x%08x (%p)\n",
-			     buf[i], val, i * 4, buf);
+			     tmp[i], val, i * 4, tmp);
 		val++;
 	}
 }
 
 /** This reads at the size that Mesa usees for software fallbacks. */
 static void
-verify_small_read(drm_intel_bo *bo, uint32_t val)
+verify_small_read(int fd, struct intel_buf *buf, uint32_t val)
 {
-	uint32_t buf[4096 / 4];
+	uint32_t tmp[4096 / 4];
 	int offset, i;
 
 	for (i = 0; i < 4096 / 4; i++)
-		buf[i] = 0x00c0ffee;
+		tmp[i] = 0x00c0ffee;
 
 	for (offset = 0; offset < size; offset += PAGE_SIZE) {
-		drm_intel_bo_get_subdata(bo, offset, PAGE_SIZE, buf);
+		gem_read(fd, buf->handle, offset, tmp, PAGE_SIZE);
 
 		for (i = 0; i < PAGE_SIZE; i += 4) {
-			igt_assert_f(buf[i / 4] == val,
+			igt_assert_f(tmp[i / 4] == val,
 				     "Unexpected value 0x%08x instead of "
 				     "0x%08x at offset 0x%08x\n",
-				     buf[i / 4], val, i * 4);
+				     tmp[i / 4], val, i * 4);
 			val++;
 		}
 	}
@@ -128,16 +127,17 @@ static igt_hang_t no_hang(int fd)
 
 static igt_hang_t bcs_hang(int fd)
 {
-	return igt_hang_ring(fd, batch->gen >= 6 ? I915_EXEC_BLT : I915_EXEC_DEFAULT);
+	return igt_hang_ring(fd, ibb->gen >= 6 ? I915_EXEC_BLT : I915_EXEC_DEFAULT);
 }
 
-static void do_test(int fd, int cache_level,
-		    drm_intel_bo *src[2],
+static void do_test(struct buf_ops *bops, int cache_level,
+		    struct intel_buf *src[2],
 		    const uint32_t start[2],
-		    drm_intel_bo *tmp[2],
+		    struct intel_buf *tmp[2],
 		    int loop, do_hang do_hang_func)
 {
 	igt_hang_t hang;
+	int fd = buf_ops_get_fd(bops);
 
 	if (cache_level != -1) {
 		gem_set_caching(fd, tmp[0]->handle, cache_level);
@@ -146,55 +146,52 @@ static void do_test(int fd, int cache_level,
 
 	do {
 		/* First, do a full-buffer read after blitting */
-		intel_copy_bo(batch, tmp[0], src[0], width*height*4);
+		intel_bb_copy_intel_buf(ibb, tmp[0], src[0], size);
 		hang = do_hang_func(fd);
-		verify_large_read(tmp[0], start[0]);
+		verify_large_read(fd, tmp[0], start[0]);
 		igt_post_hang_ring(fd, hang);
-		intel_copy_bo(batch, tmp[0], src[1], width*height*4);
+		intel_bb_copy_intel_buf(ibb, tmp[0], src[1], size);
 		hang = do_hang_func(fd);
-		verify_large_read(tmp[0], start[1]);
+		verify_large_read(fd, tmp[0], start[1]);
 		igt_post_hang_ring(fd, hang);
 
-		intel_copy_bo(batch, tmp[0], src[0], width*height*4);
+		intel_bb_copy_intel_buf(ibb, tmp[0], src[0], size);
 		hang = do_hang_func(fd);
-		verify_small_read(tmp[0], start[0]);
+		verify_small_read(fd, tmp[0], start[0]);
 		igt_post_hang_ring(fd, hang);
-		intel_copy_bo(batch, tmp[0], src[1], width*height*4);
+		intel_bb_copy_intel_buf(ibb, tmp[0], src[1], size);
 		hang = do_hang_func(fd);
-		verify_small_read(tmp[0], start[1]);
+		verify_small_read(fd, tmp[0], start[1]);
 		igt_post_hang_ring(fd, hang);
 
-		intel_copy_bo(batch, tmp[0], src[0], width*height*4);
+		intel_bb_copy_intel_buf(ibb, tmp[0], src[0], size);
 		hang = do_hang_func(fd);
-		verify_large_read(tmp[0], start[0]);
+		verify_large_read(fd, tmp[0], start[0]);
 		igt_post_hang_ring(fd, hang);
 
-		intel_copy_bo(batch, tmp[0], src[0], width*height*4);
-		intel_copy_bo(batch, tmp[1], src[1], width*height*4);
+		intel_bb_copy_intel_buf(ibb, tmp[0], src[0], size);
+		intel_bb_copy_intel_buf(ibb, tmp[1], src[1], size);
 		hang = do_hang_func(fd);
-		verify_large_read(tmp[0], start[0]);
-		verify_large_read(tmp[1], start[1]);
+		verify_large_read(fd, tmp[0], start[0]);
+		verify_large_read(fd, tmp[1], start[1]);
 		igt_post_hang_ring(fd, hang);
 
-		intel_copy_bo(batch, tmp[0], src[0], width*height*4);
-		intel_copy_bo(batch, tmp[1], src[1], width*height*4);
+		intel_bb_copy_intel_buf(ibb, tmp[0], src[0], size);
+		intel_bb_copy_intel_buf(ibb, tmp[1], src[1], size);
 		hang = do_hang_func(fd);
-		verify_large_read(tmp[1], start[1]);
-		verify_large_read(tmp[0], start[0]);
+		verify_large_read(fd, tmp[1], start[1]);
+		verify_large_read(fd, tmp[0], start[0]);
 		igt_post_hang_ring(fd, hang);
 
-		intel_copy_bo(batch, tmp[1], src[0], width*height*4);
-		intel_copy_bo(batch, tmp[0], src[1], width*height*4);
+		intel_bb_copy_intel_buf(ibb, tmp[1], src[0], size);
+		intel_bb_copy_intel_buf(ibb, tmp[0], src[1], size);
 		hang = do_hang_func(fd);
-		verify_large_read(tmp[0], start[1]);
-		verify_large_read(tmp[1], start[0]);
+		verify_large_read(fd, tmp[0], start[1]);
+		verify_large_read(fd, tmp[1], start[0]);
 		igt_post_hang_ring(fd, hang);
 	} while (--loop);
 }
 
-drm_intel_bo *src[2], *dst[2];
-int fd;
-
 igt_main
 {
 	const uint32_t start[2] = {0, 1024 * 1024 / 4};
@@ -208,43 +205,47 @@ igt_main
 		{ "display", 2 },
 		{ NULL, -1 },
 	}, *t;
+	struct intel_buf *src[2], *dst[2];
+	struct buf_ops *bops;
+	int fd;
 
 	igt_fixture {
 		fd = drm_open_driver(DRIVER_INTEL);
 		igt_require_gem(fd);
 
-		bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
-		drm_intel_bufmgr_gem_enable_reuse(bufmgr);
-		batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
+		bops = buf_ops_create(fd);
+		ibb = intel_bb_create(fd, 4096);
 
-		src[0] = create_bo(start[0]);
-		src[1] = create_bo(start[1]);
+		src[0] = create_bo(bops, start[0]);
+		src[1] = create_bo(bops, start[1]);
 
-		dst[0] = drm_intel_bo_alloc(bufmgr, "dst bo", size, 4096);
-		dst[1] = drm_intel_bo_alloc(bufmgr, "dst bo", size, 4096);
+		dst[0] = intel_buf_create(bops, width, height, 32, 4096,
+					  I915_TILING_NONE, I915_COMPRESSION_NONE);
+		dst[1] = intel_buf_create(bops, width, height, 32, 4096,
+					  I915_TILING_NONE, I915_COMPRESSION_NONE);
 	}
 
 	for (t = tests; t->name; t++) {
 		igt_subtest_f("%s-normal", t->name)
-			do_test(fd, t->cache, src, start, dst, 1, no_hang);
+			do_test(bops, t->cache, src, start, dst, 1, no_hang);
 
 		igt_fork_signal_helper();
 		igt_subtest_f("%s-interruptible", t->name)
-			do_test(fd, t->cache, src, start, dst, 100, no_hang);
+			do_test(bops, t->cache, src, start, dst, 100, no_hang);
 		igt_stop_signal_helper();
 
 		igt_subtest_f("%s-hang", t->name)
-			do_test(fd, t->cache, src, start, dst, 1, bcs_hang);
+			do_test(bops, t->cache, src, start, dst, 1, bcs_hang);
 	}
 
 	igt_fixture {
-		drm_intel_bo_unreference(src[0]);
-		drm_intel_bo_unreference(src[1]);
-		drm_intel_bo_unreference(dst[0]);
-		drm_intel_bo_unreference(dst[1]);
+		intel_buf_destroy(src[0]);
+		intel_buf_destroy(src[1]);
+		intel_buf_destroy(dst[0]);
+		intel_buf_destroy(dst[1]);
 
-		intel_batchbuffer_free(batch);
-		drm_intel_bufmgr_destroy(bufmgr);
+		intel_bb_destroy(ibb);
+		buf_ops_destroy(bops);
 	}
 
 	igt_fixture
-- 
2.20.1

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[igt-dev] [PATCH i-g-t v4 08/25] i915/gem_threaded_access_tiled.c: Remove libdrm dependency

[Dominik Grzegorzek]

Use intel_bb / intel_buf to remove libdrm dependency.

Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 tests/i915/gem_threaded_access_tiled.c | 38 ++++++++++++--------------
 1 file changed, 18 insertions(+), 20 deletions(-)

diff --git a/tests/i915/gem_threaded_access_tiled.c b/tests/i915/gem_threaded_access_tiled.c
index 6442d589..47b2962e 100644
--- a/tests/i915/gem_threaded_access_tiled.c
+++ b/tests/i915/gem_threaded_access_tiled.c
@@ -31,8 +31,6 @@
 #include <unistd.h>
 #include <pthread.h>
 
-#include "intel_bufmgr.h"
-
 IGT_TEST_DESCRIPTION("Check parallel access to tiled memory.");
 
 /* Testcase: check parallel access to tiled memory
@@ -45,10 +43,10 @@ IGT_TEST_DESCRIPTION("Check parallel access to tiled memory.");
 #define HEIGHT 4096
 
 struct thread_ctx {
-	drm_intel_bo *bo;
+	struct intel_buf *buf;
 };
 
-static drm_intel_bufmgr *bufmgr;
+static struct buf_ops *bops;
 static struct thread_ctx tctx[NUM_THREADS];
 
 static void *copy_fn(void *p)
@@ -60,13 +58,13 @@ static void *copy_fn(void *p)
 	if (buf == NULL)
 		return (void *)1;
 
-	memcpy(buf, c->bo->virtual, WIDTH * HEIGHT);
+	memcpy(buf, c->buf->ptr, WIDTH * HEIGHT);
 
 	free(buf);
 	return (void *)0;
 }
 
-static int copy_tile_threaded(drm_intel_bo *bo)
+static int copy_tile_threaded(struct intel_buf *buf)
 {
 	int i;
 	int r;
@@ -74,7 +72,7 @@ static int copy_tile_threaded(drm_intel_bo *bo)
 	void *status;
 
 	for (i = 0; i < NUM_THREADS; i++) {
-		tctx[i].bo = bo;
+		tctx[i].buf = buf;
 		r = pthread_create(&thr[i], NULL, copy_fn, (void *)&tctx[i]);
 		igt_assert_eq(r, 0);
 	}
@@ -90,9 +88,8 @@ static int copy_tile_threaded(drm_intel_bo *bo)
 igt_simple_main
 {
 	int fd;
-	drm_intel_bo *bo;
+	struct intel_buf *buf;
 	uint32_t tiling_mode = I915_TILING_Y;
-	unsigned long pitch = 0;
 	int r;
 
 	fd = drm_open_driver(DRIVER_INTEL);
@@ -100,24 +97,25 @@ igt_simple_main
 
 	igt_require(gem_available_fences(fd) > 0);
 
-	bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
-	igt_assert(bufmgr);
+	bops = buf_ops_create(fd);
 
-	bo = drm_intel_bo_alloc_tiled(bufmgr, "mmap bo", WIDTH, HEIGHT, 1,
-				      &tiling_mode, &pitch, 0);
-	igt_assert(bo);
+	buf = intel_buf_create(bops, WIDTH, HEIGHT, 8, 0, tiling_mode,
+			       I915_COMPRESSION_NONE);
+	igt_assert(buf);
 
-	r = drm_intel_gem_bo_map_gtt(bo);
-	igt_assert(!r);
+	buf->ptr = __gem_mmap__gtt(fd, buf->handle, buf->surface[0].size,
+				   PROT_WRITE | PROT_READ);
+	igt_assert(buf->ptr);
 
-	r = copy_tile_threaded(bo);
+	r = copy_tile_threaded(buf);
 	igt_assert(!r);
 
-	r = drm_intel_gem_bo_unmap_gtt(bo);
+	r = gem_munmap(buf->ptr, buf->surface[0].size);
+	buf->ptr = NULL;
 	igt_assert(!r);
 
-	drm_intel_bo_unreference(bo);
-	drm_intel_bufmgr_destroy(bufmgr);
+	intel_buf_destroy(buf);
+	buf_ops_destroy(bops);
 
 	close(fd);
 }
-- 
2.20.1

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[igt-dev] [PATCH i-g-t v4 09/25] i915/gem_tiled_blits: Remove libdrm dependency

[Dominik Grzegorzek]

Use intel_bb / intel_buf to remove libdrm dependency.

Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 tests/i915/gem_tiled_blits.c | 75 ++++++++++++++++++------------------
 1 file changed, 38 insertions(+), 37 deletions(-)

diff --git a/tests/i915/gem_tiled_blits.c b/tests/i915/gem_tiled_blits.c
index 36e96785..acbe1e37 100644
--- a/tests/i915/gem_tiled_blits.c
+++ b/tests/i915/gem_tiled_blits.c
@@ -60,49 +60,51 @@ IGT_TEST_DESCRIPTION("Test doing many tiled blits, with a working set larger"
 
 static int width = 512, height = 512;
 
-static drm_intel_bo *
-create_bo(drm_intel_bufmgr *bufmgr, struct intel_batchbuffer *batch, uint32_t x)
+static struct intel_buf *
+create_bo(struct buf_ops *bops, struct intel_bb *ibb, uint32_t x)
 {
-	drm_intel_bo *bo, *linear_bo;
+	struct intel_buf *buf, *linear_buf;
 	uint32_t *linear;
 	uint32_t tiling = I915_TILING_X;
 	int i;
 
-	bo = drm_intel_bo_alloc(bufmgr, "tiled bo", 1024 * 1024, 4096);
-	do_or_die(drm_intel_bo_set_tiling(bo, &tiling, width * 4));
-	igt_assert(tiling == I915_TILING_X);
+	buf = intel_buf_create(bops, width, height, 32, 4096, tiling,
+			       I915_COMPRESSION_NONE);
 
-	linear_bo = drm_intel_bo_alloc(bufmgr, "linear src", 1024 * 1024, 4096);
+	linear_buf = intel_buf_create(bops, width, height, 32, 4096,
+				      I915_TILING_NONE, I915_COMPRESSION_NONE);
 
 	/* Fill the BO with dwords starting at start_val */
-	do_or_die(drm_intel_bo_map(linear_bo, 1));
-	linear = linear_bo->virtual;
+	intel_buf_cpu_map(linear_buf, 1);
+	linear = linear_buf->ptr;
 	for (i = 0; i < 1024 * 1024 / 4; i++)
 		linear[i] = x++;
-	drm_intel_bo_unmap(linear_bo);
+	intel_buf_unmap(linear_buf);
 
-	intel_copy_bo (batch, bo, linear_bo, width*height*4);
+	intel_bb_copy_intel_buf(ibb, buf, linear_buf, width*height*4);
+	intel_bb_reset(ibb, true);
 
-	drm_intel_bo_unreference(linear_bo);
+	intel_buf_destroy(linear_buf);
 
-	return bo;
+	return buf;
 }
 
 static void
-check_bo(drm_intel_bo *bo, uint32_t val, struct intel_batchbuffer *batch)
+check_bo(struct intel_buf *buf, uint32_t val, struct intel_bb *ibb)
 {
-	drm_intel_bo *linear_bo;
+	struct intel_buf *linear_buf;
 	uint32_t *linear;
 	int num_errors;
 	int i;
 
-	linear_bo = drm_intel_bo_alloc(bo->bufmgr, "linear dst",
-				       1024 * 1024, 4096);
+	linear_buf = intel_buf_create(buf->bops, width, height, 32, 4096,
+				      I915_TILING_NONE, I915_COMPRESSION_NONE);
 
-	intel_copy_bo(batch, linear_bo, bo, width*height*4);
+	intel_bb_copy_intel_buf(ibb, linear_buf, buf, width*height*4);
+	intel_bb_reset(ibb, true);
 
-	do_or_die(drm_intel_bo_map(linear_bo, 0));
-	linear = linear_bo->virtual;
+	intel_buf_cpu_map(linear_buf, 0);
+	linear = linear_buf->ptr;
 
 	num_errors = 0;
 	for (i = 0; i < 1024 * 1024 / 4; i++) {
@@ -112,31 +114,28 @@ check_bo(drm_intel_bo *bo, uint32_t val, struct intel_batchbuffer *batch)
 		val++;
 	}
 	igt_assert_eq(num_errors, 0);
-	drm_intel_bo_unmap(linear_bo);
+	intel_buf_unmap(linear_buf);
 
-	drm_intel_bo_unreference(linear_bo);
+	intel_buf_destroy(linear_buf);
 }
 
 static void run_test(int fd, int count)
 {
-	struct intel_batchbuffer *batch;
-	drm_intel_bufmgr *bufmgr;
-	drm_intel_bo **bo;
+	struct intel_bb *ibb;
+	struct buf_ops *bops;
+	struct intel_buf **bo;
 	uint32_t *bo_start_val;
 	uint32_t start = 0;
 	int i;
 
-	bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
-	drm_intel_bufmgr_gem_set_vma_cache_size(bufmgr, 32);
-	drm_intel_bufmgr_gem_enable_reuse(bufmgr);
-	batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
+	bops = buf_ops_create(fd);
+	ibb = intel_bb_create(fd, 4096);
 
-
-	bo = malloc(sizeof(drm_intel_bo *)*count);
+	bo = malloc(sizeof(struct intel_buf *)*count);
 	bo_start_val = malloc(sizeof(uint32_t)*count);
 
 	for (i = 0; i < count; i++) {
-		bo[i] = create_bo(bufmgr, batch, start);
+		bo[i] = create_bo(bops, ibb, start);
 		bo_start_val[i] = start;
 		start += 1024 * 1024 / 4;
 	}
@@ -148,20 +147,22 @@ static void run_test(int fd, int count)
 		if (src == dst)
 			continue;
 
-		intel_copy_bo(batch, bo[dst], bo[src], width*height*4);
+		intel_bb_copy_intel_buf(ibb, bo[dst], bo[src], width*height*4);
+		intel_bb_reset(ibb, true);
+
 		bo_start_val[dst] = bo_start_val[src];
 	}
 
 	for (i = 0; i < count; i++) {
-		check_bo(bo[i], bo_start_val[i], batch);
-		drm_intel_bo_unreference(bo[i]);
+		check_bo(bo[i], bo_start_val[i], ibb);
+		intel_buf_destroy(bo[i]);
 	}
 
 	free(bo_start_val);
 	free(bo);
 
-	intel_batchbuffer_free(batch);
-	drm_intel_bufmgr_destroy(bufmgr);
+	intel_bb_destroy(ibb);
+	buf_ops_destroy(bops);
 }
 
 #define MAX_32b ((1ull << 32) - 4096)
-- 
2.20.1

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[igt-dev] [PATCH i-g-t v4 10/25] i915/gem_unfence_active_buffers.c: Remove librdm dependency

[Dominik Grzegorzek]

Use intel_bb / intel_buf to remove libdrm dependency.

Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 tests/i915/gem_unfence_active_buffers.c | 134 ++++++++++++------------
 1 file changed, 69 insertions(+), 65 deletions(-)

diff --git a/tests/i915/gem_unfence_active_buffers.c b/tests/i915/gem_unfence_active_buffers.c
index 1e69c70d..fc30755f 100644
--- a/tests/i915/gem_unfence_active_buffers.c
+++ b/tests/i915/gem_unfence_active_buffers.c
@@ -51,23 +51,22 @@
 #include "drm.h"
 #include "i915/gem.h"
 #include "igt.h"
-#include "intel_bufmgr.h"
 
 IGT_TEST_DESCRIPTION("Check for use-after-free in the fence stealing code.");
 
-static drm_intel_bufmgr *bufmgr;
-struct intel_batchbuffer *batch;
-uint32_t devid;
-
-#define TEST_SIZE (1024*1024)
-#define TEST_STRIDE (4*1024)
+#define WIDTH 1024
+#define HEIGHT 1024
+#define TEST_SIZE (WIDTH*HEIGHT)
+#define TEST_STRIDE (4*WIDTH)
 
 uint32_t data[TEST_SIZE/4];
 
 igt_simple_main
 {
 	int i, ret, fd, num_fences;
-	drm_intel_bo *busy_bo, *test_bo;
+	struct intel_bb *ibb;
+	struct buf_ops *bops;
+	struct intel_buf *busy_buf, *test_buf;
 	uint32_t tiling = I915_TILING_X;
 
 	for (i = 0; i < 1024*256; i++)
@@ -77,86 +76,91 @@ igt_simple_main
 	igt_require_gem(fd);
 	gem_require_blitter(fd);
 
-	bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
-	drm_intel_bufmgr_gem_enable_reuse(bufmgr);
-	devid = intel_get_drm_devid(fd);
-	batch = intel_batchbuffer_alloc(bufmgr, devid);
+	bops = buf_ops_create(fd);
+	ibb = intel_bb_create(fd, 4 * 4096);
 
 	igt_info("filling ring\n");
-	busy_bo = drm_intel_bo_alloc(bufmgr, "busy bo bo", 16*1024*1024, 4096);
+	busy_buf = intel_buf_create(bops, WIDTH, HEIGHT, 16, 4096, I915_TILING_NONE,
+				   I915_COMPRESSION_NONE);
 
 	for (i = 0; i < 250; i++) {
-		BLIT_COPY_BATCH_START(0);
-		OUT_BATCH((3 << 24) | /* 32 bits */
+		intel_bb_blit_start(ibb, 0);
+		intel_bb_out(ibb, (3 << 24) | /* 32 bits */
 			  (0xcc << 16) | /* copy ROP */
 			  2*1024*4);
-		OUT_BATCH(0 << 16 | 1024);
-		OUT_BATCH((2048) << 16 | (2048));
-		OUT_RELOC_FENCED(busy_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
-		OUT_BATCH(0 << 16 | 0);
-		OUT_BATCH(2*1024*4);
-		OUT_RELOC_FENCED(busy_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
-		ADVANCE_BATCH();
-
-		if (batch->gen >= 6) {
-			BEGIN_BATCH(3, 0);
-			OUT_BATCH(XY_SETUP_CLIP_BLT_CMD);
-			OUT_BATCH(0);
-			OUT_BATCH(0);
-			ADVANCE_BATCH();
+		intel_bb_out(ibb, 0 << 16 | 1024);
+		intel_bb_out(ibb, (2048) << 16 | (2048));
+		intel_bb_emit_reloc_fenced(ibb, busy_buf->handle,
+					   I915_GEM_DOMAIN_RENDER,
+					   I915_GEM_DOMAIN_RENDER, 0, 0x0);
+		intel_bb_out(ibb, 0 << 16 | 0);
+		intel_bb_out(ibb, 2*1024*4);
+		intel_bb_emit_reloc_fenced(ibb, busy_buf->handle,
+					   I915_GEM_DOMAIN_RENDER, 0, 0, 0x0);
+
+		if (ibb->gen >= 6) {
+			intel_bb_out(ibb, XY_SETUP_CLIP_BLT_CMD);
+			intel_bb_out(ibb, 0);
+			intel_bb_out(ibb, 0);
 		}
 	}
-	intel_batchbuffer_flush(batch);
+	intel_bb_flush_blit(ibb);
 
 	num_fences = gem_available_fences(fd);
 	igt_info("creating havoc on %i fences\n", num_fences);
 
 	for (i = 0; i < num_fences*2; i++) {
-		test_bo = drm_intel_bo_alloc(bufmgr, "test_bo",
-					     TEST_SIZE, 4096);
-		ret = drm_intel_bo_set_tiling(test_bo, &tiling, TEST_STRIDE);
+		test_buf = intel_buf_create(bops, WIDTH, HEIGHT, 32, 4096,
+					    tiling, I915_COMPRESSION_NONE);
 		igt_assert(ret == 0);
 
-		drm_intel_bo_disable_reuse(test_bo);
-
-		BLIT_COPY_BATCH_START(0);
-		OUT_BATCH((3 << 24) | /* 32 bits */
+		intel_bb_blit_start(ibb, 0);
+		intel_bb_out(ibb, (3 << 24) | /* 32 bits */
 			  (0xcc << 16) | /* copy ROP */
 			  TEST_STRIDE);
-		OUT_BATCH(0 << 16 | 0);
-		OUT_BATCH((1) << 16 | (1));
-		OUT_RELOC_FENCED(test_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
-		OUT_BATCH(0 << 16 | 0);
-		OUT_BATCH(TEST_STRIDE);
-		OUT_RELOC_FENCED(test_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
-		ADVANCE_BATCH();
-		intel_batchbuffer_flush(batch);
-		igt_info("test bo offset: %#lx\n", test_bo->offset);
-
-		drm_intel_bo_unreference(test_bo);
+		intel_bb_out(ibb, 0 << 16 | 0);
+		intel_bb_out(ibb, (1) << 16 | (1));
+		intel_bb_emit_reloc_fenced(ibb, test_buf->handle,
+					   I915_GEM_DOMAIN_RENDER,
+					   I915_GEM_DOMAIN_RENDER, 0, 0x0);
+		intel_bb_out(ibb, 0 << 16 | 0);
+		intel_bb_out(ibb, TEST_STRIDE);
+		intel_bb_emit_reloc_fenced(ibb, test_buf->handle,
+					   I915_GEM_DOMAIN_RENDER, 0, 0, 0x0);
+
+		intel_bb_flush_blit(ibb);
+		igt_info("test bo offset: %#lx\n",
+			 intel_bb_get_object_offset(ibb, test_buf->handle));
+
+		intel_buf_destroy(test_buf);
+		intel_bb_reset(ibb, true);
 	}
 
 	/* launch a few batchs to ensure the damaged slab objects get reused. */
 	for (i = 0; i < 10; i++) {
-		BLIT_COPY_BATCH_START(0);
-		OUT_BATCH((3 << 24) | /* 32 bits */
+		intel_bb_blit_start(ibb, 0);
+		intel_bb_out(ibb, (3 << 24) | /* 32 bits */
 			  (0xcc << 16) | /* copy ROP */
 			  2*1024*4);
-		OUT_BATCH(0 << 16 | 1024);
-		OUT_BATCH((1) << 16 | (1));
-		OUT_RELOC_FENCED(busy_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
-		OUT_BATCH(0 << 16 | 0);
-		OUT_BATCH(2*1024*4);
-		OUT_RELOC_FENCED(busy_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
-		ADVANCE_BATCH();
-
-		if (batch->gen >= 8) {
-			BEGIN_BATCH(3, 0);
-			OUT_BATCH(XY_SETUP_CLIP_BLT_CMD);
-			OUT_BATCH(0);
-			OUT_BATCH(0);
-			ADVANCE_BATCH();
+		intel_bb_out(ibb, 0 << 16 | 1024);
+		intel_bb_out(ibb, (1) << 16 | (1));
+		intel_bb_emit_reloc_fenced(ibb, busy_buf->handle,
+					   I915_GEM_DOMAIN_RENDER,
+					   I915_GEM_DOMAIN_RENDER, 0, 0x0);
+		intel_bb_out(ibb, 0 << 16 | 0);
+		intel_bb_out(ibb, 2*1024*4);
+		intel_bb_emit_reloc_fenced(ibb, busy_buf->handle,
+					   I915_GEM_DOMAIN_RENDER, 0, 0, 0x0);
+
+		if (ibb->gen >= 8) {
+			intel_bb_out(ibb, XY_SETUP_CLIP_BLT_CMD);
+			intel_bb_out(ibb, 0);
+			intel_bb_out(ibb, 0);
 		}
 	}
-	intel_batchbuffer_flush(batch);
+	intel_bb_flush_blit(ibb);
+
+	intel_buf_destroy(busy_buf);
+	intel_bb_destroy(ibb);
+	buf_ops_destroy(bops);
 }
-- 
2.20.1

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[igt-dev] [PATCH i-g-t v4 11/25] i915/gem_unref_active_buffers.c: Remove libdrm dependency

[Dominik Grzegorzek]

Use intel_bb / intel_buf to remove libdrm dependency.

Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 tests/i915/gem_unref_active_buffers.c | 56 +++++++++++++--------------
 1 file changed, 27 insertions(+), 29 deletions(-)

diff --git a/tests/i915/gem_unref_active_buffers.c b/tests/i915/gem_unref_active_buffers.c
index 75394794..6a8cefd5 100644
--- a/tests/i915/gem_unref_active_buffers.c
+++ b/tests/i915/gem_unref_active_buffers.c
@@ -29,8 +29,7 @@
  * Testcase: Unreferencing of active buffers
  *
  * Execs buffers and immediately unreferences them, hence the kernel active list
- * will be the last one to hold a reference on them. Usually libdrm bo caching
- * prevents that by keeping another reference.
+ * will be the last one to hold a reference on them.
  */
 #include <stdlib.h>
 #include <stdio.h>
@@ -44,55 +43,54 @@
 #include "drm.h"
 #include "i915/gem.h"
 #include "igt.h"
-#include "intel_bufmgr.h"
 
 IGT_TEST_DESCRIPTION("Test unreferencing of active buffers.");
 
-static drm_intel_bufmgr *bufmgr;
-struct intel_batchbuffer *batch;
-static drm_intel_bo *load_bo;
-
 igt_simple_main
 {
+	struct intel_buf *load_bo;
+	struct intel_bb *ibb;
+	struct buf_ops *bops;
 	int fd, i;
 
 	fd = drm_open_driver(DRIVER_INTEL);
 	igt_require_gem(fd);
 	gem_require_blitter(fd);
 
-	bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
-	igt_assert(bufmgr);
-	/* don't enable buffer reuse!! */
-	//drm_intel_bufmgr_gem_enable_reuse(bufmgr);
-
-	batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
-	igt_assert(batch);
+	bops = buf_ops_create(fd);
+	ibb = intel_bb_create(fd, 4096);
 
 	/* put some load onto the gpu to keep the light buffers active for long
 	 * enough */
 	for (i = 0; i < 1000; i++) {
-		load_bo = drm_intel_bo_alloc(bufmgr, "target bo", 1024*4096, 4096);
-		igt_assert(load_bo);
+		load_bo = intel_buf_create(bops, 1024, 1024, 32, 4096,
+					   I915_TILING_NONE,
+					   I915_COMPRESSION_NONE);
 
-		BLIT_COPY_BATCH_START(0);
-		OUT_BATCH((3 << 24) | /* 32 bits */
+		intel_bb_add_intel_buf(ibb, load_bo, true);
+		intel_bb_blit_start(ibb, 0);
+		intel_bb_out(ibb, (3 << 24) | /* 32 bits */
 			  (0xcc << 16) | /* copy ROP */
 			  4096);
-		OUT_BATCH(0); /* dst x1,y1 */
-		OUT_BATCH((1024 << 16) | 512);
-		OUT_RELOC_FENCED(load_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
-		OUT_BATCH((0 << 16) | 512); /* src x1, y1 */
-		OUT_BATCH(4096);
-		OUT_RELOC_FENCED(load_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
-		ADVANCE_BATCH();
+		intel_bb_out(ibb, 0); /* dst x1,y1 */
+		intel_bb_out(ibb, (1024 << 16) | 512);
+		intel_bb_emit_reloc_fenced(ibb, load_bo->handle,
+					   I915_GEM_DOMAIN_RENDER,
+					   I915_GEM_DOMAIN_RENDER, 0, 0x0);
+		intel_bb_out(ibb, (0 << 16) | 512); /* src x1, y1 */
+		intel_bb_out(ibb, 4096);
+		intel_bb_emit_reloc_fenced(ibb, load_bo->handle,
+					   I915_GEM_DOMAIN_RENDER,
+					   0, 0, 0x0);
 
-		intel_batchbuffer_flush(batch);
+		intel_bb_flush_blit(ibb);
 
-		drm_intel_bo_disable_reuse(load_bo);
-		drm_intel_bo_unreference(load_bo);
+		intel_buf_destroy(load_bo);
+		intel_bb_reset(ibb, true);
 	}
 
-	drm_intel_bufmgr_destroy(bufmgr);
+	intel_bb_destroy(ibb);
+	buf_ops_destroy(bops);
 
 	close(fd);
 }
-- 
2.20.1

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[igt-dev] [PATCH i-g-t v4 12/25] i915/gem_tiled_partial_pwrite_pread: Remove libdrm dependency

[Dominik Grzegorzek]

Use intel_bb / intel_buf to remove libdrm dependency.

Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 tests/i915/gem_tiled_partial_pwrite_pread.c | 123 ++++++++++----------
 1 file changed, 60 insertions(+), 63 deletions(-)

diff --git a/tests/i915/gem_tiled_partial_pwrite_pread.c b/tests/i915/gem_tiled_partial_pwrite_pread.c
index 7de5358b..6e7ec593 100644
--- a/tests/i915/gem_tiled_partial_pwrite_pread.c
+++ b/tests/i915/gem_tiled_partial_pwrite_pread.c
@@ -53,68 +53,69 @@ IGT_TEST_DESCRIPTION("Test pwrite/pread consistency when touching partial"
  *
  */
 
-static drm_intel_bufmgr *bufmgr;
-struct intel_batchbuffer *batch;
+static struct buf_ops *bops;
+static struct intel_bb *ibb;
 
-drm_intel_bo *scratch_bo;
-drm_intel_bo *staging_bo;
-drm_intel_bo *tiled_staging_bo;
-unsigned long scratch_pitch;
+struct intel_buf *scratch_buf;
+struct intel_buf *staging_buf;
+struct intel_buf *tiled_staging_buf;
 #define BO_SIZE (32*4096)
-uint32_t devid;
 int fd;
 
 static void
-copy_bo(drm_intel_bo *src, int src_tiled,
-	drm_intel_bo *dst, int dst_tiled)
+copy_bo(struct intel_buf *src, int src_tiled,
+	struct intel_buf *dst, int dst_tiled)
 {
-	unsigned long dst_pitch = scratch_pitch;
-	unsigned long src_pitch = scratch_pitch;
+	unsigned long dst_pitch = dst->surface[0].stride;
+	unsigned long src_pitch = src->surface[0].stride;
+	unsigned long scratch_pitch = src->surface[0].stride;
 	uint32_t cmd_bits = 0;
 
 	/* dst is tiled ... */
-	if (intel_gen(devid) >= 4 && dst_tiled) {
+	if (ibb->gen >= 4 && dst_tiled) {
 		dst_pitch /= 4;
 		cmd_bits |= XY_SRC_COPY_BLT_DST_TILED;
 	}
 
-	if (intel_gen(devid) >= 4 && dst_tiled) {
+	if (ibb->gen >= 4 && src_tiled) {
 		src_pitch /= 4;
 		cmd_bits |= XY_SRC_COPY_BLT_SRC_TILED;
 	}
 
-	BLIT_COPY_BATCH_START(cmd_bits);
-	OUT_BATCH((3 << 24) | /* 32 bits */
+	intel_bb_add_intel_buf(ibb, dst, true);
+	intel_bb_blit_start(ibb, cmd_bits);
+	intel_bb_out(ibb, (3 << 24) | /* 32 bits */
 		  (0xcc << 16) | /* copy ROP */
 		  dst_pitch);
-	OUT_BATCH(0 << 16 | 0);
-	OUT_BATCH(BO_SIZE/scratch_pitch << 16 | 1024);
-	OUT_RELOC_FENCED(dst, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
-	OUT_BATCH(0 << 16 | 0);
-	OUT_BATCH(src_pitch);
-	OUT_RELOC_FENCED(src, I915_GEM_DOMAIN_RENDER, 0, 0);
-	ADVANCE_BATCH();
-
-	intel_batchbuffer_flush(batch);
+	intel_bb_out(ibb, 0 << 16 | 0);
+	intel_bb_out(ibb, BO_SIZE/scratch_pitch << 16 | 1024);
+	intel_bb_emit_reloc_fenced(ibb, dst->handle, I915_GEM_DOMAIN_RENDER,
+				   I915_GEM_DOMAIN_RENDER, 0, dst->addr.offset);
+	intel_bb_out(ibb, 0 << 16 | 0);
+	intel_bb_out(ibb, src_pitch);
+	intel_bb_emit_reloc_fenced(ibb, src->handle, I915_GEM_DOMAIN_RENDER, 0,
+				   0, src->addr.offset);
+
+	intel_bb_flush_blit(ibb);
 }
 
 static void
-blt_bo_fill(drm_intel_bo *tmp_bo, drm_intel_bo *bo, int val)
+blt_bo_fill(struct intel_buf *tmp_buf, struct intel_buf *buf, int val)
 {
 	uint8_t *gtt_ptr;
 	int i;
 
-	drm_intel_gem_bo_map_gtt(tmp_bo);
-	gtt_ptr = tmp_bo->virtual;
+	gtt_ptr = gem_mmap__gtt(fd, tmp_buf->handle, tmp_buf->surface[0].size,
+				PROT_WRITE);
 
 	for (i = 0; i < BO_SIZE; i++)
 		gtt_ptr[i] = val;
 
-	drm_intel_gem_bo_unmap_gtt(tmp_bo);
+	gem_munmap(gtt_ptr, tmp_buf->surface[0].size);
 
 	igt_drop_caches_set(fd, DROP_BOUND);
 
-	copy_bo(tmp_bo, 0, bo, 1);
+	copy_bo(tmp_buf, 0, buf, 1);
 }
 
 #define MAX_BLT_SIZE 128
@@ -130,12 +131,12 @@ static void test_partial_reads(void)
 		int start, len;
 		int val = i % 256;
 
-		blt_bo_fill(staging_bo, scratch_bo, i);
+		blt_bo_fill(staging_buf, scratch_buf, i);
 
 		start = random() % BO_SIZE;
 		len = random() % (BO_SIZE-start) + 1;
 
-		drm_intel_bo_get_subdata(scratch_bo, start, len, tmp);
+		gem_read(fd, scratch_buf->handle, start, tmp, len);
 		for (j = 0; j < len; j++) {
 			igt_assert_f(tmp[j] == val,
 				     "mismatch at %i, got: %i, expected: %i\n",
@@ -154,18 +155,17 @@ static void test_partial_writes(void)
 		int start, len;
 		int val = i % 256;
 
-		blt_bo_fill(staging_bo, scratch_bo, i);
+		blt_bo_fill(staging_buf, scratch_buf, i);
 
 		start = random() % BO_SIZE;
 		len = random() % (BO_SIZE-start) + 1;
 
 		memset(tmp, i + 63, BO_SIZE);
 
-		drm_intel_bo_subdata(scratch_bo, start, len, tmp);
+		gem_write(fd, scratch_buf->handle, start, tmp, len);
 
-		copy_bo(scratch_bo, 1, tiled_staging_bo, 1);
-		drm_intel_bo_get_subdata(tiled_staging_bo, 0, BO_SIZE,
-					 compare_tmp);
+		copy_bo(scratch_buf, 1, tiled_staging_buf, 1);
+		gem_read(fd, tiled_staging_buf->handle, 0, compare_tmp, BO_SIZE);
 
 		for (j = 0; j < start; j++) {
 			igt_assert_f(compare_tmp[j] == val,
@@ -182,7 +182,6 @@ static void test_partial_writes(void)
 				     "mismatch at %i, got: %i, expected: %i\n",
 				     j, tmp[j], val);
 		}
-		drm_intel_gem_bo_unmap_gtt(staging_bo);
 
 		igt_progress("partial writes test: ", i, ROUNDS);
 	}
@@ -196,13 +195,13 @@ static void test_partial_read_writes(void)
 		int start, len;
 		int val = i % 256;
 
-		blt_bo_fill(staging_bo, scratch_bo, i);
+		blt_bo_fill(staging_buf, scratch_buf, i);
 
 		/* partial read */
 		start = random() % BO_SIZE;
 		len = random() % (BO_SIZE-start) + 1;
 
-		drm_intel_bo_get_subdata(scratch_bo, start, len, tmp);
+		gem_read(fd, scratch_buf->handle, start, tmp, len);
 		for (j = 0; j < len; j++) {
 			igt_assert_f(tmp[j] == val,
 				     "mismatch in read at %i, got: %i, expected: %i\n",
@@ -212,7 +211,7 @@ static void test_partial_read_writes(void)
 		/* Change contents through gtt to make the pread cachelines
 		 * stale. */
 		val = (i + 17) % 256;
-		blt_bo_fill(staging_bo, scratch_bo, val);
+		blt_bo_fill(staging_buf, scratch_buf, val);
 
 		/* partial write */
 		start = random() % BO_SIZE;
@@ -220,11 +219,10 @@ static void test_partial_read_writes(void)
 
 		memset(tmp, i + 63, BO_SIZE);
 
-		drm_intel_bo_subdata(scratch_bo, start, len, tmp);
+		gem_write(fd, scratch_buf->handle, start, tmp, len);
 
-		copy_bo(scratch_bo, 1, tiled_staging_bo, 1);
-		drm_intel_bo_get_subdata(tiled_staging_bo, 0, BO_SIZE,
-					 compare_tmp);
+		copy_bo(scratch_buf, 1, tiled_staging_buf, 1);
+		gem_read(fd, tiled_staging_buf->handle, 0, compare_tmp, BO_SIZE);
 
 		for (j = 0; j < start; j++) {
 			igt_assert_f(compare_tmp[j] == val,
@@ -241,7 +239,6 @@ static void test_partial_read_writes(void)
 				     "mismatch at %i, got: %i, expected: %i\n",
 				     j, tmp[j], val);
 		}
-		drm_intel_gem_bo_unmap_gtt(staging_bo);
 
 		igt_progress("partial read/writes test: ", i, ROUNDS);
 	}
@@ -261,8 +258,6 @@ static bool known_swizzling(uint32_t handle)
 
 igt_main
 {
-	uint32_t tiling_mode = I915_TILING_X;
-
 	srandom(0xdeadbeef);
 
 	igt_fixture {
@@ -271,28 +266,26 @@ igt_main
 		gem_require_mappable_ggtt(fd);
 		gem_require_blitter(fd);
 
-		bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
-		//drm_intel_bufmgr_gem_enable_reuse(bufmgr);
-		devid = intel_get_drm_devid(fd);
-		batch = intel_batchbuffer_alloc(bufmgr, devid);
+		bops = buf_ops_create(fd);
+		ibb = intel_bb_create(fd, 4096);
 
 		/* overallocate the buffers we're actually using because */
-		scratch_bo = drm_intel_bo_alloc_tiled(bufmgr, "scratch bo", 1024,
-						      BO_SIZE/4096, 4,
-						      &tiling_mode, &scratch_pitch, 0);
-		igt_assert(tiling_mode == I915_TILING_X);
-		igt_assert(scratch_pitch == 4096);
+		scratch_buf = intel_buf_create(bops, 1024, BO_SIZE/4096, 32, 0,
+					       I915_TILING_X,
+					       I915_COMPRESSION_NONE);
 
 		/*
 		 * As we want to compare our template tiled pattern against
 		 * the target bo, we need consistent swizzling on both.
 		 */
-		igt_require(known_swizzling(scratch_bo->handle));
-		staging_bo = drm_intel_bo_alloc(bufmgr, "staging bo", BO_SIZE, 4096);
-		tiled_staging_bo = drm_intel_bo_alloc_tiled(bufmgr, "scratch bo", 1024,
-							    BO_SIZE/4096, 4,
-							    &tiling_mode,
-							    &scratch_pitch, 0);
+		igt_require(known_swizzling(scratch_buf->handle));
+		staging_buf = intel_buf_create(bops, 1024, BO_SIZE/4096, 32,
+					       4096, I915_TILING_NONE,
+					       I915_COMPRESSION_NONE);
+
+		tiled_staging_buf = intel_buf_create(bops, 1024, BO_SIZE/4096,
+						     32, 0, I915_TILING_X,
+						     I915_COMPRESSION_NONE);
 	}
 
 	igt_subtest("reads")
@@ -305,7 +298,11 @@ igt_main
 		test_partial_read_writes();
 
 	igt_fixture {
-		drm_intel_bufmgr_destroy(bufmgr);
+		intel_buf_destroy(scratch_buf);
+		intel_buf_destroy(staging_buf);
+		intel_buf_destroy(tiled_staging_buf);
+		intel_bb_destroy(ibb);
+		buf_ops_destroy(bops);
 
 		close(fd);
 	}
-- 
2.20.1

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[igt-dev] [PATCH i-g-t v4 13/25] i915/gem_set_tiling_vs_blit.c: Remove libdrm dependency

[Dominik Grzegorzek]

Use intel_bb / intel_buf to remove libdrm dependency. The tests
had depended on buffer reuse mechanism, so logic was changed a bit.

Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 tests/i915/gem_set_tiling_vs_blt.c | 219 +++++++++++++++--------------
 1 file changed, 115 insertions(+), 104 deletions(-)

diff --git a/tests/i915/gem_set_tiling_vs_blt.c b/tests/i915/gem_set_tiling_vs_blt.c
index cb164154..c48b13b9 100644
--- a/tests/i915/gem_set_tiling_vs_blt.c
+++ b/tests/i915/gem_set_tiling_vs_blt.c
@@ -57,15 +57,10 @@
 #include "drm.h"
 #include "i915/gem.h"
 #include "igt.h"
-#include "intel_bufmgr.h"
 
 IGT_TEST_DESCRIPTION("Check for proper synchronization of tiling changes vs."
 		     " tiled gpu access.");
 
-static drm_intel_bufmgr *bufmgr;
-struct intel_batchbuffer *batch;
-uint32_t devid;
-
 #define TEST_SIZE (1024*1024)
 #define TEST_STRIDE (4*1024)
 #define TEST_HEIGHT(stride)	(TEST_SIZE/(stride))
@@ -73,159 +68,174 @@ uint32_t devid;
 
 uint32_t data[TEST_SIZE/4];
 
-static void do_test(uint32_t tiling, unsigned stride,
+static void __set_tiling(struct buf_ops *bops, struct intel_buf *buf,
+			 uint32_t tiling, unsigned stride)
+{
+	int ret;
+
+	ret = __gem_set_tiling(buf_ops_get_fd(bops), buf->handle, tiling, stride);
+
+	buf->surface[0].stride = TEST_WIDTH(stride);
+	buf->surface[0].size = buf->surface[0].stride * stride;
+	buf->tiling = tiling;
+
+	igt_assert_eq(ret, 0);
+}
+
+static void do_test(struct buf_ops *bops, uint32_t tiling, unsigned stride,
 		    uint32_t tiling_after, unsigned stride_after)
 {
-	drm_intel_bo *busy_bo, *test_bo, *target_bo;
-	int i, ret;
+	struct intel_buf *busy_buf, *test_buf, *target_buf;
+	struct intel_bb *ibb;
+	int i, fd = buf_ops_get_fd(bops);
 	uint32_t *ptr;
-	uint32_t test_bo_handle;
+	uint32_t test_buf_handle;
 	uint32_t blt_stride, blt_bits;
 	bool tiling_changed = false;
 
 	igt_info("filling ring .. ");
-	busy_bo = drm_intel_bo_alloc(bufmgr, "busy bo bo", 16*1024*1024, 4096);
+	busy_buf = intel_buf_create(bops, 1024, 1024, 16, 4096,
+				    I915_TILING_NONE, I915_COMPRESSION_NONE);
+	ibb = intel_bb_create_with_relocs(fd, 4 * 4096);
 
+	intel_bb_set_fencing(ibb, false);
+	intel_bb_add_intel_buf(ibb, busy_buf, true);
 	for (i = 0; i < 250; i++) {
-		BLIT_COPY_BATCH_START(0);
-		OUT_BATCH((3 << 24) | /* 32 bits */
+		intel_bb_blit_start(ibb, 0);
+		intel_bb_out(ibb, (3 << 24) | /* 32 bits */
 			  (0xcc << 16) | /* copy ROP */
 			  2*1024*4);
-		OUT_BATCH(0 << 16 | 1024);
-		OUT_BATCH((2048) << 16 | (2048));
-		OUT_RELOC_FENCED(busy_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
-		OUT_BATCH(0 << 16 | 0);
-		OUT_BATCH(2*1024*4);
-		OUT_RELOC_FENCED(busy_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
-		ADVANCE_BATCH();
-
-		if (batch->gen >= 6) {
-			BEGIN_BATCH(3, 0);
-			OUT_BATCH(XY_SETUP_CLIP_BLT_CMD);
-			OUT_BATCH(0);
-			OUT_BATCH(0);
-			ADVANCE_BATCH();
+		intel_bb_out(ibb, 1024 << 16 | 0);
+		intel_bb_out(ibb, 2048 << 16 | 2048);
+		intel_bb_emit_reloc_fenced(ibb, busy_buf->handle,
+					   I915_GEM_DOMAIN_RENDER,
+					   I915_GEM_DOMAIN_RENDER, 0, 0);
+		intel_bb_out(ibb, 0 << 16 | 0);
+		intel_bb_out(ibb, 2*1024*4);
+		intel_bb_emit_reloc_fenced(ibb, busy_buf->handle,
+					   I915_GEM_DOMAIN_RENDER, 0, 0, 0);
+
+		if (ibb->gen >= 6) {
+			intel_bb_out(ibb, XY_SETUP_CLIP_BLT_CMD);
+			intel_bb_out(ibb, 0);
+			intel_bb_out(ibb, 0);
 		}
 	}
-	intel_batchbuffer_flush(batch);
-
+	intel_bb_flush_blit(ibb);
+	intel_bb_set_fencing(ibb, true);
 	igt_info("playing tricks .. ");
 	/* first allocate the target so it gets out of the way of playing funky
 	 * tricks */
-	target_bo = drm_intel_bo_alloc(bufmgr, "target bo", TEST_SIZE, 4096);
+	target_buf = intel_buf_create(bops, TEST_WIDTH(TEST_STRIDE),
+				      TEST_HEIGHT(TEST_STRIDE), 32, 4096,
+				      I915_TILING_NONE, I915_COMPRESSION_NONE);
 
+	intel_bb_add_intel_buf(ibb, target_buf, true);
 	/* allocate buffer with parameters _after_ transition we want to check
 	 * and touch it, so that it's properly aligned in the gtt. */
-	test_bo = drm_intel_bo_alloc(bufmgr, "tiled busy bo", TEST_SIZE, 4096);
-	test_bo_handle = test_bo->handle;
-	ret = drm_intel_bo_set_tiling(test_bo, &tiling_after, stride_after);
-	igt_assert_eq(ret, 0);
-	drm_intel_gem_bo_map_gtt(test_bo);
-	ptr = test_bo->virtual;
-	*ptr = 0;
-	ptr = NULL;
-	drm_intel_gem_bo_unmap_gtt(test_bo);
+	test_buf = intel_buf_create(bops, TEST_WIDTH(stride_after),
+				   TEST_HEIGHT(stride_after), 32, 4096,
+				   tiling_after, I915_COMPRESSION_NONE);
 
-	drm_intel_bo_unreference(test_bo);
+	intel_bb_add_intel_buf(ibb, test_buf, true);
 
-	test_bo = NULL;
+	test_buf_handle = test_buf->handle;
 
-	/* note we need a bo bigger than batches, otherwise the buffer reuse
-	 * trick will fail. */
-	test_bo = drm_intel_bo_alloc(bufmgr, "busy bo", TEST_SIZE, 4096);
-	/* double check that the reuse trick worked */
-	igt_assert(test_bo_handle == test_bo->handle);
+	ptr = gem_mmap__gtt(fd, test_buf->handle, TEST_SIZE,
+			    PROT_READ | PROT_WRITE);
+	*ptr = 0;
+	gem_munmap(ptr, TEST_SIZE);
 
-	test_bo_handle = test_bo->handle;
-	/* ensure we have the right tiling before we start. */
-	ret = drm_intel_bo_set_tiling(test_bo, &tiling, stride);
-	igt_assert_eq(ret, 0);
+	/* Reuse previously aligned in the gtt object */
+	intel_buf_init_using_handle(bops, test_buf_handle, test_buf,
+				    TEST_WIDTH(stride), TEST_HEIGHT(stride), 32,
+				    4096, tiling, I915_COMPRESSION_NONE);
+	intel_buf_set_ownership(test_buf, true);
 
 	if (tiling == I915_TILING_NONE) {
-		drm_intel_bo_subdata(test_bo, 0, TEST_SIZE, data);
+		gem_write(fd, test_buf->handle, 0, data, TEST_SIZE);
 	} else {
-		drm_intel_gem_bo_map_gtt(test_bo);
-		ptr = test_bo->virtual;
+		ptr = gem_mmap__gtt(fd, test_buf->handle, TEST_SIZE,
+				    PROT_READ | PROT_WRITE);
+
 		memcpy(ptr, data, TEST_SIZE);
 		ptr = NULL;
-		drm_intel_gem_bo_unmap_gtt(test_bo);
+		gem_munmap(ptr, TEST_SIZE);
 	}
 
 	blt_stride = stride;
 	blt_bits = 0;
-	if (intel_gen(devid) >= 4 && tiling != I915_TILING_NONE) {
+	if (intel_gen(ibb->devid) >= 4 && tiling != I915_TILING_NONE) {
 		blt_stride /= 4;
 		blt_bits = XY_SRC_COPY_BLT_SRC_TILED;
 	}
 
-	BLIT_COPY_BATCH_START(blt_bits);
-	OUT_BATCH((3 << 24) | /* 32 bits */
+	intel_bb_blit_start(ibb, blt_bits);
+	intel_bb_out(ibb, (3 << 24) | /* 32 bits */
 		  (0xcc << 16) | /* copy ROP */
 		  stride);
-	OUT_BATCH(0 << 16 | 0);
-	OUT_BATCH((TEST_HEIGHT(stride)) << 16 | (TEST_WIDTH(stride)));
-	OUT_RELOC_FENCED(target_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
-	OUT_BATCH(0 << 16 | 0);
-	OUT_BATCH(blt_stride);
-	OUT_RELOC_FENCED(test_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
-	ADVANCE_BATCH();
-	intel_batchbuffer_flush(batch);
-
-	drm_intel_bo_unreference(test_bo);
-
-	test_bo = drm_intel_bo_alloc_for_render(bufmgr, "tiled busy bo", TEST_SIZE, 4096);
-	/* double check that the reuse trick worked */
-	igt_assert(test_bo_handle == test_bo->handle);
-	ret = drm_intel_bo_set_tiling(test_bo, &tiling_after, stride_after);
-	igt_assert_eq(ret, 0);
+	intel_bb_out(ibb, 0 << 16 | 0);
+	intel_bb_out(ibb, (TEST_HEIGHT(stride)) << 16 | (TEST_WIDTH(stride)));
+	intel_bb_emit_reloc_fenced(ibb, target_buf->handle,
+				   I915_GEM_DOMAIN_RENDER,
+				   I915_GEM_DOMAIN_RENDER, 0, 0);
+	intel_bb_out(ibb, 0 << 16 | 0);
+	intel_bb_out(ibb, blt_stride);
+	intel_bb_emit_reloc_fenced(ibb, test_buf->handle,
+				   I915_GEM_DOMAIN_RENDER, 0, 0, 0);
+	intel_bb_flush_blit(ibb);
+
+	__set_tiling(bops, test_buf, tiling_after, stride_after);
 
 	/* Note: We don't care about gen4+ here because the blitter doesn't use
 	 * fences there. So not setting tiling flags on the tiled buffer is ok.
 	 */
-	BLIT_COPY_BATCH_START(0);
-	OUT_BATCH((3 << 24) | /* 32 bits */
+
+	intel_bb_blit_start(ibb, 0);
+	intel_bb_out(ibb, (3 << 24) | /* 32 bits */
 		  (0xcc << 16) | /* copy ROP */
 		  stride_after);
-	OUT_BATCH(0 << 16 | 0);
-	OUT_BATCH((1) << 16 | (1));
-	OUT_RELOC_FENCED(test_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
-	OUT_BATCH(0 << 16 | 0);
-	OUT_BATCH(stride_after);
-	OUT_RELOC_FENCED(test_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
-	ADVANCE_BATCH();
-	intel_batchbuffer_flush(batch);
-
+	intel_bb_out(ibb, 0 << 16 | 0);
+	intel_bb_out(ibb, (1) << 16 | (1));
+	intel_bb_emit_reloc_fenced(ibb, test_buf->handle,
+				   I915_GEM_DOMAIN_RENDER,
+				   I915_GEM_DOMAIN_RENDER, 0, 0);
+	intel_bb_out(ibb, 0 << 16 | 0);
+	intel_bb_out(ibb, stride_after);
+	intel_bb_emit_reloc_fenced(ibb, test_buf->handle,
+				   I915_GEM_DOMAIN_RENDER, 0, 0, 0);
+	intel_bb_flush_blit(ibb);
 	/* Now try to trick the kernel the kernel into changing up the fencing
 	 * too early. */
-
 	igt_info("checking .. ");
 	memset(data, 0, TEST_SIZE);
-	drm_intel_bo_get_subdata(target_bo, 0, TEST_SIZE, data);
+
+	gem_read(fd, target_buf->handle, 0, data, TEST_SIZE);
 	for (i = 0; i < TEST_SIZE/4; i++)
 		igt_assert(data[i] == i);
+	/* check whether tiling on the test_buf actually changed. */
+	ptr = gem_mmap__gtt(fd, test_buf->handle, TEST_SIZE,
+			    PROT_WRITE | PROT_READ);
 
-	/* check whether tiling on the test_bo actually changed. */
-	drm_intel_gem_bo_map_gtt(test_bo);
-	ptr = test_bo->virtual;
 	for (i = 0; i < TEST_SIZE/4; i++)
 		if (ptr[i] != data[i])
 			tiling_changed = true;
-	ptr = NULL;
-	drm_intel_gem_bo_unmap_gtt(test_bo);
+
+	gem_munmap(ptr, TEST_SIZE);
 	igt_assert(tiling_changed);
 
-	drm_intel_bo_unreference(test_bo);
-	drm_intel_bo_unreference(target_bo);
-	drm_intel_bo_unreference(busy_bo);
+	intel_buf_destroy(test_buf);
+	intel_buf_destroy(target_buf);
+	intel_buf_destroy(busy_buf);
+
 	igt_info("done\n");
 }
 
-int fd;
-
 igt_main
 {
-	int i;
+	int fd, i;
 	uint32_t tiling, tiling_after;
+	struct buf_ops *bops;
 
 	igt_fixture {
 		for (i = 0; i < 1024*256; i++)
@@ -235,17 +245,13 @@ igt_main
 		igt_require_gem(fd);
 		gem_require_blitter(fd);
 		igt_require(gem_available_fences(fd) > 0);
-
-		bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
-		drm_intel_bufmgr_gem_enable_reuse(bufmgr);
-		devid = intel_get_drm_devid(fd);
-		batch = intel_batchbuffer_alloc(bufmgr, devid);
+		bops = buf_ops_create(fd);
 	}
 
 	igt_subtest("untiled-to-tiled") {
 		tiling = I915_TILING_NONE;
 		tiling_after = I915_TILING_X;
-		do_test(tiling, TEST_STRIDE, tiling_after, TEST_STRIDE);
+		do_test(bops, tiling, TEST_STRIDE, tiling_after, TEST_STRIDE);
 		igt_assert(tiling == I915_TILING_NONE);
 		igt_assert(tiling_after == I915_TILING_X);
 	}
@@ -253,7 +259,7 @@ igt_main
 	igt_subtest("tiled-to-untiled") {
 		tiling = I915_TILING_X;
 		tiling_after = I915_TILING_NONE;
-		do_test(tiling, TEST_STRIDE, tiling_after, TEST_STRIDE);
+		do_test(bops, tiling, TEST_STRIDE, tiling_after, TEST_STRIDE);
 		igt_assert(tiling == I915_TILING_X);
 		igt_assert(tiling_after == I915_TILING_NONE);
 	}
@@ -261,8 +267,13 @@ igt_main
 	igt_subtest("tiled-to-tiled") {
 		tiling = I915_TILING_X;
 		tiling_after = I915_TILING_X;
-		do_test(tiling, TEST_STRIDE/2, tiling_after, TEST_STRIDE);
+		do_test(bops, tiling, TEST_STRIDE/2, tiling_after, TEST_STRIDE);
 		igt_assert(tiling == I915_TILING_X);
 		igt_assert(tiling_after == I915_TILING_X);
 	}
+
+	igt_fixture{
+		buf_ops_destroy(bops);
+		close(fd);
+	}
 }
-- 
2.20.1

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[igt-dev] [PATCH i-g-t v4 14/25] tests/kms_fence_pin_leak.c: Remove libdrm dependency

[Dominik Grzegorzek]

Use intel_bb / intel_buf to remove libdrm dependency.

Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 tests/kms_fence_pin_leak.c | 83 +++++++++++++++++++++-----------------
 1 file changed, 45 insertions(+), 38 deletions(-)

diff --git a/tests/kms_fence_pin_leak.c b/tests/kms_fence_pin_leak.c
index b59efc0a..a86f2cdb 100644
--- a/tests/kms_fence_pin_leak.c
+++ b/tests/kms_fence_pin_leak.c
@@ -37,34 +37,45 @@ IGT_TEST_DESCRIPTION("Exercises full ppgtt fence pin_count leak in the "
 typedef struct {
 	int drm_fd;
 	uint32_t devid;
-	drm_intel_bufmgr *bufmgr;
+	struct buf_ops *bops;
 	igt_display_t display;
-	drm_intel_bo *bos[64]; /* >= num fence registers */
+	struct intel_buf *bos[64]; /* >= num fence registers */
 } data_t;
 
-static void exec_nop(data_t *data, uint32_t handle, drm_intel_context *context)
+static void exec_nop(data_t *data, struct igt_fb *fb, uint32_t context)
 {
-	drm_intel_bo *dst;
-	struct intel_batchbuffer *batch;
+	struct intel_buf *dst;
+	struct intel_bb *ibb;
+	uint32_t name, handle, tiling, stride, width, height, bpp, size;
 
-	dst = gem_handle_to_libdrm_bo(data->bufmgr, data->drm_fd, "", handle);
-	igt_assert(dst);
+	tiling = igt_fb_mod_to_tiling(fb->modifier);
+	stride = fb->strides[0];
+	bpp = fb->plane_bpp[0];
+	size = fb->size;
+	width = stride / (bpp / 8);
+	height = size / stride;
 
-	batch = intel_batchbuffer_alloc(data->bufmgr, data->devid);
-	igt_assert(batch);
+	name = gem_flink(data->drm_fd, fb->gem_handle);
+	handle = gem_open(data->drm_fd, name);
+	dst = intel_buf_create_using_handle(data->bops, handle,
+				    width, height, bpp, 0, tiling, 0);
+	intel_buf_set_ownership(dst, true);
+
+	ibb = intel_bb_create(buf_ops_get_fd(data->bops), 4096);
 
 	/* add the reloc to make sure the kernel will think we write to dst */
-	BEGIN_BATCH(4, 1);
-	OUT_BATCH(MI_BATCH_BUFFER_END);
-	OUT_BATCH(MI_NOOP);
-	OUT_RELOC(dst, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
-	OUT_BATCH(MI_NOOP);
-	ADVANCE_BATCH();
+	intel_bb_add_intel_buf(ibb, dst, true);
+	intel_bb_out(ibb, MI_BATCH_BUFFER_END);
+	intel_bb_out(ibb, MI_NOOP);
+	intel_bb_emit_reloc(ibb, dst->handle, I915_GEM_DOMAIN_RENDER,
+			    I915_GEM_DOMAIN_RENDER, 0, 0x0);
+	intel_bb_out(ibb, MI_NOOP);
+
+	intel_bb_flush_render_with_context(ibb, context);
 
-	intel_batchbuffer_flush_with_context(batch, context);
-	intel_batchbuffer_free(batch);
+	intel_bb_destroy(ibb);
 
-	drm_intel_bo_unreference(dst);
+	intel_buf_destroy(dst);
 }
 
 static void alloc_fence_objs(data_t *data)
@@ -72,13 +83,13 @@ static void alloc_fence_objs(data_t *data)
 	int i;
 
 	for (i = 0; i < ARRAY_SIZE(data->bos); i++) {
-		drm_intel_bo *bo;
+		struct intel_buf *buf;
 
-		bo = drm_intel_bo_alloc(data->bufmgr, "fence bo", 4096, 4096);
-		igt_assert(bo);
-		gem_set_tiling(data->drm_fd, bo->handle, I915_TILING_X, 512);
+		buf = intel_buf_create(data->bops, 32, 32, 32, 4096,
+				       I915_TILING_NONE, I915_COMPRESSION_NONE);
+		gem_set_tiling(data->drm_fd, buf->handle, I915_TILING_X, 512);
 
-		data->bos[i] = bo;
+		data->bos[i] = buf;
 	}
 }
 
@@ -102,7 +113,7 @@ static void free_fence_objs(data_t *data)
 	int i;
 
 	for (i = 0; i < ARRAY_SIZE(data->bos); i++)
-		drm_intel_bo_unreference(data->bos[i]);
+		intel_buf_destroy(data->bos[i]);
 }
 
 static void run_single_test(data_t *data, enum pipe pipe, igt_output_t *output)
@@ -133,19 +144,18 @@ static void run_single_test(data_t *data, enum pipe pipe, igt_output_t *output)
 	igt_display_commit(display);
 
 	for (i = 0; i < 64; i++) {
-		drm_intel_context *ctx;
+		uint32_t ctx;
 
 		/*
 		 * Link fb.gem_handle to the ppgtt vm of ctx so that the context
 		 * destruction will unbind the obj from the ppgtt vm in question.
 		 */
-		ctx = drm_intel_gem_context_create(data->bufmgr);
-		igt_assert(ctx);
-		exec_nop(data, fb[i&1].gem_handle, ctx);
-		drm_intel_gem_context_destroy(ctx);
+		ctx = gem_context_create(data->drm_fd);
+		exec_nop(data, &fb[i&1], ctx);
+		gem_context_destroy(data->drm_fd, ctx);
 
 		/* Force a context switch to make sure ctx gets destroyed for real. */
-		exec_nop(data, fb[i&1].gem_handle, NULL);
+		exec_nop(data, &fb[i&1], 0);
 
 		gem_sync(data->drm_fd, fb[i&1].gem_handle);
 
@@ -196,7 +206,7 @@ static void run_test(data_t *data)
 
 igt_simple_main
 {
-	drm_intel_context *ctx;
+	uint32_t ctx;
 	data_t data = {};
 
 	data.drm_fd = drm_open_driver_master(DRIVER_INTEL);
@@ -207,15 +217,12 @@ igt_simple_main
 
 	kmstest_set_vt_graphics_mode();
 
-	data.bufmgr = drm_intel_bufmgr_gem_init(data.drm_fd, 4096);
-	igt_assert(data.bufmgr);
-	drm_intel_bufmgr_gem_enable_reuse(data.bufmgr);
+	data.bops = buf_ops_create(data.drm_fd);
 
 	igt_display_require(&data.display, data.drm_fd);
 
-	ctx = drm_intel_gem_context_create(data.bufmgr);
-	igt_require(ctx);
-	drm_intel_gem_context_destroy(ctx);
+	ctx = gem_context_create(data.drm_fd);
+	gem_context_destroy(data.drm_fd, ctx);
 
 	alloc_fence_objs(&data);
 
@@ -223,6 +230,6 @@ igt_simple_main
 
 	free_fence_objs(&data);
 
-	drm_intel_bufmgr_destroy(data.bufmgr);
+	buf_ops_destroy(data.bops);
 	igt_display_fini(&data.display);
 }
-- 
2.20.1

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[igt-dev] [PATCH i-g-t v4 15/25] tests/kms_flip.c: Remove libdrm dependency

[Dominik Grzegorzek]

Use intel_bb / intel_buf to remove libdrm dependency.

Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 tests/kms_flip.c | 22 ++++++++--------------
 1 file changed, 8 insertions(+), 14 deletions(-)

diff --git a/tests/kms_flip.c b/tests/kms_flip.c
index b33cfe9c..525cccc7 100755
--- a/tests/kms_flip.c
+++ b/tests/kms_flip.c
@@ -86,8 +86,7 @@
 
 drmModeRes *resources;
 int drm_fd;
-static drm_intel_bufmgr *bufmgr;
-struct intel_batchbuffer *batch;
+static struct buf_ops *bops;
 uint32_t devid;
 int test_time = 3;
 static bool monotonic_timestamp;
@@ -211,20 +210,19 @@ static void emit_fence_stress(struct test_output *o)
 	struct drm_i915_gem_execbuffer2 execbuf;
 	struct drm_i915_gem_exec_object2 *exec;
 	uint32_t buf[2] = { MI_BATCH_BUFFER_END, 0 };
-	drm_intel_bo **bo;
+	struct intel_buf **bo;
 	int i;
 
-	igt_require(bufmgr);
+	igt_require(bops);
 
 	igt_assert(num_fences);
 	bo = calloc(sizeof(*bo), num_fences);
 	exec = calloc(sizeof(*exec), num_fences+1);
 	for (i = 0; i < num_fences - 1; i++) {
 		uint32_t tiling = I915_TILING_X;
-		unsigned long pitch = 0;
-		bo[i] = drm_intel_bo_alloc_tiled(bufmgr,
-						 "X tiled bo", 1024, 1024, 4,
-						 &tiling, &pitch, 0);
+		bo[i] = intel_buf_create(bops, 1024, 1024, 32, 4096, tiling,
+					 I915_COMPRESSION_NONE);
+
 		exec[i].handle = bo[i]->handle;
 		exec[i].flags = EXEC_OBJECT_NEEDS_FENCE;
 	}
@@ -244,7 +242,7 @@ static void emit_fence_stress(struct test_output *o)
 
 	gem_close(drm_fd, exec[i].handle);
 	for (i = 0; i < num_fences - 1; i++)
-		drm_intel_bo_unreference(bo[i]);
+		intel_buf_destroy(bo[i]);
 	free(bo);
 	free(exec);
 }
@@ -1664,11 +1662,7 @@ igt_main
 		get_timestamp_format();
 
 		if (is_i915_device(drm_fd)) {
-			bufmgr = drm_intel_bufmgr_gem_init(drm_fd, 4096);
-			if (bufmgr) {
-				devid = intel_get_drm_devid(drm_fd);
-				batch = intel_batchbuffer_alloc(bufmgr, devid);
-			}
+			bops = buf_ops_create(drm_fd);
 		}
 	}
 
-- 
2.20.1

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[igt-dev] [PATCH i-g-t v4 16/25] tests/kms_psr2_su.c: Get rid of unused bufmgr

[Dominik Grzegorzek]

Removal of bufmgr that was only set but not used.

Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 tests/kms_psr2_su.c | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/tests/kms_psr2_su.c b/tests/kms_psr2_su.c
index d549d9a3..9215c59d 100644
--- a/tests/kms_psr2_su.c
+++ b/tests/kms_psr2_su.c
@@ -30,7 +30,6 @@
 #include <stdio.h>
 #include <string.h>
 #include <sys/timerfd.h>
-#include "intel_bufmgr.h"
 
 IGT_TEST_DESCRIPTION("Test PSR2 selective update");
 
@@ -65,7 +64,6 @@ typedef struct {
 	int drm_fd;
 	int debugfs_fd;
 	igt_display_t display;
-	drm_intel_bufmgr *bufmgr;
 	drmModeModeInfo *mode;
 	igt_output_t *output;
 	struct igt_fb fb[2];
@@ -247,10 +245,6 @@ igt_main
 					       data.debugfs_fd, PSR_MODE_2),
 			      "Sink does not support PSR2\n");
 
-		data.bufmgr = drm_intel_bufmgr_gem_init(data.drm_fd, 4096);
-		igt_assert(data.bufmgr);
-		drm_intel_bufmgr_gem_enable_reuse(data.bufmgr);
-
 		display_init(&data);
 
 		/* Test if PSR2 can be enabled */
@@ -287,7 +281,6 @@ igt_main
 
 	igt_fixture {
 		close(data.debugfs_fd);
-		drm_intel_bufmgr_destroy(data.bufmgr);
 		display_fini(&data);
 	}
 }
-- 
2.20.1

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[igt-dev] [PATCH i-g-t v4 17/25] benchmarks: Remove libdrm dependency

[Dominik Grzegorzek]

Thanks to intel_bb / intel_buf we could get rid of libdrm.
Source buffer creation moved outside do_render function,
because we are not reusing buffers any more so this would wrongly
affect the results.

Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 benchmarks/intel_upload_blit_large.c     | 69 +++++++++++-----------
 benchmarks/intel_upload_blit_large_gtt.c | 72 +++++++++++------------
 benchmarks/intel_upload_blit_large_map.c | 74 ++++++++++++------------
 benchmarks/intel_upload_blit_small.c     | 68 +++++++++++-----------
 4 files changed, 142 insertions(+), 141 deletions(-)

diff --git a/benchmarks/intel_upload_blit_large.c b/benchmarks/intel_upload_blit_large.c
index 12bbae3d..33a8d72b 100644
--- a/benchmarks/intel_upload_blit_large.c
+++ b/benchmarks/intel_upload_blit_large.c
@@ -72,74 +72,73 @@ get_time_in_secs(void)
 }
 
 static void
-do_render(drm_intel_bufmgr *bufmgr, struct intel_batchbuffer *batch,
-	  drm_intel_bo *dst_bo, int width, int height)
+do_render(int fd, struct intel_bb *ibb, struct intel_buf *src_buf,
+	  struct intel_buf *dst_buf, int width, int height)
 {
 	uint32_t data[width * height];
-	drm_intel_bo *src_bo;
 	int i;
 	static uint32_t seed = 1;
 
 	/* Generate some junk.  Real workloads would be doing a lot more
 	 * work to generate the junk.
 	 */
-	for (i = 0; i < width * height; i++) {
+	for (i = 0; i < width * height; i++)
 		data[i] = seed++;
-	}
 
 	/* Upload the junk. */
-	src_bo = drm_intel_bo_alloc(bufmgr, "src", sizeof(data), 4096);
-	drm_intel_bo_subdata(src_bo, 0, sizeof(data), data);
+	gem_write(fd, src_buf->handle, 0, data, sizeof(data));
 
 	/* Render the junk to the dst. */
-	BLIT_COPY_BATCH_START(0);
-	OUT_BATCH((3 << 24) | /* 32 bits */
+	intel_bb_blit_start(ibb, 0);
+	intel_bb_out(ibb, (3 << 24) | /* 32 bits */
 		  (0xcc << 16) | /* copy ROP */
 		  (width * 4) /* dst pitch */);
-	OUT_BATCH(0); /* dst x1,y1 */
-	OUT_BATCH((height << 16) | width); /* dst x2,y2 */
-	OUT_RELOC(dst_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
-	OUT_BATCH(0); /* src x1,y1 */
-	OUT_BATCH(width * 4); /* src pitch */
-	OUT_RELOC(src_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
-	ADVANCE_BATCH();
-
-	intel_batchbuffer_flush(batch);
-
-	drm_intel_bo_unreference(src_bo);
+	intel_bb_out(ibb, 0); /* dst x1,y1 */
+	intel_bb_out(ibb, (height << 16) | width); /* dst x2,y2 */
+	intel_bb_emit_reloc(ibb, dst_buf->handle, I915_GEM_DOMAIN_RENDER,
+			    I915_GEM_DOMAIN_RENDER, 0, dst_buf->addr.offset);
+	intel_bb_out(ibb, 0); /* src x1,y1 */
+	intel_bb_out(ibb, width * 4); /* src pitch */
+	intel_bb_emit_reloc(ibb, src_buf->handle, I915_GEM_DOMAIN_RENDER, 0, 0,
+			    src_buf->addr.offset);
+
+	intel_bb_flush_blit(ibb);
 }
 
 int main(int argc, char **argv)
 {
 	int fd;
-	int object_size = OBJECT_WIDTH * OBJECT_HEIGHT * 4;
 	double start_time, end_time;
-	drm_intel_bo *dst_bo;
-	drm_intel_bufmgr *bufmgr;
-	struct intel_batchbuffer *batch;
+	struct intel_buf *src_buf, *dst_buf;
+	struct buf_ops *bops;
+	struct intel_bb *ibb;
 	int i;
 
 	fd = drm_open_driver(DRIVER_INTEL);
 
-	bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
-	drm_intel_bufmgr_gem_enable_reuse(bufmgr);
+	bops = buf_ops_create(fd);
 
-	batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
+	ibb = intel_bb_create(fd, 4096);
 
-	dst_bo = drm_intel_bo_alloc(bufmgr, "dst", object_size, 4096);
+	dst_buf = intel_buf_create(bops, OBJECT_WIDTH, OBJECT_HEIGHT, 32, 4096,
+				   I915_TILING_NONE, I915_COMPRESSION_NONE);
+	src_buf = intel_buf_create(bops, OBJECT_WIDTH, OBJECT_HEIGHT, 32, 4096,
+				   I915_TILING_NONE, I915_COMPRESSION_NONE);
 
 	/* Prep loop to get us warmed up. */
 	for (i = 0; i < 60; i++) {
-		do_render(bufmgr, batch, dst_bo, OBJECT_WIDTH, OBJECT_HEIGHT);
+		do_render(fd, ibb, src_buf, dst_buf,
+			  OBJECT_WIDTH, OBJECT_HEIGHT);
 	}
-	drm_intel_bo_wait_rendering(dst_bo);
+	intel_bb_sync(ibb);
 
 	/* Do the actual timing. */
 	start_time = get_time_in_secs();
 	for (i = 0; i < 200; i++) {
-		do_render(bufmgr, batch, dst_bo, OBJECT_WIDTH, OBJECT_HEIGHT);
+		do_render(fd, ibb, src_buf, dst_buf,
+			  OBJECT_WIDTH, OBJECT_HEIGHT);
 	}
-	drm_intel_bo_wait_rendering(dst_bo);
+	intel_bb_sync(ibb);
 	end_time = get_time_in_secs();
 
 	printf("%d iterations in %.03f secs: %.01f MB/sec\n", i,
@@ -147,8 +146,10 @@ int main(int argc, char **argv)
 	       (double)i * OBJECT_WIDTH * OBJECT_HEIGHT * 4 / 1024.0 / 1024.0 /
 	       (end_time - start_time));
 
-	intel_batchbuffer_free(batch);
-	drm_intel_bufmgr_destroy(bufmgr);
+	intel_buf_destroy(src_buf);
+	intel_buf_destroy(dst_buf);
+	intel_bb_destroy(ibb);
+	buf_ops_destroy(bops);
 
 	close(fd);
 
diff --git a/benchmarks/intel_upload_blit_large_gtt.c b/benchmarks/intel_upload_blit_large_gtt.c
index 0b704b57..da28686f 100644
--- a/benchmarks/intel_upload_blit_large_gtt.c
+++ b/benchmarks/intel_upload_blit_large_gtt.c
@@ -69,74 +69,70 @@ get_time_in_secs(void)
 }
 
 static void
-do_render(drm_intel_bufmgr *bufmgr, struct intel_batchbuffer *batch,
-	  drm_intel_bo *dst_bo, int width, int height)
+do_render(int fd, struct intel_bb *ibb, struct intel_buf *src_buf,
+	  struct intel_buf *dst_buf, int width, int height)
 {
 	uint32_t *data;
-	drm_intel_bo *src_bo;
 	int i;
 	static uint32_t seed = 1;
 
-	src_bo = drm_intel_bo_alloc(bufmgr, "src", width * height * 4, 4096);
+	data = gem_mmap__gtt(fd, src_buf->handle,
+			     src_buf->surface[0].size, PROT_WRITE);
 
-	drm_intel_gem_bo_map_gtt(src_bo);
-
-	data = src_bo->virtual;
-	for (i = 0; i < width * height; i++) {
+	for (i = 0; i < width * height; i++)
 		data[i] = seed++;
-	}
 
-	drm_intel_gem_bo_unmap_gtt(src_bo);
+	gem_munmap(data, src_buf->surface[0].size);
 
 	/* Render the junk to the dst. */
-	BLIT_COPY_BATCH_START(0);
-	OUT_BATCH((3 << 24) | /* 32 bits */
+	intel_bb_blit_start(ibb, 0);
+	intel_bb_out(ibb, (3 << 24) | /* 32 bits */
 		  (0xcc << 16) | /* copy ROP */
 		  (width * 4) /* dst pitch */);
-	OUT_BATCH(0); /* dst x1,y1 */
-	OUT_BATCH((height << 16) | width); /* dst x2,y2 */
-	OUT_RELOC(dst_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
-	OUT_BATCH(0); /* src x1,y1 */
-	OUT_BATCH(width * 4); /* src pitch */
-	OUT_RELOC(src_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
-	ADVANCE_BATCH();
-
-	intel_batchbuffer_flush(batch);
-
-	drm_intel_bo_unreference(src_bo);
+	intel_bb_out(ibb, 0); /* dst x1,y1 */
+	intel_bb_out(ibb, (height << 16) | width); /* dst x2,y2 */
+	intel_bb_emit_reloc(ibb, dst_buf->handle, I915_GEM_DOMAIN_RENDER,
+			    I915_GEM_DOMAIN_RENDER, 0, dst_buf->addr.offset);
+	intel_bb_out(ibb, 0); /* src x1,y1 */
+	intel_bb_out(ibb, width * 4); /* src pitch */
+	intel_bb_emit_reloc(ibb, src_buf->handle, I915_GEM_DOMAIN_RENDER, 0, 0,
+			    src_buf->addr.offset);
+
+	intel_bb_flush_blit(ibb);
 }
 
 int main(int argc, char **argv)
 {
 	int fd;
-	int object_size = OBJECT_WIDTH * OBJECT_HEIGHT * 4;
 	double start_time, end_time;
-	drm_intel_bo *dst_bo;
-	drm_intel_bufmgr *bufmgr;
-	struct intel_batchbuffer *batch;
+	struct intel_buf *src_buf, *dst_buf;
+	struct buf_ops *bops;
+	struct intel_bb *ibb;
 	int i;
 
 	fd = drm_open_driver(DRIVER_INTEL);
 
-	bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
-	drm_intel_bufmgr_gem_enable_reuse(bufmgr);
+	bops = buf_ops_create(fd);
 
-	batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
+	ibb = intel_bb_create(fd, 4096);
 
-	dst_bo = drm_intel_bo_alloc(bufmgr, "dst", object_size, 4096);
+	dst_buf = intel_buf_create(bops, OBJECT_WIDTH, OBJECT_HEIGHT, 32, 4096,
+				   I915_TILING_NONE, I915_COMPRESSION_NONE);
+	src_buf = intel_buf_create(bops, OBJECT_WIDTH, OBJECT_HEIGHT, 32, 4096,
+				   I915_TILING_NONE, I915_COMPRESSION_NONE);
 
 	/* Prep loop to get us warmed up. */
 	for (i = 0; i < 60; i++) {
-		do_render(bufmgr, batch, dst_bo, OBJECT_WIDTH, OBJECT_HEIGHT);
+		do_render(fd, ibb, src_buf, dst_buf, OBJECT_WIDTH, OBJECT_HEIGHT);
 	}
-	drm_intel_bo_wait_rendering(dst_bo);
+	intel_bb_sync(ibb);
 
 	/* Do the actual timing. */
 	start_time = get_time_in_secs();
 	for (i = 0; i < 200; i++) {
-		do_render(bufmgr, batch, dst_bo, OBJECT_WIDTH, OBJECT_HEIGHT);
+		do_render(fd, ibb, src_buf, dst_buf, OBJECT_WIDTH, OBJECT_HEIGHT);
 	}
-	drm_intel_bo_wait_rendering(dst_bo);
+	intel_bb_sync(ibb);
 	end_time = get_time_in_secs();
 
 	printf("%d iterations in %.03f secs: %.01f MB/sec\n", i,
@@ -144,8 +140,10 @@ int main(int argc, char **argv)
 	       (double)i * OBJECT_WIDTH * OBJECT_HEIGHT * 4 / 1024.0 / 1024.0 /
 	       (end_time - start_time));
 
-	intel_batchbuffer_free(batch);
-	drm_intel_bufmgr_destroy(bufmgr);
+	intel_buf_destroy(src_buf);
+	intel_buf_destroy(dst_buf);
+	intel_bb_destroy(ibb);
+	buf_ops_destroy(bops);
 
 	close(fd);
 
diff --git a/benchmarks/intel_upload_blit_large_map.c b/benchmarks/intel_upload_blit_large_map.c
index ae05434f..542512c9 100644
--- a/benchmarks/intel_upload_blit_large_map.c
+++ b/benchmarks/intel_upload_blit_large_map.c
@@ -72,74 +72,72 @@ get_time_in_secs(void)
 }
 
 static void
-do_render(drm_intel_bufmgr *bufmgr, struct intel_batchbuffer *batch,
-	  drm_intel_bo *dst_bo, int width, int height)
+do_render(struct intel_bb *ibb, struct intel_buf *src_buf,
+	  struct intel_buf *dst_buf, int width, int height)
 {
 	uint32_t *data;
-	drm_intel_bo *src_bo;
 	int i;
 	static uint32_t seed = 1;
 
-	src_bo = drm_intel_bo_alloc(bufmgr, "src", width * height * 4, 4096);
+	intel_buf_cpu_map(src_buf, true);
 
-	drm_intel_bo_map(src_bo, 1);
-
-	data = src_bo->virtual;
-	for (i = 0; i < width * height; i++) {
+	data = src_buf->ptr;
+	for (i = 0; i < width * height; i++)
 		data[i] = seed++;
-	}
 
-	drm_intel_bo_unmap(src_bo);
+	intel_buf_unmap(src_buf);
 
 	/* Render the junk to the dst. */
-	BLIT_COPY_BATCH_START(0);
-	OUT_BATCH((3 << 24) | /* 32 bits */
+	intel_bb_blit_start(ibb, 0);
+	intel_bb_out(ibb, (3 << 24) | /* 32 bits */
 		  (0xcc << 16) | /* copy ROP */
 		  (width * 4) /* dst pitch */);
-	OUT_BATCH(0); /* dst x1,y1 */
-	OUT_BATCH((height << 16) | width); /* dst x2,y2 */
-	OUT_RELOC(dst_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
-	OUT_BATCH(0); /* src x1,y1 */
-	OUT_BATCH(width * 4); /* src pitch */
-	OUT_RELOC(src_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
-	ADVANCE_BATCH();
-
-	intel_batchbuffer_flush(batch);
-
-	drm_intel_bo_unreference(src_bo);
+	intel_bb_out(ibb, 0); /* dst x1,y1 */
+	intel_bb_out(ibb, (height << 16) | width); /* dst x2,y2 */
+	intel_bb_emit_reloc(ibb, dst_buf->handle, I915_GEM_DOMAIN_RENDER,
+			    I915_GEM_DOMAIN_RENDER, 0, dst_buf->addr.offset);
+	intel_bb_out(ibb, 0); /* src x1,y1 */
+	intel_bb_out(ibb, width * 4); /* src pitch */
+	intel_bb_emit_reloc(ibb, src_buf->handle, I915_GEM_DOMAIN_RENDER, 0, 0,
+			    src_buf->addr.offset);
+
+	intel_bb_flush_blit(ibb);
 }
 
 int main(int argc, char **argv)
 {
 	int fd;
-	int object_size = OBJECT_WIDTH * OBJECT_HEIGHT * 4;
 	double start_time, end_time;
-	drm_intel_bo *dst_bo;
-	drm_intel_bufmgr *bufmgr;
-	struct intel_batchbuffer *batch;
+	struct intel_buf *src_buf, *dst_buf;
+	struct buf_ops *bops;
+	struct intel_bb *ibb;
 	int i;
 
 	fd = drm_open_driver(DRIVER_INTEL);
 
-	bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
-	drm_intel_bufmgr_gem_enable_reuse(bufmgr);
+	bops = buf_ops_create(fd);
 
-	batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
+	ibb = intel_bb_create(fd, 4096);
 
-	dst_bo = drm_intel_bo_alloc(bufmgr, "dst", object_size, 4096);
+	dst_buf = intel_buf_create(bops, OBJECT_WIDTH, OBJECT_HEIGHT, 32, 4096,
+				   I915_TILING_NONE, I915_COMPRESSION_NONE);
+	src_buf = intel_buf_create(bops, OBJECT_WIDTH, OBJECT_HEIGHT, 32, 4096,
+				   I915_TILING_NONE, I915_COMPRESSION_NONE);
 
 	/* Prep loop to get us warmed up. */
 	for (i = 0; i < 60; i++) {
-		do_render(bufmgr, batch, dst_bo, OBJECT_WIDTH, OBJECT_HEIGHT);
+		do_render(ibb, src_buf, dst_buf,
+			  OBJECT_WIDTH, OBJECT_HEIGHT);
 	}
-	drm_intel_bo_wait_rendering(dst_bo);
+	intel_bb_sync(ibb);
 
 	/* Do the actual timing. */
 	start_time = get_time_in_secs();
 	for (i = 0; i < 200; i++) {
-		do_render(bufmgr, batch, dst_bo, OBJECT_WIDTH, OBJECT_HEIGHT);
+		do_render(ibb, src_buf, dst_buf,
+			  OBJECT_WIDTH, OBJECT_HEIGHT);
 	}
-	drm_intel_bo_wait_rendering(dst_bo);
+	intel_bb_sync(ibb);
 	end_time = get_time_in_secs();
 
 	printf("%d iterations in %.03f secs: %.01f MB/sec\n", i,
@@ -147,8 +145,10 @@ int main(int argc, char **argv)
 	       (double)i * OBJECT_WIDTH * OBJECT_HEIGHT * 4 / 1024.0 / 1024.0 /
 	       (end_time - start_time));
 
-	intel_batchbuffer_free(batch);
-	drm_intel_bufmgr_destroy(bufmgr);
+	intel_buf_destroy(src_buf);
+	intel_buf_destroy(dst_buf);
+	intel_bb_destroy(ibb);
+	buf_ops_destroy(bops);
 
 	close(fd);
 
diff --git a/benchmarks/intel_upload_blit_small.c b/benchmarks/intel_upload_blit_small.c
index 7e3346eb..327a6230 100644
--- a/benchmarks/intel_upload_blit_small.c
+++ b/benchmarks/intel_upload_blit_small.c
@@ -66,16 +66,13 @@ get_time_in_secs(void)
 }
 
 static void
-do_render(drm_intel_bufmgr *bufmgr, struct intel_batchbuffer *batch,
-	  drm_intel_bo *dst_bo, int width, int height)
+do_render(int fd, struct intel_bb *ibb, struct intel_buf *src_buf,
+	  struct intel_buf *dst_buf, int width, int height)
 {
 	uint32_t data[64];
-	drm_intel_bo *src_bo;
 	int i;
 	static uint32_t seed = 1;
 
-	src_bo = drm_intel_bo_alloc(bufmgr, "src", width * height * 4, 4096);
-
 	/* Upload some junk.  Real workloads would be doing a lot more
 	 * work to generate the junk.
 	 */
@@ -96,60 +93,63 @@ do_render(drm_intel_bufmgr *bufmgr, struct intel_batchbuffer *batch,
 			data[j] = seed++;
 
 		/* Upload the junk. */
-		drm_intel_bo_subdata(src_bo, i * 4, size * 4, data);
+		gem_write(fd, src_buf->handle, i * 4, data,
+			  size * 4);
 
 		i += size;
 	}
 
 	/* Render the junk to the dst. */
-	BLIT_COPY_BATCH_START(0);
-	OUT_BATCH((3 << 24) | /* 32 bits */
+	intel_bb_blit_start(ibb, 0);
+	intel_bb_out(ibb, (3 << 24) | /* 32 bits */
 		  (0xcc << 16) | /* copy ROP */
 		  (width * 4) /* dst pitch */);
-	OUT_BATCH(0); /* dst x1,y1 */
-	OUT_BATCH((height << 16) | width); /* dst x2,y2 */
-	OUT_RELOC(dst_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
-	OUT_BATCH(0); /* src x1,y1 */
-	OUT_BATCH(width * 4); /* src pitch */
-	OUT_RELOC(src_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
-	ADVANCE_BATCH();
-
-	intel_batchbuffer_flush(batch);
-
-	drm_intel_bo_unreference(src_bo);
+	intel_bb_out(ibb, 0); /* dst x1,y1 */
+	intel_bb_out(ibb, (height << 16) | width); /* dst x2,y2 */
+	intel_bb_emit_reloc(ibb, dst_buf->handle, I915_GEM_DOMAIN_RENDER,
+			    I915_GEM_DOMAIN_RENDER, 0, dst_buf->addr.offset);
+	intel_bb_out(ibb, 0); /* src x1,y1 */
+	intel_bb_out(ibb, width * 4); /* src pitch */
+	intel_bb_emit_reloc(ibb, src_buf->handle, I915_GEM_DOMAIN_RENDER, 0, 0,
+			    src_buf->addr.offset);
+
+	intel_bb_flush_blit(ibb);
 }
 
 int main(int argc, char **argv)
 {
 	int fd;
-	int object_size = OBJECT_WIDTH * OBJECT_HEIGHT * 4;
 	double start_time, end_time;
-	drm_intel_bo *dst_bo;
-	drm_intel_bufmgr *bufmgr;
-	struct intel_batchbuffer *batch;
+	struct intel_buf *src_buf, *dst_buf;
+	struct buf_ops *bops;
+	struct intel_bb *ibb;
 	int i;
 
 	fd = drm_open_driver(DRIVER_INTEL);
 
-	bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
-	drm_intel_bufmgr_gem_enable_reuse(bufmgr);
+	bops = buf_ops_create(fd);
 
-	batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
+	ibb = intel_bb_create(fd, 4096);
 
-	dst_bo = drm_intel_bo_alloc(bufmgr, "dst", object_size, 4096);
+	dst_buf = intel_buf_create(bops, OBJECT_WIDTH, OBJECT_HEIGHT, 32, 4096,
+				   I915_TILING_NONE, I915_COMPRESSION_NONE);
+	src_buf = intel_buf_create(bops, OBJECT_WIDTH, OBJECT_HEIGHT, 32, 4096,
+				   I915_TILING_NONE, I915_COMPRESSION_NONE);
 
 	/* Prep loop to get us warmed up. */
 	for (i = 0; i < 20; i++) {
-		do_render(bufmgr, batch, dst_bo, OBJECT_WIDTH, OBJECT_HEIGHT);
+		do_render(fd, ibb, src_buf, dst_buf,
+			  OBJECT_WIDTH, OBJECT_HEIGHT);
 	}
-	drm_intel_bo_wait_rendering(dst_bo);
+	intel_bb_sync(ibb);
 
 	/* Do the actual timing. */
 	start_time = get_time_in_secs();
 	for (i = 0; i < 1000; i++) {
-		do_render(bufmgr, batch, dst_bo, OBJECT_WIDTH, OBJECT_HEIGHT);
+		do_render(fd, ibb, src_buf, dst_buf,
+			  OBJECT_WIDTH, OBJECT_HEIGHT);
 	}
-	drm_intel_bo_wait_rendering(dst_bo);
+	intel_bb_sync(ibb);
 	end_time = get_time_in_secs();
 
 	printf("%d iterations in %.03f secs: %.01f MB/sec\n", i,
@@ -157,8 +157,10 @@ int main(int argc, char **argv)
 	       (double)i * OBJECT_WIDTH * OBJECT_HEIGHT * 4 / 1024.0 / 1024.0 /
 	       (end_time - start_time));
 
-	intel_batchbuffer_free(batch);
-	drm_intel_bufmgr_destroy(bufmgr);
+	intel_buf_destroy(src_buf);
+	intel_buf_destroy(dst_buf);
+	intel_bb_destroy(ibb);
+	buf_ops_destroy(bops);
 
 	close(fd);
 
-- 
2.20.1

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[igt-dev] [PATCH i-g-t v4 18/25] tests/prime_mmap_coherency.c: Remove libdrm dependency

[Dominik Grzegorzek]

Use intel_bb / intel_buf to remove libdrm dependency.

Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 tests/prime_mmap_coherency.c | 105 ++++++++++++++++++-----------------
 1 file changed, 55 insertions(+), 50 deletions(-)

diff --git a/tests/prime_mmap_coherency.c b/tests/prime_mmap_coherency.c
index 2a074957..b998f594 100644
--- a/tests/prime_mmap_coherency.c
+++ b/tests/prime_mmap_coherency.c
@@ -36,8 +36,8 @@ IGT_TEST_DESCRIPTION("Test dma-buf mmap on !llc platforms mostly and provoke"
 		" coherency bugs so we know for sure where we need the sync ioctls.");
 
 int fd;
-static drm_intel_bufmgr *bufmgr;
-struct intel_batchbuffer *batch;
+static struct buf_ops *bops;
+static struct intel_bb *ibb;
 static int width = 1024, height = 1024;
 
 /*
@@ -49,29 +49,32 @@ static int width = 1024, height = 1024;
  */
 static int test_read_flush(void)
 {
-	drm_intel_bo *bo_1;
-	drm_intel_bo *bo_2;
+	struct intel_buf *buf_1;
+	struct intel_buf *buf_2;
 	uint32_t *ptr_cpu;
 	uint32_t *ptr_gtt;
 	int dma_buf_fd, i;
 	int stale = 0;
 
-	bo_1 = drm_intel_bo_alloc(bufmgr, "BO 1", width * height * 4, 4096);
-
+	buf_1 = intel_buf_create(bops, width, height, 32, 4096,
+				 I915_TILING_NONE, I915_COMPRESSION_NONE);
 	/* STEP #1: put the BO 1 in GTT domain. We use the blitter to copy and fill
 	 * zeros to BO 1, so commands will be submitted and likely to place BO 1 in
 	 * the GTT domain. */
-	bo_2 = drm_intel_bo_alloc(bufmgr, "BO 2", width * height * 4, 4096);
-	intel_copy_bo(batch, bo_1, bo_2, width * height);
-	drm_intel_bo_unreference(bo_2);
+	buf_2 = intel_buf_create(bops, width, height, 32, 4096,
+				 I915_TILING_NONE, I915_COMPRESSION_NONE);
+	intel_bb_copy_intel_buf(ibb, buf_1, buf_2, width * height * 4);
+	intel_buf_destroy(buf_2);
 
 	/* STEP #2: read BO 1 using the dma-buf CPU mmap. This dirties the CPU caches. */
-	dma_buf_fd = prime_handle_to_fd_for_mmap(fd, bo_1->handle);
+	dma_buf_fd = prime_handle_to_fd_for_mmap(fd, buf_1->handle);
 
 	/* STEP #3: write 0x11 into BO 1. */
-	bo_2 = drm_intel_bo_alloc(bufmgr, "BO 2", width * height * 4, 4096);
-	ptr_gtt = gem_mmap__device_coherent(fd, bo_2->handle, 0, width * height, PROT_READ | PROT_WRITE);
-	gem_set_domain(fd, bo_2->handle,
+	buf_2 = intel_buf_create(bops, width, height, 32, 4096,
+				 I915_TILING_NONE, I915_COMPRESSION_NONE);
+	ptr_gtt = gem_mmap__device_coherent(fd, buf_2->handle, 0, width * height,
+					    PROT_READ | PROT_WRITE);
+	gem_set_domain(fd, buf_2->handle,
 		       I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
 	memset(ptr_gtt, 0xc5, width * height);
 	munmap(ptr_gtt, width * height);
@@ -85,8 +88,8 @@ static int test_read_flush(void)
 		igt_assert_eq(ptr_cpu[i], 0);
 	prime_sync_end(dma_buf_fd, false);
 
-	intel_copy_bo(batch, bo_1, bo_2, width * height);
-	drm_intel_bo_unreference(bo_2);
+	intel_bb_copy_intel_buf(ibb, buf_1, buf_2, width * height * 4);
+	intel_buf_destroy(buf_2);
 
 	/* STEP #4: read again using the CPU mmap. Doing #1 before #3 makes sure we
 	 * don't do a full CPU cache flush in step #3 again. That makes sure all the
@@ -99,7 +102,7 @@ static int test_read_flush(void)
 			stale++;
 	prime_sync_end(dma_buf_fd, false);
 
-	drm_intel_bo_unreference(bo_1);
+	intel_buf_destroy(buf_1);
 	munmap(ptr_cpu, width * height);
 
 	close(dma_buf_fd);
@@ -116,24 +119,26 @@ static int test_read_flush(void)
  */
 static int test_write_flush(void)
 {
-	drm_intel_bo *bo_1;
-	drm_intel_bo *bo_2;
+	struct intel_buf *buf_1;
+	struct intel_buf *buf_2;
 	uint32_t *ptr_cpu;
 	uint32_t *ptr2_cpu;
 	int dma_buf_fd, dma_buf2_fd, i;
 	int stale = 0;
 
-	bo_1 = drm_intel_bo_alloc(bufmgr, "BO 1", width * height * 4, 4096);
+	buf_1 = intel_buf_create(bops, width, height, 32, 4096,
+				 I915_TILING_NONE, I915_COMPRESSION_NONE);
 
 	/* STEP #1: Put the BO 1 in GTT domain. We use the blitter to copy and fill
 	 * zeros to BO 1, so commands will be submitted and likely to place BO 1 in
 	 * the GTT domain. */
-	bo_2 = drm_intel_bo_alloc(bufmgr, "BO 2", width * height * 4, 4096);
-	intel_copy_bo(batch, bo_1, bo_2, width * height);
-	drm_intel_bo_unreference(bo_2);
+	buf_2 = intel_buf_create(bops, width, height, 32, 4096,
+				 I915_TILING_NONE, I915_COMPRESSION_NONE);
+	intel_bb_copy_intel_buf(ibb, buf_1, buf_2, width * height * 4);
+	intel_buf_destroy(buf_2);
 
 	/* STEP #2: Write '1's into BO 1 using the dma-buf CPU mmap. */
-	dma_buf_fd = prime_handle_to_fd_for_mmap(fd, bo_1->handle);
+	dma_buf_fd = prime_handle_to_fd_for_mmap(fd, buf_1->handle);
 	igt_skip_on(errno == EINVAL);
 
 	ptr_cpu = mmap(NULL, width * height, PROT_READ | PROT_WRITE,
@@ -147,13 +152,14 @@ static int test_write_flush(void)
 	prime_sync_end(dma_buf_fd, true);
 
 	/* STEP #3: Copy BO 1 into BO 2, using blitter. */
-	bo_2 = drm_intel_bo_alloc(bufmgr, "BO 2", width * height * 4, 4096);
-	intel_copy_bo(batch, bo_2, bo_1, width * height);
+	buf_2 = intel_buf_create(bops, width, height, 32, 4096,
+				 I915_TILING_NONE, I915_COMPRESSION_NONE);
+	intel_bb_copy_intel_buf(ibb, buf_2, buf_1, width * height * 4);
 
 	/* STEP #4: compare BO 2 against written BO 1. In !llc hardware, there
 	 * should be some cache lines that didn't get flushed out and are still 0,
 	 * requiring cache flush before the write in step 2. */
-	dma_buf2_fd = prime_handle_to_fd_for_mmap(fd, bo_2->handle);
+	dma_buf2_fd = prime_handle_to_fd_for_mmap(fd, buf_2->handle);
 	igt_skip_on(errno == EINVAL);
 
 	ptr2_cpu = mmap(NULL, width * height, PROT_READ | PROT_WRITE,
@@ -168,8 +174,8 @@ static int test_write_flush(void)
 
 	prime_sync_end(dma_buf2_fd, false);
 
-	drm_intel_bo_unreference(bo_1);
-	drm_intel_bo_unreference(bo_2);
+	intel_buf_destroy(buf_1);
+	intel_buf_destroy(buf_2);
 	munmap(ptr_cpu, width * height);
 
 	close(dma_buf2_fd);
@@ -180,33 +186,32 @@ static int test_write_flush(void)
 
 static void blit_and_cmp(void)
 {
-	drm_intel_bo *bo_1;
-	drm_intel_bo *bo_2;
+	struct intel_buf *buf_1;
+	struct intel_buf *buf_2;
 	uint32_t *ptr_cpu;
 	uint32_t *ptr2_cpu;
 	int dma_buf_fd, dma_buf2_fd, i;
 	int local_fd;
-	drm_intel_bufmgr *local_bufmgr;
-	struct intel_batchbuffer *local_batch;
-
+	struct buf_ops *local_bops;
+	struct intel_bb *local_ibb;
 	/* recreate process local variables */
 	local_fd = drm_open_driver(DRIVER_INTEL);
-	local_bufmgr = drm_intel_bufmgr_gem_init(local_fd, 4096);
-	igt_assert(local_bufmgr);
+	local_bops = buf_ops_create(local_fd);
 
-	local_batch = intel_batchbuffer_alloc(local_bufmgr, intel_get_drm_devid(local_fd));
-	igt_assert(local_batch);
+	local_ibb = intel_bb_create(local_fd, 4096);
 
-	bo_1 = drm_intel_bo_alloc(local_bufmgr, "BO 1", width * height * 4, 4096);
-	dma_buf_fd = prime_handle_to_fd_for_mmap(local_fd, bo_1->handle);
+	buf_1 = intel_buf_create(local_bops, width, height, 32, 4096,
+				 I915_TILING_NONE, I915_COMPRESSION_NONE);
+	dma_buf_fd = prime_handle_to_fd_for_mmap(local_fd, buf_1->handle);
 	igt_skip_on(errno == EINVAL);
 
 	ptr_cpu = mmap(NULL, width * height, PROT_READ | PROT_WRITE,
 		       MAP_SHARED, dma_buf_fd, 0);
 	igt_assert(ptr_cpu != MAP_FAILED);
 
-	bo_2 = drm_intel_bo_alloc(local_bufmgr, "BO 2", width * height * 4, 4096);
-	dma_buf2_fd = prime_handle_to_fd_for_mmap(local_fd, bo_2->handle);
+	buf_2 = intel_buf_create(local_bops, width, height, 32, 4096,
+				 I915_TILING_NONE, I915_COMPRESSION_NONE);
+	dma_buf2_fd = prime_handle_to_fd_for_mmap(local_fd, buf_2->handle);
 
 	ptr2_cpu = mmap(NULL, width * height, PROT_READ | PROT_WRITE,
 			MAP_SHARED, dma_buf2_fd, 0);
@@ -222,7 +227,7 @@ static void blit_and_cmp(void)
 	prime_sync_end(dma_buf2_fd, true);
 
 	/* Copy BO 1 into BO 2, using blitter. */
-	intel_copy_bo(local_batch, bo_2, bo_1, width * height);
+	intel_bb_copy_intel_buf(ibb, buf_2, buf_1, width * height * 4);
 	usleep(0); /* let someone else claim the mutex */
 
 	/* Compare BOs. If prime_sync_* were executed properly, the caches
@@ -232,16 +237,16 @@ static void blit_and_cmp(void)
 		igt_fail_on_f(ptr2_cpu[i] != 0x11111111, "Found 0x%08x at offset 0x%08x\n", ptr2_cpu[i], i);
 	prime_sync_end(dma_buf2_fd, false);
 
-	drm_intel_bo_unreference(bo_1);
-	drm_intel_bo_unreference(bo_2);
+	intel_buf_destroy(buf_1);
+	intel_buf_destroy(buf_2);
 	munmap(ptr_cpu, width * height);
 	munmap(ptr2_cpu, width * height);
 
 	close(dma_buf_fd);
 	close(dma_buf2_fd);
 
-	intel_batchbuffer_free(local_batch);
-	drm_intel_bufmgr_destroy(local_bufmgr);
+	intel_bb_destroy(local_ibb);
+	buf_ops_destroy(local_bops);
 	close(local_fd);
 }
 
@@ -286,8 +291,8 @@ igt_main
 		fd = drm_open_driver(DRIVER_INTEL);
 		igt_require_gem(fd);
 
-		bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
-		batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
+		bops = buf_ops_create(fd);
+		ibb = intel_bb_create(fd, 4096);
 	}
 
 	/* Cache coherency and the eviction are pretty much unpredictable, so
@@ -315,8 +320,8 @@ igt_main
 	}
 
 	igt_fixture {
-		intel_batchbuffer_free(batch);
-		drm_intel_bufmgr_destroy(bufmgr);
+		intel_bb_destroy(ibb);
+		buf_ops_destroy(bops);
 
 		close(fd);
 	}
-- 
2.20.1

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[igt-dev] [PATCH i-g-t v4 19/25] tools/intel_perf_counters: Remove libdrm dependency

[Dominik Grzegorzek]

Use intel_bb / intel_buf to remove libdrm dependency.

Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 tools/intel_perf_counters.c | 109 ++++++++++++++++++------------------
 1 file changed, 56 insertions(+), 53 deletions(-)

diff --git a/tools/intel_perf_counters.c b/tools/intel_perf_counters.c
index 5824d9c1..6273aecd 100644
--- a/tools/intel_perf_counters.c
+++ b/tools/intel_perf_counters.c
@@ -46,9 +46,9 @@
 #include "i915_drm.h"
 #include "drmtest.h"
 #include "intel_io.h"
-#include "intel_bufmgr.h"
 #include "intel_batchbuffer.h"
 #include "intel_chipset.h"
+#include "intel_bufops.h"
 
 #define GEN5_COUNTER_COUNT 29
 
@@ -298,8 +298,8 @@ const int gen7_counter_format = 5; /* 0b101 */
 int have_totals = 0;
 uint32_t *totals;
 uint32_t *last_counter;
-static drm_intel_bufmgr *bufmgr;
-struct intel_batchbuffer *batch;
+static struct buf_ops *bops;
+static struct intel_bb *ibb;
 
 /* DW0 */
 #define GEN5_MI_REPORT_PERF_COUNT ((0x26 << 23) | (3 - 2))
@@ -327,30 +327,30 @@ static void
 gen5_get_counters(void)
 {
 	int i;
-	drm_intel_bo *stats_bo;
+	struct intel_buf *stats_buf;
 	uint32_t *stats_result;
 
-	stats_bo = drm_intel_bo_alloc(bufmgr, "stats", 4096, 4096);
+	stats_buf = intel_buf_create(bops, 32, 32, 32, 4096, I915_TILING_NONE,
+				     I915_COMPRESSION_NONE);
 
-	BEGIN_BATCH(6, 2);
-	OUT_BATCH(GEN5_MI_REPORT_PERF_COUNT | MI_COUNTER_SET_0);
-	OUT_RELOC(stats_bo,
-		  I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
-		  0);
-	OUT_BATCH(0);
 
-	OUT_BATCH(GEN5_MI_REPORT_PERF_COUNT | MI_COUNTER_SET_1);
-	OUT_RELOC(stats_bo,
-		  I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
-		  64);
-	OUT_BATCH(0);
+	intel_bb_out(ibb, GEN5_MI_REPORT_PERF_COUNT | MI_COUNTER_SET_0);
+	intel_bb_emit_reloc(ibb, stats_buf->handle, I915_GEM_DOMAIN_INSTRUCTION,
+			    I915_GEM_DOMAIN_INSTRUCTION, 0,
+			    stats_buf->addr.offset);
+	intel_bb_out(ibb, 0);
 
-	ADVANCE_BATCH();
+	intel_bb_out(ibb, GEN5_MI_REPORT_PERF_COUNT | MI_COUNTER_SET_1);
+	intel_bb_emit_reloc(ibb, stats_buf->handle, I915_GEM_DOMAIN_INSTRUCTION,
+			    I915_GEM_DOMAIN_INSTRUCTION, 64,
+			    stats_buf->addr.offset);
+	intel_bb_out(ibb, 0);
 
-	intel_batchbuffer_flush(batch);
+	intel_bb_flush_blit(ibb);
+	intel_bb_sync(ibb);
 
-	drm_intel_bo_map(stats_bo, 0);
-	stats_result = stats_bo->virtual;
+	intel_buf_cpu_map(stats_buf, false);
+	stats_result = stats_buf->ptr;
 	/* skip REPORT_ID, TIMESTAMP */
 	stats_result += 3;
 	for (i = 0 ; i < GEN5_COUNTER_COUNT; i++) {
@@ -358,15 +358,15 @@ gen5_get_counters(void)
 		last_counter[i] = stats_result[i];
 	}
 
-	drm_intel_bo_unmap(stats_bo);
-	drm_intel_bo_unreference(stats_bo);
+	intel_buf_unmap(stats_buf);
+	intel_buf_destroy(stats_buf);
 }
 
 static void
 gen6_get_counters(void)
 {
 	int i;
-	drm_intel_bo *stats_bo;
+	struct intel_buf *stats_buf;
 	uint32_t *stats_result;
 
 	/* Map from counter names to their index in the buffer object */
@@ -378,49 +378,49 @@ gen6_get_counters(void)
 		31, 30, 29, 28, 27, 26, 25, 24,
 	};
 
-	stats_bo = drm_intel_bo_alloc(bufmgr, "stats", 4096, 4096);
+	stats_buf = intel_buf_create(bops, 32, 32, 32, 4096, I915_TILING_NONE,
+				     I915_COMPRESSION_NONE);
+	intel_bb_out(ibb, GEN6_MI_REPORT_PERF_COUNT | (3 - 2));
+	intel_bb_emit_reloc(ibb, stats_buf->handle, I915_GEM_DOMAIN_INSTRUCTION,
+			    I915_GEM_DOMAIN_INSTRUCTION,
+			    MI_COUNTER_ADDRESS_GTT, stats_buf->addr.offset);
+	intel_bb_out(ibb, 0);
 
-	BEGIN_BATCH(3, 1);
-	OUT_BATCH(GEN6_MI_REPORT_PERF_COUNT | (3 - 2));
-	OUT_RELOC(stats_bo,
-		  I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
-		  MI_COUNTER_ADDRESS_GTT);
-	OUT_BATCH(0);
-	ADVANCE_BATCH();
+	intel_bb_flush_render(ibb);
+	intel_bb_sync(ibb);
 
-	intel_batchbuffer_flush_on_ring(batch, I915_EXEC_RENDER);
-
-	drm_intel_bo_map(stats_bo, 0);
-	stats_result = stats_bo->virtual;
+	intel_buf_cpu_map(stats_buf, 0);
+	stats_result = stats_buf->ptr;
 	for (i = 0; i < GEN6_COUNTER_COUNT; i++) {
 		totals[i] += stats_result[buffer_index[i]] - last_counter[i];
 		last_counter[i] = stats_result[buffer_index[i]];
 	}
 
-	drm_intel_bo_unmap(stats_bo);
-	drm_intel_bo_unreference(stats_bo);
+	intel_buf_unmap(stats_buf);
+	intel_buf_destroy(stats_buf);
 }
 
 static void
 gen7_get_counters(void)
 {
 	int i;
-	drm_intel_bo *stats_bo;
+	struct intel_buf *stats_buf;
 	uint32_t *stats_result;
 
-	stats_bo = drm_intel_bo_alloc(bufmgr, "stats", 4096, 4096);
+	stats_buf = intel_buf_create(bops, 32, 32, 32, 4096, I915_TILING_NONE,
+				     I915_COMPRESSION_NONE);
 
-	BEGIN_BATCH(3, 1);
-	OUT_BATCH(GEN6_MI_REPORT_PERF_COUNT | (3 - 2));
-	OUT_RELOC(stats_bo,
-		  I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0);
-	OUT_BATCH(0);
-	ADVANCE_BATCH();
+	intel_bb_out(ibb, GEN6_MI_REPORT_PERF_COUNT | (3 - 2));
+	intel_bb_emit_reloc(ibb, stats_buf->handle, I915_GEM_DOMAIN_INSTRUCTION,
+			    I915_GEM_DOMAIN_INSTRUCTION, 0,
+			    stats_buf->addr.offset);
+	intel_bb_out(ibb, 0);
 
-	intel_batchbuffer_flush_on_ring(batch, I915_EXEC_RENDER);
+	intel_bb_flush_render(ibb);
+	intel_bb_sync(ibb);
 
-	drm_intel_bo_map(stats_bo, 0);
-	stats_result = stats_bo->virtual;
+	intel_buf_cpu_map(stats_buf, false);
+	stats_result = stats_buf->ptr;
 	/* skip REPORT_ID, TIMESTAMP */
 	stats_result += 3;
 	for (i = 0; i < GEN7_COUNTER_COUNT; i++) {
@@ -431,8 +431,8 @@ gen7_get_counters(void)
 		last_counter[i] = stats_result[i];
 	}
 
-	drm_intel_bo_unmap(stats_bo);
-	drm_intel_bo_unreference(stats_bo);
+	intel_buf_unmap(stats_buf);
+	intel_buf_destroy(stats_buf);
 }
 
 #define STATS_CHECK_FREQUENCY	100
@@ -458,9 +458,8 @@ main(int argc, char **argv)
 	fd = drm_open_driver(DRIVER_INTEL);
 	devid = intel_get_drm_devid(fd);
 
-	bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
-	drm_intel_bufmgr_gem_enable_reuse(bufmgr);
-	batch = intel_batchbuffer_alloc(bufmgr, devid);
+	bops = buf_ops_create(fd);
+	ibb = intel_bb_create(fd, 4096);
 
 	if (IS_GEN5(devid)) {
 		counter_name = gen5_counter_names;
@@ -531,5 +530,9 @@ main(int argc, char **argv)
 	free(totals);
 	free(last_counter);
 
+	intel_bb_destroy(ibb);
+	buf_ops_destroy(bops);
+	close(fd);
+
 	return 0;
 }
-- 
2.20.1

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[igt-dev] [PATCH i-g-t v4 20/25] tests/prime_udl: Remove libdrm dependency

[Dominik Grzegorzek]

Use intel_bb / intel_buf to remove libdrm dependency.

Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 tests/prime_udl.c | 44 ++++++++++++++++++++------------------------
 1 file changed, 20 insertions(+), 24 deletions(-)

diff --git a/tests/prime_udl.c b/tests/prime_udl.c
index 9b600659..b2e94160 100644
--- a/tests/prime_udl.c
+++ b/tests/prime_udl.c
@@ -27,14 +27,13 @@
 #include "xf86drm.h"
 #include <xf86drmMode.h>
 
-#include "intel_bufmgr.h"
-
 int intel_fd = -1, udl_fd = -1;
-drm_intel_bufmgr *bufmgr;
-uint32_t devid;
-struct intel_batchbuffer *intel_batch;
+struct buf_ops *bops;
+
+#define WIDTH 640
+#define HEIGHT 480
+#define BO_SIZE (WIDTH*HEIGHT*2)
 
-#define BO_SIZE (640*480*2)
 
 static int find_and_open_devices(void)
 {
@@ -94,34 +93,38 @@ static int dumb_bo_destroy(int fd, uint32_t handle)
  */
 static int test1(void)
 {
-	drm_intel_bo *test_intel_bo;
+	struct intel_buf *test_intel_buf;
 	int prime_fd;
 	int ret;
 	uint32_t udl_handle;
 
-	test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", BO_SIZE, 4096);
+	test_intel_buf = intel_buf_create(bops, WIDTH, HEIGHT, 16, 4096,
+					  I915_TILING_NONE,
+					  I915_COMPRESSION_NONE);
 
-	drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd);
+	prime_fd = prime_handle_to_fd(intel_fd, test_intel_buf->handle);
 
 	ret = drmPrimeFDToHandle(udl_fd, prime_fd, &udl_handle);
 
 	dumb_bo_destroy(udl_fd, udl_handle);
-	drm_intel_bo_unreference(test_intel_bo);
+	intel_buf_destroy(test_intel_buf);
 	return ret;
 }
 
 static int test2(void)
 {
-	drm_intel_bo *test_intel_bo;
+	struct intel_buf *test_intel_buf;
 	uint32_t fb_id;
 	drmModeClip clip;
 	int prime_fd;
 	uint32_t udl_handle;
 	int ret;
 
-	test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", BO_SIZE, 4096);
+	test_intel_buf = intel_buf_create(bops, WIDTH, HEIGHT, 16, 4096,
+					  I915_TILING_NONE,
+					  I915_COMPRESSION_NONE);
 
-	drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd);
+	prime_fd = prime_handle_to_fd(intel_fd, test_intel_buf->handle);
 
 	ret = drmPrimeFDToHandle(udl_fd, prime_fd, &udl_handle);
 	if (ret)
@@ -141,7 +144,7 @@ static int test2(void)
 	}
 out:
 	dumb_bo_destroy(udl_fd, udl_handle);
-	drm_intel_bo_unreference(test_intel_bo);
+	intel_buf_destroy(test_intel_buf);
 	return ret;
 }
 
@@ -152,22 +155,15 @@ igt_simple_main
 	igt_skip_on(udl_fd == -1);
 	igt_skip_on(intel_fd == -1);
 
-	/* set up intel bufmgr */
-	bufmgr = drm_intel_bufmgr_gem_init(intel_fd, 4096);
-	drm_intel_bufmgr_gem_enable_reuse(bufmgr);
-
-	/* set up an intel batch buffer */
-	devid = intel_get_drm_devid(intel_fd);
-	intel_batch = intel_batchbuffer_alloc(bufmgr, devid);
+	/* set up intel buf ops */
+	bops = buf_ops_create(intel_fd);
 
 	/* create an object on the i915 */
 	igt_assert(test1() == 0);
 
 	igt_assert(test2() == 0);
 
-	intel_batchbuffer_free(intel_batch);
-
-	drm_intel_bufmgr_destroy(bufmgr);
+	buf_ops_destroy(bops);
 
 	close(intel_fd);
 	close(udl_fd);
-- 
2.20.1

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[igt-dev] [PATCH i-g-t v4 21/25] tests/prime_nv_pcopy.c: Remove libdrm dependency

[Dominik Grzegorzek]

Use intel_bb / intel_buf to remove libdrm dependency.

Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 tests/prime_nv_pcopy.c | 103 ++++++++++++++++++++---------------------
 1 file changed, 50 insertions(+), 53 deletions(-)

diff --git a/tests/prime_nv_pcopy.c b/tests/prime_nv_pcopy.c
index bbcf7680..15d79975 100644
--- a/tests/prime_nv_pcopy.c
+++ b/tests/prime_nv_pcopy.c
@@ -25,15 +25,13 @@
 #include <sys/ioctl.h>
 #include <errno.h>
 
-#include "intel_bufmgr.h"
 #include "nouveau.h"
 
 static int intel_fd = -1, nouveau_fd = -1;
-static drm_intel_bufmgr *bufmgr;
+static struct buf_ops *bops;
 static struct nouveau_device *ndev;
 static struct nouveau_client *nclient;
-static uint32_t devid;
-static struct intel_batchbuffer *batch;
+static struct intel_bb *ibb;
 static struct nouveau_object *nchannel, *pcopy;
 static struct nouveau_bufctx *nbufctx;
 static struct nouveau_pushbuf *npush;
@@ -161,16 +159,15 @@ BEGIN_NVXX(struct nouveau_pushbuf *push, int subc, int mthd, int size)
 }
 
 static void
-noop_intel(drm_intel_bo *bo)
+noop_intel(struct intel_buf *buf)
 {
-	BEGIN_BATCH(3, 1);
-	OUT_BATCH(MI_NOOP);
-	OUT_BATCH(MI_BATCH_BUFFER_END);
-	OUT_RELOC(bo, I915_GEM_DOMAIN_RENDER,
-			I915_GEM_DOMAIN_RENDER, 0);
-	ADVANCE_BATCH();
-
-	intel_batchbuffer_flush(batch);
+	intel_bb_out(ibb, MI_NOOP);
+	intel_bb_out(ibb, MI_BATCH_BUFFER_END);
+	intel_bb_emit_reloc(ibb, buf->handle, I915_GEM_DOMAIN_RENDER,
+			    I915_GEM_DOMAIN_RENDER, 0, buf->addr.offset);
+
+	intel_bb_flush_blit(ibb);
+	intel_bb_sync(ibb);
 }
 
 static void find_and_open_devices(void)
@@ -542,24 +539,25 @@ static void test1_micro(void)
 {
 	struct nouveau_bo *bo_intel = NULL, *bo_nvidia = NULL, *bo_linear = NULL;
 	rect intel, nvidia, linear;
-	uint32_t tiling = I915_TILING_Y;
 
 	uint32_t src_x = 0, src_y = 0;
 	uint32_t dst_x = 0, dst_y = 0;
 	uint32_t x, y, w = 256, h = 64;
+	uint8_t *test_intel_buf_ptr;
 
-	drm_intel_bo *test_intel_bo;
+	struct intel_buf *test_intel_buf;
 	int prime_fd;
 
-	test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", w * h, 4096);
-	igt_assert(test_intel_bo);
-	drm_intel_bo_set_tiling(test_intel_bo, &tiling, w);
-	igt_assert(tiling == I915_TILING_Y);
-	igt_assert(drm_intel_gem_bo_map_gtt(test_intel_bo) == 0);
+	test_intel_buf = intel_buf_create(bops, w, h, 8, 4096,
+					  I915_TILING_Y, I915_COMPRESSION_NONE);
+
+	test_intel_buf_ptr = gem_mmap__gtt(intel_fd, test_intel_buf->handle,
+					    test_intel_buf->surface[0].size,
+					    PROT_READ | PROT_WRITE);
 
-	drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd);
+	prime_fd = prime_handle_to_fd(intel_fd, test_intel_buf->handle);
 	igt_assert_lte(0, prime_fd);
-	noop_intel(test_intel_bo);
+	noop_intel(test_intel_buf);
 
 	nv_bo_alloc(&bo_intel, &intel, w, h, tile_intel_y, prime_fd, 0);
 	nv_bo_alloc(&bo_nvidia, &nvidia, w, h, 0x10, -1, NOUVEAU_BO_VRAM);
@@ -584,15 +582,16 @@ static void test1_micro(void)
 	if (pcopy)
 		perform_copy(bo_intel, &intel, dst_x, dst_y, bo_nvidia, &nvidia, src_x, src_y, w, h);
 	else
-		swtile_y(test_intel_bo->virtual, bo_linear->map, w, h);
+		swtile_y(test_intel_buf_ptr, bo_linear->map, w, h);
 
-	noop_intel(test_intel_bo);
-	check1_micro(test_intel_bo->virtual, intel.pitch, intel.h, dst_x, dst_y, w, h);
+	noop_intel(test_intel_buf);
+	check1_micro(test_intel_buf_ptr, intel.pitch, intel.h, dst_x, dst_y, w, h);
 
 	nouveau_bo_ref(NULL, &bo_linear);
 	nouveau_bo_ref(NULL, &bo_nvidia);
 	nouveau_bo_ref(NULL, &bo_intel);
-	drm_intel_bo_unreference(test_intel_bo);
+	gem_munmap(test_intel_buf_ptr, test_intel_buf->surface[0].size);
+	intel_buf_destroy(test_intel_buf);
 }
 
 /* test 2, see if we can copy from linear to intel X format safely
@@ -685,43 +684,44 @@ static void test3_base(int tile_src, int tile_dst)
 	uint32_t dst_x = 2 * cpp, dst_y = 26;
 	uint32_t w = 298 * cpp, h = 298;
 
-	drm_intel_bo *test_intel_bo;
+	struct intel_buf *test_intel_buf;
 	int prime_fd;
 
-	test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", 2048 * cpp * 768, 4096);
-	igt_assert(test_intel_bo);
+	test_intel_buf = intel_buf_create(bops, 2048, 768, cpp * 8, 4096,
+					  I915_TILING_NONE,
+					  I915_COMPRESSION_NONE);
 
-	drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd);
+	prime_fd = prime_handle_to_fd(intel_fd, test_intel_buf->handle);
 	igt_assert_lte(0, prime_fd);
 
 	nv_bo_alloc(&bo_intel, &intel, 2048 * cpp, 768, tile_dst, prime_fd, 0);
 	nv_bo_alloc(&bo_nvidia, &nvidia, 300 * cpp, 300, tile_src, -1, NOUVEAU_BO_VRAM);
 	nv_bo_alloc(&bo_linear, &linear, 2048 * cpp, 768, 0, -1, NOUVEAU_BO_GART);
 
-	noop_intel(test_intel_bo);
+	noop_intel(test_intel_buf);
 	memset(bo_linear->map, 0x80, bo_linear->size);
 	perform_copy(bo_intel, &intel, 0, 0, bo_linear, &linear, 0, 0, linear.pitch, linear.h);
-	noop_intel(test_intel_bo);
+	noop_intel(test_intel_buf);
 
 	memset(bo_linear->map, 0x04, bo_linear->size);
 	perform_copy(bo_nvidia, &nvidia, 0, 0, bo_linear, &linear, 0, 0, nvidia.pitch, nvidia.h);
 
 	/* Perform the actual sub rectangle copy */
-	noop_intel(test_intel_bo);
+	noop_intel(test_intel_buf);
 	perform_copy(bo_intel, &intel, dst_x, dst_y, bo_nvidia, &nvidia, src_x, src_y, w, h);
-	noop_intel(test_intel_bo);
+	noop_intel(test_intel_buf);
 
 	memset(bo_linear->map, 0x3, bo_linear->size);
-	noop_intel(test_intel_bo);
+	noop_intel(test_intel_buf);
 	perform_copy(bo_linear, &linear, 0, 0, bo_intel, &intel, 0, 0, intel.pitch, intel.h);
-	noop_intel(test_intel_bo);
+	noop_intel(test_intel_buf);
 
 	check3(bo_linear->map, linear.pitch, linear.h, dst_x, dst_y, w, h);
 
 	nouveau_bo_ref(NULL, &bo_linear);
 	nouveau_bo_ref(NULL, &bo_nvidia);
 	nouveau_bo_ref(NULL, &bo_intel);
-	drm_intel_bo_unreference(test_intel_bo);
+	intel_buf_destroy(test_intel_buf);
 }
 
 static void test3_1(void)
@@ -767,7 +767,7 @@ static void test3_5(void)
 /* Test only new style semaphores, old ones are AWFUL */
 static void test_semaphore(void)
 {
-	drm_intel_bo *test_intel_bo = NULL;
+	struct intel_buf *test_intel_buf = NULL;
 	struct nouveau_bo *sema_bo = NULL;
 	int prime_fd;
 	uint32_t *sema;
@@ -776,16 +776,17 @@ static void test_semaphore(void)
 	igt_skip_on(ndev->chipset < 0x84);
 
 	/* Should probably be kept in sysmem */
-	test_intel_bo = drm_intel_bo_alloc(bufmgr, "semaphore bo", 4096, 4096);
-	igt_assert(test_intel_bo);
+	test_intel_buf = intel_buf_create(bops, 32, 32, 32, 4096,
+					  I915_TILING_NONE,
+					  I915_COMPRESSION_NONE);
 
-	drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd);
+	prime_fd = prime_handle_to_fd(intel_fd, test_intel_buf->handle);
 	igt_assert_lte(0, prime_fd);
 	igt_assert(nouveau_bo_prime_handle_ref(ndev, prime_fd, &sema_bo) == 0);
 	close(prime_fd);
 
-	igt_assert(drm_intel_gem_bo_map_gtt(test_intel_bo) == 0);
-	sema = test_intel_bo->virtual;
+	sema = gem_mmap__gtt(intel_fd, test_intel_buf->handle,
+			     test_intel_buf->surface[0].size, PROT_WRITE);
 	sema++;
 	*sema = 0;
 
@@ -845,7 +846,8 @@ static void test_semaphore(void)
 	igt_assert(*sema == 9);
 
 	nouveau_bo_ref(NULL, &sema_bo);
-	drm_intel_bo_unreference(test_intel_bo);
+	gem_munmap(sema, test_intel_buf->surface[0].size);
+	intel_buf_destroy(test_intel_buf);
 }
 
 igt_main
@@ -857,18 +859,13 @@ igt_main
 		igt_require(intel_fd != -1);
 
 		/* set up intel bufmgr */
-		bufmgr = drm_intel_bufmgr_gem_init(intel_fd, 4096);
-		igt_assert(bufmgr);
-		/* Do not enable reuse, we share (almost) all buffers. */
-		//drm_intel_bufmgr_gem_enable_reuse(bufmgr);
+		bops = buf_ops_create(intel_fd);
 
 		/* set up nouveau bufmgr */
 		init_nouveau();
 
 		/* set up an intel batch buffer */
-		devid = intel_get_drm_devid(intel_fd);
-		batch = intel_batchbuffer_alloc(bufmgr, devid);
-		igt_assert(batch);
+		ibb = intel_bb_create(intel_fd, 4096);
 	}
 
 #define xtest(x, args...) \
@@ -893,11 +890,11 @@ igt_main
 		nouveau_pushbuf_del(&npush);
 		nouveau_object_del(&nchannel);
 
-		intel_batchbuffer_free(batch);
+		intel_bb_destroy(ibb);
 
 		nouveau_client_del(&nclient);
 		nouveau_device_del(&ndev);
-		drm_intel_bufmgr_destroy(bufmgr);
+		buf_ops_destroy(bops);
 
 		close(intel_fd);
 		close(nouveau_fd);
-- 
2.20.1

_______________________________________________
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igt-dev@lists.freedesktop.org
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[igt-dev] [PATCH i-g-t v4 22/25] tests/prime_nv_api.c: Remove libdrm dependency

[Dominik Grzegorzek]

Use intel_bb / intel_buf to remove libdrm dependency.

Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 tests/prime_nv_api.c | 203 +++++++++++++++++++++++--------------------
 1 file changed, 111 insertions(+), 92 deletions(-)

diff --git a/tests/prime_nv_api.c b/tests/prime_nv_api.c
index 054a1ec6..a3adeddc 100644
--- a/tests/prime_nv_api.c
+++ b/tests/prime_nv_api.c
@@ -15,18 +15,18 @@
 #include <fcntl.h>
 #include <sys/stat.h>
 
-#include "intel_bufmgr.h"
 #include "nouveau.h"
 
-#define BO_SIZE (256*1024)
+#define WIDTH 256
+#define HEIGHT 256
+
+#define BO_SIZE (WIDTH*HEIGHT*4)
 
 int intel_fd = -1, intel_fd2 = -1, nouveau_fd = -1, nouveau_fd2 = -1;
-drm_intel_bufmgr *bufmgr;
-drm_intel_bufmgr *bufmgr2;
+struct buf_ops *bops;
+struct buf_ops *bops2;
 struct nouveau_device *ndev, *ndev2;
 struct nouveau_client *nclient, *nclient2;
-uint32_t devid;
-struct intel_batchbuffer *intel_batch;
 
 static void find_and_open_devices(void)
 {
@@ -69,13 +69,15 @@ static void find_and_open_devices(void)
 
 static void test_i915_nv_import_twice(void)
 {
-	drm_intel_bo *test_intel_bo;
+	struct intel_buf *test_intel_buf;
 	int prime_fd;
 	struct nouveau_bo *nvbo = NULL, *nvbo2 = NULL;
 
-	test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", BO_SIZE, 4096);
+	test_intel_buf = intel_buf_create(bops, WIDTH, HEIGHT, 32, 4096,
+					  I915_TILING_NONE,
+					  I915_COMPRESSION_NONE);
 
-	igt_assert(drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd) == 0);
+	prime_fd = prime_handle_to_fd(intel_fd, test_intel_buf->handle);
 
 	igt_assert(nouveau_bo_prime_handle_ref(ndev, prime_fd, &nvbo) == 0);
 	igt_assert(nouveau_bo_prime_handle_ref(ndev2, prime_fd, &nvbo2) == 0);
@@ -83,19 +85,21 @@ static void test_i915_nv_import_twice(void)
 
 	nouveau_bo_ref(NULL, &nvbo2);
 	nouveau_bo_ref(NULL, &nvbo);
-	drm_intel_bo_unreference(test_intel_bo);
+	intel_buf_destroy(test_intel_buf);
 }
 
 static void test_i915_nv_import_twice_check_flink_name(void)
 {
-	drm_intel_bo *test_intel_bo;
+	struct intel_buf *test_intel_buf;
 	int prime_fd;
 	struct nouveau_bo *nvbo = NULL, *nvbo2 = NULL;
 	uint32_t flink_name1, flink_name2;
 
-	test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", BO_SIZE, 4096);
+	test_intel_buf = intel_buf_create(bops, WIDTH, HEIGHT, 32, 4096,
+					  I915_TILING_NONE,
+					  I915_COMPRESSION_NONE);
 
-	igt_assert(drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd) == 0);
+	prime_fd = prime_handle_to_fd(intel_fd, test_intel_buf->handle);
 
 	igt_assert(nouveau_bo_prime_handle_ref(ndev, prime_fd, &nvbo) == 0);
 	igt_assert(nouveau_bo_prime_handle_ref(ndev2, prime_fd, &nvbo2) == 0);
@@ -108,25 +112,27 @@ static void test_i915_nv_import_twice_check_flink_name(void)
 
 	nouveau_bo_ref(NULL, &nvbo2);
 	nouveau_bo_ref(NULL, &nvbo);
-	drm_intel_bo_unreference(test_intel_bo);
+	intel_buf_destroy(test_intel_buf);
 }
 
 static void test_i915_nv_reimport_twice_check_flink_name(void)
 {
-	drm_intel_bo *test_intel_bo;
+	struct intel_buf *test_intel_buf;
 	int prime_fd;
 	struct nouveau_bo *nvbo = NULL, *nvbo2 = NULL;
 	uint32_t flink_name1, flink_name2;
 
-	test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", BO_SIZE, 4096);
+	test_intel_buf = intel_buf_create(bops, WIDTH, HEIGHT, 32, 4096,
+					  I915_TILING_NONE,
+					  I915_COMPRESSION_NONE);
 
-	igt_assert(drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd) == 0);
+	prime_fd = prime_handle_to_fd(intel_fd, test_intel_buf->handle);
 
 	igt_assert(nouveau_bo_prime_handle_ref(ndev, prime_fd, &nvbo) == 0);
 
 	/* create a new dma-buf */
 	close(prime_fd);
-	igt_assert(drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd) == 0);
+	prime_handle_to_fd(intel_fd, test_intel_buf->handle);
 
 	igt_assert(nouveau_bo_prime_handle_ref(ndev2, prime_fd, &nvbo2) == 0);
 	close(prime_fd);
@@ -138,79 +144,91 @@ static void test_i915_nv_reimport_twice_check_flink_name(void)
 
 	nouveau_bo_ref(NULL, &nvbo2);
 	nouveau_bo_ref(NULL, &nvbo);
-	drm_intel_bo_unreference(test_intel_bo);
+	intel_buf_destroy(test_intel_buf);
 }
 
 static void test_nv_i915_import_twice_check_flink_name(void)
 {
-	drm_intel_bo *intel_bo = NULL, *intel_bo2 = NULL;
+	struct intel_buf *intel_buf1 = NULL, *intel_buf2 = NULL;
 	int prime_fd;
 	struct nouveau_bo *nvbo = NULL;
-	uint32_t flink_name1, flink_name2;
+	uint32_t flink_name1, flink_name2, handle;
 
 	igt_assert(nouveau_bo_new(ndev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP,
 				  0, BO_SIZE, NULL, &nvbo) == 0);
 
 	igt_assert(nouveau_bo_set_prime(nvbo, &prime_fd) == 0);
 
-	intel_bo = drm_intel_bo_gem_create_from_prime(bufmgr, prime_fd, BO_SIZE);
-	igt_assert(intel_bo);
-
-	intel_bo2 = drm_intel_bo_gem_create_from_prime(bufmgr2, prime_fd, BO_SIZE);
-	igt_assert(intel_bo2);
+	handle = prime_fd_to_handle(intel_fd, prime_fd);
+	intel_buf1 = intel_buf_create_using_handle(bops, handle,  WIDTH, HEIGHT,
+						   32, 4096, I915_TILING_NONE,
+						   I915_COMPRESSION_NONE);
+	intel_buf_set_ownership(intel_buf1, true);
+
+	handle = prime_fd_to_handle(intel_fd2, prime_fd);
+	intel_buf2 = intel_buf_create_using_handle(bops2, handle,  WIDTH, HEIGHT,
+						   32, 4096, I915_TILING_NONE,
+						   I915_COMPRESSION_NONE);
+	intel_buf_set_ownership(intel_buf2, true);
 	close(prime_fd);
 
-	igt_assert(drm_intel_bo_flink(intel_bo, &flink_name1) == 0);
-	igt_assert(drm_intel_bo_flink(intel_bo2, &flink_name2) == 0);
+	flink_name1 = gem_flink(intel_fd, intel_buf1->handle);
+	flink_name2 = gem_flink(intel_fd2, intel_buf2->handle);
 
 	igt_assert_eq_u32(flink_name1, flink_name2);
 
 	nouveau_bo_ref(NULL, &nvbo);
-	drm_intel_bo_unreference(intel_bo);
-	drm_intel_bo_unreference(intel_bo2);
+	intel_buf_destroy(intel_buf1);
+	intel_buf_destroy(intel_buf2);
 }
 
 static void test_nv_i915_reimport_twice_check_flink_name(void)
 {
-	drm_intel_bo *intel_bo = NULL, *intel_bo2 = NULL;
+	struct intel_buf *intel_buf1 = NULL, *intel_buf2 = NULL;
 	int prime_fd;
 	struct nouveau_bo *nvbo = NULL;
-	uint32_t flink_name1, flink_name2;
+	uint32_t flink_name1, flink_name2, handle;
 
 	igt_assert(nouveau_bo_new(ndev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP,
 				  0, BO_SIZE, NULL, &nvbo) == 0);
 
 	igt_assert(nouveau_bo_set_prime(nvbo, &prime_fd) == 0);
 
-	intel_bo = drm_intel_bo_gem_create_from_prime(bufmgr, prime_fd, BO_SIZE);
-	igt_assert(intel_bo);
-	close(prime_fd);
-	igt_assert(nouveau_bo_set_prime(nvbo, &prime_fd) == 0);
+	handle = prime_fd_to_handle(intel_fd, prime_fd);
+	intel_buf1 = intel_buf_create_using_handle(bops, handle,  WIDTH, HEIGHT,
+						   32, 4096, I915_TILING_NONE,
+						   I915_COMPRESSION_NONE);
+	intel_buf_set_ownership(intel_buf1, true);
 
-	intel_bo2 = drm_intel_bo_gem_create_from_prime(bufmgr2, prime_fd, BO_SIZE);
-	igt_assert(intel_bo2);
+	igt_assert(nouveau_bo_set_prime(nvbo, &prime_fd) == 0);
+	handle = prime_fd_to_handle(intel_fd2, prime_fd);
+	intel_buf2 = intel_buf_create_using_handle(bops2, handle,  WIDTH, HEIGHT,
+						   32, 4096, I915_TILING_NONE,
+						   I915_COMPRESSION_NONE);
+	intel_buf_set_ownership(intel_buf2, true);
 	close(prime_fd);
 
-	igt_assert(drm_intel_bo_flink(intel_bo, &flink_name1) == 0);
-	igt_assert(drm_intel_bo_flink(intel_bo2, &flink_name2) == 0);
+	flink_name1 = gem_flink(intel_fd, intel_buf1->handle);
+	flink_name2 = gem_flink(intel_fd2, intel_buf2->handle);
 
 	igt_assert_eq_u32(flink_name1, flink_name2);
 
 	nouveau_bo_ref(NULL, &nvbo);
-	drm_intel_bo_unreference(intel_bo);
-	drm_intel_bo_unreference(intel_bo2);
+	intel_buf_destroy(intel_buf1);
+	intel_buf_destroy(intel_buf2);
 }
 
 static void test_i915_nv_import_vs_close(void)
 {
-	drm_intel_bo *test_intel_bo;
+	struct intel_buf *test_intel_buf;
 	int prime_fd;
 	struct nouveau_bo *nvbo = NULL, *nvbo2 = NULL;
 
-	test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", BO_SIZE, 4096);
-	igt_assert(test_intel_bo);
+	test_intel_buf = intel_buf_create(bops, WIDTH, HEIGHT, 32, 4096,
+					  I915_TILING_NONE,
+					  I915_COMPRESSION_NONE);
 
-	igt_assert(drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd) == 0);
+	prime_fd = prime_handle_to_fd(intel_fd, test_intel_buf->handle);
 
 	igt_assert(nouveau_bo_prime_handle_ref(ndev, prime_fd, &nvbo) == 0);
 	close(prime_fd);
@@ -218,21 +236,21 @@ static void test_i915_nv_import_vs_close(void)
 
 	nouveau_bo_ref(NULL, &nvbo2);
 	nouveau_bo_ref(NULL, &nvbo);
-	drm_intel_bo_unreference(test_intel_bo);
+	intel_buf_destroy(test_intel_buf);
 }
 
 /* import handle twice on one driver */
 static void test_i915_nv_double_import(void)
 {
-	drm_intel_bo *test_intel_bo;
+	struct intel_buf *test_intel_buf;
 	int prime_fd;
 	struct nouveau_bo *nvbo = NULL, *nvbo2 = NULL;
 
-	test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", BO_SIZE, 4096);
-	igt_assert(test_intel_bo);
-
-	igt_assert(drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd) == 0);
+	test_intel_buf = intel_buf_create(bops, WIDTH, HEIGHT, 32, 4096,
+					  I915_TILING_NONE,
+					  I915_COMPRESSION_NONE);
 
+	prime_fd = prime_handle_to_fd(intel_fd, test_intel_buf->handle);
 	igt_assert(nouveau_bo_prime_handle_ref(ndev, prime_fd, &nvbo) == 0);
 	igt_assert(nouveau_bo_prime_handle_ref(ndev, prime_fd, &nvbo2) == 0);
 	close(prime_fd);
@@ -241,23 +259,24 @@ static void test_i915_nv_double_import(void)
 
 	nouveau_bo_ref(NULL, &nvbo2);
 	nouveau_bo_ref(NULL, &nvbo);
-	drm_intel_bo_unreference(test_intel_bo);
+	intel_buf_destroy(test_intel_buf);
 }
 
 /* export handle twice from one driver - import twice
    see if we get same object */
 static void test_i915_nv_double_export(void)
 {
-	drm_intel_bo *test_intel_bo;
+	struct intel_buf *test_intel_buf;
 	int prime_fd, prime_fd2;
 	struct nouveau_bo *nvbo = NULL, *nvbo2 = NULL;
 
-	test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", BO_SIZE, 4096);
-	igt_assert(test_intel_bo);
+	test_intel_buf = intel_buf_create(bops, WIDTH, HEIGHT, 32, 4096,
+					  I915_TILING_NONE,
+					  I915_COMPRESSION_NONE);
 
-	drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd);
+	prime_fd = prime_handle_to_fd(intel_fd, test_intel_buf->handle);
 
-	drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd2);
+	prime_fd2 = prime_handle_to_fd(intel_fd, test_intel_buf->handle);
 
 	igt_assert(nouveau_bo_prime_handle_ref(ndev, prime_fd, &nvbo) == 0);
 	close(prime_fd);
@@ -268,27 +287,33 @@ static void test_i915_nv_double_export(void)
 
 	nouveau_bo_ref(NULL, &nvbo2);
 	nouveau_bo_ref(NULL, &nvbo);
-	drm_intel_bo_unreference(test_intel_bo);
+	intel_buf_destroy(test_intel_buf);
 }
 
 /* export handle from intel driver - reimport to intel driver
    see if you get same object */
 static void test_i915_self_import(void)
 {
-	drm_intel_bo *test_intel_bo, *test_intel_bo2;
+	struct intel_buf *test_intel_buf, *test_intel_buf2;
+	uint32_t handle;
 	int prime_fd;
 
-	test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", BO_SIZE, 4096);
+	test_intel_buf = intel_buf_create(bops, WIDTH, HEIGHT, 32, 4096,
+					  I915_TILING_NONE,
+					  I915_COMPRESSION_NONE);
 
-	drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd);
+	prime_fd = prime_handle_to_fd(intel_fd, test_intel_buf->handle);
 
-	test_intel_bo2 = drm_intel_bo_gem_create_from_prime(bufmgr, prime_fd, BO_SIZE);
-	close(prime_fd);
-	igt_assert(test_intel_bo2);
+	handle = prime_fd_to_handle(intel_fd, prime_fd);
+	test_intel_buf2 = intel_buf_create_using_handle(bops, handle, WIDTH,
+							HEIGHT, 32, 4096,
+							I915_TILING_NONE,
+							I915_COMPRESSION_NONE);
 
-	igt_assert(test_intel_bo->handle == test_intel_bo2->handle);
+	igt_assert(test_intel_buf->handle == test_intel_buf2->handle);
 
-	drm_intel_bo_unreference(test_intel_bo);
+	intel_buf_destroy(test_intel_buf);
+	intel_buf_destroy(test_intel_buf2);
 }
 
 /* nouveau export reimport test */
@@ -309,23 +334,31 @@ static void test_nv_self_import(void)
 	nouveau_bo_ref(NULL, &nvbo2);
 }
 
-/* export handle from intel driver - reimport to another intel driver bufmgr
+/* export handle from intel driver - reimport to another intel driver
    see if you get same object */
 static void test_i915_self_import_to_different_fd(void)
 {
-	drm_intel_bo *test_intel_bo, *test_intel_bo2;
+	struct intel_buf *test_intel_buf, *test_intel_buf2;
+	uint32_t handle;
 	int prime_fd;
 
-	test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", BO_SIZE, 4096);
+	test_intel_buf = intel_buf_create(bops, WIDTH, HEIGHT, 32, 4096,
+					  I915_TILING_NONE,
+					  I915_COMPRESSION_NONE);
 
-	drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd);
+	prime_fd = prime_handle_to_fd(intel_fd, test_intel_buf->handle);
+
+	handle = prime_fd_to_handle(intel_fd2, prime_fd);
+	test_intel_buf2 = intel_buf_create_using_handle(bops2, handle, WIDTH,
+							HEIGHT, 32, 4096,
+							I915_TILING_NONE,
+							I915_COMPRESSION_NONE);
+	intel_buf_set_ownership(test_intel_buf2, true);
 
-	test_intel_bo2 = drm_intel_bo_gem_create_from_prime(bufmgr2, prime_fd, BO_SIZE);
 	close(prime_fd);
-	igt_assert(test_intel_bo2);
 
-	drm_intel_bo_unreference(test_intel_bo2);
-	drm_intel_bo_unreference(test_intel_bo);
+	intel_buf_destroy(test_intel_buf);
+	intel_buf_destroy(test_intel_buf2);
 }
 
 /* nouveau export reimport to other driver test */
@@ -357,14 +390,8 @@ igt_main
 		igt_require(intel_fd2 != -1);
 
 		/* set up intel bufmgr */
-		bufmgr = drm_intel_bufmgr_gem_init(intel_fd, 4096);
-		igt_assert(bufmgr);
-		/* Do not enable reuse, we share (almost) all buffers. */
-		//drm_intel_bufmgr_gem_enable_reuse(bufmgr);
-
-		bufmgr2 = drm_intel_bufmgr_gem_init(intel_fd2, 4096);
-		igt_assert(bufmgr2);
-		drm_intel_bufmgr_gem_enable_reuse(bufmgr2);
+		bops = buf_ops_create(intel_fd);
+		bops2 = buf_ops_create(intel_fd2);
 
 		/* set up nouveau bufmgr */
 		igt_assert(nouveau_device_wrap(nouveau_fd, 0, &ndev) >= 0);
@@ -374,11 +401,6 @@ igt_main
 		igt_assert(nouveau_device_wrap(nouveau_fd2, 0, &ndev2) >= 0);
 
 		igt_assert(nouveau_client_new(ndev2, &nclient2) >= 0);;
-
-		/* set up an intel batch buffer */
-		devid = intel_get_drm_devid(intel_fd);
-		intel_batch = intel_batchbuffer_alloc(bufmgr, devid);
-		igt_assert(intel_batch);
 	}
 
 #define xtest(name) \
@@ -399,11 +421,8 @@ igt_main
 	xtest(nv_self_import_to_different_fd);
 	
 	igt_fixture {
-		intel_batchbuffer_free(intel_batch);
-
 		nouveau_device_del(&ndev);
-		drm_intel_bufmgr_destroy(bufmgr);
-
+		buf_ops_destroy(bops);
 		close(intel_fd);
 		close(nouveau_fd);
 	}
-- 
2.20.1

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[igt-dev] [PATCH i-g-t v4 23/25] tests/prime_nv_test.c: Remove libdrm dependency

[Dominik Grzegorzek]

Use intel_bb / intel_buf to remove libdrm dependency.

Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 tests/prime_nv_test.c | 189 +++++++++++++++++++++++-------------------
 1 file changed, 106 insertions(+), 83 deletions(-)

diff --git a/tests/prime_nv_test.c b/tests/prime_nv_test.c
index b4714dcb..37aea69d 100644
--- a/tests/prime_nv_test.c
+++ b/tests/prime_nv_test.c
@@ -23,17 +23,17 @@
 #include <sys/stat.h>
 #include <sys/ioctl.h>
 
-#include "intel_bufmgr.h"
 #include "nouveau.h"
 
 int intel_fd = -1, nouveau_fd = -1;
-drm_intel_bufmgr *bufmgr;
+struct buf_ops *bops;
 struct nouveau_device *ndev;
 struct nouveau_client *nclient;
-uint32_t devid;
-struct intel_batchbuffer *intel_batch;
+struct intel_bb *ibb;
 
-#define BO_SIZE (256*1024)
+#define WIDTH 256
+#define HEIGHT 256
+#define BO_SIZE (WIDTH*HEIGHT*4)
 
 static int find_and_open_devices(void)
 {
@@ -83,20 +83,21 @@ static int find_and_open_devices(void)
  */
 static void test_i915_nv_sharing(void)
 {
-	drm_intel_bo *test_intel_bo;
+	struct intel_buf *test_intel_buf;
 	int prime_fd;
 	struct nouveau_bo *nvbo;
 
-	test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", BO_SIZE, 4096);
-	igt_assert(test_intel_bo);
+	test_intel_buf = intel_buf_create(bops, WIDTH, HEIGHT, 32, 4096,
+					  I915_TILING_NONE,
+					  I915_COMPRESSION_NONE);
 
-	drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd);
+	prime_fd = prime_handle_to_fd(intel_fd, test_intel_buf->handle);
 
 	igt_assert(nouveau_bo_prime_handle_ref(ndev, prime_fd, &nvbo) == 0);
 	close(prime_fd);
 
 	nouveau_bo_ref(NULL, &nvbo);
-	drm_intel_bo_unreference(test_intel_bo);
+	intel_buf_destroy(test_intel_buf);
 }
 
 /*
@@ -109,7 +110,8 @@ static void test_i915_nv_sharing(void)
  */
 static void test_nv_i915_sharing(void)
 {
-	drm_intel_bo *test_intel_bo;
+	struct intel_buf *test_intel_buf;
+	uint32_t handle;
 	int prime_fd;
 	struct nouveau_bo *nvbo;
 
@@ -117,12 +119,16 @@ static void test_nv_i915_sharing(void)
 				  0, BO_SIZE, NULL, &nvbo) == 0);
 	igt_assert(nouveau_bo_set_prime(nvbo, &prime_fd) == 0);
 
-	test_intel_bo = drm_intel_bo_gem_create_from_prime(bufmgr, prime_fd, BO_SIZE);
+	handle = prime_fd_to_handle(intel_fd, prime_fd);
+	test_intel_buf = intel_buf_create_using_handle(bops, handle, WIDTH,
+						       HEIGHT, 32, 4096,
+						       I915_TILING_NONE,
+						       I915_COMPRESSION_NONE);
+	intel_buf_set_ownership(test_intel_buf, true);
 	close(prime_fd);
-	igt_assert(test_intel_bo);
 
 	nouveau_bo_ref(NULL, &nvbo);
-	drm_intel_bo_unreference(test_intel_bo);
+	intel_buf_destroy(test_intel_buf);
 }
 
 /*
@@ -131,14 +137,16 @@ static void test_nv_i915_sharing(void)
  */
 static void test_nv_write_i915_cpu_mmap_read(void)
 {
-	drm_intel_bo *test_intel_bo;
+	struct intel_buf *test_intel_buf;
 	int prime_fd;
 	struct nouveau_bo *nvbo = NULL;
 	uint32_t *ptr;
 
-	test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", BO_SIZE, 4096);
+	test_intel_buf = intel_buf_create(bops, WIDTH, HEIGHT, 32, 4096,
+					  I915_TILING_NONE,
+					  I915_COMPRESSION_NONE);
 
-	drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd);
+	prime_fd = prime_handle_to_fd(intel_fd, test_intel_buf->handle);
 
 	igt_assert(nouveau_bo_prime_handle_ref(ndev, prime_fd, &nvbo) == 0);
 	close(prime_fd);
@@ -147,13 +155,14 @@ static void test_nv_write_i915_cpu_mmap_read(void)
 	ptr = nvbo->map;
 	*ptr = 0xdeadbeef;
 
-	drm_intel_bo_map(test_intel_bo, 1);
-	ptr = test_intel_bo->virtual;
+	intel_buf_cpu_map(test_intel_buf, true);
+	ptr = test_intel_buf->ptr;
 	igt_assert(ptr);
 
 	igt_assert(*ptr == 0xdeadbeef);
 	nouveau_bo_ref(NULL, &nvbo);
-	drm_intel_bo_unreference(test_intel_bo);
+	intel_buf_unmap(test_intel_buf);
+	intel_buf_destroy(test_intel_buf);
 }
 
 /*
@@ -162,14 +171,16 @@ static void test_nv_write_i915_cpu_mmap_read(void)
  */
 static void test_nv_write_i915_gtt_mmap_read(void)
 {
-	drm_intel_bo *test_intel_bo;
+	struct intel_buf *test_intel_buf;
 	int prime_fd;
 	struct nouveau_bo *nvbo = NULL;
 	uint32_t *ptr;
 
-	test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", BO_SIZE, 4096);
+	test_intel_buf = intel_buf_create(bops, WIDTH, HEIGHT, 32, 4096,
+					  I915_TILING_NONE,
+					  I915_COMPRESSION_NONE);
 
-	drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd);
+	prime_fd = prime_handle_to_fd(intel_fd, test_intel_buf->handle);
 
 	igt_assert(nouveau_bo_prime_handle_ref(ndev, prime_fd, &nvbo) == 0);
 	close(prime_fd);
@@ -177,14 +188,16 @@ static void test_nv_write_i915_gtt_mmap_read(void)
 	ptr = nvbo->map;
 	*ptr = 0xdeadbeef;
 
-	drm_intel_gem_bo_map_gtt(test_intel_bo);
-	ptr = test_intel_bo->virtual;
+	ptr = gem_mmap__gtt(intel_fd, test_intel_buf->handle,
+			    test_intel_buf->surface[0].size, PROT_READ);
+
 	igt_assert(ptr);
 
 	igt_assert(*ptr == 0xdeadbeef);
 
 	nouveau_bo_ref(NULL, &nvbo);
-	drm_intel_bo_unreference(test_intel_bo);
+	gem_munmap(ptr, test_intel_buf->surface[0].size);
+	intel_buf_destroy(test_intel_buf);
 }
 
 /* test drm_intel_bo_map doesn't work properly,
@@ -192,32 +205,37 @@ static void test_nv_write_i915_gtt_mmap_read(void)
    for these objects */
 static void test_i915_import_cpu_mmap(void)
 {
-	drm_intel_bo *test_intel_bo;
+	struct intel_buf *test_intel_buf;
 	int prime_fd;
 	struct nouveau_bo *nvbo;
-	uint32_t *ptr;
+	uint32_t *ptr, handle;
 
 	igt_skip("cpu mmap support for imported dma-bufs not yet implemented\n");
 
 	igt_assert(nouveau_bo_new(ndev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP,
 				  0, BO_SIZE, NULL, &nvbo) == 0);
 	igt_assert(nouveau_bo_set_prime(nvbo, &prime_fd) == 0);
-	test_intel_bo = drm_intel_bo_gem_create_from_prime(bufmgr, prime_fd, BO_SIZE);
+
+	handle = prime_fd_to_handle(intel_fd, prime_fd);
+	test_intel_buf = intel_buf_create_using_handle(bops, handle, WIDTH,
+						       HEIGHT, 32, 4096,
+						       I915_TILING_NONE,
+						       I915_COMPRESSION_NONE);
+	intel_buf_set_ownership(test_intel_buf, true);
 	close(prime_fd);
-	igt_assert(test_intel_bo);
 
 	igt_assert(nouveau_bo_map(nvbo, NOUVEAU_BO_RDWR, nclient) == 0);
 
 	ptr = nvbo->map;
 	*ptr = 0xdeadbeef;
 
-	igt_assert(drm_intel_bo_map(test_intel_bo, 0) == 0);
-	igt_assert(test_intel_bo->virtual);
-	ptr = test_intel_bo->virtual;
+	intel_buf_cpu_map(test_intel_buf, false);
+	ptr = test_intel_buf->ptr;
 
 	igt_assert(*ptr == 0xdeadbeef);
 	nouveau_bo_ref(NULL, &nvbo);
-	drm_intel_bo_unreference(test_intel_bo);
+	intel_buf_unmap(test_intel_buf);
+	intel_buf_destroy(test_intel_buf);
 }
 
 /* test drm_intel_bo_map_gtt works properly,
@@ -225,18 +243,22 @@ static void test_i915_import_cpu_mmap(void)
    for these objects */
 static void test_i915_import_gtt_mmap(void)
 {
-	drm_intel_bo *test_intel_bo;
+	struct intel_buf *test_intel_buf;
 	int prime_fd;
 	struct nouveau_bo *nvbo;
-	uint32_t *ptr;
+	uint32_t *ptr, handle;
 
 	igt_assert(nouveau_bo_new(ndev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP,
 				  0, BO_SIZE, NULL, &nvbo) == 0);
 	igt_assert(nouveau_bo_set_prime(nvbo, &prime_fd) == 0);
 
-	test_intel_bo = drm_intel_bo_gem_create_from_prime(bufmgr, prime_fd, BO_SIZE);
+	handle = prime_fd_to_handle(intel_fd, prime_fd);
+	test_intel_buf = intel_buf_create_using_handle(bops, handle, WIDTH,
+						       HEIGHT, 32, 4096,
+						       I915_TILING_NONE,
+						       I915_COMPRESSION_NONE);
+	intel_buf_set_ownership(test_intel_buf, true);
 	close(prime_fd);
-	igt_assert(test_intel_bo);
 
 	igt_assert(nouveau_bo_map(nvbo, NOUVEAU_BO_RDWR, nclient) == 0);
 
@@ -244,107 +266,112 @@ static void test_i915_import_gtt_mmap(void)
 	*ptr = 0xdeadbeef;
 	*(ptr + 1) = 0xa55a55;
 
-	igt_assert(drm_intel_gem_bo_map_gtt(test_intel_bo) == 0);
-	igt_assert(test_intel_bo->virtual);
-	ptr = test_intel_bo->virtual;
+	ptr = gem_mmap__gtt(intel_fd, test_intel_buf->handle,
+			    test_intel_buf->surface[0].size, PROT_READ);
 
 	igt_assert(*ptr == 0xdeadbeef);
 	nouveau_bo_ref(NULL, &nvbo);
-	drm_intel_bo_unreference(test_intel_bo);
+	gem_munmap(ptr, test_intel_buf->surface[0].size);
+	intel_buf_destroy(test_intel_buf);
 }
 
 /* test 7 - import from nouveau into intel, test pread/pwrite fail */
 static void test_i915_import_pread_pwrite(void)
 {
-	drm_intel_bo *test_intel_bo;
+	struct intel_buf *test_intel_buf;
 	int prime_fd;
 	struct nouveau_bo *nvbo;
-	uint32_t *ptr;
+	uint32_t *ptr, handle;
 	uint32_t buf[64];
 
 	igt_assert(nouveau_bo_new(ndev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP,
 				  0, BO_SIZE, NULL, &nvbo) == 0);
 	igt_assert(nouveau_bo_set_prime(nvbo, &prime_fd) == 0);
 
-	test_intel_bo = drm_intel_bo_gem_create_from_prime(bufmgr, prime_fd, BO_SIZE);
+	handle = prime_fd_to_handle(intel_fd, prime_fd);
+	test_intel_buf = intel_buf_create_using_handle(bops, handle, WIDTH,
+						       HEIGHT, 32, 4096,
+						       I915_TILING_NONE,
+						       I915_COMPRESSION_NONE);
+	intel_buf_set_ownership(test_intel_buf, true);
 	close(prime_fd);
-	igt_assert(test_intel_bo);
 
 	igt_assert(nouveau_bo_map(nvbo, NOUVEAU_BO_RDWR, nclient) == 0);
 
 	ptr = nvbo->map;
 	*ptr = 0xdeadbeef;
 
-	gem_read(intel_fd, test_intel_bo->handle, 0, buf, 256);
+	gem_read(intel_fd, test_intel_buf->handle, 0, buf, 256);
 	igt_assert(buf[0] == 0xdeadbeef);
 	buf[0] = 0xabcdef55;
 
-	gem_write(intel_fd, test_intel_bo->handle, 0, buf, 4);
+	gem_write(intel_fd, test_intel_buf->handle, 0, buf, 4);
 
 	igt_assert(*ptr == 0xabcdef55);
 
 	nouveau_bo_ref(NULL, &nvbo);
-	drm_intel_bo_unreference(test_intel_bo);
+	intel_buf_destroy(test_intel_buf);
 }
 
 static void
-set_bo(drm_intel_bo *bo, uint32_t val, int width, int height)
+set_bo(struct intel_buf *buf, uint32_t val, int width, int height)
 {
-        int size = width * height;
-        uint32_t *vaddr;
+	int size = width * height;
+	uint32_t *vaddr;
+
+	vaddr = gem_mmap__gtt(intel_fd, buf->handle, buf->surface[0].size,
+			      PROT_WRITE);
+	while (size--)
+		*vaddr++ = val;
 
-        drm_intel_gem_bo_start_gtt_access(bo, true);
-        vaddr = bo->virtual;
-        while (size--)
-                *vaddr++ = val;
+	gem_munmap(vaddr, buf->surface[0].size);
 }
 
-static drm_intel_bo *
-create_bo(drm_intel_bufmgr *ibufmgr, uint32_t val, int width, int height)
+static struct intel_buf *
+create_bo(struct buf_ops *ibops, uint32_t val, int width, int height)
 {
-        drm_intel_bo *bo;
-
-        bo = drm_intel_bo_alloc(ibufmgr, "bo", 4*width*height, 0);
-        igt_assert(bo);
+	struct intel_buf *buf;
 
-        /* gtt map doesn't have a write parameter, so just keep the mapping
-         * around (to avoid the set_domain with the gtt write domain set) and
-         * manually tell the kernel when we start access the gtt. */
-        drm_intel_gem_bo_map_gtt(bo);
+	buf = intel_buf_create(ibops, width, height, 32, 0, I915_TILING_NONE,
+			       I915_COMPRESSION_NONE);
 
-        set_bo(bo, val, width, height);
+	set_bo(buf, val, width, height);
 
-        return bo;
+	return buf;
 }
 
 /* use intel hw to fill the BO with a blit from another BO,
    then readback from the nouveau bo, check value is correct */
 static void test_i915_blt_fill_nv_read(void)
 {
-	drm_intel_bo *test_intel_bo, *src_bo;
+	struct intel_buf *test_intel_buf, *src_buf;
 	int prime_fd;
 	struct nouveau_bo *nvbo = NULL;
 	uint32_t *ptr;
 
-	src_bo = create_bo(bufmgr, 0xaa55aa55, 256, 1);
+	src_buf = create_bo(bops, 0xaa55aa55, 256, 1);
 
-	test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", BO_SIZE, 4096);
+	test_intel_buf = intel_buf_create(bops, WIDTH, HEIGHT, 32, 4096,
+					  I915_TILING_NONE,
+					  I915_COMPRESSION_NONE);
 
-	drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd);
+	prime_fd = prime_handle_to_fd(intel_fd, test_intel_buf->handle);
 
 	igt_assert(nouveau_bo_prime_handle_ref(ndev, prime_fd, &nvbo) == 0);
 	close(prime_fd);
 
-	intel_copy_bo(intel_batch, test_intel_bo, src_bo, BO_SIZE);
+	intel_bb_copy_intel_buf(ibb, test_intel_buf, src_buf,
+				src_buf->surface[0].size);
 
 	igt_assert(nouveau_bo_map(nvbo, NOUVEAU_BO_RDWR, nclient) == 0);
 
-	drm_intel_bo_map(test_intel_bo, 0);
+	intel_buf_cpu_map(test_intel_buf, 0);
 
 	ptr = nvbo->map;
 	igt_assert(*ptr == 0xaa55aa55);
 	nouveau_bo_ref(NULL, &nvbo);
-	drm_intel_bo_unreference(test_intel_bo);
+	intel_buf_unmap(test_intel_buf);
+	intel_buf_destroy(test_intel_buf);
 }
 
 /* test 8 use nouveau to do blit */
@@ -360,18 +387,14 @@ igt_main
 		igt_require(intel_fd != -1);
 
 		/* set up intel bufmgr */
-		bufmgr = drm_intel_bufmgr_gem_init(intel_fd, 4096);
-		igt_assert(bufmgr);
-		/* Do not enable reuse, we share (almost) all buffers. */
-		//drm_intel_bufmgr_gem_enable_reuse(bufmgr);
+		bops = buf_ops_create(intel_fd);
 
 		/* set up nouveau bufmgr */
 		igt_assert(nouveau_device_wrap(nouveau_fd, 0, &ndev) == 0);
 		igt_assert(nouveau_client_new(ndev, &nclient) == 0);
 
 		/* set up an intel batch buffer */
-		devid = intel_get_drm_devid(intel_fd);
-		intel_batch = intel_batchbuffer_alloc(bufmgr, devid);
+		ibb = intel_bb_create(intel_fd, 4096);
 	}
 
 #define xtest(name) \
@@ -388,10 +411,10 @@ igt_main
 	xtest(i915_blt_fill_nv_read);
 
 	igt_fixture {
-		intel_batchbuffer_free(intel_batch);
+		intel_bb_destroy(ibb);
 
 		nouveau_device_del(&ndev);
-		drm_intel_bufmgr_destroy(bufmgr);
+		buf_ops_destroy(bops);
 
 		close(intel_fd);
 		close(nouveau_fd);
-- 
2.20.1

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[igt-dev] [PATCH i-g-t v4 24/25] tests/i915/gem_ppgtt: make copying more readable

[Dominik Grzegorzek]

Use intel_bb_copy_intel_buf instead of intel_bb_blit_copy
to make the code simplier.

Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 tests/i915/gem_ppgtt.c | 16 ++++------------
 1 file changed, 4 insertions(+), 12 deletions(-)

diff --git a/tests/i915/gem_ppgtt.c b/tests/i915/gem_ppgtt.c
index 949601ac..8d7e1a81 100644
--- a/tests/i915/gem_ppgtt.c
+++ b/tests/i915/gem_ppgtt.c
@@ -165,12 +165,8 @@ static void fork_bcs_copy(int timeout, uint32_t final,
 			src[1] = create_bo(dst[child]->bops,
 					   i++ | child << 16);
 
-			intel_bb_blt_copy(ibb, src[1], 0, 0, 4096,
-					  src[0], 0, 0, 4096,
-					  4096/4, SIZE/4096, 32);
-			intel_bb_blt_copy(ibb, src[0], 0, 0, 4096,
-					  dst[child], 0, 0, 4096,
-					  4096/4, SIZE/4096, 32);
+			intel_bb_copy_intel_buf(ibb, src[0], src[1], SIZE);
+			intel_bb_copy_intel_buf(ibb, dst[child], src[0], SIZE);
 
 			intel_buf_destroy(src[1]);
 			intel_buf_destroy(src[0]);
@@ -180,12 +176,8 @@ static void fork_bcs_copy(int timeout, uint32_t final,
 		src[1] = create_bo(dst[child]->bops,
 				   final | child << 16);
 
-		intel_bb_blt_copy(ibb, src[1], 0, 0, 4096,
-				  src[0], 0, 0, 4096,
-				  4096/4, SIZE/4096, 32);
-		intel_bb_blt_copy(ibb, src[0], 0, 0, 4096,
-				  dst[child], 0, 0, 4096,
-				  4096/4, SIZE/4096, 32);
+		intel_bb_copy_intel_buf(ibb, src[0], src[1], SIZE);
+		intel_bb_copy_intel_buf(ibb, dst[child], src[0], SIZE);
 
 		intel_buf_destroy(src[1]);
 		intel_buf_destroy(src[0]);
-- 
2.20.1

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[igt-dev] [PATCH i-g-t v4 25/25] HAX: run changed tests in BAT only.

[Dominik Grzegorzek]

gem_tiled_blits will fail on !llc platforms
https://gitlab.freedesktop.org/drm/intel/-/issues/2328

Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
---
 tests/intel-ci/fast-feedback.testlist | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/tests/intel-ci/fast-feedback.testlist b/tests/intel-ci/fast-feedback.testlist
index aa2eb329..887f331d 100644
--- a/tests/intel-ci/fast-feedback.testlist
+++ b/tests/intel-ci/fast-feedback.testlist
@@ -32,12 +32,22 @@ igt@gem_huc_copy@huc-copy
 igt@gem_linear_blits@basic
 igt@gem_mmap@basic
 igt@gem_mmap_gtt@basic
+igt@gem_pipe_control_store_loop@fresh-buffer
+igt@gem_pipe_control_store_loop@reused-buffer
+igt@gem_ppgtt@blt-vs-render-ctx0
+igt@gem_ppgtt@blt-vs-render-ctxn
+igt@gem_ppgtt@flink-and-close-vma-leak
 igt@gem_render_linear_blits@basic
 igt@gem_render_tiled_blits@basic
 igt@gem_ringfill@basic-all
+igt@gem_set_tiling_vs_blt@untiled-to-tiled
+igt@gem_set_tiling_vs_blt@tiled-to-untiled
+igt@gem_set_tiling_vs_blt@tiled-to-tiled
 igt@gem_sync@basic-all
 igt@gem_sync@basic-each
 igt@gem_tiled_blits@basic
+igt@gem_tiled_blits@normal
+igt@gem_tiled_blits@interruptible
 igt@gem_tiled_fence_blits@basic
 igt@gem_tiled_pread_basic
 igt@gem_wait@busy@all
-- 
2.20.1

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Re: [igt-dev] [PATCH i-g-t v4 01/25] i915/gem_mmap: Modified offset in subtest "bad-size"

[Grzegorzek, Dominik]

Added to this series by mistake. Please Ignore.
On Tue, 2020-09-22 at 13:52 +0200, Dominik Grzegorzek wrote:
> From: Apoorva Singh <apoorva1.singh@intel.com>
> 
> Subtest "bad-size" should keep valid/good offset
> corresponding to buffer object being mapped.
> Currently, subtest will pass for any value of size
> provided as the offset value itself will not allow
> to map any size of memory which defies the purpose
> of this subtest.
> 
> The subtest should not pass due to bad offset value
> while it should pass only due to bad size provided.
> 
> v2: Added new offset. Updated the same changes in
> "bad-size" subtest of gem_mmap_wc too.
> 
> Signed-off-by: Apoorva Singh <apoorva1.singh@intel.com>
> Cc: Melkaveri, Arjun <arjun.melkaveri@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>  tests/i915/gem_mmap.c    | 25 ++++++++++++++++---------
>  tests/i915/gem_mmap_wc.c | 26 ++++++++++++++++----------
>  2 files changed, 32 insertions(+), 19 deletions(-)
> 
> diff --git a/tests/i915/gem_mmap.c b/tests/i915/gem_mmap.c
> index f8cf052e..8bad9b14 100644
> --- a/tests/i915/gem_mmap.c
> +++ b/tests/i915/gem_mmap.c
> @@ -214,18 +214,25 @@ igt_main
>  			2 * 4096,
>  			~0,
>  		};
> +		uint64_t offset[] = {
> +			4096,
> +			0
> +		};
>  
> -		for (int i = 0; i < ARRAY_SIZE(bad_size); i++) {
> -			struct drm_i915_gem_mmap arg = {
> -				.handle = gem_create(fd, 4096),
> -				.offset = 4096,
> -				.size = bad_size[i],
> -			};
> +		for(int i = 0; i < ARRAY_SIZE(offset); i++) {
> +			for (int j = 0; j < ARRAY_SIZE(bad_size); j++)
> {
> +				struct drm_i915_gem_mmap arg = {
> +					.handle = gem_create(fd, 4096),
> +					.offset = offset[i],
> +					.size = bad_size[j],
> +				};
>  
> -			igt_debug("Trying to mmap bad size; size:
> %'"PRIu64"\n", bad_size[i]);
> -			igt_assert_eq(mmap_ioctl(fd, &arg), -EINVAL);
> +				igt_debug("Trying to mmap bad size;
> size: %'"PRIu64", offset: %'"PRIu64"\n",
> +						bad_size[j],
> offset[i]);
> +				igt_assert_eq(mmap_ioctl(fd, &arg),
> -EINVAL);
>  
> -			gem_close(fd, arg.handle);
> +				gem_close(fd, arg.handle);
> +			}
>  		}
>  	}
>  
> diff --git a/tests/i915/gem_mmap_wc.c b/tests/i915/gem_mmap_wc.c
> index f44b406d..fe1283e5 100644
> --- a/tests/i915/gem_mmap_wc.c
> +++ b/tests/i915/gem_mmap_wc.c
> @@ -563,17 +563,23 @@ igt_main
>  			2 * 4096,
>  			~0,
>  		};
> +		uint64_t offset[] = {
> +			4096,
> +			0
> +		};
>  
> -		for (int i = 0; i < ARRAY_SIZE(bad_size); i++) {
> -			struct drm_i915_gem_mmap arg = {
> -				.handle = gem_create(fd, 4096),
> -				.offset = 4096,
> -				.size = bad_size[i],
> -				.flags = I915_MMAP_WC,
> -			};
> -
> -			igt_assert_eq(mmap_ioctl(fd, &arg), -EINVAL);
> -			gem_close(fd, arg.handle);
> +		for(int i = 0; i < ARRAY_SIZE(offset); i++) {
> +			for (int j = 0; j < ARRAY_SIZE(bad_size); j++)
> {
> +				struct drm_i915_gem_mmap arg = {
> +					.handle = gem_create(fd, 4096),
> +					.offset = offset[i],
> +					.size = bad_size[j],
> +					.flags = I915_MMAP_WC,
> +				};
> +
> +				igt_assert_eq(mmap_ioctl(fd, &arg),
> -EINVAL);
> +				gem_close(fd, arg.handle);
> +			}
>  		}
>  	}

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[igt-dev] ✗ Fi.CI.BAT: failure for tests/benchmarks: Libdrm removal (rev4)

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 8324 bytes --]

== Series Details ==

Series: tests/benchmarks: Libdrm removal (rev4)
URL   : https://patchwork.freedesktop.org/series/81782/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9033 -> IGTPW_5003
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_5003 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_5003, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5003/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_5003:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_pipe_control_store_loop@reused-buffer:
    - fi-snb-2600:        NOTRUN -> [FAIL][1] +1 similar issue
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5003/fi-snb-2600/igt@gem_pipe_control_store_loop@reused-buffer.html
    - fi-snb-2520m:       NOTRUN -> [FAIL][2] +1 similar issue
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5003/fi-snb-2520m/igt@gem_pipe_control_store_loop@reused-buffer.html

  * igt@gem_set_tiling_vs_blt@untiled-to-tiled:
    - fi-blb-e6850:       NOTRUN -> [FAIL][3]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5003/fi-blb-e6850/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html
    - fi-pnv-d510:        NOTRUN -> [FAIL][4]
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5003/fi-pnv-d510/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html

  * igt@gem_tiled_blits@basic:
    - fi-elk-e7500:       [PASS][5] -> [FAIL][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9033/fi-elk-e7500/igt@gem_tiled_blits@basic.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5003/fi-elk-e7500/igt@gem_tiled_blits@basic.html
    - fi-ilk-650:         [PASS][7] -> [FAIL][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9033/fi-ilk-650/igt@gem_tiled_blits@basic.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5003/fi-ilk-650/igt@gem_tiled_blits@basic.html
    - fi-byt-j1900:       [PASS][9] -> [FAIL][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9033/fi-byt-j1900/igt@gem_tiled_blits@basic.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5003/fi-byt-j1900/igt@gem_tiled_blits@basic.html
    - fi-pnv-d510:        [PASS][11] -> [FAIL][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9033/fi-pnv-d510/igt@gem_tiled_blits@basic.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5003/fi-pnv-d510/igt@gem_tiled_blits@basic.html
    - fi-blb-e6850:       [PASS][13] -> [FAIL][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9033/fi-blb-e6850/igt@gem_tiled_blits@basic.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5003/fi-blb-e6850/igt@gem_tiled_blits@basic.html
    - fi-bwr-2160:        [PASS][15] -> [FAIL][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9033/fi-bwr-2160/igt@gem_tiled_blits@basic.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5003/fi-bwr-2160/igt@gem_tiled_blits@basic.html

  
Known issues
------------

  Here are the changes found in IGTPW_5003 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_tiled_blits@basic:
    - fi-apl-guc:         [PASS][17] -> [FAIL][18] ([i915#1635])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9033/fi-apl-guc/igt@gem_tiled_blits@basic.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5003/fi-apl-guc/igt@gem_tiled_blits@basic.html

  * igt@i915_selftest@live@objects:
    - fi-apl-guc:         [PASS][19] -> [INCOMPLETE][20] ([i915#1635])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9033/fi-apl-guc/igt@i915_selftest@live@objects.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5003/fi-apl-guc/igt@i915_selftest@live@objects.html

  * igt@kms_busy@basic@flip:
    - fi-kbl-x1275:       [PASS][21] -> [DMESG-WARN][22] ([i915#62] / [i915#92] / [i915#95])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9033/fi-kbl-x1275/igt@kms_busy@basic@flip.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5003/fi-kbl-x1275/igt@kms_busy@basic@flip.html

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-kbl-7500u:       [PASS][23] -> [DMESG-WARN][24] ([i915#2203])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9033/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5003/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - fi-byt-j1900:       [PASS][25] -> [DMESG-WARN][26] ([i915#1982])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9033/fi-byt-j1900/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5003/fi-byt-j1900/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@basic-flip-before-cursor-atomic:
    - fi-icl-u2:          [PASS][27] -> [DMESG-WARN][28] ([i915#1982]) +1 similar issue
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9033/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5003/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html

  
#### Possible fixes ####

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - fi-icl-u2:          [DMESG-WARN][29] ([i915#1982]) -> [PASS][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9033/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5003/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  
#### Warnings ####

  * igt@i915_pm_rpm@module-reload:
    - fi-kbl-x1275:       [DMESG-FAIL][31] ([i915#62] / [i915#95]) -> [DMESG-FAIL][32] ([i915#62])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9033/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5003/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html

  * igt@kms_cursor_legacy@basic-flip-before-cursor-legacy:
    - fi-kbl-x1275:       [DMESG-WARN][33] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][34] ([i915#62] / [i915#92]) +3 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9033/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-before-cursor-legacy.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5003/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-before-cursor-legacy.html

  * igt@kms_flip@basic-flip-vs-modeset@a-dp1:
    - fi-kbl-x1275:       [DMESG-WARN][35] ([i915#62] / [i915#92]) -> [DMESG-WARN][36] ([i915#62] / [i915#92] / [i915#95]) +4 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9033/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset@a-dp1.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5003/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset@a-dp1.html

  
  [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
  [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
  [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95


Participating hosts (43 -> 37)
------------------------------

  Missing    (6): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_5787 -> IGTPW_5003

  CI-20190529: 20190529
  CI_DRM_9033: afeb3835029ad70d17802a9c7148a8372fb08479 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_5003: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5003/index.html
  IGT_5787: 0ec962017c8131de14e0cb038f7f76b1f17ed637 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5003/index.html

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Re: [igt-dev] [PATCH i-g-t v4 03/25] lib/intel_batchbuffer: add intel_bb_blit_copy wrapper

[Zbigniew Kempczyński]

On Tue, Sep 22, 2020 at 01:52:07PM +0200, Dominik Grzegorzek wrote:
> This patch adds intel_bb_copy_intel_buf to make copying a whole
> intel_buf easier and more readable.
> 
> Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>  lib/intel_batchbuffer.c | 23 +++++++++++++++++++++++
>  lib/intel_batchbuffer.h |  3 +++
>  2 files changed, 26 insertions(+)
> 
> diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
> index 079d6389..259b15c5 100644
> --- a/lib/intel_batchbuffer.c
> +++ b/lib/intel_batchbuffer.c
> @@ -2545,6 +2545,29 @@ void intel_bb_blt_copy(struct intel_bb *ibb,
>  	intel_bb_flush_blit(ibb);
>  }
>  
> +/**
> + * intel_bb_copy_intel_buf:
> + * @batch: batchbuffer object
> + * @src: source buffer (intel_buf)
> + * @dst: destination libdrm buffer object
> + * @size: size of the copy range in bytes
> + *
> + * Tmits a copy operation using blitter commands into the supplied batch
> + * buffer object. A total of @size bytes from the start of @src is copied
> + * over to @dst. Note that @size must be page-aligned.
> + */

Small nits:

s/Tmits/Emits/

s/batch buffer object/intel_bb/ or just batch. 

> +void intel_bb_copy_intel_buf(struct intel_bb *ibb,
> +			     struct intel_buf *dst, struct intel_buf *src,
> +			     long int size)
> +{
> +	igt_assert(size % 4096 == 0);
> +
> +	intel_bb_blt_copy(ibb,
> +		       src, 0, 0, 4096,
> +		       dst, 0, 0, 4096,
> +		       4096/4, size/4096, 32);
> +}
> +
>  /**
>   * igt_get_huc_copyfunc:
>   * @devid: pci device id
> diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
> index cbfbe25f..a23ba9af 100644
> --- a/lib/intel_batchbuffer.h
> +++ b/lib/intel_batchbuffer.h
> @@ -654,6 +654,9 @@ void intel_bb_blt_copy(struct intel_bb *ibb,
>  		       struct intel_buf *dst,
>  		       int dst_x1, int dst_y1, int dst_pitch,
>  		       int width, int height, int bpp);
> +void intel_bb_copy_intel_buf(struct intel_bb *ibb,
> +			     struct intel_buf *dst, struct intel_buf *src,
> +			     long int size);
                             |
                             ^---- I guess indentation is not valid.

Then:

Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

>  
>  /**
>   * igt_huc_copyfunc_t:
> -- 
> 2.20.1
> 
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Re: [igt-dev] [PATCH i-g-t v4 06/25] i915/gem_pipe_control_store_loop.c: Remove libdrm dependency

[Zbigniew Kempczyński]

On Tue, Sep 22, 2020 at 01:52:10PM +0200, Dominik Grzegorzek wrote:
> Use intel_bb / intel_buf to remove libdrm dependency.
> 
> Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>  tests/i915/gem_pipe_control_store_loop.c | 143 +++++++++++------------
>  1 file changed, 69 insertions(+), 74 deletions(-)
> 
> diff --git a/tests/i915/gem_pipe_control_store_loop.c b/tests/i915/gem_pipe_control_store_loop.c
> index 863a4871..d508ea29 100644
> --- a/tests/i915/gem_pipe_control_store_loop.c
> +++ b/tests/i915/gem_pipe_control_store_loop.c
> @@ -43,13 +43,11 @@
>  #include "drm.h"
>  #include "i915/gem.h"
>  #include "igt.h"
> -#include "intel_bufmgr.h"
>  
>  IGT_TEST_DESCRIPTION("Test (TLB-)Coherency of pipe_control QW writes.");
>  
> -static drm_intel_bufmgr *bufmgr;
> -struct intel_batchbuffer *batch;
> -uint32_t devid;
> +static struct buf_ops *bops;
> +static struct intel_bb *ibb;
>  
>  #define GFX_OP_PIPE_CONTROL	((0x3<<29)|(0x3<<27)|(0x2<<24)|2)
>  #define   PIPE_CONTROL_WRITE_IMMEDIATE	(1<<14)
> @@ -68,96 +66,102 @@ store_pipe_control_loop(bool preuse_buffer, int timeout)
>  {
>  	int val = 0;
>  	uint32_t *buf;
> -	drm_intel_bo *target_bo;
> +	struct intel_buf *target_buf;
>  
>  	igt_until_timeout(timeout) {
>  		/* we want to check tlb consistency of the pipe_control target,
>  		 * so get a new buffer every time around */
> -		target_bo = drm_intel_bo_alloc(bufmgr, "target bo", 4096, 4096);
> -		igt_assert(target_bo);
> +		target_buf = intel_buf_create(bops, 32, 32, 32, 4096,
> +					      I915_TILING_NONE,
> +					      I915_COMPRESSION_NONE);
> +		intel_bb_add_intel_buf(ibb, target_buf, true);
>  
>  		if (preuse_buffer) {
> -			COLOR_BLIT_COPY_BATCH_START(0);
> -			OUT_BATCH((3 << 24) | (0xf0 << 16) | 64);
> -			OUT_BATCH(0);
> -			OUT_BATCH(1 << 16 | 1);
> +			intel_bb_out(ibb, XY_COLOR_BLT_CMD_NOLEN |
> +				     COLOR_BLT_WRITE_ALPHA |
> +				     XY_COLOR_BLT_WRITE_RGB |
> +				     (4 + (ibb->gen >= 8)));
> +
> +			intel_bb_out(ibb, (3 << 24) | (0xf0 << 16) | 64);
> +			intel_bb_out(ibb, 0);
> +			intel_bb_out(ibb, 1 << 16 | 1);
>  
>  			/*
>  			 * IMPORTANT: We need to preuse the buffer in a
>  			 * different domain than what the pipe control write
>  			 * (and kernel wa) uses!
>  			 */
> -			OUT_RELOC_FENCED(target_bo,
> -			     I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
> -			     0);
> -			OUT_BATCH(0xdeadbeef);
> -			ADVANCE_BATCH();
> +			intel_bb_emit_reloc_fenced(ibb, target_buf->handle,
> +						   I915_GEM_DOMAIN_RENDER,
> +						   I915_GEM_DOMAIN_RENDER,
> +						   0, target_buf->addr.offset);
> +			intel_bb_out(ibb, 0xdeadbeef);
>  
> -			intel_batchbuffer_flush(batch);
> +			intel_bb_flush_blit(ibb);
>  		}
>  
>  		/* gem_storedw_batches_loop.c is a bit overenthusiastic with
>  		 * creating new batchbuffers - with buffer reuse disabled, the
>  		 * support code will do that for us. */
> -		if (batch->gen >= 8) {
> -			BEGIN_BATCH(4, 1);
> -			OUT_BATCH(GFX_OP_PIPE_CONTROL + 1);
> -			OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
> -			OUT_RELOC_FENCED(target_bo,
> -			     I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
> -			     PIPE_CONTROL_GLOBAL_GTT);
> -			OUT_BATCH(val); /* write data */
> -			ADVANCE_BATCH();
> -
> -		} else if (batch->gen >= 6) {
> +		if (ibb->gen >= 8) {
> +			intel_bb_out(ibb, GFX_OP_PIPE_CONTROL + 1);
> +			intel_bb_out(ibb, PIPE_CONTROL_WRITE_IMMEDIATE);
> +			intel_bb_emit_reloc_fenced(ibb, target_buf->handle,
> +						   I915_GEM_DOMAIN_INSTRUCTION,
> +						   I915_GEM_DOMAIN_INSTRUCTION,
> +						   PIPE_CONTROL_GLOBAL_GTT,
> +						   target_buf->addr.offset);
> +			intel_bb_out(ibb, val); /* write data */
> +		} else if (ibb->gen >= 6) {
>  			/* work-around hw issue, see intel_emit_post_sync_nonzero_flush
>  			 * in mesa sources. */
> -			BEGIN_BATCH(4, 1);
> -			OUT_BATCH(GFX_OP_PIPE_CONTROL);
> -			OUT_BATCH(PIPE_CONTROL_CS_STALL |
> -			     PIPE_CONTROL_STALL_AT_SCOREBOARD);
> -			OUT_BATCH(0); /* address */
> -			OUT_BATCH(0); /* write data */
> -			ADVANCE_BATCH();
> -
> -			BEGIN_BATCH(4, 1);
> -			OUT_BATCH(GFX_OP_PIPE_CONTROL);
> -			OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
> -			OUT_RELOC(target_bo,
> -			     I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 
> -			     PIPE_CONTROL_GLOBAL_GTT);
> -			OUT_BATCH(val); /* write data */
> -			ADVANCE_BATCH();
> -		} else if (batch->gen >= 4) {
> -			BEGIN_BATCH(4, 1);
> -			OUT_BATCH(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_WC_FLUSH |
> -					PIPE_CONTROL_TC_FLUSH |
> -					PIPE_CONTROL_WRITE_IMMEDIATE | 2);
> -			OUT_RELOC(target_bo,
> -				I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
> -				PIPE_CONTROL_GLOBAL_GTT);
> -			OUT_BATCH(val);
> -			OUT_BATCH(0xdeadbeef);
> -			ADVANCE_BATCH();
> +			intel_bb_out(ibb, GFX_OP_PIPE_CONTROL);
> +			intel_bb_out(ibb, PIPE_CONTROL_CS_STALL |
> +				     PIPE_CONTROL_STALL_AT_SCOREBOARD);
> +			intel_bb_out(ibb, 0); /* address */
> +			intel_bb_out(ibb, 0); /* write data */
> +
> +			intel_bb_out(ibb, GFX_OP_PIPE_CONTROL);
> +			intel_bb_out(ibb, PIPE_CONTROL_WRITE_IMMEDIATE);
> +			intel_bb_emit_reloc(ibb, target_buf->handle,
> +					    I915_GEM_DOMAIN_INSTRUCTION,
> +					    I915_GEM_DOMAIN_INSTRUCTION,
> +					    PIPE_CONTROL_GLOBAL_GTT,
> +					    target_buf->addr.offset);
> +			intel_bb_out(ibb, val); /* write data */
> +		} else if (ibb->gen >= 4) {
> +			intel_bb_out(ibb, GFX_OP_PIPE_CONTROL |
> +				     PIPE_CONTROL_WC_FLUSH |
> +				     PIPE_CONTROL_TC_FLUSH |
> +				     PIPE_CONTROL_WRITE_IMMEDIATE | 2);
> +			intel_bb_emit_reloc(ibb, target_buf->handle,
> +					    I915_GEM_DOMAIN_INSTRUCTION,
> +					    I915_GEM_DOMAIN_INSTRUCTION,
> +					    PIPE_CONTROL_GLOBAL_GTT,
> +					    target_buf->addr.offset);
> +			intel_bb_out(ibb, val);
> +			intel_bb_out(ibb, 0xdeadbeef);
>  		}
>  
> -		intel_batchbuffer_flush_on_ring(batch, 0);
> +		intel_bb_flush(ibb, ibb->ctx, 0);
> +		intel_bb_sync(ibb);

That's not needed. 
>  
> -		drm_intel_bo_map(target_bo, 1);
> +		intel_buf_cpu_map(target_buf, 0);

Original code maps for write, leave it untouched. We don't want to change
test behavior. 

>  
> -		buf = target_bo->virtual;
> +		buf = target_buf->ptr;
>  		igt_assert(buf[0] == val);
>  
> -		drm_intel_bo_unmap(target_bo);
> +		intel_buf_unmap(target_buf);
>  		/* Make doublesure that this buffer won't get reused. */
> -		drm_intel_bo_disable_reuse(target_bo);
> -		drm_intel_bo_unreference(target_bo);
> +		intel_bb_reset(ibb, true);
>  
> +		intel_buf_destroy(target_buf);
>  		val++;
>  	}
>  }
>  
>  int fd;
> +uint32_t devid;
>  
>  igt_main
>  {
> @@ -167,20 +171,12 @@ igt_main
>  		gem_require_blitter(fd);
>  
>  		devid = intel_get_drm_devid(fd);
> -
> -		bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
> -		igt_assert(bufmgr);
> +		bops = buf_ops_create(fd);
>  
>  		igt_skip_on(IS_GEN2(devid) || IS_GEN3(devid));
>  		igt_skip_on(devid == PCI_CHIP_I965_G); /* has totally broken pipe control */
>  
> -		/* IMPORTANT: No call to
> -		 * drm_intel_bufmgr_gem_enable_reuse(bufmgr);
> -		 * here because we wan't to have fresh buffers (to trash the tlb)
> -		 * every time! */
> -
> -		batch = intel_batchbuffer_alloc(bufmgr, devid);
> -		igt_assert(batch);
> +		ibb = intel_bb_create(fd, 4096);

I would at least reword this comment. It is helpful to understand idea of the test.

--
Zbigniew

>  	}
>  
>  	igt_subtest("fresh-buffer")
> @@ -190,9 +186,8 @@ igt_main
>  		store_pipe_control_loop(true, 2);
>  
>  	igt_fixture {
> -		intel_batchbuffer_free(batch);
> -		drm_intel_bufmgr_destroy(bufmgr);
> -
> +		intel_bb_destroy(ibb);
> +		buf_ops_destroy(bops);
>  		close(fd);
>  	}
>  }
> -- 
> 2.20.1
> 
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Re: [igt-dev] [PATCH i-g-t v4 07/25] i915/gem_pread_after_blit.c: Remove libdrm dependency

[Zbigniew Kempczyński]

On Tue, Sep 22, 2020 at 01:52:11PM +0200, Dominik Grzegorzek wrote:
> Use intel_bb / intel_buf to remove libdrm dependency.
> 
> Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>  tests/i915/gem_pread_after_blit.c | 135 +++++++++++++++---------------
>  1 file changed, 68 insertions(+), 67 deletions(-)
> 
> diff --git a/tests/i915/gem_pread_after_blit.c b/tests/i915/gem_pread_after_blit.c
> index 81454c93..5919011c 100644
> --- a/tests/i915/gem_pread_after_blit.c
> +++ b/tests/i915/gem_pread_after_blit.c
> @@ -50,70 +50,69 @@
>  
>  IGT_TEST_DESCRIPTION("Test pread behavior when getting values out of"
>  		     " just-drawn-to buffers.");
> -
> -static drm_intel_bufmgr *bufmgr;
> -struct intel_batchbuffer *batch;
> +static struct intel_bb *ibb;
>  static const int width = 512, height = 512;
>  static const int size = 1024 * 1024;
>  
>  #define PAGE_SIZE 4096
>  
> -static drm_intel_bo *
> -create_bo(uint32_t val)
> +static struct intel_buf *
> +create_bo(struct buf_ops *bops, uint32_t val)
>  {
> -	drm_intel_bo *bo;
> +	struct intel_buf *buf;
>  	uint32_t *vaddr;
>  	int i;
>  
> -	bo = drm_intel_bo_alloc(bufmgr, "src bo", size, 4096);
> +	buf = intel_buf_create(bops, width, height, 32, 0, I915_TILING_NONE,
> +			       I915_COMPRESSION_NONE);
>  
>  	/* Fill the BO with dwords starting at start_val */
> -	drm_intel_bo_map(bo, 1);
> -	vaddr = bo->virtual;
> +	intel_buf_cpu_map(buf, 1);

We'll likely touch bug on !llc but keep cpu mapping there.

> +	vaddr = buf->ptr;
>  
>  	for (i = 0; i < 1024 * 1024 / 4; i++)
>  		vaddr[i] = val++;
>  
> -	drm_intel_bo_unmap(bo);
> +	intel_buf_unmap(buf);
>  
> -	return bo;
> +	return buf;
>  }
>  
>  static void
> -verify_large_read(drm_intel_bo *bo, uint32_t val)
> +verify_large_read(int fd, struct intel_buf *buf, uint32_t val)
>  {
> -	uint32_t buf[size / 4];
> +	uint32_t tmp[size / 4];
>  	int i;
>  
> -	drm_intel_bo_get_subdata(bo, 0, size, buf);
> +	gem_read(fd, buf->handle, 0, tmp, size);
>  
>  	for (i = 0; i < size / 4; i++) {
> -		igt_assert_f(buf[i] == val,
> +		igt_assert_f(tmp[i] == val,
>  			     "Unexpected value 0x%08x instead of "
>  			     "0x%08x at offset 0x%08x (%p)\n",
> -			     buf[i], val, i * 4, buf);
> +			     tmp[i], val, i * 4, tmp);
>  		val++;
>  	}
>  }
>  
>  /** This reads at the size that Mesa usees for software fallbacks. */
>  static void
> -verify_small_read(drm_intel_bo *bo, uint32_t val)
> +verify_small_read(int fd, struct intel_buf *buf, uint32_t val)
>  {
> -	uint32_t buf[4096 / 4];
> +	uint32_t tmp[4096 / 4];
>  	int offset, i;
>  
>  	for (i = 0; i < 4096 / 4; i++)
> -		buf[i] = 0x00c0ffee;
> +		tmp[i] = 0x00c0ffee;
>  
>  	for (offset = 0; offset < size; offset += PAGE_SIZE) {
> -		drm_intel_bo_get_subdata(bo, offset, PAGE_SIZE, buf);
> +		gem_read(fd, buf->handle, offset, tmp, PAGE_SIZE);
>  
>  		for (i = 0; i < PAGE_SIZE; i += 4) {
> -			igt_assert_f(buf[i / 4] == val,
> +			igt_assert_f(tmp[i / 4] == val,
>  				     "Unexpected value 0x%08x instead of "
>  				     "0x%08x at offset 0x%08x\n",
> -				     buf[i / 4], val, i * 4);
> +				     tmp[i / 4], val, i * 4);
>  			val++;
>  		}
>  	}
> @@ -128,16 +127,17 @@ static igt_hang_t no_hang(int fd)
>  
>  static igt_hang_t bcs_hang(int fd)
>  {
> -	return igt_hang_ring(fd, batch->gen >= 6 ? I915_EXEC_BLT : I915_EXEC_DEFAULT);
> +	return igt_hang_ring(fd, ibb->gen >= 6 ? I915_EXEC_BLT : I915_EXEC_DEFAULT);
>  }
>  
> -static void do_test(int fd, int cache_level,
> -		    drm_intel_bo *src[2],
> +static void do_test(struct buf_ops *bops, int cache_level,
> +		    struct intel_buf *src[2],
>  		    const uint32_t start[2],
> -		    drm_intel_bo *tmp[2],
> +		    struct intel_buf *tmp[2],
>  		    int loop, do_hang do_hang_func)
>  {
>  	igt_hang_t hang;
> +	int fd = buf_ops_get_fd(bops);
>  
>  	if (cache_level != -1) {
>  		gem_set_caching(fd, tmp[0]->handle, cache_level);
> @@ -146,55 +146,52 @@ static void do_test(int fd, int cache_level,
>  
>  	do {
>  		/* First, do a full-buffer read after blitting */
> -		intel_copy_bo(batch, tmp[0], src[0], width*height*4);
> +		intel_bb_copy_intel_buf(ibb, tmp[0], src[0], size);

Much cleaner.

Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

>  		hang = do_hang_func(fd);
> -		verify_large_read(tmp[0], start[0]);
> +		verify_large_read(fd, tmp[0], start[0]);
>  		igt_post_hang_ring(fd, hang);
> -		intel_copy_bo(batch, tmp[0], src[1], width*height*4);
> +		intel_bb_copy_intel_buf(ibb, tmp[0], src[1], size);
>  		hang = do_hang_func(fd);
> -		verify_large_read(tmp[0], start[1]);
> +		verify_large_read(fd, tmp[0], start[1]);
>  		igt_post_hang_ring(fd, hang);
>  
> -		intel_copy_bo(batch, tmp[0], src[0], width*height*4);
> +		intel_bb_copy_intel_buf(ibb, tmp[0], src[0], size);
>  		hang = do_hang_func(fd);
> -		verify_small_read(tmp[0], start[0]);
> +		verify_small_read(fd, tmp[0], start[0]);
>  		igt_post_hang_ring(fd, hang);
> -		intel_copy_bo(batch, tmp[0], src[1], width*height*4);
> +		intel_bb_copy_intel_buf(ibb, tmp[0], src[1], size);
>  		hang = do_hang_func(fd);
> -		verify_small_read(tmp[0], start[1]);
> +		verify_small_read(fd, tmp[0], start[1]);
>  		igt_post_hang_ring(fd, hang);
>  
> -		intel_copy_bo(batch, tmp[0], src[0], width*height*4);
> +		intel_bb_copy_intel_buf(ibb, tmp[0], src[0], size);
>  		hang = do_hang_func(fd);
> -		verify_large_read(tmp[0], start[0]);
> +		verify_large_read(fd, tmp[0], start[0]);
>  		igt_post_hang_ring(fd, hang);
>  
> -		intel_copy_bo(batch, tmp[0], src[0], width*height*4);
> -		intel_copy_bo(batch, tmp[1], src[1], width*height*4);
> +		intel_bb_copy_intel_buf(ibb, tmp[0], src[0], size);
> +		intel_bb_copy_intel_buf(ibb, tmp[1], src[1], size);
>  		hang = do_hang_func(fd);
> -		verify_large_read(tmp[0], start[0]);
> -		verify_large_read(tmp[1], start[1]);
> +		verify_large_read(fd, tmp[0], start[0]);
> +		verify_large_read(fd, tmp[1], start[1]);
>  		igt_post_hang_ring(fd, hang);
>  
> -		intel_copy_bo(batch, tmp[0], src[0], width*height*4);
> -		intel_copy_bo(batch, tmp[1], src[1], width*height*4);
> +		intel_bb_copy_intel_buf(ibb, tmp[0], src[0], size);
> +		intel_bb_copy_intel_buf(ibb, tmp[1], src[1], size);
>  		hang = do_hang_func(fd);
> -		verify_large_read(tmp[1], start[1]);
> -		verify_large_read(tmp[0], start[0]);
> +		verify_large_read(fd, tmp[1], start[1]);
> +		verify_large_read(fd, tmp[0], start[0]);
>  		igt_post_hang_ring(fd, hang);
>  
> -		intel_copy_bo(batch, tmp[1], src[0], width*height*4);
> -		intel_copy_bo(batch, tmp[0], src[1], width*height*4);
> +		intel_bb_copy_intel_buf(ibb, tmp[1], src[0], size);
> +		intel_bb_copy_intel_buf(ibb, tmp[0], src[1], size);
>  		hang = do_hang_func(fd);
> -		verify_large_read(tmp[0], start[1]);
> -		verify_large_read(tmp[1], start[0]);
> +		verify_large_read(fd, tmp[0], start[1]);
> +		verify_large_read(fd, tmp[1], start[0]);
>  		igt_post_hang_ring(fd, hang);
>  	} while (--loop);
>  }
>  
> -drm_intel_bo *src[2], *dst[2];
> -int fd;
> -
>  igt_main
>  {
>  	const uint32_t start[2] = {0, 1024 * 1024 / 4};
> @@ -208,43 +205,47 @@ igt_main
>  		{ "display", 2 },
>  		{ NULL, -1 },
>  	}, *t;
> +	struct intel_buf *src[2], *dst[2];
> +	struct buf_ops *bops;
> +	int fd;
>  
>  	igt_fixture {
>  		fd = drm_open_driver(DRIVER_INTEL);
>  		igt_require_gem(fd);
>  
> -		bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
> -		drm_intel_bufmgr_gem_enable_reuse(bufmgr);
> -		batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
> +		bops = buf_ops_create(fd);
> +		ibb = intel_bb_create(fd, 4096);
>  
> -		src[0] = create_bo(start[0]);
> -		src[1] = create_bo(start[1]);
> +		src[0] = create_bo(bops, start[0]);
> +		src[1] = create_bo(bops, start[1]);
>  
> -		dst[0] = drm_intel_bo_alloc(bufmgr, "dst bo", size, 4096);
> -		dst[1] = drm_intel_bo_alloc(bufmgr, "dst bo", size, 4096);
> +		dst[0] = intel_buf_create(bops, width, height, 32, 4096,
> +					  I915_TILING_NONE, I915_COMPRESSION_NONE);
> +		dst[1] = intel_buf_create(bops, width, height, 32, 4096,
> +					  I915_TILING_NONE, I915_COMPRESSION_NONE);
>  	}
>  
>  	for (t = tests; t->name; t++) {
>  		igt_subtest_f("%s-normal", t->name)
> -			do_test(fd, t->cache, src, start, dst, 1, no_hang);
> +			do_test(bops, t->cache, src, start, dst, 1, no_hang);
>  
>  		igt_fork_signal_helper();
>  		igt_subtest_f("%s-interruptible", t->name)
> -			do_test(fd, t->cache, src, start, dst, 100, no_hang);
> +			do_test(bops, t->cache, src, start, dst, 100, no_hang);
>  		igt_stop_signal_helper();
>  
>  		igt_subtest_f("%s-hang", t->name)
> -			do_test(fd, t->cache, src, start, dst, 1, bcs_hang);
> +			do_test(bops, t->cache, src, start, dst, 1, bcs_hang);
>  	}
>  
>  	igt_fixture {
> -		drm_intel_bo_unreference(src[0]);
> -		drm_intel_bo_unreference(src[1]);
> -		drm_intel_bo_unreference(dst[0]);
> -		drm_intel_bo_unreference(dst[1]);
> +		intel_buf_destroy(src[0]);
> +		intel_buf_destroy(src[1]);
> +		intel_buf_destroy(dst[0]);
> +		intel_buf_destroy(dst[1]);
>  
> -		intel_batchbuffer_free(batch);
> -		drm_intel_bufmgr_destroy(bufmgr);
> +		intel_bb_destroy(ibb);
> +		buf_ops_destroy(bops);
>  	}
>  
>  	igt_fixture
> -- 
> 2.20.1
> 
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Re: [igt-dev] [PATCH i-g-t v4 06/25] i915/gem_pipe_control_store_loop.c: Remove libdrm dependency

[Grzegorzek, Dominik]

On Tue, 2020-09-22 at 15:51 +0200, Zbigniew Kempczyński wrote:
> On Tue, Sep 22, 2020 at 01:52:10PM +0200, Dominik Grzegorzek wrote:
> > Use intel_bb / intel_buf to remove libdrm dependency.
> > 
> > Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
> > Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > ---
> >  tests/i915/gem_pipe_control_store_loop.c | 143 +++++++++++------
> > ------
> >  1 file changed, 69 insertions(+), 74 deletions(-)
> > 
> > diff --git a/tests/i915/gem_pipe_control_store_loop.c
> > b/tests/i915/gem_pipe_control_store_loop.c
> > index 863a4871..d508ea29 100644
> > --- a/tests/i915/gem_pipe_control_store_loop.c
> > +++ b/tests/i915/gem_pipe_control_store_loop.c
> > @@ -43,13 +43,11 @@
> >  #include "drm.h"
> >  #include "i915/gem.h"
> >  #include "igt.h"
> > -#include "intel_bufmgr.h"
> >  
> >  IGT_TEST_DESCRIPTION("Test (TLB-)Coherency of pipe_control QW
> > writes.");
> >  
> > -static drm_intel_bufmgr *bufmgr;
> > -struct intel_batchbuffer *batch;
> > -uint32_t devid;
> > +static struct buf_ops *bops;
> > +static struct intel_bb *ibb;
> >  
> >  #define GFX_OP_PIPE_CONTROL	((0x3<<29)|(0x3<<27)|(0x2<<24)|
> > 2)
> >  #define   PIPE_CONTROL_WRITE_IMMEDIATE	(1<<14)
> > @@ -68,96 +66,102 @@ store_pipe_control_loop(bool preuse_buffer,
> > int timeout)
> >  {
> >  	int val = 0;
> >  	uint32_t *buf;
> > -	drm_intel_bo *target_bo;
> > +	struct intel_buf *target_buf;
> >  
> >  	igt_until_timeout(timeout) {
> >  		/* we want to check tlb consistency of the pipe_control
> > target,
> >  		 * so get a new buffer every time around */
> > -		target_bo = drm_intel_bo_alloc(bufmgr, "target bo",
> > 4096, 4096);
> > -		igt_assert(target_bo);
> > +		target_buf = intel_buf_create(bops, 32, 32, 32, 4096,
> > +					      I915_TILING_NONE,
> > +					      I915_COMPRESSION_NONE);
> > +		intel_bb_add_intel_buf(ibb, target_buf, true);
> >  
> >  		if (preuse_buffer) {
> > -			COLOR_BLIT_COPY_BATCH_START(0);
> > -			OUT_BATCH((3 << 24) | (0xf0 << 16) | 64);
> > -			OUT_BATCH(0);
> > -			OUT_BATCH(1 << 16 | 1);
> > +			intel_bb_out(ibb, XY_COLOR_BLT_CMD_NOLEN |
> > +				     COLOR_BLT_WRITE_ALPHA |
> > +				     XY_COLOR_BLT_WRITE_RGB |
> > +				     (4 + (ibb->gen >= 8)));
> > +
> > +			intel_bb_out(ibb, (3 << 24) | (0xf0 << 16) |
> > 64);
> > +			intel_bb_out(ibb, 0);
> > +			intel_bb_out(ibb, 1 << 16 | 1);
> >  
> >  			/*
> >  			 * IMPORTANT: We need to preuse the buffer in a
> >  			 * different domain than what the pipe control
> > write
> >  			 * (and kernel wa) uses!
> >  			 */
> > -			OUT_RELOC_FENCED(target_bo,
> > -			     I915_GEM_DOMAIN_RENDER,
> > I915_GEM_DOMAIN_RENDER,
> > -			     0);
> > -			OUT_BATCH(0xdeadbeef);
> > -			ADVANCE_BATCH();
> > +			intel_bb_emit_reloc_fenced(ibb, target_buf-
> > >handle,
> > +						   I915_GEM_DOMAIN_REND
> > ER,
> > +						   I915_GEM_DOMAIN_REND
> > ER,
> > +						   0, target_buf-
> > >addr.offset);
> > +			intel_bb_out(ibb, 0xdeadbeef);
> >  
> > -			intel_batchbuffer_flush(batch);
> > +			intel_bb_flush_blit(ibb);
> >  		}
> >  
> >  		/* gem_storedw_batches_loop.c is a bit overenthusiastic
> > with
> >  		 * creating new batchbuffers - with buffer reuse
> > disabled, the
> >  		 * support code will do that for us. */
> > -		if (batch->gen >= 8) {
> > -			BEGIN_BATCH(4, 1);
> > -			OUT_BATCH(GFX_OP_PIPE_CONTROL + 1);
> > -			OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
> > -			OUT_RELOC_FENCED(target_bo,
> > -			     I915_GEM_DOMAIN_INSTRUCTION,
> > I915_GEM_DOMAIN_INSTRUCTION,
> > -			     PIPE_CONTROL_GLOBAL_GTT);
> > -			OUT_BATCH(val); /* write data */
> > -			ADVANCE_BATCH();
> > -
> > -		} else if (batch->gen >= 6) {
> > +		if (ibb->gen >= 8) {
> > +			intel_bb_out(ibb, GFX_OP_PIPE_CONTROL + 1);
> > +			intel_bb_out(ibb,
> > PIPE_CONTROL_WRITE_IMMEDIATE);
> > +			intel_bb_emit_reloc_fenced(ibb, target_buf-
> > >handle,
> > +						   I915_GEM_DOMAIN_INST
> > RUCTION,
> > +						   I915_GEM_DOMAIN_INST
> > RUCTION,
> > +						   PIPE_CONTROL_GLOBAL_
> > GTT,
> > +						   target_buf-
> > >addr.offset);
> > +			intel_bb_out(ibb, val); /* write data */
> > +		} else if (ibb->gen >= 6) {
> >  			/* work-around hw issue, see
> > intel_emit_post_sync_nonzero_flush
> >  			 * in mesa sources. */
> > -			BEGIN_BATCH(4, 1);
> > -			OUT_BATCH(GFX_OP_PIPE_CONTROL);
> > -			OUT_BATCH(PIPE_CONTROL_CS_STALL |
> > -			     PIPE_CONTROL_STALL_AT_SCOREBOARD);
> > -			OUT_BATCH(0); /* address */
> > -			OUT_BATCH(0); /* write data */
> > -			ADVANCE_BATCH();
> > -
> > -			BEGIN_BATCH(4, 1);
> > -			OUT_BATCH(GFX_OP_PIPE_CONTROL);
> > -			OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
> > -			OUT_RELOC(target_bo,
> > -			     I915_GEM_DOMAIN_INSTRUCTION,
> > I915_GEM_DOMAIN_INSTRUCTION, 
> > -			     PIPE_CONTROL_GLOBAL_GTT);
> > -			OUT_BATCH(val); /* write data */
> > -			ADVANCE_BATCH();
> > -		} else if (batch->gen >= 4) {
> > -			BEGIN_BATCH(4, 1);
> > -			OUT_BATCH(GFX_OP_PIPE_CONTROL |
> > PIPE_CONTROL_WC_FLUSH |
> > -					PIPE_CONTROL_TC_FLUSH |
> > -					PIPE_CONTROL_WRITE_IMMEDIATE |
> > 2);
> > -			OUT_RELOC(target_bo,
> > -				I915_GEM_DOMAIN_INSTRUCTION,
> > I915_GEM_DOMAIN_INSTRUCTION,
> > -				PIPE_CONTROL_GLOBAL_GTT);
> > -			OUT_BATCH(val);
> > -			OUT_BATCH(0xdeadbeef);
> > -			ADVANCE_BATCH();
> > +			intel_bb_out(ibb, GFX_OP_PIPE_CONTROL);
> > +			intel_bb_out(ibb, PIPE_CONTROL_CS_STALL |
> > +				     PIPE_CONTROL_STALL_AT_SCOREBOARD);
> > +			intel_bb_out(ibb, 0); /* address */
> > +			intel_bb_out(ibb, 0); /* write data */
> > +
> > +			intel_bb_out(ibb, GFX_OP_PIPE_CONTROL);
> > +			intel_bb_out(ibb,
> > PIPE_CONTROL_WRITE_IMMEDIATE);
> > +			intel_bb_emit_reloc(ibb, target_buf->handle,
> > +					    I915_GEM_DOMAIN_INSTRUCTION
> > ,
> > +					    I915_GEM_DOMAIN_INSTRUCTION
> > ,
> > +					    PIPE_CONTROL_GLOBAL_GTT,
> > +					    target_buf->addr.offset);
> > +			intel_bb_out(ibb, val); /* write data */
> > +		} else if (ibb->gen >= 4) {
> > +			intel_bb_out(ibb, GFX_OP_PIPE_CONTROL |
> > +				     PIPE_CONTROL_WC_FLUSH |
> > +				     PIPE_CONTROL_TC_FLUSH |
> > +				     PIPE_CONTROL_WRITE_IMMEDIATE | 2);
> > +			intel_bb_emit_reloc(ibb, target_buf->handle,
> > +					    I915_GEM_DOMAIN_INSTRUCTION
> > ,
> > +					    I915_GEM_DOMAIN_INSTRUCTION
> > ,
> > +					    PIPE_CONTROL_GLOBAL_GTT,
> > +					    target_buf->addr.offset);
> > +			intel_bb_out(ibb, val);
> > +			intel_bb_out(ibb, 0xdeadbeef);
> >  		}
> >  
> > -		intel_batchbuffer_flush_on_ring(batch, 0);
> > +		intel_bb_flush(ibb, ibb->ctx, 0);
> > +		intel_bb_sync(ibb);
> 
> That's not needed. 
> >  
> > -		drm_intel_bo_map(target_bo, 1);
> > +		intel_buf_cpu_map(target_buf, 0);
> 
> Original code maps for write, leave it untouched. We don't want to
> change
> test behavior. 
> 
> >  
> > -		buf = target_bo->virtual;
> > +		buf = target_buf->ptr;
> >  		igt_assert(buf[0] == val);
> >  
> > -		drm_intel_bo_unmap(target_bo);
> > +		intel_buf_unmap(target_buf);
> >  		/* Make doublesure that this buffer won't get reused.
> > */
> > -		drm_intel_bo_disable_reuse(target_bo);
> > -		drm_intel_bo_unreference(target_bo);
> > +		intel_bb_reset(ibb, true);
> >  
> > +		intel_buf_destroy(target_buf);
> >  		val++;
> >  	}
> >  }
> >  
> >  int fd;
> > +uint32_t devid;
> >  
> >  igt_main
> >  {
> > @@ -167,20 +171,12 @@ igt_main
> >  		gem_require_blitter(fd);
> >  
> >  		devid = intel_get_drm_devid(fd);
> > -
> > -		bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
> > -		igt_assert(bufmgr);
> > +		bops = buf_ops_create(fd);
> >  
> >  		igt_skip_on(IS_GEN2(devid) || IS_GEN3(devid));
> >  		igt_skip_on(devid == PCI_CHIP_I965_G); /* has totally
> > broken pipe control */
> >  
> > -		/* IMPORTANT: No call to
> > -		 * drm_intel_bufmgr_gem_enable_reuse(bufmgr);
> > -		 * here because we wan't to have fresh buffers (to
> > trash the tlb)
> > -		 * every time! */
> > -
> > -		batch = intel_batchbuffer_alloc(bufmgr, devid);
> > -		igt_assert(batch);
> > +		ibb = intel_bb_create(fd, 4096);
> 
> I would at least reword this comment. It is helpful to understand
> idea of the test.
> --
> Zbigniew

Actually, there is already similar comment above. 
 "/* we want to check tlb consistency of the pipe_control target,
  /* so get a new buffer every time around */

Dominik

> 
> >  	}
> >  
> >  	igt_subtest("fresh-buffer")
> > @@ -190,9 +186,8 @@ igt_main
> >  		store_pipe_control_loop(true, 2);
> >  
> >  	igt_fixture {
> > -		intel_batchbuffer_free(batch);
> > -		drm_intel_bufmgr_destroy(bufmgr);
> > -
> > +		intel_bb_destroy(ibb);
> > +		buf_ops_destroy(bops);
> >  		close(fd);
> >  	}
> >  }
> > -- 
> > 2.20.1
> > 
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Re: [igt-dev] [PATCH i-g-t v4 06/25] i915/gem_pipe_control_store_loop.c: Remove libdrm dependency

[Zbigniew Kempczyński]

On Wed, Sep 23, 2020 at 09:19:55AM +0200, Grzegorzek, Dominik wrote:
> On Tue, 2020-09-22 at 15:51 +0200, Zbigniew Kempczyński wrote:
> > On Tue, Sep 22, 2020 at 01:52:10PM +0200, Dominik Grzegorzek wrote:
> > > Use intel_bb / intel_buf to remove libdrm dependency.
> > > 
> > > Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
> > > Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> > > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > > ---
> > >  tests/i915/gem_pipe_control_store_loop.c | 143 +++++++++++------
> > > ------
> > >  1 file changed, 69 insertions(+), 74 deletions(-)
> > > 
> > > diff --git a/tests/i915/gem_pipe_control_store_loop.c
> > > b/tests/i915/gem_pipe_control_store_loop.c
> > > index 863a4871..d508ea29 100644
> > > --- a/tests/i915/gem_pipe_control_store_loop.c
> > > +++ b/tests/i915/gem_pipe_control_store_loop.c
> > > @@ -43,13 +43,11 @@
> > >  #include "drm.h"
> > >  #include "i915/gem.h"
> > >  #include "igt.h"
> > > -#include "intel_bufmgr.h"
> > >  
> > >  IGT_TEST_DESCRIPTION("Test (TLB-)Coherency of pipe_control QW
> > > writes.");
> > >  
> > > -static drm_intel_bufmgr *bufmgr;
> > > -struct intel_batchbuffer *batch;
> > > -uint32_t devid;
> > > +static struct buf_ops *bops;
> > > +static struct intel_bb *ibb;
> > >  
> > >  #define GFX_OP_PIPE_CONTROL	((0x3<<29)|(0x3<<27)|(0x2<<24)|
> > > 2)
> > >  #define   PIPE_CONTROL_WRITE_IMMEDIATE	(1<<14)
> > > @@ -68,96 +66,102 @@ store_pipe_control_loop(bool preuse_buffer,
> > > int timeout)
> > >  {
> > >  	int val = 0;
> > >  	uint32_t *buf;
> > > -	drm_intel_bo *target_bo;
> > > +	struct intel_buf *target_buf;
> > >  
> > >  	igt_until_timeout(timeout) {
> > >  		/* we want to check tlb consistency of the pipe_control
> > > target,
> > >  		 * so get a new buffer every time around */
> > > -		target_bo = drm_intel_bo_alloc(bufmgr, "target bo",
> > > 4096, 4096);
> > > -		igt_assert(target_bo);
> > > +		target_buf = intel_buf_create(bops, 32, 32, 32, 4096,
> > > +					      I915_TILING_NONE,
> > > +					      I915_COMPRESSION_NONE);
> > > +		intel_bb_add_intel_buf(ibb, target_buf, true);
> > >  
> > >  		if (preuse_buffer) {
> > > -			COLOR_BLIT_COPY_BATCH_START(0);
> > > -			OUT_BATCH((3 << 24) | (0xf0 << 16) | 64);
> > > -			OUT_BATCH(0);
> > > -			OUT_BATCH(1 << 16 | 1);
> > > +			intel_bb_out(ibb, XY_COLOR_BLT_CMD_NOLEN |
> > > +				     COLOR_BLT_WRITE_ALPHA |
> > > +				     XY_COLOR_BLT_WRITE_RGB |
> > > +				     (4 + (ibb->gen >= 8)));
> > > +
> > > +			intel_bb_out(ibb, (3 << 24) | (0xf0 << 16) |
> > > 64);
> > > +			intel_bb_out(ibb, 0);
> > > +			intel_bb_out(ibb, 1 << 16 | 1);
> > >  
> > >  			/*
> > >  			 * IMPORTANT: We need to preuse the buffer in a
> > >  			 * different domain than what the pipe control
> > > write
> > >  			 * (and kernel wa) uses!
> > >  			 */
> > > -			OUT_RELOC_FENCED(target_bo,
> > > -			     I915_GEM_DOMAIN_RENDER,
> > > I915_GEM_DOMAIN_RENDER,
> > > -			     0);
> > > -			OUT_BATCH(0xdeadbeef);
> > > -			ADVANCE_BATCH();
> > > +			intel_bb_emit_reloc_fenced(ibb, target_buf-
> > > >handle,
> > > +						   I915_GEM_DOMAIN_REND
> > > ER,
> > > +						   I915_GEM_DOMAIN_REND
> > > ER,
> > > +						   0, target_buf-
> > > >addr.offset);
> > > +			intel_bb_out(ibb, 0xdeadbeef);
> > >  
> > > -			intel_batchbuffer_flush(batch);
> > > +			intel_bb_flush_blit(ibb);
> > >  		}
> > >  
> > >  		/* gem_storedw_batches_loop.c is a bit overenthusiastic
> > > with
> > >  		 * creating new batchbuffers - with buffer reuse
> > > disabled, the
> > >  		 * support code will do that for us. */
> > > -		if (batch->gen >= 8) {
> > > -			BEGIN_BATCH(4, 1);
> > > -			OUT_BATCH(GFX_OP_PIPE_CONTROL + 1);
> > > -			OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
> > > -			OUT_RELOC_FENCED(target_bo,
> > > -			     I915_GEM_DOMAIN_INSTRUCTION,
> > > I915_GEM_DOMAIN_INSTRUCTION,
> > > -			     PIPE_CONTROL_GLOBAL_GTT);
> > > -			OUT_BATCH(val); /* write data */
> > > -			ADVANCE_BATCH();
> > > -
> > > -		} else if (batch->gen >= 6) {
> > > +		if (ibb->gen >= 8) {
> > > +			intel_bb_out(ibb, GFX_OP_PIPE_CONTROL + 1);
> > > +			intel_bb_out(ibb,
> > > PIPE_CONTROL_WRITE_IMMEDIATE);
> > > +			intel_bb_emit_reloc_fenced(ibb, target_buf-
> > > >handle,
> > > +						   I915_GEM_DOMAIN_INST
> > > RUCTION,
> > > +						   I915_GEM_DOMAIN_INST
> > > RUCTION,
> > > +						   PIPE_CONTROL_GLOBAL_
> > > GTT,
> > > +						   target_buf-
> > > >addr.offset);
> > > +			intel_bb_out(ibb, val); /* write data */
> > > +		} else if (ibb->gen >= 6) {
> > >  			/* work-around hw issue, see
> > > intel_emit_post_sync_nonzero_flush
> > >  			 * in mesa sources. */
> > > -			BEGIN_BATCH(4, 1);
> > > -			OUT_BATCH(GFX_OP_PIPE_CONTROL);
> > > -			OUT_BATCH(PIPE_CONTROL_CS_STALL |
> > > -			     PIPE_CONTROL_STALL_AT_SCOREBOARD);
> > > -			OUT_BATCH(0); /* address */
> > > -			OUT_BATCH(0); /* write data */
> > > -			ADVANCE_BATCH();
> > > -
> > > -			BEGIN_BATCH(4, 1);
> > > -			OUT_BATCH(GFX_OP_PIPE_CONTROL);
> > > -			OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
> > > -			OUT_RELOC(target_bo,
> > > -			     I915_GEM_DOMAIN_INSTRUCTION,
> > > I915_GEM_DOMAIN_INSTRUCTION, 
> > > -			     PIPE_CONTROL_GLOBAL_GTT);
> > > -			OUT_BATCH(val); /* write data */
> > > -			ADVANCE_BATCH();
> > > -		} else if (batch->gen >= 4) {
> > > -			BEGIN_BATCH(4, 1);
> > > -			OUT_BATCH(GFX_OP_PIPE_CONTROL |
> > > PIPE_CONTROL_WC_FLUSH |
> > > -					PIPE_CONTROL_TC_FLUSH |
> > > -					PIPE_CONTROL_WRITE_IMMEDIATE |
> > > 2);
> > > -			OUT_RELOC(target_bo,
> > > -				I915_GEM_DOMAIN_INSTRUCTION,
> > > I915_GEM_DOMAIN_INSTRUCTION,
> > > -				PIPE_CONTROL_GLOBAL_GTT);
> > > -			OUT_BATCH(val);
> > > -			OUT_BATCH(0xdeadbeef);
> > > -			ADVANCE_BATCH();
> > > +			intel_bb_out(ibb, GFX_OP_PIPE_CONTROL);
> > > +			intel_bb_out(ibb, PIPE_CONTROL_CS_STALL |
> > > +				     PIPE_CONTROL_STALL_AT_SCOREBOARD);
> > > +			intel_bb_out(ibb, 0); /* address */
> > > +			intel_bb_out(ibb, 0); /* write data */
> > > +
> > > +			intel_bb_out(ibb, GFX_OP_PIPE_CONTROL);
> > > +			intel_bb_out(ibb,
> > > PIPE_CONTROL_WRITE_IMMEDIATE);
> > > +			intel_bb_emit_reloc(ibb, target_buf->handle,
> > > +					    I915_GEM_DOMAIN_INSTRUCTION
> > > ,
> > > +					    I915_GEM_DOMAIN_INSTRUCTION
> > > ,
> > > +					    PIPE_CONTROL_GLOBAL_GTT,
> > > +					    target_buf->addr.offset);
> > > +			intel_bb_out(ibb, val); /* write data */
> > > +		} else if (ibb->gen >= 4) {
> > > +			intel_bb_out(ibb, GFX_OP_PIPE_CONTROL |
> > > +				     PIPE_CONTROL_WC_FLUSH |
> > > +				     PIPE_CONTROL_TC_FLUSH |
> > > +				     PIPE_CONTROL_WRITE_IMMEDIATE | 2);
> > > +			intel_bb_emit_reloc(ibb, target_buf->handle,
> > > +					    I915_GEM_DOMAIN_INSTRUCTION
> > > ,
> > > +					    I915_GEM_DOMAIN_INSTRUCTION
> > > ,
> > > +					    PIPE_CONTROL_GLOBAL_GTT,
> > > +					    target_buf->addr.offset);
> > > +			intel_bb_out(ibb, val);
> > > +			intel_bb_out(ibb, 0xdeadbeef);
> > >  		}
> > >  
> > > -		intel_batchbuffer_flush_on_ring(batch, 0);
> > > +		intel_bb_flush(ibb, ibb->ctx, 0);
> > > +		intel_bb_sync(ibb);
> > 
> > That's not needed. 
> > >  
> > > -		drm_intel_bo_map(target_bo, 1);
> > > +		intel_buf_cpu_map(target_buf, 0);
> > 
> > Original code maps for write, leave it untouched. We don't want to
> > change
> > test behavior. 
> > 
> > >  
> > > -		buf = target_bo->virtual;
> > > +		buf = target_buf->ptr;
> > >  		igt_assert(buf[0] == val);
> > >  
> > > -		drm_intel_bo_unmap(target_bo);
> > > +		intel_buf_unmap(target_buf);
> > >  		/* Make doublesure that this buffer won't get reused.
> > > */
> > > -		drm_intel_bo_disable_reuse(target_bo);
> > > -		drm_intel_bo_unreference(target_bo);
> > > +		intel_bb_reset(ibb, true);
> > >  
> > > +		intel_buf_destroy(target_buf);
> > >  		val++;
> > >  	}
> > >  }
> > >  
> > >  int fd;
> > > +uint32_t devid;
> > >  
> > >  igt_main
> > >  {
> > > @@ -167,20 +171,12 @@ igt_main
> > >  		gem_require_blitter(fd);
> > >  
> > >  		devid = intel_get_drm_devid(fd);
> > > -
> > > -		bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
> > > -		igt_assert(bufmgr);
> > > +		bops = buf_ops_create(fd);
> > >  
> > >  		igt_skip_on(IS_GEN2(devid) || IS_GEN3(devid));
> > >  		igt_skip_on(devid == PCI_CHIP_I965_G); /* has totally
> > > broken pipe control */
> > >  
> > > -		/* IMPORTANT: No call to
> > > -		 * drm_intel_bufmgr_gem_enable_reuse(bufmgr);
> > > -		 * here because we wan't to have fresh buffers (to
> > > trash the tlb)
> > > -		 * every time! */
> > > -
> > > -		batch = intel_batchbuffer_alloc(bufmgr, devid);
> > > -		igt_assert(batch);
> > > +		ibb = intel_bb_create(fd, 4096);
> > 
> > I would at least reword this comment. It is helpful to understand
> > idea of the test.
> > --
> > Zbigniew
> 
> Actually, there is already similar comment above. 
>  "/* we want to check tlb consistency of the pipe_control target,
>   /* so get a new buffer every time around */
> 
> Dominik

Right. So that's ok, R-B.

--
Zbigniew
> 
> > 
> > >  	}
> > >  
> > >  	igt_subtest("fresh-buffer")
> > > @@ -190,9 +186,8 @@ igt_main
> > >  		store_pipe_control_loop(true, 2);
> > >  
> > >  	igt_fixture {
> > > -		intel_batchbuffer_free(batch);
> > > -		drm_intel_bufmgr_destroy(bufmgr);
> > > -
> > > +		intel_bb_destroy(ibb);
> > > +		buf_ops_destroy(bops);
> > >  		close(fd);
> > >  	}
> > >  }
> > > -- 
> > > 2.20.1
> > > 
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Re: [igt-dev] [PATCH i-g-t v4 10/25] i915/gem_unfence_active_buffers.c: Remove librdm dependency

[Zbigniew Kempczyński]

On Tue, Sep 22, 2020 at 01:52:14PM +0200, Dominik Grzegorzek wrote:
> Use intel_bb / intel_buf to remove libdrm dependency.
> 
> Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>  tests/i915/gem_unfence_active_buffers.c | 134 ++++++++++++------------
>  1 file changed, 69 insertions(+), 65 deletions(-)
> 
> diff --git a/tests/i915/gem_unfence_active_buffers.c b/tests/i915/gem_unfence_active_buffers.c
> index 1e69c70d..fc30755f 100644
> --- a/tests/i915/gem_unfence_active_buffers.c
> +++ b/tests/i915/gem_unfence_active_buffers.c
> @@ -51,23 +51,22 @@
>  #include "drm.h"
>  #include "i915/gem.h"
>  #include "igt.h"
> -#include "intel_bufmgr.h"
>  
>  IGT_TEST_DESCRIPTION("Check for use-after-free in the fence stealing code.");
>  
> -static drm_intel_bufmgr *bufmgr;
> -struct intel_batchbuffer *batch;
> -uint32_t devid;
> -
> -#define TEST_SIZE (1024*1024)
> -#define TEST_STRIDE (4*1024)
> +#define WIDTH 1024
> +#define HEIGHT 1024
> +#define TEST_SIZE (WIDTH*HEIGHT)
> +#define TEST_STRIDE (4*WIDTH)
>  
>  uint32_t data[TEST_SIZE/4];
>  
>  igt_simple_main
>  {
>  	int i, ret, fd, num_fences;
> -	drm_intel_bo *busy_bo, *test_bo;
> +	struct intel_bb *ibb;
> +	struct buf_ops *bops;
> +	struct intel_buf *busy_buf, *test_buf;
>  	uint32_t tiling = I915_TILING_X;
>  
>  	for (i = 0; i < 1024*256; i++)
> @@ -77,86 +76,91 @@ igt_simple_main
>  	igt_require_gem(fd);
>  	gem_require_blitter(fd);
>  
> -	bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
> -	drm_intel_bufmgr_gem_enable_reuse(bufmgr);
> -	devid = intel_get_drm_devid(fd);
> -	batch = intel_batchbuffer_alloc(bufmgr, devid);
> +	bops = buf_ops_create(fd);
> +	ibb = intel_bb_create(fd, 4 * 4096);

We likely want to relocate, so I would do:

	ibb = intel_bb_create_with_relocs(fd, 4 * 4096);

We also don't want to serialize so:

	intel_bb_set_fencing(ibb, false);

would help.

>  
>  	igt_info("filling ring\n");
> -	busy_bo = drm_intel_bo_alloc(bufmgr, "busy bo bo", 16*1024*1024, 4096);
> +	busy_buf = intel_buf_create(bops, WIDTH, HEIGHT, 16, 4096, I915_TILING_NONE,
> +				   I915_COMPRESSION_NONE);

WIDTH * HEIGHT * 2B (16bit) != 16 * 1024 * 1024

>  
>  	for (i = 0; i < 250; i++) {
> -		BLIT_COPY_BATCH_START(0);
> -		OUT_BATCH((3 << 24) | /* 32 bits */
> +		intel_bb_blit_start(ibb, 0);
> +		intel_bb_out(ibb, (3 << 24) | /* 32 bits */
>  			  (0xcc << 16) | /* copy ROP */
>  			  2*1024*4);
> -		OUT_BATCH(0 << 16 | 1024);
> -		OUT_BATCH((2048) << 16 | (2048));
> -		OUT_RELOC_FENCED(busy_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
> -		OUT_BATCH(0 << 16 | 0);
> -		OUT_BATCH(2*1024*4);
> -		OUT_RELOC_FENCED(busy_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
> -		ADVANCE_BATCH();
> -
> -		if (batch->gen >= 6) {
> -			BEGIN_BATCH(3, 0);
> -			OUT_BATCH(XY_SETUP_CLIP_BLT_CMD);
> -			OUT_BATCH(0);
> -			OUT_BATCH(0);
> -			ADVANCE_BATCH();
> +		intel_bb_out(ibb, 0 << 16 | 1024);
> +		intel_bb_out(ibb, (2048) << 16 | (2048));
> +		intel_bb_emit_reloc_fenced(ibb, busy_buf->handle,
> +					   I915_GEM_DOMAIN_RENDER,
> +					   I915_GEM_DOMAIN_RENDER, 0, 0x0);

Use busy_buf->addr.offset instead of 0 or INTEL_BUF_INVALID_ADDRESS to make
difference between offset and presumed_offset. Apply also for other relocs. 
	
> +		intel_bb_out(ibb, 0 << 16 | 0);
> +		intel_bb_out(ibb, 2*1024*4);
> +		intel_bb_emit_reloc_fenced(ibb, busy_buf->handle,
> +					   I915_GEM_DOMAIN_RENDER, 0, 0, 0x0);
> +
> +		if (ibb->gen >= 6) {
> +			intel_bb_out(ibb, XY_SETUP_CLIP_BLT_CMD);
> +			intel_bb_out(ibb, 0);
> +			intel_bb_out(ibb, 0);
>  		}
>  	}
> -	intel_batchbuffer_flush(batch);
> +	intel_bb_flush_blit(ibb);
>  
>  	num_fences = gem_available_fences(fd);
>  	igt_info("creating havoc on %i fences\n", num_fences);
>  
>  	for (i = 0; i < num_fences*2; i++) {
> -		test_bo = drm_intel_bo_alloc(bufmgr, "test_bo",
> -					     TEST_SIZE, 4096);
> -		ret = drm_intel_bo_set_tiling(test_bo, &tiling, TEST_STRIDE);
> +		test_buf = intel_buf_create(bops, WIDTH, HEIGHT, 32, 4096,
> +					    tiling, I915_COMPRESSION_NONE);
>  		igt_assert(ret == 0);
>  
> -		drm_intel_bo_disable_reuse(test_bo);
> -
> -		BLIT_COPY_BATCH_START(0);
> -		OUT_BATCH((3 << 24) | /* 32 bits */
> +		intel_bb_blit_start(ibb, 0);
> +		intel_bb_out(ibb, (3 << 24) | /* 32 bits */
>  			  (0xcc << 16) | /* copy ROP */
>  			  TEST_STRIDE);
> -		OUT_BATCH(0 << 16 | 0);
> -		OUT_BATCH((1) << 16 | (1));
> -		OUT_RELOC_FENCED(test_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
> -		OUT_BATCH(0 << 16 | 0);
> -		OUT_BATCH(TEST_STRIDE);
> -		OUT_RELOC_FENCED(test_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
> -		ADVANCE_BATCH();
> -		intel_batchbuffer_flush(batch);
> -		igt_info("test bo offset: %#lx\n", test_bo->offset);
> -
> -		drm_intel_bo_unreference(test_bo);
> +		intel_bb_out(ibb, 0 << 16 | 0);
> +		intel_bb_out(ibb, (1) << 16 | (1));
> +		intel_bb_emit_reloc_fenced(ibb, test_buf->handle,
> +					   I915_GEM_DOMAIN_RENDER,
> +					   I915_GEM_DOMAIN_RENDER, 0, 0x0);
> +		intel_bb_out(ibb, 0 << 16 | 0);
> +		intel_bb_out(ibb, TEST_STRIDE);
> +		intel_bb_emit_reloc_fenced(ibb, test_buf->handle,
> +					   I915_GEM_DOMAIN_RENDER, 0, 0, 0x0);
> +
> +		intel_bb_flush_blit(ibb);
> +		igt_info("test bo offset: %#lx\n",
> +			 intel_bb_get_object_offset(ibb, test_buf->handle));
> +
> +		intel_buf_destroy(test_buf);
> +		intel_bb_reset(ibb, true);
>  	}
>  
>  	/* launch a few batchs to ensure the damaged slab objects get reused. */
>  	for (i = 0; i < 10; i++) {
> -		BLIT_COPY_BATCH_START(0);
> -		OUT_BATCH((3 << 24) | /* 32 bits */
> +		intel_bb_blit_start(ibb, 0);
> +		intel_bb_out(ibb, (3 << 24) | /* 32 bits */
>  			  (0xcc << 16) | /* copy ROP */
>  			  2*1024*4);
> -		OUT_BATCH(0 << 16 | 1024);
> -		OUT_BATCH((1) << 16 | (1));
> -		OUT_RELOC_FENCED(busy_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
> -		OUT_BATCH(0 << 16 | 0);
> -		OUT_BATCH(2*1024*4);
> -		OUT_RELOC_FENCED(busy_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
> -		ADVANCE_BATCH();
> -
> -		if (batch->gen >= 8) {
> -			BEGIN_BATCH(3, 0);
> -			OUT_BATCH(XY_SETUP_CLIP_BLT_CMD);
> -			OUT_BATCH(0);
> -			OUT_BATCH(0);
> -			ADVANCE_BATCH();
> +		intel_bb_out(ibb, 0 << 16 | 1024);
> +		intel_bb_out(ibb, (1) << 16 | (1));
> +		intel_bb_emit_reloc_fenced(ibb, busy_buf->handle,
> +					   I915_GEM_DOMAIN_RENDER,
> +					   I915_GEM_DOMAIN_RENDER, 0, 0x0);
> +		intel_bb_out(ibb, 0 << 16 | 0);
> +		intel_bb_out(ibb, 2*1024*4);
> +		intel_bb_emit_reloc_fenced(ibb, busy_buf->handle,
> +					   I915_GEM_DOMAIN_RENDER, 0, 0, 0x0);
> +
> +		if (ibb->gen >= 8) {
> +			intel_bb_out(ibb, XY_SETUP_CLIP_BLT_CMD);
> +			intel_bb_out(ibb, 0);
> +			intel_bb_out(ibb, 0);
>  		}
>  	}
> -	intel_batchbuffer_flush(batch);
> +	intel_bb_flush_blit(ibb);
> +
> +	intel_buf_destroy(busy_buf);
> +	intel_bb_destroy(ibb);
> +	buf_ops_destroy(bops);
>  }

I have some doubts regarding offsets proposed from kernel with intel_bb
and with libdrm usage so I need to dig it more to explain the difference. 
In case libdrm we got addresses in gtt which adhere. With intel_bb 
I see for 1MB objects objects are aligned to 2MB. 

--
Zbigniew
> -- 
> 2.20.1
> 
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Re: [igt-dev] [PATCH i-g-t v4 11/25] i915/gem_unref_active_buffers.c: Remove libdrm dependency

[Zbigniew Kempczyński]

On Tue, Sep 22, 2020 at 01:52:15PM +0200, Dominik Grzegorzek wrote:
> Use intel_bb / intel_buf to remove libdrm dependency.
> 
> Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>  tests/i915/gem_unref_active_buffers.c | 56 +++++++++++++--------------
>  1 file changed, 27 insertions(+), 29 deletions(-)
> 
> diff --git a/tests/i915/gem_unref_active_buffers.c b/tests/i915/gem_unref_active_buffers.c
> index 75394794..6a8cefd5 100644
> --- a/tests/i915/gem_unref_active_buffers.c
> +++ b/tests/i915/gem_unref_active_buffers.c
> @@ -29,8 +29,7 @@
>   * Testcase: Unreferencing of active buffers
>   *
>   * Execs buffers and immediately unreferences them, hence the kernel active list
> - * will be the last one to hold a reference on them. Usually libdrm bo caching
> - * prevents that by keeping another reference.
> + * will be the last one to hold a reference on them.
>   */
>  #include <stdlib.h>
>  #include <stdio.h>
> @@ -44,55 +43,54 @@
>  #include "drm.h"
>  #include "i915/gem.h"
>  #include "igt.h"
> -#include "intel_bufmgr.h"
>  
>  IGT_TEST_DESCRIPTION("Test unreferencing of active buffers.");
>  
> -static drm_intel_bufmgr *bufmgr;
> -struct intel_batchbuffer *batch;
> -static drm_intel_bo *load_bo;
> -
>  igt_simple_main
>  {
> +	struct intel_buf *load_bo;
> +	struct intel_bb *ibb;
> +	struct buf_ops *bops;
>  	int fd, i;
>  
>  	fd = drm_open_driver(DRIVER_INTEL);
>  	igt_require_gem(fd);
>  	gem_require_blitter(fd);
>  
> -	bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
> -	igt_assert(bufmgr);
> -	/* don't enable buffer reuse!! */
> -	//drm_intel_bufmgr_gem_enable_reuse(bufmgr);
> -
> -	batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
> -	igt_assert(batch);
> +	bops = buf_ops_create(fd);
> +	ibb = intel_bb_create(fd, 4096);

We want to use with relocs and fencing == false.

--
Zbigniew
>  
>  	/* put some load onto the gpu to keep the light buffers active for long
>  	 * enough */
>  	for (i = 0; i < 1000; i++) {
> -		load_bo = drm_intel_bo_alloc(bufmgr, "target bo", 1024*4096, 4096);
> -		igt_assert(load_bo);
> +		load_bo = intel_buf_create(bops, 1024, 1024, 32, 4096,
> +					   I915_TILING_NONE,
> +					   I915_COMPRESSION_NONE);
> -		BLIT_COPY_BATCH_START(0);
> -		OUT_BATCH((3 << 24) | /* 32 bits */
> +		intel_bb_add_intel_buf(ibb, load_bo, true);
> +		intel_bb_blit_start(ibb, 0);
> +		intel_bb_out(ibb, (3 << 24) | /* 32 bits */
>  			  (0xcc << 16) | /* copy ROP */
>  			  4096);
> -		OUT_BATCH(0); /* dst x1,y1 */
> -		OUT_BATCH((1024 << 16) | 512);
> -		OUT_RELOC_FENCED(load_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
> -		OUT_BATCH((0 << 16) | 512); /* src x1, y1 */
> -		OUT_BATCH(4096);
> -		OUT_RELOC_FENCED(load_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
> -		ADVANCE_BATCH();
> +		intel_bb_out(ibb, 0); /* dst x1,y1 */
> +		intel_bb_out(ibb, (1024 << 16) | 512);
> +		intel_bb_emit_reloc_fenced(ibb, load_bo->handle,
> +					   I915_GEM_DOMAIN_RENDER,
> +					   I915_GEM_DOMAIN_RENDER, 0, 0x0);
> +		intel_bb_out(ibb, (0 << 16) | 512); /* src x1, y1 */
> +		intel_bb_out(ibb, 4096);
> +		intel_bb_emit_reloc_fenced(ibb, load_bo->handle,
> +					   I915_GEM_DOMAIN_RENDER,
> +					   0, 0, 0x0);
>  
> -		intel_batchbuffer_flush(batch);
> +		intel_bb_flush_blit(ibb);
>  
> -		drm_intel_bo_disable_reuse(load_bo);
> -		drm_intel_bo_unreference(load_bo);
> +		intel_buf_destroy(load_bo);
> +		intel_bb_reset(ibb, true);
>  	}
>  
> -	drm_intel_bufmgr_destroy(bufmgr);
> +	intel_bb_destroy(ibb);
> +	buf_ops_destroy(bops);
>  
>  	close(fd);
>  }
> -- 
> 2.20.1
> 
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Re: [igt-dev] [PATCH i-g-t v4 12/25] i915/gem_tiled_partial_pwrite_pread: Remove libdrm dependency

[Zbigniew Kempczyński]

On Tue, Sep 22, 2020 at 01:52:16PM +0200, Dominik Grzegorzek wrote:
> Use intel_bb / intel_buf to remove libdrm dependency.
> 
> Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>  tests/i915/gem_tiled_partial_pwrite_pread.c | 123 ++++++++++----------
>  1 file changed, 60 insertions(+), 63 deletions(-)

Looks ok.

Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

> 
> diff --git a/tests/i915/gem_tiled_partial_pwrite_pread.c b/tests/i915/gem_tiled_partial_pwrite_pread.c
> index 7de5358b..6e7ec593 100644
> --- a/tests/i915/gem_tiled_partial_pwrite_pread.c
> +++ b/tests/i915/gem_tiled_partial_pwrite_pread.c
> @@ -53,68 +53,69 @@ IGT_TEST_DESCRIPTION("Test pwrite/pread consistency when touching partial"
>   *
>   */
>  
> -static drm_intel_bufmgr *bufmgr;
> -struct intel_batchbuffer *batch;
> +static struct buf_ops *bops;
> +static struct intel_bb *ibb;
>  
> -drm_intel_bo *scratch_bo;
> -drm_intel_bo *staging_bo;
> -drm_intel_bo *tiled_staging_bo;
> -unsigned long scratch_pitch;
> +struct intel_buf *scratch_buf;
> +struct intel_buf *staging_buf;
> +struct intel_buf *tiled_staging_buf;
>  #define BO_SIZE (32*4096)
> -uint32_t devid;
>  int fd;
>  
>  static void
> -copy_bo(drm_intel_bo *src, int src_tiled,
> -	drm_intel_bo *dst, int dst_tiled)
> +copy_bo(struct intel_buf *src, int src_tiled,
> +	struct intel_buf *dst, int dst_tiled)
>  {
> -	unsigned long dst_pitch = scratch_pitch;
> -	unsigned long src_pitch = scratch_pitch;
> +	unsigned long dst_pitch = dst->surface[0].stride;
> +	unsigned long src_pitch = src->surface[0].stride;
> +	unsigned long scratch_pitch = src->surface[0].stride;
>  	uint32_t cmd_bits = 0;
>  
>  	/* dst is tiled ... */
> -	if (intel_gen(devid) >= 4 && dst_tiled) {
> +	if (ibb->gen >= 4 && dst_tiled) {
>  		dst_pitch /= 4;
>  		cmd_bits |= XY_SRC_COPY_BLT_DST_TILED;
>  	}
>  
> -	if (intel_gen(devid) >= 4 && dst_tiled) {
> +	if (ibb->gen >= 4 && src_tiled) {
>  		src_pitch /= 4;
>  		cmd_bits |= XY_SRC_COPY_BLT_SRC_TILED;
>  	}
>  
> -	BLIT_COPY_BATCH_START(cmd_bits);
> -	OUT_BATCH((3 << 24) | /* 32 bits */
> +	intel_bb_add_intel_buf(ibb, dst, true);
> +	intel_bb_blit_start(ibb, cmd_bits);
> +	intel_bb_out(ibb, (3 << 24) | /* 32 bits */
>  		  (0xcc << 16) | /* copy ROP */
>  		  dst_pitch);
> -	OUT_BATCH(0 << 16 | 0);
> -	OUT_BATCH(BO_SIZE/scratch_pitch << 16 | 1024);
> -	OUT_RELOC_FENCED(dst, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
> -	OUT_BATCH(0 << 16 | 0);
> -	OUT_BATCH(src_pitch);
> -	OUT_RELOC_FENCED(src, I915_GEM_DOMAIN_RENDER, 0, 0);
> -	ADVANCE_BATCH();
> -
> -	intel_batchbuffer_flush(batch);
> +	intel_bb_out(ibb, 0 << 16 | 0);
> +	intel_bb_out(ibb, BO_SIZE/scratch_pitch << 16 | 1024);
> +	intel_bb_emit_reloc_fenced(ibb, dst->handle, I915_GEM_DOMAIN_RENDER,
> +				   I915_GEM_DOMAIN_RENDER, 0, dst->addr.offset);
> +	intel_bb_out(ibb, 0 << 16 | 0);
> +	intel_bb_out(ibb, src_pitch);
> +	intel_bb_emit_reloc_fenced(ibb, src->handle, I915_GEM_DOMAIN_RENDER, 0,
> +				   0, src->addr.offset);
> +
> +	intel_bb_flush_blit(ibb);
>  }
>  
>  static void
> -blt_bo_fill(drm_intel_bo *tmp_bo, drm_intel_bo *bo, int val)
> +blt_bo_fill(struct intel_buf *tmp_buf, struct intel_buf *buf, int val)
>  {
>  	uint8_t *gtt_ptr;
>  	int i;
>  
> -	drm_intel_gem_bo_map_gtt(tmp_bo);
> -	gtt_ptr = tmp_bo->virtual;
> +	gtt_ptr = gem_mmap__gtt(fd, tmp_buf->handle, tmp_buf->surface[0].size,
> +				PROT_WRITE);
>  
>  	for (i = 0; i < BO_SIZE; i++)
>  		gtt_ptr[i] = val;
>  
> -	drm_intel_gem_bo_unmap_gtt(tmp_bo);
> +	gem_munmap(gtt_ptr, tmp_buf->surface[0].size);
>  
>  	igt_drop_caches_set(fd, DROP_BOUND);
>  
> -	copy_bo(tmp_bo, 0, bo, 1);
> +	copy_bo(tmp_buf, 0, buf, 1);
>  }
>  
>  #define MAX_BLT_SIZE 128
> @@ -130,12 +131,12 @@ static void test_partial_reads(void)
>  		int start, len;
>  		int val = i % 256;
>  
> -		blt_bo_fill(staging_bo, scratch_bo, i);
> +		blt_bo_fill(staging_buf, scratch_buf, i);
>  
>  		start = random() % BO_SIZE;
>  		len = random() % (BO_SIZE-start) + 1;
>  
> -		drm_intel_bo_get_subdata(scratch_bo, start, len, tmp);
> +		gem_read(fd, scratch_buf->handle, start, tmp, len);
>  		for (j = 0; j < len; j++) {
>  			igt_assert_f(tmp[j] == val,
>  				     "mismatch at %i, got: %i, expected: %i\n",
> @@ -154,18 +155,17 @@ static void test_partial_writes(void)
>  		int start, len;
>  		int val = i % 256;
>  
> -		blt_bo_fill(staging_bo, scratch_bo, i);
> +		blt_bo_fill(staging_buf, scratch_buf, i);
>  
>  		start = random() % BO_SIZE;
>  		len = random() % (BO_SIZE-start) + 1;
>  
>  		memset(tmp, i + 63, BO_SIZE);
>  
> -		drm_intel_bo_subdata(scratch_bo, start, len, tmp);
> +		gem_write(fd, scratch_buf->handle, start, tmp, len);
>  
> -		copy_bo(scratch_bo, 1, tiled_staging_bo, 1);
> -		drm_intel_bo_get_subdata(tiled_staging_bo, 0, BO_SIZE,
> -					 compare_tmp);
> +		copy_bo(scratch_buf, 1, tiled_staging_buf, 1);
> +		gem_read(fd, tiled_staging_buf->handle, 0, compare_tmp, BO_SIZE);
>  
>  		for (j = 0; j < start; j++) {
>  			igt_assert_f(compare_tmp[j] == val,
> @@ -182,7 +182,6 @@ static void test_partial_writes(void)
>  				     "mismatch at %i, got: %i, expected: %i\n",
>  				     j, tmp[j], val);
>  		}
> -		drm_intel_gem_bo_unmap_gtt(staging_bo);
>  
>  		igt_progress("partial writes test: ", i, ROUNDS);
>  	}
> @@ -196,13 +195,13 @@ static void test_partial_read_writes(void)
>  		int start, len;
>  		int val = i % 256;
>  
> -		blt_bo_fill(staging_bo, scratch_bo, i);
> +		blt_bo_fill(staging_buf, scratch_buf, i);
>  
>  		/* partial read */
>  		start = random() % BO_SIZE;
>  		len = random() % (BO_SIZE-start) + 1;
>  
> -		drm_intel_bo_get_subdata(scratch_bo, start, len, tmp);
> +		gem_read(fd, scratch_buf->handle, start, tmp, len);
>  		for (j = 0; j < len; j++) {
>  			igt_assert_f(tmp[j] == val,
>  				     "mismatch in read at %i, got: %i, expected: %i\n",
> @@ -212,7 +211,7 @@ static void test_partial_read_writes(void)
>  		/* Change contents through gtt to make the pread cachelines
>  		 * stale. */
>  		val = (i + 17) % 256;
> -		blt_bo_fill(staging_bo, scratch_bo, val);
> +		blt_bo_fill(staging_buf, scratch_buf, val);
>  
>  		/* partial write */
>  		start = random() % BO_SIZE;
> @@ -220,11 +219,10 @@ static void test_partial_read_writes(void)
>  
>  		memset(tmp, i + 63, BO_SIZE);
>  
> -		drm_intel_bo_subdata(scratch_bo, start, len, tmp);
> +		gem_write(fd, scratch_buf->handle, start, tmp, len);
>  
> -		copy_bo(scratch_bo, 1, tiled_staging_bo, 1);
> -		drm_intel_bo_get_subdata(tiled_staging_bo, 0, BO_SIZE,
> -					 compare_tmp);
> +		copy_bo(scratch_buf, 1, tiled_staging_buf, 1);
> +		gem_read(fd, tiled_staging_buf->handle, 0, compare_tmp, BO_SIZE);
>  
>  		for (j = 0; j < start; j++) {
>  			igt_assert_f(compare_tmp[j] == val,
> @@ -241,7 +239,6 @@ static void test_partial_read_writes(void)
>  				     "mismatch at %i, got: %i, expected: %i\n",
>  				     j, tmp[j], val);
>  		}
> -		drm_intel_gem_bo_unmap_gtt(staging_bo);
>  
>  		igt_progress("partial read/writes test: ", i, ROUNDS);
>  	}
> @@ -261,8 +258,6 @@ static bool known_swizzling(uint32_t handle)
>  
>  igt_main
>  {
> -	uint32_t tiling_mode = I915_TILING_X;
> -
>  	srandom(0xdeadbeef);
>  
>  	igt_fixture {
> @@ -271,28 +266,26 @@ igt_main
>  		gem_require_mappable_ggtt(fd);
>  		gem_require_blitter(fd);
>  
> -		bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
> -		//drm_intel_bufmgr_gem_enable_reuse(bufmgr);
> -		devid = intel_get_drm_devid(fd);
> -		batch = intel_batchbuffer_alloc(bufmgr, devid);
> +		bops = buf_ops_create(fd);
> +		ibb = intel_bb_create(fd, 4096);
>  
>  		/* overallocate the buffers we're actually using because */
> -		scratch_bo = drm_intel_bo_alloc_tiled(bufmgr, "scratch bo", 1024,
> -						      BO_SIZE/4096, 4,
> -						      &tiling_mode, &scratch_pitch, 0);
> -		igt_assert(tiling_mode == I915_TILING_X);
> -		igt_assert(scratch_pitch == 4096);
> +		scratch_buf = intel_buf_create(bops, 1024, BO_SIZE/4096, 32, 0,
> +					       I915_TILING_X,
> +					       I915_COMPRESSION_NONE);
>  
>  		/*
>  		 * As we want to compare our template tiled pattern against
>  		 * the target bo, we need consistent swizzling on both.
>  		 */
> -		igt_require(known_swizzling(scratch_bo->handle));
> -		staging_bo = drm_intel_bo_alloc(bufmgr, "staging bo", BO_SIZE, 4096);
> -		tiled_staging_bo = drm_intel_bo_alloc_tiled(bufmgr, "scratch bo", 1024,
> -							    BO_SIZE/4096, 4,
> -							    &tiling_mode,
> -							    &scratch_pitch, 0);
> +		igt_require(known_swizzling(scratch_buf->handle));
> +		staging_buf = intel_buf_create(bops, 1024, BO_SIZE/4096, 32,
> +					       4096, I915_TILING_NONE,
> +					       I915_COMPRESSION_NONE);
> +
> +		tiled_staging_buf = intel_buf_create(bops, 1024, BO_SIZE/4096,
> +						     32, 0, I915_TILING_X,
> +						     I915_COMPRESSION_NONE);
>  	}
>  
>  	igt_subtest("reads")
> @@ -305,7 +298,11 @@ igt_main
>  		test_partial_read_writes();
>  
>  	igt_fixture {
> -		drm_intel_bufmgr_destroy(bufmgr);
> +		intel_buf_destroy(scratch_buf);
> +		intel_buf_destroy(staging_buf);
> +		intel_buf_destroy(tiled_staging_buf);
> +		intel_bb_destroy(ibb);
> +		buf_ops_destroy(bops);
>  
>  		close(fd);
>  	}
> -- 
> 2.20.1
> 
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Re: [igt-dev] [PATCH i-g-t v4 14/25] tests/kms_fence_pin_leak.c: Remove libdrm dependency

[Zbigniew Kempczyński]

On Tue, Sep 22, 2020 at 01:52:18PM +0200, Dominik Grzegorzek wrote:
> Use intel_bb / intel_buf to remove libdrm dependency.
> 
> Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>  tests/kms_fence_pin_leak.c | 83 +++++++++++++++++++++-----------------
>  1 file changed, 45 insertions(+), 38 deletions(-)
> 
> diff --git a/tests/kms_fence_pin_leak.c b/tests/kms_fence_pin_leak.c
> index b59efc0a..a86f2cdb 100644
> --- a/tests/kms_fence_pin_leak.c
> +++ b/tests/kms_fence_pin_leak.c
> @@ -37,34 +37,45 @@ IGT_TEST_DESCRIPTION("Exercises full ppgtt fence pin_count leak in the "
>  typedef struct {
>  	int drm_fd;
>  	uint32_t devid;
> -	drm_intel_bufmgr *bufmgr;
> +	struct buf_ops *bops;
>  	igt_display_t display;
> -	drm_intel_bo *bos[64]; /* >= num fence registers */
> +	struct intel_buf *bos[64]; /* >= num fence registers */
>  } data_t;
>  
> -static void exec_nop(data_t *data, uint32_t handle, drm_intel_context *context)
> +static void exec_nop(data_t *data, struct igt_fb *fb, uint32_t context)
>  {
> -	drm_intel_bo *dst;
> -	struct intel_batchbuffer *batch;
> +	struct intel_buf *dst;
> +	struct intel_bb *ibb;
> +	uint32_t name, handle, tiling, stride, width, height, bpp, size;
>  
> -	dst = gem_handle_to_libdrm_bo(data->bufmgr, data->drm_fd, "", handle);
> -	igt_assert(dst);
> +	tiling = igt_fb_mod_to_tiling(fb->modifier);
> +	stride = fb->strides[0];
> +	bpp = fb->plane_bpp[0];
> +	size = fb->size;
> +	width = stride / (bpp / 8);
> +	height = size / stride;
>  
> -	batch = intel_batchbuffer_alloc(data->bufmgr, data->devid);
> -	igt_assert(batch);
> +	name = gem_flink(data->drm_fd, fb->gem_handle);
> +	handle = gem_open(data->drm_fd, name);
> +	dst = intel_buf_create_using_handle(data->bops, handle,
> +				    width, height, bpp, 0, tiling, 0);

Indentation.

> +	intel_buf_set_ownership(dst, true);
> +
> +	ibb = intel_bb_create(buf_ops_get_fd(data->bops), 4096);
>  
>  	/* add the reloc to make sure the kernel will think we write to dst */
> -	BEGIN_BATCH(4, 1);
> -	OUT_BATCH(MI_BATCH_BUFFER_END);
> -	OUT_BATCH(MI_NOOP);
> -	OUT_RELOC(dst, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
> -	OUT_BATCH(MI_NOOP);
> -	ADVANCE_BATCH();
> +	intel_bb_add_intel_buf(ibb, dst, true);
> +	intel_bb_out(ibb, MI_BATCH_BUFFER_END);
> +	intel_bb_out(ibb, MI_NOOP);
> +	intel_bb_emit_reloc(ibb, dst->handle, I915_GEM_DOMAIN_RENDER,
> +			    I915_GEM_DOMAIN_RENDER, 0, 0x0);
> +	intel_bb_out(ibb, MI_NOOP);
> +
> +	intel_bb_flush_render_with_context(ibb, context);
>  
> -	intel_batchbuffer_flush_with_context(batch, context);
> -	intel_batchbuffer_free(batch);
> +	intel_bb_destroy(ibb);
>  
> -	drm_intel_bo_unreference(dst);
> +	intel_buf_destroy(dst);
>  }
>  
>  static void alloc_fence_objs(data_t *data)
> @@ -72,13 +83,13 @@ static void alloc_fence_objs(data_t *data)
>  	int i;
>  
>  	for (i = 0; i < ARRAY_SIZE(data->bos); i++) {
> -		drm_intel_bo *bo;
> +		struct intel_buf *buf;
>  
> -		bo = drm_intel_bo_alloc(data->bufmgr, "fence bo", 4096, 4096);
> -		igt_assert(bo);
> -		gem_set_tiling(data->drm_fd, bo->handle, I915_TILING_X, 512);
> +		buf = intel_buf_create(data->bops, 32, 32, 32, 4096,
> +				       I915_TILING_NONE, I915_COMPRESSION_NONE);
> +		gem_set_tiling(data->drm_fd, buf->handle, I915_TILING_X, 512);

Better use:

	for (i = 0; i < ARRAY_SIZE(data->bos); i++) {
		struct intel_buf *buf;

		buf = intel_buf_create(data->bops, 128, 8, 32, 0,
				       I915_TILING_X, I915_COMPRESSION_NONE);
		igt_assert(buf->surface[0].stride == 512);
		data->bos[i] = buf;
	}

--
Zbigniew
>  
> -		data->bos[i] = bo;
> +		data->bos[i] = buf;
>  	}
>  }
>  
> @@ -102,7 +113,7 @@ static void free_fence_objs(data_t *data)
>  	int i;
>  
>  	for (i = 0; i < ARRAY_SIZE(data->bos); i++)
> -		drm_intel_bo_unreference(data->bos[i]);
> +		intel_buf_destroy(data->bos[i]);
>  }
>  
>  static void run_single_test(data_t *data, enum pipe pipe, igt_output_t *output)
> @@ -133,19 +144,18 @@ static void run_single_test(data_t *data, enum pipe pipe, igt_output_t *output)
>  	igt_display_commit(display);
>  
>  	for (i = 0; i < 64; i++) {
> -		drm_intel_context *ctx;
> +		uint32_t ctx;
>  
>  		/*
>  		 * Link fb.gem_handle to the ppgtt vm of ctx so that the context
>  		 * destruction will unbind the obj from the ppgtt vm in question.
>  		 */
> -		ctx = drm_intel_gem_context_create(data->bufmgr);
> -		igt_assert(ctx);
> -		exec_nop(data, fb[i&1].gem_handle, ctx);
> -		drm_intel_gem_context_destroy(ctx);
> +		ctx = gem_context_create(data->drm_fd);
> +		exec_nop(data, &fb[i&1], ctx);
> +		gem_context_destroy(data->drm_fd, ctx);
>  
>  		/* Force a context switch to make sure ctx gets destroyed for real. */
> -		exec_nop(data, fb[i&1].gem_handle, NULL);
> +		exec_nop(data, &fb[i&1], 0);
>  
>  		gem_sync(data->drm_fd, fb[i&1].gem_handle);
>  
> @@ -196,7 +206,7 @@ static void run_test(data_t *data)
>  
>  igt_simple_main
>  {
> -	drm_intel_context *ctx;
> +	uint32_t ctx;
>  	data_t data = {};
>  
>  	data.drm_fd = drm_open_driver_master(DRIVER_INTEL);
> @@ -207,15 +217,12 @@ igt_simple_main
>  
>  	kmstest_set_vt_graphics_mode();
>  
> -	data.bufmgr = drm_intel_bufmgr_gem_init(data.drm_fd, 4096);
> -	igt_assert(data.bufmgr);
> -	drm_intel_bufmgr_gem_enable_reuse(data.bufmgr);
> +	data.bops = buf_ops_create(data.drm_fd);
>  
>  	igt_display_require(&data.display, data.drm_fd);
>  
> -	ctx = drm_intel_gem_context_create(data.bufmgr);
> -	igt_require(ctx);
> -	drm_intel_gem_context_destroy(ctx);
> +	ctx = gem_context_create(data.drm_fd);
> +	gem_context_destroy(data.drm_fd, ctx);
>  
>  	alloc_fence_objs(&data);
>  
> @@ -223,6 +230,6 @@ igt_simple_main
>  
>  	free_fence_objs(&data);
>  
> -	drm_intel_bufmgr_destroy(data.bufmgr);
> +	buf_ops_destroy(data.bops);
>  	igt_display_fini(&data.display);
>  }
> -- 
> 2.20.1
> 
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Re: [igt-dev] [PATCH i-g-t v4 15/25] tests/kms_flip.c: Remove libdrm dependency

[Zbigniew Kempczyński]

On Tue, Sep 22, 2020 at 01:52:19PM +0200, Dominik Grzegorzek wrote:
> Use intel_bb / intel_buf to remove libdrm dependency.
> 
> Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>  tests/kms_flip.c | 22 ++++++++--------------
>  1 file changed, 8 insertions(+), 14 deletions(-)
> 
> diff --git a/tests/kms_flip.c b/tests/kms_flip.c
> index b33cfe9c..525cccc7 100755
> --- a/tests/kms_flip.c
> +++ b/tests/kms_flip.c
> @@ -86,8 +86,7 @@
>  
>  drmModeRes *resources;
>  int drm_fd;
> -static drm_intel_bufmgr *bufmgr;
> -struct intel_batchbuffer *batch;
> +static struct buf_ops *bops;
>  uint32_t devid;
>  int test_time = 3;
>  static bool monotonic_timestamp;
> @@ -211,20 +210,19 @@ static void emit_fence_stress(struct test_output *o)
>  	struct drm_i915_gem_execbuffer2 execbuf;
>  	struct drm_i915_gem_exec_object2 *exec;
>  	uint32_t buf[2] = { MI_BATCH_BUFFER_END, 0 };
> -	drm_intel_bo **bo;
> +	struct intel_buf **bo;
>  	int i;
>  
> -	igt_require(bufmgr);
> +	igt_require(bops);
>  
>  	igt_assert(num_fences);
>  	bo = calloc(sizeof(*bo), num_fences);
>  	exec = calloc(sizeof(*exec), num_fences+1);
>  	for (i = 0; i < num_fences - 1; i++) {
>  		uint32_t tiling = I915_TILING_X;
> -		unsigned long pitch = 0;
> -		bo[i] = drm_intel_bo_alloc_tiled(bufmgr,
> -						 "X tiled bo", 1024, 1024, 4,
> -						 &tiling, &pitch, 0);
> +		bo[i] = intel_buf_create(bops, 1024, 1024, 32, 4096, tiling,
> +					 I915_COMPRESSION_NONE);
> +

Small nit - 4096 above is for linear surface, so pass 0 here. And it is
stride alignment, not page. 

Fix above and you have:

Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

>  		exec[i].handle = bo[i]->handle;
>  		exec[i].flags = EXEC_OBJECT_NEEDS_FENCE;
>  	}
> @@ -244,7 +242,7 @@ static void emit_fence_stress(struct test_output *o)
>  
>  	gem_close(drm_fd, exec[i].handle);
>  	for (i = 0; i < num_fences - 1; i++)
> -		drm_intel_bo_unreference(bo[i]);
> +		intel_buf_destroy(bo[i]);
>  	free(bo);
>  	free(exec);
>  }
> @@ -1664,11 +1662,7 @@ igt_main
>  		get_timestamp_format();
>  
>  		if (is_i915_device(drm_fd)) {
> -			bufmgr = drm_intel_bufmgr_gem_init(drm_fd, 4096);
> -			if (bufmgr) {
> -				devid = intel_get_drm_devid(drm_fd);
> -				batch = intel_batchbuffer_alloc(bufmgr, devid);
> -			}
> +			bops = buf_ops_create(drm_fd);
>  		}
>  	}
>  
> -- 
> 2.20.1
> 
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Re: [igt-dev] [PATCH i-g-t v4 06/25] i915/gem_pipe_control_store_loop.c: Remove libdrm dependency

[Zbigniew Kempczyński]

On Wed, Sep 23, 2020 at 09:19:55AM +0200, Grzegorzek, Dominik wrote:
> On Tue, 2020-09-22 at 15:51 +0200, Zbigniew Kempczyński wrote:
> > On Tue, Sep 22, 2020 at 01:52:10PM +0200, Dominik Grzegorzek wrote:
> > > Use intel_bb / intel_buf to remove libdrm dependency.
> > > 
> > > Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
> > > Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> > > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > > ---
> > >  tests/i915/gem_pipe_control_store_loop.c | 143 +++++++++++------
> > > ------

To make patchwork happy:

Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

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Re: [igt-dev] [PATCH i-g-t v4 16/25] tests/kms_psr2_su.c: Get rid of unused bufmgr

[Zbigniew Kempczyński]

On Tue, Sep 22, 2020 at 01:52:20PM +0200, Dominik Grzegorzek wrote:
> Removal of bufmgr that was only set but not used.
> 
> Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>

Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

> ---
>  tests/kms_psr2_su.c | 7 -------
>  1 file changed, 7 deletions(-)
> 
> diff --git a/tests/kms_psr2_su.c b/tests/kms_psr2_su.c
> index d549d9a3..9215c59d 100644
> --- a/tests/kms_psr2_su.c
> +++ b/tests/kms_psr2_su.c
> @@ -30,7 +30,6 @@
>  #include <stdio.h>
>  #include <string.h>
>  #include <sys/timerfd.h>
> -#include "intel_bufmgr.h"
>  
>  IGT_TEST_DESCRIPTION("Test PSR2 selective update");
>  
> @@ -65,7 +64,6 @@ typedef struct {
>  	int drm_fd;
>  	int debugfs_fd;
>  	igt_display_t display;
> -	drm_intel_bufmgr *bufmgr;
>  	drmModeModeInfo *mode;
>  	igt_output_t *output;
>  	struct igt_fb fb[2];
> @@ -247,10 +245,6 @@ igt_main
>  					       data.debugfs_fd, PSR_MODE_2),
>  			      "Sink does not support PSR2\n");
>  
> -		data.bufmgr = drm_intel_bufmgr_gem_init(data.drm_fd, 4096);
> -		igt_assert(data.bufmgr);
> -		drm_intel_bufmgr_gem_enable_reuse(data.bufmgr);
> -
>  		display_init(&data);
>  
>  		/* Test if PSR2 can be enabled */
> @@ -287,7 +281,6 @@ igt_main
>  
>  	igt_fixture {
>  		close(data.debugfs_fd);
> -		drm_intel_bufmgr_destroy(data.bufmgr);
>  		display_fini(&data);
>  	}
>  }
> -- 
> 2.20.1
> 
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Re: [igt-dev] [PATCH i-g-t v4 22/25] tests/prime_nv_api.c: Remove libdrm dependency

[Zbigniew Kempczyński]

On Tue, Sep 22, 2020 at 01:52:26PM +0200, Dominik Grzegorzek wrote:
> Use intel_bb / intel_buf to remove libdrm dependency.
> 
> Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>  tests/prime_nv_api.c | 203 +++++++++++++++++++++++--------------------
>  1 file changed, 111 insertions(+), 92 deletions(-)
> 
> diff --git a/tests/prime_nv_api.c b/tests/prime_nv_api.c
> index 054a1ec6..a3adeddc 100644
> --- a/tests/prime_nv_api.c
> +++ b/tests/prime_nv_api.c
> @@ -15,18 +15,18 @@
>  #include <fcntl.h>
>  #include <sys/stat.h>
>  
> -#include "intel_bufmgr.h"
>  #include "nouveau.h"
>  
> -#define BO_SIZE (256*1024)
> +#define WIDTH 256
> +#define HEIGHT 256
> +
> +#define BO_SIZE (WIDTH*HEIGHT*4)
>  
>  int intel_fd = -1, intel_fd2 = -1, nouveau_fd = -1, nouveau_fd2 = -1;
> -drm_intel_bufmgr *bufmgr;
> -drm_intel_bufmgr *bufmgr2;
> +struct buf_ops *bops;
> +struct buf_ops *bops2;
>  struct nouveau_device *ndev, *ndev2;
>  struct nouveau_client *nclient, *nclient2;
> -uint32_t devid;
> -struct intel_batchbuffer *intel_batch;
>  
>  static void find_and_open_devices(void)
>  {
> @@ -69,13 +69,15 @@ static void find_and_open_devices(void)
>  
>  static void test_i915_nv_import_twice(void)
>  {
> -	drm_intel_bo *test_intel_bo;
> +	struct intel_buf *test_intel_buf;
>  	int prime_fd;
>  	struct nouveau_bo *nvbo = NULL, *nvbo2 = NULL;
>  
> -	test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", BO_SIZE, 4096);
> +	test_intel_buf = intel_buf_create(bops, WIDTH, HEIGHT, 32, 4096,
> +					  I915_TILING_NONE,
> +					  I915_COMPRESSION_NONE);

0 instead 4096.

>  
> -	igt_assert(drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd) == 0);
> +	prime_fd = prime_handle_to_fd(intel_fd, test_intel_buf->handle);

prime_handle_to_fd_for_mmap(), likely doesn't differ for that case but 
we don't want to change test coverage.

>  
>  	igt_assert(nouveau_bo_prime_handle_ref(ndev, prime_fd, &nvbo) == 0);
>  	igt_assert(nouveau_bo_prime_handle_ref(ndev2, prime_fd, &nvbo2) == 0);
> @@ -83,19 +85,21 @@ static void test_i915_nv_import_twice(void)
>  
>  	nouveau_bo_ref(NULL, &nvbo2);
>  	nouveau_bo_ref(NULL, &nvbo);
> -	drm_intel_bo_unreference(test_intel_bo);
> +	intel_buf_destroy(test_intel_buf);
>  }
>  
>  static void test_i915_nv_import_twice_check_flink_name(void)
>  {
> -	drm_intel_bo *test_intel_bo;
> +	struct intel_buf *test_intel_buf;
>  	int prime_fd;
>  	struct nouveau_bo *nvbo = NULL, *nvbo2 = NULL;
>  	uint32_t flink_name1, flink_name2;
>  
> -	test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", BO_SIZE, 4096);
> +	test_intel_buf = intel_buf_create(bops, WIDTH, HEIGHT, 32, 4096,
> +					  I915_TILING_NONE,
> +					  I915_COMPRESSION_NONE);
>  
> -	igt_assert(drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd) == 0);
> +	prime_fd = prime_handle_to_fd(intel_fd, test_intel_buf->handle);

Same as above.

>  
>  	igt_assert(nouveau_bo_prime_handle_ref(ndev, prime_fd, &nvbo) == 0);
>  	igt_assert(nouveau_bo_prime_handle_ref(ndev2, prime_fd, &nvbo2) == 0);
> @@ -108,25 +112,27 @@ static void test_i915_nv_import_twice_check_flink_name(void)
>  
>  	nouveau_bo_ref(NULL, &nvbo2);
>  	nouveau_bo_ref(NULL, &nvbo);
> -	drm_intel_bo_unreference(test_intel_bo);
> +	intel_buf_destroy(test_intel_buf);
>  }
>  
>  static void test_i915_nv_reimport_twice_check_flink_name(void)
>  {
> -	drm_intel_bo *test_intel_bo;
> +	struct intel_buf *test_intel_buf;
>  	int prime_fd;
>  	struct nouveau_bo *nvbo = NULL, *nvbo2 = NULL;
>  	uint32_t flink_name1, flink_name2;
>  
> -	test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", BO_SIZE, 4096);
> +	test_intel_buf = intel_buf_create(bops, WIDTH, HEIGHT, 32, 4096,
> +					  I915_TILING_NONE,
> +					  I915_COMPRESSION_NONE);
>  
> -	igt_assert(drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd) == 0);
> +	prime_fd = prime_handle_to_fd(intel_fd, test_intel_buf->handle);
>  
>  	igt_assert(nouveau_bo_prime_handle_ref(ndev, prime_fd, &nvbo) == 0);
>  
>  	/* create a new dma-buf */
>  	close(prime_fd);
> -	igt_assert(drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd) == 0);
> +	prime_handle_to_fd(intel_fd, test_intel_buf->handle);

Same as above.

>  
>  	igt_assert(nouveau_bo_prime_handle_ref(ndev2, prime_fd, &nvbo2) == 0);
>  	close(prime_fd);
> @@ -138,79 +144,91 @@ static void test_i915_nv_reimport_twice_check_flink_name(void)
>  
>  	nouveau_bo_ref(NULL, &nvbo2);
>  	nouveau_bo_ref(NULL, &nvbo);
> -	drm_intel_bo_unreference(test_intel_bo);
> +	intel_buf_destroy(test_intel_buf);
>  }
>  
>  static void test_nv_i915_import_twice_check_flink_name(void)
>  {
> -	drm_intel_bo *intel_bo = NULL, *intel_bo2 = NULL;
> +	struct intel_buf *intel_buf1 = NULL, *intel_buf2 = NULL;
>  	int prime_fd;
>  	struct nouveau_bo *nvbo = NULL;
> -	uint32_t flink_name1, flink_name2;
> +	uint32_t flink_name1, flink_name2, handle;
>  
>  	igt_assert(nouveau_bo_new(ndev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP,
>  				  0, BO_SIZE, NULL, &nvbo) == 0);
>  
>  	igt_assert(nouveau_bo_set_prime(nvbo, &prime_fd) == 0);
>  
> -	intel_bo = drm_intel_bo_gem_create_from_prime(bufmgr, prime_fd, BO_SIZE);
> -	igt_assert(intel_bo);
> -
> -	intel_bo2 = drm_intel_bo_gem_create_from_prime(bufmgr2, prime_fd, BO_SIZE);
> -	igt_assert(intel_bo2);
> +	handle = prime_fd_to_handle(intel_fd, prime_fd);
> +	intel_buf1 = intel_buf_create_using_handle(bops, handle,  WIDTH, HEIGHT,
> +						   32, 4096, I915_TILING_NONE,
> +						   I915_COMPRESSION_NONE);
> +	intel_buf_set_ownership(intel_buf1, true);

Assert if intel_buf_bo_size(buf) is not equal to BO_SIZE. 

> +
> +	handle = prime_fd_to_handle(intel_fd2, prime_fd);
> +	intel_buf2 = intel_buf_create_using_handle(bops2, handle,  WIDTH, HEIGHT,
> +						   32, 4096, I915_TILING_NONE,
> +						   I915_COMPRESSION_NONE);
> +	intel_buf_set_ownership(intel_buf2, true);
>  	close(prime_fd);
>  
> -	igt_assert(drm_intel_bo_flink(intel_bo, &flink_name1) == 0);
> -	igt_assert(drm_intel_bo_flink(intel_bo2, &flink_name2) == 0);
> +	flink_name1 = gem_flink(intel_fd, intel_buf1->handle);
> +	flink_name2 = gem_flink(intel_fd2, intel_buf2->handle);
>  
>  	igt_assert_eq_u32(flink_name1, flink_name2);
>  
>  	nouveau_bo_ref(NULL, &nvbo);
> -	drm_intel_bo_unreference(intel_bo);
> -	drm_intel_bo_unreference(intel_bo2);
> +	intel_buf_destroy(intel_buf1);
> +	intel_buf_destroy(intel_buf2);
>  }
>  
>  static void test_nv_i915_reimport_twice_check_flink_name(void)
>  {
> -	drm_intel_bo *intel_bo = NULL, *intel_bo2 = NULL;
> +	struct intel_buf *intel_buf1 = NULL, *intel_buf2 = NULL;
>  	int prime_fd;
>  	struct nouveau_bo *nvbo = NULL;
> -	uint32_t flink_name1, flink_name2;
> +	uint32_t flink_name1, flink_name2, handle;
>  
>  	igt_assert(nouveau_bo_new(ndev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP,
>  				  0, BO_SIZE, NULL, &nvbo) == 0);
>  
>  	igt_assert(nouveau_bo_set_prime(nvbo, &prime_fd) == 0);
>  
> -	intel_bo = drm_intel_bo_gem_create_from_prime(bufmgr, prime_fd, BO_SIZE);
> -	igt_assert(intel_bo);
> -	close(prime_fd);
> -	igt_assert(nouveau_bo_set_prime(nvbo, &prime_fd) == 0);
> +	handle = prime_fd_to_handle(intel_fd, prime_fd);
> +	intel_buf1 = intel_buf_create_using_handle(bops, handle,  WIDTH, HEIGHT,
> +						   32, 4096, I915_TILING_NONE,
> +						   I915_COMPRESSION_NONE);
> +	intel_buf_set_ownership(intel_buf1, true);

Check intel_buf size like above.

>  
> -	intel_bo2 = drm_intel_bo_gem_create_from_prime(bufmgr2, prime_fd, BO_SIZE);
> -	igt_assert(intel_bo2);
> +	igt_assert(nouveau_bo_set_prime(nvbo, &prime_fd) == 0);
> +	handle = prime_fd_to_handle(intel_fd2, prime_fd);
> +	intel_buf2 = intel_buf_create_using_handle(bops2, handle,  WIDTH, HEIGHT,
> +						   32, 4096, I915_TILING_NONE,
> +						   I915_COMPRESSION_NONE);
> +	intel_buf_set_ownership(intel_buf2, true);
>  	close(prime_fd);
>  
> -	igt_assert(drm_intel_bo_flink(intel_bo, &flink_name1) == 0);
> -	igt_assert(drm_intel_bo_flink(intel_bo2, &flink_name2) == 0);
> +	flink_name1 = gem_flink(intel_fd, intel_buf1->handle);
> +	flink_name2 = gem_flink(intel_fd2, intel_buf2->handle);
>  
>  	igt_assert_eq_u32(flink_name1, flink_name2);
>  
>  	nouveau_bo_ref(NULL, &nvbo);
> -	drm_intel_bo_unreference(intel_bo);
> -	drm_intel_bo_unreference(intel_bo2);
> +	intel_buf_destroy(intel_buf1);
> +	intel_buf_destroy(intel_buf2);
>  }
>  
>  static void test_i915_nv_import_vs_close(void)
>  {
> -	drm_intel_bo *test_intel_bo;
> +	struct intel_buf *test_intel_buf;
>  	int prime_fd;
>  	struct nouveau_bo *nvbo = NULL, *nvbo2 = NULL;
>  
> -	test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", BO_SIZE, 4096);
> -	igt_assert(test_intel_bo);
> +	test_intel_buf = intel_buf_create(bops, WIDTH, HEIGHT, 32, 4096,
> +					  I915_TILING_NONE,
> +					  I915_COMPRESSION_NONE);

0 instead 4096.

>  
> -	igt_assert(drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd) == 0);
> +	prime_fd = prime_handle_to_fd(intel_fd, test_intel_buf->handle);

prime_handle_to_fd_for_mmap().

>  
>  	igt_assert(nouveau_bo_prime_handle_ref(ndev, prime_fd, &nvbo) == 0);
>  	close(prime_fd);
> @@ -218,21 +236,21 @@ static void test_i915_nv_import_vs_close(void)
>  
>  	nouveau_bo_ref(NULL, &nvbo2);
>  	nouveau_bo_ref(NULL, &nvbo);
> -	drm_intel_bo_unreference(test_intel_bo);
> +	intel_buf_destroy(test_intel_buf);
>  }
>  
>  /* import handle twice on one driver */
>  static void test_i915_nv_double_import(void)
>  {
> -	drm_intel_bo *test_intel_bo;
> +	struct intel_buf *test_intel_buf;
>  	int prime_fd;
>  	struct nouveau_bo *nvbo = NULL, *nvbo2 = NULL;
>  
> -	test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", BO_SIZE, 4096);
> -	igt_assert(test_intel_bo);
> -
> -	igt_assert(drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd) == 0);
> +	test_intel_buf = intel_buf_create(bops, WIDTH, HEIGHT, 32, 4096,
> +					  I915_TILING_NONE,
> +					  I915_COMPRESSION_NONE);
>  
> +	prime_fd = prime_handle_to_fd(intel_fd, test_intel_buf->handle);

Same as above.

>  	igt_assert(nouveau_bo_prime_handle_ref(ndev, prime_fd, &nvbo) == 0);
>  	igt_assert(nouveau_bo_prime_handle_ref(ndev, prime_fd, &nvbo2) == 0);
>  	close(prime_fd);
> @@ -241,23 +259,24 @@ static void test_i915_nv_double_import(void)
>  
>  	nouveau_bo_ref(NULL, &nvbo2);
>  	nouveau_bo_ref(NULL, &nvbo);
> -	drm_intel_bo_unreference(test_intel_bo);
> +	intel_buf_destroy(test_intel_buf);
>  }
>  
>  /* export handle twice from one driver - import twice
>     see if we get same object */
>  static void test_i915_nv_double_export(void)
>  {
> -	drm_intel_bo *test_intel_bo;
> +	struct intel_buf *test_intel_buf;
>  	int prime_fd, prime_fd2;
>  	struct nouveau_bo *nvbo = NULL, *nvbo2 = NULL;
>  
> -	test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", BO_SIZE, 4096);
> -	igt_assert(test_intel_bo);
> +	test_intel_buf = intel_buf_create(bops, WIDTH, HEIGHT, 32, 4096,
> +					  I915_TILING_NONE,
> +					  I915_COMPRESSION_NONE);
>  
> -	drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd);
> +	prime_fd = prime_handle_to_fd(intel_fd, test_intel_buf->handle);
>  
> -	drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd2);
> +	prime_fd2 = prime_handle_to_fd(intel_fd, test_intel_buf->handle);

Same as above.

>  
>  	igt_assert(nouveau_bo_prime_handle_ref(ndev, prime_fd, &nvbo) == 0);
>  	close(prime_fd);
> @@ -268,27 +287,33 @@ static void test_i915_nv_double_export(void)
>  
>  	nouveau_bo_ref(NULL, &nvbo2);
>  	nouveau_bo_ref(NULL, &nvbo);
> -	drm_intel_bo_unreference(test_intel_bo);
> +	intel_buf_destroy(test_intel_buf);
>  }
>  
>  /* export handle from intel driver - reimport to intel driver
>     see if you get same object */
>  static void test_i915_self_import(void)
>  {
> -	drm_intel_bo *test_intel_bo, *test_intel_bo2;
> +	struct intel_buf *test_intel_buf, *test_intel_buf2;
> +	uint32_t handle;
>  	int prime_fd;
>  
> -	test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", BO_SIZE, 4096);
> +	test_intel_buf = intel_buf_create(bops, WIDTH, HEIGHT, 32, 4096,
> +					  I915_TILING_NONE,
> +					  I915_COMPRESSION_NONE);
>  
> -	drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd);
> +	prime_fd = prime_handle_to_fd(intel_fd, test_intel_buf->handle);
>  
> -	test_intel_bo2 = drm_intel_bo_gem_create_from_prime(bufmgr, prime_fd, BO_SIZE);
> -	close(prime_fd);
> -	igt_assert(test_intel_bo2);
> +	handle = prime_fd_to_handle(intel_fd, prime_fd);
> +	test_intel_buf2 = intel_buf_create_using_handle(bops, handle, WIDTH,
> +							HEIGHT, 32, 4096,
> +							I915_TILING_NONE,
> +							I915_COMPRESSION_NONE);

Same as above.

>  
> -	igt_assert(test_intel_bo->handle == test_intel_bo2->handle);
> +	igt_assert(test_intel_buf->handle == test_intel_buf2->handle);
>  
> -	drm_intel_bo_unreference(test_intel_bo);
> +	intel_buf_destroy(test_intel_buf);
> +	intel_buf_destroy(test_intel_buf2);
>  }
>  
>  /* nouveau export reimport test */
> @@ -309,23 +334,31 @@ static void test_nv_self_import(void)
>  	nouveau_bo_ref(NULL, &nvbo2);
>  }
>  
> -/* export handle from intel driver - reimport to another intel driver bufmgr
> +/* export handle from intel driver - reimport to another intel driver
>     see if you get same object */
>  static void test_i915_self_import_to_different_fd(void)
>  {
> -	drm_intel_bo *test_intel_bo, *test_intel_bo2;
> +	struct intel_buf *test_intel_buf, *test_intel_buf2;
> +	uint32_t handle;
>  	int prime_fd;
>  
> -	test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", BO_SIZE, 4096);
> +	test_intel_buf = intel_buf_create(bops, WIDTH, HEIGHT, 32, 4096,
> +					  I915_TILING_NONE,
> +					  I915_COMPRESSION_NONE);
>  
> -	drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd);
> +	prime_fd = prime_handle_to_fd(intel_fd, test_intel_buf->handle);
> +
> +	handle = prime_fd_to_handle(intel_fd2, prime_fd);
> +	test_intel_buf2 = intel_buf_create_using_handle(bops2, handle, WIDTH,
> +							HEIGHT, 32, 4096,
> +							I915_TILING_NONE,
> +							I915_COMPRESSION_NONE);
> +	intel_buf_set_ownership(test_intel_buf2, true);

Same as above. 

>  
> -	test_intel_bo2 = drm_intel_bo_gem_create_from_prime(bufmgr2, prime_fd, BO_SIZE);
>  	close(prime_fd);
> -	igt_assert(test_intel_bo2);
>  
> -	drm_intel_bo_unreference(test_intel_bo2);
> -	drm_intel_bo_unreference(test_intel_bo);
> +	intel_buf_destroy(test_intel_buf);
> +	intel_buf_destroy(test_intel_buf2);
>  }
>  
>  /* nouveau export reimport to other driver test */
> @@ -357,14 +390,8 @@ igt_main
>  		igt_require(intel_fd2 != -1);
>  
>  		/* set up intel bufmgr */
> -		bufmgr = drm_intel_bufmgr_gem_init(intel_fd, 4096);
> -		igt_assert(bufmgr);
> -		/* Do not enable reuse, we share (almost) all buffers. */
> -		//drm_intel_bufmgr_gem_enable_reuse(bufmgr);
> -
> -		bufmgr2 = drm_intel_bufmgr_gem_init(intel_fd2, 4096);
> -		igt_assert(bufmgr2);
> -		drm_intel_bufmgr_gem_enable_reuse(bufmgr2);

I've checked the code and it seems reusing has no influence for tests
behavior here.

> +		bops = buf_ops_create(intel_fd);
> +		bops2 = buf_ops_create(intel_fd2);
>  
>  		/* set up nouveau bufmgr */
>  		igt_assert(nouveau_device_wrap(nouveau_fd, 0, &ndev) >= 0);
> @@ -374,11 +401,6 @@ igt_main
>  		igt_assert(nouveau_device_wrap(nouveau_fd2, 0, &ndev2) >= 0);
>  
>  		igt_assert(nouveau_client_new(ndev2, &nclient2) >= 0);;
> -
> -		/* set up an intel batch buffer */
> -		devid = intel_get_drm_devid(intel_fd);
> -		intel_batch = intel_batchbuffer_alloc(bufmgr, devid);
> -		igt_assert(intel_batch);
>  	}
>  
>  #define xtest(name) \
> @@ -399,11 +421,8 @@ igt_main
>  	xtest(nv_self_import_to_different_fd);
>  	
>  	igt_fixture {
> -		intel_batchbuffer_free(intel_batch);
> -
>  		nouveau_device_del(&ndev);
> -		drm_intel_bufmgr_destroy(bufmgr);
> -
> +		buf_ops_destroy(bops);

bops2 also should be destroyed, someone missed releasing bufmgr2.

>  		close(intel_fd);
>  		close(nouveau_fd);
>  	}
> -- 
> 2.20.1
> 
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Re: [igt-dev] [PATCH i-g-t v4 23/25] tests/prime_nv_test.c: Remove libdrm dependency

[Zbigniew Kempczyński]

On Tue, Sep 22, 2020 at 01:52:27PM +0200, Dominik Grzegorzek wrote:
> Use intel_bb / intel_buf to remove libdrm dependency.
> 
> Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>  tests/prime_nv_test.c | 189 +++++++++++++++++++++++-------------------
>  1 file changed, 106 insertions(+), 83 deletions(-)

Generally same issues like previous review - alignment (0 instead 4096),
prime_handle_to_fd_for_mmap() and intel_buf size check is equal to BO_SIZE.

Prepare nv intel libdrm removal as separate series.

--
Zbigniew

> 
> diff --git a/tests/prime_nv_test.c b/tests/prime_nv_test.c
> index b4714dcb..37aea69d 100644
> --- a/tests/prime_nv_test.c
> +++ b/tests/prime_nv_test.c
> @@ -23,17 +23,17 @@
>  #include <sys/stat.h>
>  #include <sys/ioctl.h>
>  
> -#include "intel_bufmgr.h"
>  #include "nouveau.h"
>  
>  int intel_fd = -1, nouveau_fd = -1;
> -drm_intel_bufmgr *bufmgr;
> +struct buf_ops *bops;
>  struct nouveau_device *ndev;
>  struct nouveau_client *nclient;
> -uint32_t devid;
> -struct intel_batchbuffer *intel_batch;
> +struct intel_bb *ibb;
>  
> -#define BO_SIZE (256*1024)
> +#define WIDTH 256
> +#define HEIGHT 256
> +#define BO_SIZE (WIDTH*HEIGHT*4)
>  
>  static int find_and_open_devices(void)
>  {
> @@ -83,20 +83,21 @@ static int find_and_open_devices(void)
>   */
>  static void test_i915_nv_sharing(void)
>  {
> -	drm_intel_bo *test_intel_bo;
> +	struct intel_buf *test_intel_buf;
>  	int prime_fd;
>  	struct nouveau_bo *nvbo;
>  
> -	test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", BO_SIZE, 4096);
> -	igt_assert(test_intel_bo);
> +	test_intel_buf = intel_buf_create(bops, WIDTH, HEIGHT, 32, 4096,
> +					  I915_TILING_NONE,
> +					  I915_COMPRESSION_NONE);
>  
> -	drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd);
> +	prime_fd = prime_handle_to_fd(intel_fd, test_intel_buf->handle);
>  
>  	igt_assert(nouveau_bo_prime_handle_ref(ndev, prime_fd, &nvbo) == 0);
>  	close(prime_fd);
>  
>  	nouveau_bo_ref(NULL, &nvbo);
> -	drm_intel_bo_unreference(test_intel_bo);
> +	intel_buf_destroy(test_intel_buf);
>  }
>  
>  /*
> @@ -109,7 +110,8 @@ static void test_i915_nv_sharing(void)
>   */
>  static void test_nv_i915_sharing(void)
>  {
> -	drm_intel_bo *test_intel_bo;
> +	struct intel_buf *test_intel_buf;
> +	uint32_t handle;
>  	int prime_fd;
>  	struct nouveau_bo *nvbo;
>  
> @@ -117,12 +119,16 @@ static void test_nv_i915_sharing(void)
>  				  0, BO_SIZE, NULL, &nvbo) == 0);
>  	igt_assert(nouveau_bo_set_prime(nvbo, &prime_fd) == 0);
>  
> -	test_intel_bo = drm_intel_bo_gem_create_from_prime(bufmgr, prime_fd, BO_SIZE);
> +	handle = prime_fd_to_handle(intel_fd, prime_fd);
> +	test_intel_buf = intel_buf_create_using_handle(bops, handle, WIDTH,
> +						       HEIGHT, 32, 4096,
> +						       I915_TILING_NONE,
> +						       I915_COMPRESSION_NONE);
> +	intel_buf_set_ownership(test_intel_buf, true);
>  	close(prime_fd);
> -	igt_assert(test_intel_bo);
>  
>  	nouveau_bo_ref(NULL, &nvbo);
> -	drm_intel_bo_unreference(test_intel_bo);
> +	intel_buf_destroy(test_intel_buf);
>  }
>  
>  /*
> @@ -131,14 +137,16 @@ static void test_nv_i915_sharing(void)
>   */
>  static void test_nv_write_i915_cpu_mmap_read(void)
>  {
> -	drm_intel_bo *test_intel_bo;
> +	struct intel_buf *test_intel_buf;
>  	int prime_fd;
>  	struct nouveau_bo *nvbo = NULL;
>  	uint32_t *ptr;
>  
> -	test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", BO_SIZE, 4096);
> +	test_intel_buf = intel_buf_create(bops, WIDTH, HEIGHT, 32, 4096,
> +					  I915_TILING_NONE,
> +					  I915_COMPRESSION_NONE);
>  
> -	drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd);
> +	prime_fd = prime_handle_to_fd(intel_fd, test_intel_buf->handle);
>  
>  	igt_assert(nouveau_bo_prime_handle_ref(ndev, prime_fd, &nvbo) == 0);
>  	close(prime_fd);
> @@ -147,13 +155,14 @@ static void test_nv_write_i915_cpu_mmap_read(void)
>  	ptr = nvbo->map;
>  	*ptr = 0xdeadbeef;
>  
> -	drm_intel_bo_map(test_intel_bo, 1);
> -	ptr = test_intel_bo->virtual;
> +	intel_buf_cpu_map(test_intel_buf, true);
> +	ptr = test_intel_buf->ptr;
>  	igt_assert(ptr);
>  
>  	igt_assert(*ptr == 0xdeadbeef);
>  	nouveau_bo_ref(NULL, &nvbo);
> -	drm_intel_bo_unreference(test_intel_bo);
> +	intel_buf_unmap(test_intel_buf);
> +	intel_buf_destroy(test_intel_buf);
>  }
>  
>  /*
> @@ -162,14 +171,16 @@ static void test_nv_write_i915_cpu_mmap_read(void)
>   */
>  static void test_nv_write_i915_gtt_mmap_read(void)
>  {
> -	drm_intel_bo *test_intel_bo;
> +	struct intel_buf *test_intel_buf;
>  	int prime_fd;
>  	struct nouveau_bo *nvbo = NULL;
>  	uint32_t *ptr;
>  
> -	test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", BO_SIZE, 4096);
> +	test_intel_buf = intel_buf_create(bops, WIDTH, HEIGHT, 32, 4096,
> +					  I915_TILING_NONE,
> +					  I915_COMPRESSION_NONE);
>  
> -	drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd);
> +	prime_fd = prime_handle_to_fd(intel_fd, test_intel_buf->handle);
>  
>  	igt_assert(nouveau_bo_prime_handle_ref(ndev, prime_fd, &nvbo) == 0);
>  	close(prime_fd);
> @@ -177,14 +188,16 @@ static void test_nv_write_i915_gtt_mmap_read(void)
>  	ptr = nvbo->map;
>  	*ptr = 0xdeadbeef;
>  
> -	drm_intel_gem_bo_map_gtt(test_intel_bo);
> -	ptr = test_intel_bo->virtual;
> +	ptr = gem_mmap__gtt(intel_fd, test_intel_buf->handle,
> +			    test_intel_buf->surface[0].size, PROT_READ);
> +
>  	igt_assert(ptr);
>  
>  	igt_assert(*ptr == 0xdeadbeef);
>  
>  	nouveau_bo_ref(NULL, &nvbo);
> -	drm_intel_bo_unreference(test_intel_bo);
> +	gem_munmap(ptr, test_intel_buf->surface[0].size);
> +	intel_buf_destroy(test_intel_buf);
>  }
>  
>  /* test drm_intel_bo_map doesn't work properly,
> @@ -192,32 +205,37 @@ static void test_nv_write_i915_gtt_mmap_read(void)
>     for these objects */
>  static void test_i915_import_cpu_mmap(void)
>  {
> -	drm_intel_bo *test_intel_bo;
> +	struct intel_buf *test_intel_buf;
>  	int prime_fd;
>  	struct nouveau_bo *nvbo;
> -	uint32_t *ptr;
> +	uint32_t *ptr, handle;
>  
>  	igt_skip("cpu mmap support for imported dma-bufs not yet implemented\n");
>  
>  	igt_assert(nouveau_bo_new(ndev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP,
>  				  0, BO_SIZE, NULL, &nvbo) == 0);
>  	igt_assert(nouveau_bo_set_prime(nvbo, &prime_fd) == 0);
> -	test_intel_bo = drm_intel_bo_gem_create_from_prime(bufmgr, prime_fd, BO_SIZE);
> +
> +	handle = prime_fd_to_handle(intel_fd, prime_fd);
> +	test_intel_buf = intel_buf_create_using_handle(bops, handle, WIDTH,
> +						       HEIGHT, 32, 4096,
> +						       I915_TILING_NONE,
> +						       I915_COMPRESSION_NONE);
> +	intel_buf_set_ownership(test_intel_buf, true);
>  	close(prime_fd);
> -	igt_assert(test_intel_bo);
>  
>  	igt_assert(nouveau_bo_map(nvbo, NOUVEAU_BO_RDWR, nclient) == 0);
>  
>  	ptr = nvbo->map;
>  	*ptr = 0xdeadbeef;
>  
> -	igt_assert(drm_intel_bo_map(test_intel_bo, 0) == 0);
> -	igt_assert(test_intel_bo->virtual);
> -	ptr = test_intel_bo->virtual;
> +	intel_buf_cpu_map(test_intel_buf, false);
> +	ptr = test_intel_buf->ptr;
>  
>  	igt_assert(*ptr == 0xdeadbeef);
>  	nouveau_bo_ref(NULL, &nvbo);
> -	drm_intel_bo_unreference(test_intel_bo);
> +	intel_buf_unmap(test_intel_buf);
> +	intel_buf_destroy(test_intel_buf);
>  }
>  
>  /* test drm_intel_bo_map_gtt works properly,
> @@ -225,18 +243,22 @@ static void test_i915_import_cpu_mmap(void)
>     for these objects */
>  static void test_i915_import_gtt_mmap(void)
>  {
> -	drm_intel_bo *test_intel_bo;
> +	struct intel_buf *test_intel_buf;
>  	int prime_fd;
>  	struct nouveau_bo *nvbo;
> -	uint32_t *ptr;
> +	uint32_t *ptr, handle;
>  
>  	igt_assert(nouveau_bo_new(ndev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP,
>  				  0, BO_SIZE, NULL, &nvbo) == 0);
>  	igt_assert(nouveau_bo_set_prime(nvbo, &prime_fd) == 0);
>  
> -	test_intel_bo = drm_intel_bo_gem_create_from_prime(bufmgr, prime_fd, BO_SIZE);
> +	handle = prime_fd_to_handle(intel_fd, prime_fd);
> +	test_intel_buf = intel_buf_create_using_handle(bops, handle, WIDTH,
> +						       HEIGHT, 32, 4096,
> +						       I915_TILING_NONE,
> +						       I915_COMPRESSION_NONE);
> +	intel_buf_set_ownership(test_intel_buf, true);
>  	close(prime_fd);
> -	igt_assert(test_intel_bo);
>  
>  	igt_assert(nouveau_bo_map(nvbo, NOUVEAU_BO_RDWR, nclient) == 0);
>  
> @@ -244,107 +266,112 @@ static void test_i915_import_gtt_mmap(void)
>  	*ptr = 0xdeadbeef;
>  	*(ptr + 1) = 0xa55a55;
>  
> -	igt_assert(drm_intel_gem_bo_map_gtt(test_intel_bo) == 0);
> -	igt_assert(test_intel_bo->virtual);
> -	ptr = test_intel_bo->virtual;
> +	ptr = gem_mmap__gtt(intel_fd, test_intel_buf->handle,
> +			    test_intel_buf->surface[0].size, PROT_READ);
>  
>  	igt_assert(*ptr == 0xdeadbeef);
>  	nouveau_bo_ref(NULL, &nvbo);
> -	drm_intel_bo_unreference(test_intel_bo);
> +	gem_munmap(ptr, test_intel_buf->surface[0].size);
> +	intel_buf_destroy(test_intel_buf);
>  }
>  
>  /* test 7 - import from nouveau into intel, test pread/pwrite fail */
>  static void test_i915_import_pread_pwrite(void)
>  {
> -	drm_intel_bo *test_intel_bo;
> +	struct intel_buf *test_intel_buf;
>  	int prime_fd;
>  	struct nouveau_bo *nvbo;
> -	uint32_t *ptr;
> +	uint32_t *ptr, handle;
>  	uint32_t buf[64];
>  
>  	igt_assert(nouveau_bo_new(ndev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP,
>  				  0, BO_SIZE, NULL, &nvbo) == 0);
>  	igt_assert(nouveau_bo_set_prime(nvbo, &prime_fd) == 0);
>  
> -	test_intel_bo = drm_intel_bo_gem_create_from_prime(bufmgr, prime_fd, BO_SIZE);
> +	handle = prime_fd_to_handle(intel_fd, prime_fd);
> +	test_intel_buf = intel_buf_create_using_handle(bops, handle, WIDTH,
> +						       HEIGHT, 32, 4096,
> +						       I915_TILING_NONE,
> +						       I915_COMPRESSION_NONE);
> +	intel_buf_set_ownership(test_intel_buf, true);
>  	close(prime_fd);
> -	igt_assert(test_intel_bo);
>  
>  	igt_assert(nouveau_bo_map(nvbo, NOUVEAU_BO_RDWR, nclient) == 0);
>  
>  	ptr = nvbo->map;
>  	*ptr = 0xdeadbeef;
>  
> -	gem_read(intel_fd, test_intel_bo->handle, 0, buf, 256);
> +	gem_read(intel_fd, test_intel_buf->handle, 0, buf, 256);
>  	igt_assert(buf[0] == 0xdeadbeef);
>  	buf[0] = 0xabcdef55;
>  
> -	gem_write(intel_fd, test_intel_bo->handle, 0, buf, 4);
> +	gem_write(intel_fd, test_intel_buf->handle, 0, buf, 4);
>  
>  	igt_assert(*ptr == 0xabcdef55);
>  
>  	nouveau_bo_ref(NULL, &nvbo);
> -	drm_intel_bo_unreference(test_intel_bo);
> +	intel_buf_destroy(test_intel_buf);
>  }
>  
>  static void
> -set_bo(drm_intel_bo *bo, uint32_t val, int width, int height)
> +set_bo(struct intel_buf *buf, uint32_t val, int width, int height)
>  {
> -        int size = width * height;
> -        uint32_t *vaddr;
> +	int size = width * height;
> +	uint32_t *vaddr;
> +
> +	vaddr = gem_mmap__gtt(intel_fd, buf->handle, buf->surface[0].size,
> +			      PROT_WRITE);
> +	while (size--)
> +		*vaddr++ = val;
>  
> -        drm_intel_gem_bo_start_gtt_access(bo, true);
> -        vaddr = bo->virtual;
> -        while (size--)
> -                *vaddr++ = val;
> +	gem_munmap(vaddr, buf->surface[0].size);
>  }
>  
> -static drm_intel_bo *
> -create_bo(drm_intel_bufmgr *ibufmgr, uint32_t val, int width, int height)
> +static struct intel_buf *
> +create_bo(struct buf_ops *ibops, uint32_t val, int width, int height)
>  {
> -        drm_intel_bo *bo;
> -
> -        bo = drm_intel_bo_alloc(ibufmgr, "bo", 4*width*height, 0);
> -        igt_assert(bo);
> +	struct intel_buf *buf;
>  
> -        /* gtt map doesn't have a write parameter, so just keep the mapping
> -         * around (to avoid the set_domain with the gtt write domain set) and
> -         * manually tell the kernel when we start access the gtt. */
> -        drm_intel_gem_bo_map_gtt(bo);
> +	buf = intel_buf_create(ibops, width, height, 32, 0, I915_TILING_NONE,
> +			       I915_COMPRESSION_NONE);
>  
> -        set_bo(bo, val, width, height);
> +	set_bo(buf, val, width, height);
>  
> -        return bo;
> +	return buf;
>  }
>  
>  /* use intel hw to fill the BO with a blit from another BO,
>     then readback from the nouveau bo, check value is correct */
>  static void test_i915_blt_fill_nv_read(void)
>  {
> -	drm_intel_bo *test_intel_bo, *src_bo;
> +	struct intel_buf *test_intel_buf, *src_buf;
>  	int prime_fd;
>  	struct nouveau_bo *nvbo = NULL;
>  	uint32_t *ptr;
>  
> -	src_bo = create_bo(bufmgr, 0xaa55aa55, 256, 1);
> +	src_buf = create_bo(bops, 0xaa55aa55, 256, 1);
>  
> -	test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", BO_SIZE, 4096);
> +	test_intel_buf = intel_buf_create(bops, WIDTH, HEIGHT, 32, 4096,
> +					  I915_TILING_NONE,
> +					  I915_COMPRESSION_NONE);
>  
> -	drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd);
> +	prime_fd = prime_handle_to_fd(intel_fd, test_intel_buf->handle);
>  
>  	igt_assert(nouveau_bo_prime_handle_ref(ndev, prime_fd, &nvbo) == 0);
>  	close(prime_fd);
>  
> -	intel_copy_bo(intel_batch, test_intel_bo, src_bo, BO_SIZE);
> +	intel_bb_copy_intel_buf(ibb, test_intel_buf, src_buf,
> +				src_buf->surface[0].size);
>  
>  	igt_assert(nouveau_bo_map(nvbo, NOUVEAU_BO_RDWR, nclient) == 0);
>  
> -	drm_intel_bo_map(test_intel_bo, 0);
> +	intel_buf_cpu_map(test_intel_buf, 0);
>  
>  	ptr = nvbo->map;
>  	igt_assert(*ptr == 0xaa55aa55);
>  	nouveau_bo_ref(NULL, &nvbo);
> -	drm_intel_bo_unreference(test_intel_bo);
> +	intel_buf_unmap(test_intel_buf);
> +	intel_buf_destroy(test_intel_buf);
>  }
>  
>  /* test 8 use nouveau to do blit */
> @@ -360,18 +387,14 @@ igt_main
>  		igt_require(intel_fd != -1);
>  
>  		/* set up intel bufmgr */
> -		bufmgr = drm_intel_bufmgr_gem_init(intel_fd, 4096);
> -		igt_assert(bufmgr);
> -		/* Do not enable reuse, we share (almost) all buffers. */
> -		//drm_intel_bufmgr_gem_enable_reuse(bufmgr);
> +		bops = buf_ops_create(intel_fd);
>  
>  		/* set up nouveau bufmgr */
>  		igt_assert(nouveau_device_wrap(nouveau_fd, 0, &ndev) == 0);
>  		igt_assert(nouveau_client_new(ndev, &nclient) == 0);
>  
>  		/* set up an intel batch buffer */
> -		devid = intel_get_drm_devid(intel_fd);
> -		intel_batch = intel_batchbuffer_alloc(bufmgr, devid);
> +		ibb = intel_bb_create(intel_fd, 4096);
>  	}
>  
>  #define xtest(name) \
> @@ -388,10 +411,10 @@ igt_main
>  	xtest(i915_blt_fill_nv_read);
>  
>  	igt_fixture {
> -		intel_batchbuffer_free(intel_batch);
> +		intel_bb_destroy(ibb);
>  
>  		nouveau_device_del(&ndev);
> -		drm_intel_bufmgr_destroy(bufmgr);
> +		buf_ops_destroy(bops);
>  
>  		close(intel_fd);
>  		close(nouveau_fd);
> -- 
> 2.20.1
> 
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Re: [igt-dev] [PATCH i-g-t v4 24/25] tests/i915/gem_ppgtt: make copying more readable

[Zbigniew Kempczyński]

On Tue, Sep 22, 2020 at 01:52:28PM +0200, Dominik Grzegorzek wrote:
> Use intel_bb_copy_intel_buf instead of intel_bb_blit_copy
> to make the code simplier.
> 
> Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>  tests/i915/gem_ppgtt.c | 16 ++++------------
>  1 file changed, 4 insertions(+), 12 deletions(-)
> 
> diff --git a/tests/i915/gem_ppgtt.c b/tests/i915/gem_ppgtt.c
> index 949601ac..8d7e1a81 100644
> --- a/tests/i915/gem_ppgtt.c
> +++ b/tests/i915/gem_ppgtt.c
> @@ -165,12 +165,8 @@ static void fork_bcs_copy(int timeout, uint32_t final,
>  			src[1] = create_bo(dst[child]->bops,
>  					   i++ | child << 16);
>  
> -			intel_bb_blt_copy(ibb, src[1], 0, 0, 4096,
> -					  src[0], 0, 0, 4096,
> -					  4096/4, SIZE/4096, 32);
> -			intel_bb_blt_copy(ibb, src[0], 0, 0, 4096,
> -					  dst[child], 0, 0, 4096,
> -					  4096/4, SIZE/4096, 32);
> +			intel_bb_copy_intel_buf(ibb, src[0], src[1], SIZE);
> +			intel_bb_copy_intel_buf(ibb, dst[child], src[0], SIZE);
>  
>  			intel_buf_destroy(src[1]);
>  			intel_buf_destroy(src[0]);
> @@ -180,12 +176,8 @@ static void fork_bcs_copy(int timeout, uint32_t final,
>  		src[1] = create_bo(dst[child]->bops,
>  				   final | child << 16);
>  
> -		intel_bb_blt_copy(ibb, src[1], 0, 0, 4096,
> -				  src[0], 0, 0, 4096,
> -				  4096/4, SIZE/4096, 32);
> -		intel_bb_blt_copy(ibb, src[0], 0, 0, 4096,
> -				  dst[child], 0, 0, 4096,
> -				  4096/4, SIZE/4096, 32);
> +		intel_bb_copy_intel_buf(ibb, src[0], src[1], SIZE);
> +		intel_bb_copy_intel_buf(ibb, dst[child], src[0], SIZE);

I just realized intel_bb_blt_copy() uses src -> dst, but here we have
dst <- src which can be confusing in the future. 

As intel_bb_copy_intel_buf() is not yet merged I suggest to change 
arguments order to be consistent in intel_bb_blt_copy() api.

--
Zbigniew

>  
>  		intel_buf_destroy(src[1]);
>  		intel_buf_destroy(src[0]);
> -- 
> 2.20.1
> 
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Re: [igt-dev] [PATCH i-g-t v4 19/25] tools/intel_perf_counters: Remove libdrm dependency

[Zbigniew Kempczyński]

On Tue, Sep 22, 2020 at 01:52:23PM +0200, Dominik Grzegorzek wrote:
> Use intel_bb / intel_buf to remove libdrm dependency.
> 
> Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>  tools/intel_perf_counters.c | 109 ++++++++++++++++++------------------
>  1 file changed, 56 insertions(+), 53 deletions(-)
> 
> diff --git a/tools/intel_perf_counters.c b/tools/intel_perf_counters.c
> index 5824d9c1..6273aecd 100644
> --- a/tools/intel_perf_counters.c
> +++ b/tools/intel_perf_counters.c
> @@ -46,9 +46,9 @@
>  #include "i915_drm.h"
>  #include "drmtest.h"
>  #include "intel_io.h"
> -#include "intel_bufmgr.h"
>  #include "intel_batchbuffer.h"
>  #include "intel_chipset.h"
> +#include "intel_bufops.h"
>  
>  #define GEN5_COUNTER_COUNT 29
>  
> @@ -298,8 +298,8 @@ const int gen7_counter_format = 5; /* 0b101 */
>  int have_totals = 0;
>  uint32_t *totals;
>  uint32_t *last_counter;
> -static drm_intel_bufmgr *bufmgr;
> -struct intel_batchbuffer *batch;
> +static struct buf_ops *bops;
> +static struct intel_bb *ibb;
>  
>  /* DW0 */
>  #define GEN5_MI_REPORT_PERF_COUNT ((0x26 << 23) | (3 - 2))
> @@ -327,30 +327,30 @@ static void
>  gen5_get_counters(void)
>  {
>  	int i;
> -	drm_intel_bo *stats_bo;
> +	struct intel_buf *stats_buf;
>  	uint32_t *stats_result;
>  
> -	stats_bo = drm_intel_bo_alloc(bufmgr, "stats", 4096, 4096);
> +	stats_buf = intel_buf_create(bops, 32, 32, 32, 4096, I915_TILING_NONE,
> +				     I915_COMPRESSION_NONE);

I would create using (it is easier to calculate real size): 

	stats_buf = intel_buf_create(bops, 4096, 1, 8, 0, I915_TILING_NONE,
				     I915_COMPRESSION_NONE);

>  
> -	BEGIN_BATCH(6, 2);
> -	OUT_BATCH(GEN5_MI_REPORT_PERF_COUNT | MI_COUNTER_SET_0);
> -	OUT_RELOC(stats_bo,
> -		  I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
> -		  0);
> -	OUT_BATCH(0);
>  
> -	OUT_BATCH(GEN5_MI_REPORT_PERF_COUNT | MI_COUNTER_SET_1);
> -	OUT_RELOC(stats_bo,
> -		  I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
> -		  64);
> -	OUT_BATCH(0);
> +	intel_bb_out(ibb, GEN5_MI_REPORT_PERF_COUNT | MI_COUNTER_SET_0);
> +	intel_bb_emit_reloc(ibb, stats_buf->handle, I915_GEM_DOMAIN_INSTRUCTION,
> +			    I915_GEM_DOMAIN_INSTRUCTION, 0,
> +			    stats_buf->addr.offset);
> +	intel_bb_out(ibb, 0);
>  
> -	ADVANCE_BATCH();
> +	intel_bb_out(ibb, GEN5_MI_REPORT_PERF_COUNT | MI_COUNTER_SET_1);
> +	intel_bb_emit_reloc(ibb, stats_buf->handle, I915_GEM_DOMAIN_INSTRUCTION,
> +			    I915_GEM_DOMAIN_INSTRUCTION, 64,
> +			    stats_buf->addr.offset);
> +	intel_bb_out(ibb, 0);
>  
> -	intel_batchbuffer_flush(batch);
> +	intel_bb_flush_blit(ibb);
> +	intel_bb_sync(ibb);

No sync here.

>  
> -	drm_intel_bo_map(stats_bo, 0);
> -	stats_result = stats_bo->virtual;
> +	intel_buf_cpu_map(stats_buf, false);
> +	stats_result = stats_buf->ptr;
>  	/* skip REPORT_ID, TIMESTAMP */
>  	stats_result += 3;
>  	for (i = 0 ; i < GEN5_COUNTER_COUNT; i++) {
> @@ -358,15 +358,15 @@ gen5_get_counters(void)
>  		last_counter[i] = stats_result[i];
>  	}
>  
> -	drm_intel_bo_unmap(stats_bo);
> -	drm_intel_bo_unreference(stats_bo);
> +	intel_buf_unmap(stats_buf);
> +	intel_buf_destroy(stats_buf);
>  }
>  
>  static void
>  gen6_get_counters(void)
>  {
>  	int i;
> -	drm_intel_bo *stats_bo;
> +	struct intel_buf *stats_buf;
>  	uint32_t *stats_result;
>  
>  	/* Map from counter names to their index in the buffer object */
> @@ -378,49 +378,49 @@ gen6_get_counters(void)
>  		31, 30, 29, 28, 27, 26, 25, 24,
>  	};
>  
> -	stats_bo = drm_intel_bo_alloc(bufmgr, "stats", 4096, 4096);
> +	stats_buf = intel_buf_create(bops, 32, 32, 32, 4096, I915_TILING_NONE,
> +				     I915_COMPRESSION_NONE);

4096, 1, 8, 0


> +	intel_bb_out(ibb, GEN6_MI_REPORT_PERF_COUNT | (3 - 2));
> +	intel_bb_emit_reloc(ibb, stats_buf->handle, I915_GEM_DOMAIN_INSTRUCTION,
> +			    I915_GEM_DOMAIN_INSTRUCTION,
> +			    MI_COUNTER_ADDRESS_GTT, stats_buf->addr.offset);
> +	intel_bb_out(ibb, 0);
>  
> -	BEGIN_BATCH(3, 1);
> -	OUT_BATCH(GEN6_MI_REPORT_PERF_COUNT | (3 - 2));
> -	OUT_RELOC(stats_bo,
> -		  I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
> -		  MI_COUNTER_ADDRESS_GTT);
> -	OUT_BATCH(0);
> -	ADVANCE_BATCH();
> +	intel_bb_flush_render(ibb);
> +	intel_bb_sync(ibb);

No sync.

>  
> -	intel_batchbuffer_flush_on_ring(batch, I915_EXEC_RENDER);
> -
> -	drm_intel_bo_map(stats_bo, 0);
> -	stats_result = stats_bo->virtual;
> +	intel_buf_cpu_map(stats_buf, 0);
> +	stats_result = stats_buf->ptr;
>  	for (i = 0; i < GEN6_COUNTER_COUNT; i++) {
>  		totals[i] += stats_result[buffer_index[i]] - last_counter[i];
>  		last_counter[i] = stats_result[buffer_index[i]];
>  	}
>  
> -	drm_intel_bo_unmap(stats_bo);
> -	drm_intel_bo_unreference(stats_bo);
> +	intel_buf_unmap(stats_buf);
> +	intel_buf_destroy(stats_buf);
>  }
>  
>  static void
>  gen7_get_counters(void)
>  {
>  	int i;
> -	drm_intel_bo *stats_bo;
> +	struct intel_buf *stats_buf;
>  	uint32_t *stats_result;
>  
> -	stats_bo = drm_intel_bo_alloc(bufmgr, "stats", 4096, 4096);
> +	stats_buf = intel_buf_create(bops, 32, 32, 32, 4096, I915_TILING_NONE,
> +				     I915_COMPRESSION_NONE);
>  
> -	BEGIN_BATCH(3, 1);
> -	OUT_BATCH(GEN6_MI_REPORT_PERF_COUNT | (3 - 2));
> -	OUT_RELOC(stats_bo,
> -		  I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0);
> -	OUT_BATCH(0);
> -	ADVANCE_BATCH();
> +	intel_bb_out(ibb, GEN6_MI_REPORT_PERF_COUNT | (3 - 2));
> +	intel_bb_emit_reloc(ibb, stats_buf->handle, I915_GEM_DOMAIN_INSTRUCTION,
> +			    I915_GEM_DOMAIN_INSTRUCTION, 0,
> +			    stats_buf->addr.offset);
> +	intel_bb_out(ibb, 0);
>  
> -	intel_batchbuffer_flush_on_ring(batch, I915_EXEC_RENDER);
> +	intel_bb_flush_render(ibb);
> +	intel_bb_sync(ibb);

Same as above.

--
Zbigniew

>  
> -	drm_intel_bo_map(stats_bo, 0);
> -	stats_result = stats_bo->virtual;
> +	intel_buf_cpu_map(stats_buf, false);
> +	stats_result = stats_buf->ptr;
>  	/* skip REPORT_ID, TIMESTAMP */
>  	stats_result += 3;
>  	for (i = 0; i < GEN7_COUNTER_COUNT; i++) {
> @@ -431,8 +431,8 @@ gen7_get_counters(void)
>  		last_counter[i] = stats_result[i];
>  	}
>  
> -	drm_intel_bo_unmap(stats_bo);
> -	drm_intel_bo_unreference(stats_bo);
> +	intel_buf_unmap(stats_buf);
> +	intel_buf_destroy(stats_buf);
>  }
>  
>  #define STATS_CHECK_FREQUENCY	100
> @@ -458,9 +458,8 @@ main(int argc, char **argv)
>  	fd = drm_open_driver(DRIVER_INTEL);
>  	devid = intel_get_drm_devid(fd);
>  
> -	bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
> -	drm_intel_bufmgr_gem_enable_reuse(bufmgr);
> -	batch = intel_batchbuffer_alloc(bufmgr, devid);
> +	bops = buf_ops_create(fd);
> +	ibb = intel_bb_create(fd, 4096);
>  
>  	if (IS_GEN5(devid)) {
>  		counter_name = gen5_counter_names;
> @@ -531,5 +530,9 @@ main(int argc, char **argv)
>  	free(totals);
>  	free(last_counter);
>  
> +	intel_bb_destroy(ibb);
> +	buf_ops_destroy(bops);
> +	close(fd);
> +
>  	return 0;
>  }
> -- 
> 2.20.1
> 
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