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* [PATCH v8 0/2] Basic Kontron SMARC-sAL28 board support
@ 2020-09-25 11:51 Michael Walle
  2020-09-25 11:51 ` [PATCH v8 1/2] board: kontron: add sl28 support Michael Walle
  2020-09-25 11:51 ` [PATCH v8 2/2] board: sl28: add board specific nvm command Michael Walle
  0 siblings, 2 replies; 3+ messages in thread
From: Michael Walle @ 2020-09-25 11:51 UTC (permalink / raw)
  To: u-boot

Add basic board support for the Kontron SMARC-sAL28 board. Please note,
that this board doesn't support TF-a (yet). Therefore, the u-boot SPL is
the first code which is run and it has to set up the RAM.

changes since v7:
 - removed CONFIG_WDT for now until the watchdog issue is clarified
 - enabled EFIDEBUG and NVEDIT_EFI
 - disabled EFI_LOADER_BOUNCE_BUFFER, doesn't help in my case,
   because efi_load_image() will still do DMA transfers with 64bit
   addresses. ADMA2 (with 64bit address support) support for the
   eSDHC is on the way.

changes since v6:
 - moved README to doc/board/kontron/sl28.rst
 - added device tree files to MAINTAINERS
 - converted preprocessor macros to actual code using IS_ENABLED()
 - fixed sec_init(), use CONFIG_IS_ENABLED() instead of IS_ENABLED()
 - removed unnecessary #ifdef CONFIG_OF_BOARD_SETUP
 - removed CONFIG_SPL_TARGET, because we use binman, this is not needed
   anymore
 - removed unnecessary CONFIG_SYS_MONITOR_BASE macro
 - redefinded memory addresses according to the comment in
   ti_armv7_common.h
 - removed empty BOOTENV for SPL build
 - removed fdt_high and initrd_high
Thanks Tom!

changes since v5:
 - moved CONFIG_ENV_OVERWRITE to defconfig. Thanks Kuldeep!

changes since v4:
 - dropped "armv8: ls1028a: move FSL_LAYERSCAPE to kconfig" as it is
   already upstream
 - new patch "board: sl28: add board specific nvm command"
 - use binman
 - sync device trees with linux
 - use "<devicetree>-u-boot.dtsi" style
 - rebase to lastest master

changes since v3:
 - rebase to latest master
 - use CONFIG_PCI_INIT_R
 - set fdtfile in default environment

changes since v2:
 - add variant 4 support. Since the atheros PHY dt bindings were merged
   into master, we can now use them
 - add environment section in include/configs/kontron_sl28.h
 - add cover letter

changes since v1:
 - fix watchdog device tree reference

Michael Walle (2):
  board: kontron: add sl28 support
  board: sl28: add board specific nvm command

 arch/arm/Kconfig                              |  11 +
 arch/arm/dts/Makefile                         |   3 +
 .../dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi  | 135 +++++++++++++
 .../fsl-ls1028a-kontron-sl28-var3-u-boot.dtsi |   2 +
 .../arm/dts/fsl-ls1028a-kontron-sl28-var3.dts |  15 ++
 .../fsl-ls1028a-kontron-sl28-var4-u-boot.dtsi |   2 +
 .../arm/dts/fsl-ls1028a-kontron-sl28-var4.dts |  48 +++++
 arch/arm/dts/fsl-ls1028a-kontron-sl28.dts     | 189 ++++++++++++++++++
 board/kontron/sl28/Kconfig                    |  18 ++
 board/kontron/sl28/MAINTAINERS                |   7 +
 board/kontron/sl28/Makefile                   |   8 +
 board/kontron/sl28/cmds.c                     | 178 +++++++++++++++++
 board/kontron/sl28/common.c                   |  10 +
 board/kontron/sl28/ddr.c                      |  98 +++++++++
 board/kontron/sl28/sl28.c                     |  68 +++++++
 board/kontron/sl28/spl.c                      |  32 +++
 configs/kontron_sl28_defconfig                | 105 ++++++++++
 doc/board/index.rst                           |   1 +
 doc/board/kontron/index.rst                   |   9 +
 doc/board/kontron/sl28.rst                    | 160 +++++++++++++++
 include/configs/kontron_sl28.h                | 108 ++++++++++
 21 files changed, 1207 insertions(+)
 create mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi
 create mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28-var3-u-boot.dtsi
 create mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28-var3.dts
 create mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28-var4-u-boot.dtsi
 create mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts
 create mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28.dts
 create mode 100644 board/kontron/sl28/Kconfig
 create mode 100644 board/kontron/sl28/MAINTAINERS
 create mode 100644 board/kontron/sl28/Makefile
 create mode 100644 board/kontron/sl28/cmds.c
 create mode 100644 board/kontron/sl28/common.c
 create mode 100644 board/kontron/sl28/ddr.c
 create mode 100644 board/kontron/sl28/sl28.c
 create mode 100644 board/kontron/sl28/spl.c
 create mode 100644 configs/kontron_sl28_defconfig
 create mode 100644 doc/board/kontron/index.rst
 create mode 100644 doc/board/kontron/sl28.rst
 create mode 100644 include/configs/kontron_sl28.h

-- 
2.20.1

^ permalink raw reply	[flat|nested] 3+ messages in thread
* [PATCH v8 1/2] board: kontron: add sl28 support
  2020-09-25 11:51 [PATCH v8 0/2] Basic Kontron SMARC-sAL28 board support Michael Walle
@ 2020-09-25 11:51 ` Michael Walle
  2020-09-25 11:51 ` [PATCH v8 2/2] board: sl28: add board specific nvm command Michael Walle
  1 sibling, 0 replies; 3+ messages in thread
From: Michael Walle @ 2020-09-25 11:51 UTC (permalink / raw)
  To: u-boot

Add basic support for the Kontron SMARC-sAL28 board. This includes just
the bare minimum to be able to bring up the board and boot linux.

For now, the Single and Dual PHY variant is supported. Other variants
will fall back to the basic variant.

In particular, there is no watchdog support for now. This means that you
have to disable the default watchdog, otherwise you'll end up in the
recovery bootloader. See the board README for details.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Tom Rini <trini@konsulko.com>
Tested-by: Heiko Thiery <heiko.thiery@gmail.com>
---
 arch/arm/Kconfig                              |  11 +
 arch/arm/dts/Makefile                         |   3 +
 .../dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi  | 135 +++++++++++++
 .../fsl-ls1028a-kontron-sl28-var3-u-boot.dtsi |   2 +
 .../arm/dts/fsl-ls1028a-kontron-sl28-var3.dts |  15 ++
 .../fsl-ls1028a-kontron-sl28-var4-u-boot.dtsi |   2 +
 .../arm/dts/fsl-ls1028a-kontron-sl28-var4.dts |  48 +++++
 arch/arm/dts/fsl-ls1028a-kontron-sl28.dts     | 189 ++++++++++++++++++
 board/kontron/sl28/Kconfig                    |  18 ++
 board/kontron/sl28/MAINTAINERS                |   7 +
 board/kontron/sl28/Makefile                   |   8 +
 board/kontron/sl28/common.c                   |  10 +
 board/kontron/sl28/ddr.c                      |  98 +++++++++
 board/kontron/sl28/sl28.c                     |  68 +++++++
 board/kontron/sl28/spl.c                      |  32 +++
 configs/kontron_sl28_defconfig                | 105 ++++++++++
 doc/board/index.rst                           |   1 +
 doc/board/kontron/index.rst                   |   9 +
 doc/board/kontron/sl28.rst                    | 160 +++++++++++++++
 include/configs/kontron_sl28.h                | 108 ++++++++++
 20 files changed, 1029 insertions(+)
 create mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi
 create mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28-var3-u-boot.dtsi
 create mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28-var3.dts
 create mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28-var4-u-boot.dtsi
 create mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts
 create mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28.dts
 create mode 100644 board/kontron/sl28/Kconfig
 create mode 100644 board/kontron/sl28/MAINTAINERS
 create mode 100644 board/kontron/sl28/Makefile
 create mode 100644 board/kontron/sl28/common.c
 create mode 100644 board/kontron/sl28/ddr.c
 create mode 100644 board/kontron/sl28/sl28.c
 create mode 100644 board/kontron/sl28/spl.c
 create mode 100644 configs/kontron_sl28_defconfig
 create mode 100644 doc/board/kontron/index.rst
 create mode 100644 doc/board/kontron/sl28.rst
 create mode 100644 include/configs/kontron_sl28.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 80702c23d3..f57d48800d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1615,6 +1615,16 @@ config TARGET_LS1046AFRWY
 	  development platform that supports the QorIQ LS1046A
 	  Layerscape Architecture processor.
 
+config TARGET_SL28
+	bool "Support sl28"
+	select ARCH_LS1028A
+	select ARM64
+	select ARMV8_MULTIENTRY
+	select SUPPORT_SPL
+	select BINMAN
+	help
+	  Support for Kontron SMARC-sAL28 board.
+
 config TARGET_COLIBRI_PXA270
 	bool "Support colibri_pxa270"
 	select CPU_PXA
@@ -1986,6 +1996,7 @@ source "board/hisilicon/hikey/Kconfig"
 source "board/hisilicon/hikey960/Kconfig"
 source "board/hisilicon/poplar/Kconfig"
 source "board/isee/igep003x/Kconfig"
+source "board/kontron/sl28/Kconfig"
 source "board/myir/mys_6ulx/Kconfig"
 source "board/spear/spear300/Kconfig"
 source "board/spear/spear310/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index f8f529435b..b45eb6a772 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -422,6 +422,9 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
 	fsl-ls1012a-2g5rdb.dtb \
 	fsl-ls1012a-frdm.dtb \
 	fsl-ls1012a-frwy.dtb
+dtb-$(CONFIG_TARGET_SL28) += fsl-ls1028a-kontron-sl28.dtb \
+	fsl-ls1028a-kontron-sl28-var3.dtb \
+	fsl-ls1028a-kontron-sl28-var4.dtb \
 
 dtb-$(CONFIG_TARGET_DRAGONBOARD410C) += dragonboard410c.dtb
 dtb-$(CONFIG_TARGET_DRAGONBOARD820C) += dragonboard820c.dtb
diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi
new file mode 100644
index 0000000000..2375549c6e
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <config.h>
+
+/ {
+	aliases {
+		mmc0 = &esdhc0;
+		mmc1 = &esdhc1;
+		i2c0 = &i2c0;
+		i2c1 = &i2c3;
+		i2c2 = &i2c4;
+		rtc0 = &rtc;
+		ethernet0 = &enetc0;
+		ethernet1 = &enetc1;
+		ethernet2 = &enetc2;
+		ethernet3 = &enetc6;
+	};
+
+	binman {
+		filename = "u-boot.rom";
+		pad-byte = <0xff>;
+
+		u-boot-spl {
+		};
+
+		fit {
+			offset = <CONFIG_SPL_PAD_TO>;
+			description = "FIT image with multiple configurations";
+
+			images {
+				uboot {
+					description = "U-Boot";
+					type = "firmware";
+					os = "u-boot";
+					arch = "arm";
+					compression = "none";
+					load = <CONFIG_SYS_TEXT_BASE>;
+
+					u-boot-nodtb {
+					};
+				};
+
+				fdt-1 {
+					description = "fsl-ls1028a-kontron-sl28";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+
+					blob {
+						filename = "arch/arm/dts/fsl-ls1028a-kontron-sl28.dtb";
+					};
+				};
+
+				fdt-2 {
+					description = "fsl-ls1028a-kontron-sl28-var3";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+
+					blob {
+						filename = "arch/arm/dts/fsl-ls1028a-kontron-sl28-var3.dtb";
+					};
+				};
+
+				fdt-3 {
+					description = "fsl-ls1028a-kontron-sl28-var4";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+
+					blob {
+						filename = "arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dtb";
+					};
+				};
+			};
+
+			configurations {
+				default = "conf-1";
+
+				conf-1 {
+					description = "fsl-ls1028a-kontron-sl28";
+					firmware = "uboot";
+					loadables = "uboot";
+					fdt = "fdt-1";
+				};
+
+				conf-2 {
+					description = "fsl-ls1028a-kontron-sl28-var3";
+					firmware = "uboot";
+					loadables = "uboot";
+					fdt = "fdt-2";
+				};
+
+				conf-3 {
+					description = "fsl-ls1028a-kontron-sl28-var4";
+					firmware = "uboot";
+					loadables = "uboot";
+					fdt = "fdt-3";
+				};
+			};
+		};
+	};
+};
+
+&i2c0 {
+	rtc: rtc at 32 {
+	};
+};
+
+&fspi {
+	u-boot,dm-pre-reloc;
+	flash at 0 {
+		u-boot,dm-pre-reloc;
+	};
+};
+
+&dspi2 {
+	u-boot,dm-pre-reloc;
+};
+
+&esdhc0 {
+	u-boot,dm-pre-reloc;
+};
+
+&esdhc1 {
+	u-boot,dm-pre-reloc;
+};
+
+&serial0 {
+	u-boot,dm-pre-reloc;
+};
+
+&sysclk {
+	u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var3-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var3-u-boot.dtsi
new file mode 100644
index 0000000000..79b771e074
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var3-u-boot.dtsi
@@ -0,0 +1,2 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include "fsl-ls1028a-kontron-sl28-u-boot.dtsi"
diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var3.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var3.dts
new file mode 100644
index 0000000000..0c8b2af41a
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var3.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Device Tree file for the Kontron SMARC-sAL28 board.
+ *
+ * Copyright (C) 2019 Michael Walle <michael@walle.cc>
+ *
+ */
+
+/dts-v1/;
+#include "fsl-ls1028a-kontron-sl28.dts"
+
+/ {
+	model = "Kontron SMARC-sAL28 (Single PHY)";
+	compatible = "kontron,sl28-var3", "kontron,sl28", "fsl,ls1028a";
+};
diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4-u-boot.dtsi
new file mode 100644
index 0000000000..79b771e074
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4-u-boot.dtsi
@@ -0,0 +1,2 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include "fsl-ls1028a-kontron-sl28-u-boot.dtsi"
diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts
new file mode 100644
index 0000000000..33b16303ad
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Device Tree file for the Kontron SMARC-sAL28 board.
+ *
+ * This is for the network variant 4 which has two ethernet ports. It
+ * extends the base and provides one more port connected via RGMII.
+ *
+ * Copyright (C) 2019 Michael Walle <michael@walle.cc>
+ *
+ */
+
+/dts-v1/;
+#include "fsl-ls1028a-kontron-sl28.dts"
+#include <dt-bindings/net/qca-ar803x.h>
+
+/ {
+	model = "Kontron SMARC-sAL28 (Dual PHY)";
+	compatible = "kontron,sl28-var4", "kontron,sl28", "fsl,ls1028a";
+};
+
+&enetc1 {
+	phy-handle = <&phy1>;
+	phy-mode = "rgmii-id";
+	status = "okay";
+};
+
+&mdio0 {
+	phy1: ethernet-phy at 4 {
+		reg = <0x4>;
+		eee-broken-1000t;
+		eee-broken-100tx;
+
+		qca,clk-out-frequency = <125000000>;
+		qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
+
+		vddio-supply = <&vddh>;
+
+		vddio: vddio-regulator {
+			regulator-name = "VDDIO";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+		};
+
+		vddh: vddh-regulator {
+			regulator-name = "VDDH";
+		};
+	};
+};
diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28.dts
new file mode 100644
index 0000000000..9561a58562
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28.dts
@@ -0,0 +1,189 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Device Tree file for the Kontron SMARC-sAL28 board.
+ *
+ * Copyright (C) 2019 Michael Walle <michael@walle.cc>
+ *
+ */
+
+/dts-v1/;
+#include "fsl-ls1028a.dtsi"
+
+/ {
+	model = "Kontron SMARC-sAL28";
+	compatible = "kontron,sl28", "fsl,ls1028a";
+
+	aliases {
+		serial0 = &serial0;
+		serial1 = &serial1;
+		serial2 = &lpuart1;
+		spi0 = &fspi;
+		spi1 = &dspi2;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&dspi2 {
+	status = "okay";
+};
+
+&enetc0 {
+	phy-handle = <&phy0>;
+	phy-mode = "sgmii";
+	status = "okay";
+};
+
+&enetc2 {
+	status = "disabled";
+};
+
+&enetc6 {
+	status = "disabled";
+};
+
+&esdhc0 {
+	sd-uhs-sdr104;
+	sd-uhs-sdr50;
+	sd-uhs-sdr25;
+	sd-uhs-sdr12;
+	status = "okay";
+};
+
+&esdhc1 {
+	mmc-hs200-1_8v;
+	mmc-hs400-1_8v;
+	bus-width = <8>;
+	status = "okay";
+};
+
+&fspi {
+	status = "okay";
+
+	flash at 0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		m25p,fast-read;
+		spi-max-frequency = <133000000>;
+		reg = <0>;
+		/* The following setting enables 1-1-2 (CMD-ADDR-DATA) mode */
+		spi-rx-bus-width = <2>; /* 2 SPI Rx lines */
+		spi-tx-bus-width = <1>; /* 1 SPI Tx line */
+
+		partition at 0 {
+			reg = <0x000000 0x010000>;
+			label = "rcw";
+			read-only;
+		};
+
+		partition at 10000 {
+			reg = <0x010000 0x0f0000>;
+			label = "failsafe bootloader";
+			read-only;
+		};
+
+		partition at 100000 {
+			reg = <0x100000 0x040000>;
+			label = "failsafe DP firmware";
+			read-only;
+		};
+
+		partition at 140000 {
+			reg = <0x140000 0x0a0000>;
+			label = "failsafe trusted firmware";
+			read-only;
+		};
+
+		partition at 1e0000 {
+			reg = <0x1e0000 0x020000>;
+			label = "reserved";
+			read-only;
+		};
+
+		partition at 200000 {
+			reg = <0x200000 0x010000>;
+			label = "configuration store";
+		};
+
+		partition at 210000 {
+			reg = <0x210000 0x0f0000>;
+			label = "bootloader";
+		};
+
+		partition at 300000 {
+			reg = <0x300000 0x040000>;
+			label = "DP firmware";
+		};
+
+		partition at 340000 {
+			reg = <0x340000 0x0a0000>;
+			label = "trusted firmware";
+		};
+
+		partition at 3e0000 {
+			reg = <0x3e0000 0x020000>;
+			label = "bootloader environment";
+		};
+	};
+};
+
+&i2c0 {
+	status = "okay";
+
+	rtc at 32 {
+		compatible = "microcrystal,rv8803";
+		reg = <0x32>;
+	};
+
+	eeprom at 50 {
+		compatible = "atmel,24c32";
+		reg = <0x50>;
+		pagesize = <32>;
+	};
+};
+
+&i2c3 {
+	status = "okay";
+};
+
+&i2c4 {
+	status = "okay";
+
+	eeprom at 50 {
+		compatible = "atmel,24c32";
+		reg = <0x50>;
+		pagesize = <32>;
+	};
+};
+
+&lpuart1 {
+	status = "okay";
+};
+
+&mdio0 {
+	status = "okay";
+	phy0: ethernet-phy at 5 {
+		reg = <0x5>;
+		eee-broken-1000t;
+		eee-broken-100tx;
+	};
+};
+
+&serial0 {
+	status = "okay";
+};
+
+&serial1 {
+	status = "okay";
+};
+
+&usb1 {
+	status = "okay";
+};
+
+&usb2 {
+	status = "okay";
+};
diff --git a/board/kontron/sl28/Kconfig b/board/kontron/sl28/Kconfig
new file mode 100644
index 0000000000..cdec39be01
--- /dev/null
+++ b/board/kontron/sl28/Kconfig
@@ -0,0 +1,18 @@
+if TARGET_SL28
+
+config SYS_BOARD
+	default "sl28"
+
+config SYS_VENDOR
+	default "kontron"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "kontron_sl28"
+
+config SYS_TEXT_BASE
+	default 0x96000000
+
+endif
diff --git a/board/kontron/sl28/MAINTAINERS b/board/kontron/sl28/MAINTAINERS
new file mode 100644
index 0000000000..a7b0fbbdd1
--- /dev/null
+++ b/board/kontron/sl28/MAINTAINERS
@@ -0,0 +1,7 @@
+Kontron SMARC-sAL28 board
+M:	Michael Walle <michael@walle.cc>
+S:	Maintained
+F:	arch/arm/dts/fsl-ls1028a-kontron-sl28-*
+F:	board/kontron/sl28/
+F:	configs/kontron_sl28_defconfig
+F:	include/configs/kontron_sl28.h
diff --git a/board/kontron/sl28/Makefile b/board/kontron/sl28/Makefile
new file mode 100644
index 0000000000..0f1866c874
--- /dev/null
+++ b/board/kontron/sl28/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier:	GPL-2.0+
+
+ifndef CONFIG_SPL_BUILD
+obj-y += sl28.o
+endif
+
+obj-y += common.o ddr.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
diff --git a/board/kontron/sl28/common.c b/board/kontron/sl28/common.c
new file mode 100644
index 0000000000..14704f7051
--- /dev/null
+++ b/board/kontron/sl28/common.c
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <asm/arch-fsl-layerscape/soc.h>
+
+int board_early_init_f(void)
+{
+	fsl_lsch3_early_init_f();
+	return 0;
+}
diff --git a/board/kontron/sl28/ddr.c b/board/kontron/sl28/ddr.c
new file mode 100644
index 0000000000..d111b6d4c3
--- /dev/null
+++ b/board/kontron/sl28/ddr.c
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <asm/io.h>
+#include <fsl_ddr_sdram.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DCFG_GPPORCR1 0x20
+
+#define GPPORCR1_MEM_MASK		(0x7 << 5)
+#define GPPORCR1_MEM_512MB_CS0		(0x0 << 5)
+#define GPPORCR1_MEM_1GB_CS0		(0x1 << 5)
+#define GPPORCR1_MEM_2GB_CS0		(0x2 << 5)
+#define GPPORCR1_MEM_4GB_CS0_1		(0x3 << 5)
+#define GPPORCR1_MEM_4GB_CS0_2		(0x4 << 5)
+#define GPPORCR1_MEM_8GB_CS0_1_2_3	(0x5 << 5)
+#define GPPORCR1_MEM_8GB_CS0_1		(0x6 << 5)
+
+static fsl_ddr_cfg_regs_t __maybe_unused ddr_cfg_regs = {
+	.cs[0].bnds		= 0x0000007f,
+	.cs[0].config		= 0x80044402,
+	.cs[1].bnds		= 0x008000ff,
+	.cs[1].config		= 0x80004402,
+
+	.timing_cfg_0		= 0x9011010c,
+	.timing_cfg_3		= 0x010c1000,
+	.timing_cfg_1		= 0xbcb48c66,
+	.timing_cfg_2		= 0x0fc0d118,
+	.ddr_sdram_cfg		= 0xe70c000c,
+	.ddr_sdram_cfg_2	= 0x24401111,
+	.ddr_sdram_mode		= 0x00441c70,
+	.ddr_sdram_mode_3	= 0x00001c70,
+	.ddr_sdram_mode_5	= 0x00001c70,
+	.ddr_sdram_mode_7	= 0x00001c70,
+	.ddr_sdram_mode_2	= 0x00180000,
+	.ddr_sdram_mode_4	= 0x00180000,
+	.ddr_sdram_mode_6	= 0x00180000,
+	.ddr_sdram_mode_8	= 0x00180000,
+
+	.ddr_sdram_interval	= 0x0c30030c,
+	.ddr_data_init		= 0xdeadbeef,
+
+	.ddr_sdram_clk_cntl	= 0x02400000,
+
+	.timing_cfg_4		= 0x00000001,
+	.timing_cfg_5		= 0x04401400,
+
+	.ddr_zq_cntl		= 0x89080600,
+	.ddr_wrlvl_cntl		= 0x8675f606,
+	.ddr_wrlvl_cntl_2	= 0x04080700,
+	.ddr_wrlvl_cntl_3	= 0x00000009,
+
+	.ddr_cdr1		= 0x80040000,
+	.ddr_cdr2		= 0x0000bc01,
+};
+
+int fsl_initdram(void)
+{
+	u32 gpporcr1 = in_le32(DCFG_BASE + DCFG_GPPORCR1);
+	phys_size_t dram_size;
+
+	switch (gpporcr1 & GPPORCR1_MEM_MASK) {
+	case GPPORCR1_MEM_2GB_CS0:
+		dram_size = 0x80000000;
+		ddr_cfg_regs.cs[1].bnds = 0;
+		ddr_cfg_regs.cs[1].config = 0;
+		ddr_cfg_regs.cs[1].config_2 = 0;
+		break;
+	case GPPORCR1_MEM_4GB_CS0_1:
+		dram_size = 0x100000000ULL;
+		break;
+	case GPPORCR1_MEM_512MB_CS0:
+		dram_size = 0x20000000;
+		fallthrough; /* for now */
+	case GPPORCR1_MEM_1GB_CS0:
+		dram_size = 0x40000000;
+		fallthrough; /* for now */
+	case GPPORCR1_MEM_4GB_CS0_2:
+		dram_size = 0x100000000ULL;
+		fallthrough; /* for now */
+	case GPPORCR1_MEM_8GB_CS0_1:
+	case GPPORCR1_MEM_8GB_CS0_1_2_3:
+		dram_size = 0x200000000ULL;
+		fallthrough; /* for now */
+	default:
+		panic("Unsupported memory configuration (%08x)\n",
+		      gpporcr1 & GPPORCR1_MEM_MASK);
+		break;
+	}
+
+	if (!IS_ENABLED(CONFIG_SPL) || IS_ENABLED(CONFIG_SPL_BUILD))
+		fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
+
+	gd->ram_size = dram_size;
+
+	return 0;
+}
diff --git a/board/kontron/sl28/sl28.c b/board/kontron/sl28/sl28.c
new file mode 100644
index 0000000000..b18127c4d1
--- /dev/null
+++ b/board/kontron/sl28/sl28.c
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <fsl_ddr.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
+#include <env_internal.h>
+#include <asm/arch-fsl-layerscape/soc.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
+#include <i2c.h>
+#include <asm/arch/soc.h>
+#include <fsl_immap.h>
+#include <netdev.h>
+
+#include <fdtdec.h>
+#include <miiphy.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	if (CONFIG_IS_ENABLED(FSL_CAAM))
+		sec_init();
+
+	return 0;
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+	return pci_eth_init(bis);
+}
+
+int checkboard(void)
+{
+	printf("EL:    %d\n", current_el());
+	return 0;
+}
+
+void detail_board_ddr_info(void)
+{
+	puts("\nDDR    ");
+	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
+	print_ddr_info(0);
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	u64 base[CONFIG_NR_DRAM_BANKS];
+	u64 size[CONFIG_NR_DRAM_BANKS];
+	int nbanks = CONFIG_NR_DRAM_BANKS;
+	int i;
+
+	ft_cpu_setup(blob, bd);
+
+	/* fixup DT for the two GPP DDR banks */
+	for (i = 0; i < nbanks; i++) {
+		base[i] = gd->bd->bi_dram[i].start;
+		size[i] = gd->bd->bi_dram[i].size;
+	}
+
+	fdt_fixup_memory_banks(blob, base, size, nbanks);
+
+	fdt_fixup_icid(blob);
+
+	return 0;
+}
diff --git a/board/kontron/sl28/spl.c b/board/kontron/sl28/spl.c
new file mode 100644
index 0000000000..fa5829eee0
--- /dev/null
+++ b/board/kontron/sl28/spl.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/spl.h>
+
+#define DCFG_RCWSR25 0x160
+#define GPINFO_HW_VARIANT_MASK 0xff
+
+int sl28_variant(void)
+{
+	return in_le32(DCFG_BASE + DCFG_RCWSR25) & GPINFO_HW_VARIANT_MASK;
+}
+
+int board_fit_config_name_match(const char *name)
+{
+	int variant = sl28_variant();
+
+	switch (variant) {
+	case 3:
+		return strcmp(name, "fsl-ls1028a-kontron-sl28-var3");
+	case 4:
+		return strcmp(name, "fsl-ls1028a-kontron-sl28-var4");
+	default:
+		return strcmp(name, "fsl-ls1028a-kontron-sl28");
+	}
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	spl_boot_list[0] = BOOT_DEVICE_SPI;
+}
diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig
new file mode 100644
index 0000000000..a792bee4e0
--- /dev/null
+++ b/configs/kontron_sl28_defconfig
@@ -0,0 +1,105 @@
+CONFIG_ARM=y
+CONFIG_TARGET_SL28=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x3e0000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x230000
+CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
+CONFIG_SPL_TEXT_BASE=0x18010000
+CONFIG_SYS_FSL_SDHC_CLK_DIV=1
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SIZE_LIMIT=0x20000
+CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x0
+CONFIG_SPL=y
+CONFIG_ENV_OFFSET_REDUND=0x3f0000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+# CONFIG_PSCI_RESET is not set
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-kontron-sl28"
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_PCI_INIT_R=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_NVEDIT_EFI=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RNG=y
+CONFIG_MP=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIST=""
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETCONSOLE=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SCSI_AHCI=y
+CONFIG_FSL_CAAM=y
+CONFIG_SYS_FSL_DDR3=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_I2C_DEFAULT_BUS_NUMBER=0
+CONFIG_I2C_MUX=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_PHY_GIGE=y
+CONFIG_E1000=y
+CONFIG_FSL_ENETC=y
+CONFIG_NVME=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_ECAM_GENERIC=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_DM_RNG=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_RV8803=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+# CONFIG_SPL_DM_USB is not set
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_OF_LIBFDT_ASSUME_MASK=0x0
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/doc/board/index.rst b/doc/board/index.rst
index 63935abcd7..4b6a996eb1 100644
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -15,6 +15,7 @@ Board-specific doc
    freescale/index
    google/index
    intel/index
+   kontron/index
    renesas/index
    rockchip/index
    sifive/index
diff --git a/doc/board/kontron/index.rst b/doc/board/kontron/index.rst
new file mode 100644
index 0000000000..543b22e2f5
--- /dev/null
+++ b/doc/board/kontron/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Kontron
+=======
+
+.. toctree::
+   :maxdepth: 2
+
+   sl28
diff --git a/doc/board/kontron/sl28.rst b/doc/board/kontron/sl28.rst
new file mode 100644
index 0000000000..e458fbc607
--- /dev/null
+++ b/doc/board/kontron/sl28.rst
@@ -0,0 +1,160 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Summary
+=======
+
+The Kontron SMARC-sAL28 board is a TSN-enabled dual-core ARM A72
+processor module with an on-chip 6-port TSN switch and a 3D GPU.
+
+
+Quickstart
+==========
+
+Compile U-Boot
+--------------
+
+Configure and compile the binary::
+
+ $ make kontron_sl28_defconfig
+ $ CROSS_COMPILE=aarch64-linux-gnu make
+
+Copy u-boot.rom to a TFTP server.
+
+Install the bootloader on the board
+-----------------------------------
+
+Please note, this bootloader doesn't support the builtin watchdog (yet),
+therefore you have to disable it, see below. Otherwise you'll end up in
+the failsafe bootloader on every reset::
+
+ > tftp path/to/u-boot.rom
+ > sf probe 0
+ > sf update $fileaddr 0x210000 $filesize
+
+The board is fully failsafe, you can't break anything. But because you've
+disabled the builtin watchdog you might have to manually enter failsafe
+mode by asserting the ``FORCE_RECOV#`` line during board reset.
+
+Disable the builtin watchdog
+----------------------------
+
+- boot into the failsafe bootloader, either by asserting the
+  ``FORCE_RECOV#`` line or if you still have the original bootloader
+  installed you can use the command::
+
+  > wdt dev cpld_watchdog at 4a; wdt expire 1
+
+- in the failsafe bootloader use the "sl28 nvm" command to disable
+  the automatic start of the builtin watchdog::
+
+  > sl28 nvm 0008
+
+- power-cycle the board
+
+
+Useful I2C tricks
+=================
+
+The board has a board management controller which is not supported in
+u-boot (yet). But you can use the i2c command to access it.
+
+- reset into failsafe bootloader::
+
+  > i2c mw 4a 5.1 0; i2c mw 4a 6.1 6b; i2c mw 4a 4.1 42
+
+- read board management controller version::
+
+  > i2c md 4a 3.1 1
+
+
+Non-volatile Board Configuration Bits
+=====================================
+
+The board has 16 configuration bits which are stored in the CPLD and are
+non-volatile. These can be changed by the `sl28 nvm` command.
+
+===  ===============================================================
+Bit  Description
+===  ===============================================================
+  0  Power-on inhibit
+  1  Enable eMMC boot
+  2  Enable watchdog by default
+  3  Disable failsafe watchdog by default
+  4  Clock generator selection bit 0
+  5  Clock generator selection bit 1
+  6  Disable CPU SerDes clock #2 and PCIe-A clock output
+  7  Disable PCIe-B and PCIe-C clock output
+  8  Keep onboard PHYs in reset
+  9  Keep USB hub in reset
+ 10  Keep eDP-to-LVDS converter in reset
+ 11  Enable I2C stuck recovery on I2C PM and I2C GP busses
+ 12  Enable automatic onboard PHY H/W reset
+ 13  reserved
+ 14  Used by the RCW to determine boot source
+ 15  Used by the RCW to determine boot source
+===  ===============================================================
+
+Please note, that if the board is in failsafe mode, the bits will have the
+factory defaults, ie. all bits are off.
+
+Power-On Inhibit
+----------------
+
+If this is set, the board doesn't automatically turn on when power is
+applied. Instead, the user has to either toggle the ``PWR_BTN#`` line or
+use any other wake-up source such as RTC alarm or Wake-on-LAN.
+
+eMMC Boot
+---------
+
+If this is set, the RCW will be fetched from the on-board eMMC at offset
+1MiB. For further details, have a look at the `Reset Configuration Word
+Documentation`_.
+
+Watchdog
+--------
+
+By default, the CPLD watchdog is enabled in failsafe mode. Using bits 2 and
+3, the user can change its mode or disable it altogether.
+
+=====  =====  ===============================
+Bit 2  Bit 3  Description
+=====  =====  ===============================
+    0      0  Watchdog enabled, failsafe mode
+    0      1  Watchdog disabled
+    1      0  Watchdog enabled, failsafe mode
+    1      1  Watchdog enabled, normal mode
+=====  =====  ===============================
+
+Clock Generator Select
+----------------------
+
+The board is prepared to supply different SerDes clock speeds. But for now,
+only setting 0 is supported, otherwise the CPU will hang because the PLL
+will not lock.
+
+Clock Output Disable And Keep Devices In Reset
+----------------------------------------------
+
+To safe power, the user might disable different devices and clock output of
+the board. It is not supported to disable the "CPU SerDes clock #2" for
+now, otherwise the CPU will hang because the PLL will not lock.
+
+Automatic reset of the onboard PHYs
+-----------------------------------
+
+By default, there is no hardware reset of the onboard PHY. This is because
+for Wake-on-LAN, some registers have to retain their values. If you don't
+use the WOL feature and a soft reset of the PHY is not enough you can
+enable the hardware reset. The onboard PHY hardware reset follows the
+power-on reset.
+
+
+Further documentation
+=====================
+
+- `Vendor Documentation`_
+- `Reset Configuration Word Documentation`_
+
+.. _Reset Configuration Word Documentation: https://raw.githubusercontent.com/kontron/rcw-smarc-sal28/master/README.md
+.. _Vendor Documentation: https://raw.githubusercontent.com/kontron/u-boot-smarc-sal28/master/board/kontron/sl28/README.md
diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h
new file mode 100644
index 0000000000..afe512a8c7
--- /dev/null
+++ b/include/configs/kontron_sl28.h
@@ -0,0 +1,108 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __SL28_H
+#define __SL28_H
+
+#include <asm/arch/stream_id_lsch3.h>
+#include <asm/arch/config.h>
+#include <asm/arch/soc.h>
+
+/* we don't use hwconfig but this has to be defined.. */
+#define HWCONFIG_BUFFER_SIZE 256
+
+/* we don't have secure memory unless we have a BL31 */
+#ifndef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
+#undef CONFIG_SYS_MEM_RESERVE_SECURE
+#endif
+
+/* DDR */
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_CHIP_SELECTS_PER_CTRL	4
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
+#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_DDR_BLOCK2_BASE	0x2080000000ULL
+#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS	1
+
+/* early stack pointer */
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_FSL_OCRAM_BASE + 0xeff0)
+
+/* memtest command */
+#define CONFIG_SYS_MEMTEST_START        0x80000000
+#define CONFIG_SYS_MEMTEST_END          0x9fffffff
+
+/* SMP */
+#define CPU_RELEASE_ADDR		secondary_boot_addr
+
+/* generic timer */
+#define COUNTER_FREQUENCY		25000000
+
+/* size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2048 * 1024)
+
+/* early heap for SPL DM */
+#define CONFIG_MALLOC_F_ADDR		CONFIG_SYS_FSL_OCRAM_BASE
+
+/* serial port */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0) / 2)
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_SYS_CLK_FREQ		100000000
+#define CONFIG_DDR_CLK_FREQ		100000000
+#define COUNTER_FREQUENCY_REAL		(CONFIG_SYS_CLK_FREQ / 4)
+
+/* MMC */
+#ifdef CONFIG_MMC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#endif
+
+/* ethernet */
+#define CONFIG_SYS_RX_ETH_BUFFER	8
+
+/* SPL */
+#define CONFIG_SPL_BSS_START_ADDR	0x80100000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x00100000
+#define CONFIG_SPL_MAX_SIZE		0x20000
+#define CONFIG_SPL_STACK		(CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
+
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00100000
+#define CONFIG_SYS_SPL_MALLOC_START	0x80200000
+#define CONFIG_SYS_MONITOR_LEN		(1024 * 1024)
+
+/* environment */
+/* see include/configs/ti_armv7_common.h */
+#define CONFIG_SYS_LOAD_ADDR		0x82000000
+#define ENV_MEM_LAYOUT_SETTINGS \
+	"loadaddr=0x82000000\0" \
+	"kernel_addr_r=0x82000000\0" \
+	"fdt_addr_r=0x88000000\0" \
+	"bootm_size=0x10000000\0" \
+	"pxefile_addr_r=0x80100000\0" \
+	"scriptaddr=0x80000000\0" \
+	"ramdisk_addr_r=0x88080000\0"
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 1) \
+	func(MMC, mmc, 0) \
+	func(NVME, nvme, 0) \
+	func(USB, usb, 0) \
+	func(DHCP, dhcp, 0) \
+	func(PXE, pxe, 0)
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"env_addr=0x203e0004\0" \
+	"envload=env import -d -b ${env_addr}\0" \
+	"install_rcw=source 20200000\0" \
+	"fdtfile=freescale/fsl-ls1028a-kontron-sl28.dtb\0" \
+	ENV_MEM_LAYOUT_SETTINGS \
+	BOOTENV
+
+#endif /* __SL28_H */
-- 
2.20.1

^ permalink raw reply related	[flat|nested] 3+ messages in thread
* [PATCH v8 2/2] board: sl28: add board specific nvm command
  2020-09-25 11:51 [PATCH v8 0/2] Basic Kontron SMARC-sAL28 board support Michael Walle
  2020-09-25 11:51 ` [PATCH v8 1/2] board: kontron: add sl28 support Michael Walle
@ 2020-09-25 11:51 ` Michael Walle
  1 sibling, 0 replies; 3+ messages in thread
From: Michael Walle @ 2020-09-25 11:51 UTC (permalink / raw)
  To: u-boot

The board supports 16 configuration bits which can be manipulated with
this command. See the board's README for a detailed explanation on each
bit.

Signed-off-by: Michael Walle <michael@walle.cc>
---
 board/kontron/sl28/Makefile |   2 +-
 board/kontron/sl28/cmds.c   | 178 ++++++++++++++++++++++++++++++++++++
 2 files changed, 179 insertions(+), 1 deletion(-)
 create mode 100644 board/kontron/sl28/cmds.c

diff --git a/board/kontron/sl28/Makefile b/board/kontron/sl28/Makefile
index 0f1866c874..74d8012f0f 100644
--- a/board/kontron/sl28/Makefile
+++ b/board/kontron/sl28/Makefile
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 
 ifndef CONFIG_SPL_BUILD
-obj-y += sl28.o
+obj-y += sl28.o cmds.o
 endif
 
 obj-y += common.o ddr.o
diff --git a/board/kontron/sl28/cmds.c b/board/kontron/sl28/cmds.c
new file mode 100644
index 0000000000..046d3b4903
--- /dev/null
+++ b/board/kontron/sl28/cmds.c
@@ -0,0 +1,178 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * sl28 extension commands
+ *
+ * Copyright (c) 2020 Kontron Europe GmbH
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <linux/delay.h>
+
+#define CPLD_I2C_ADDR 0x4a
+#define REG_UFM_CTRL 0x02
+#define   UFM_CTRL_DCLK    BIT(1)
+#define   UFM_CTRL_DIN     BIT(2)
+#define   UFM_CTRL_PROGRAM BIT(3)
+#define   UFM_CTRL_ERASE   BIT(4)
+#define   UFM_CTRL_DSHIFT  BIT(5)
+#define   UFM_CTRL_DOUT    BIT(6)
+#define   UFM_CTRL_BUSY    BIT(7)
+
+static int ufm_shift_data(struct udevice *dev, u16 data_in, u16 *data_out)
+{
+	int i;
+	int ret;
+	u16 data = 0;
+
+	/* latch data */
+	ret = dm_i2c_reg_write(dev, REG_UFM_CTRL, 0);
+	if (ret < 0)
+		return ret;
+	ret = dm_i2c_reg_write(dev, REG_UFM_CTRL, UFM_CTRL_DCLK);
+	if (ret < 0)
+		return ret;
+
+	/* assert drshift */
+	ret = dm_i2c_reg_write(dev, REG_UFM_CTRL,
+			       UFM_CTRL_DSHIFT | UFM_CTRL_DCLK);
+	if (ret < 0)
+		return ret;
+
+	/* clock 16 data bits, reverse order */
+	for (i = 15; i >= 0; i--) {
+		u8 din = (data_in & (1 << i)) ? UFM_CTRL_DIN : 0;
+
+		ret = dm_i2c_reg_write(dev, REG_UFM_CTRL, UFM_CTRL_DSHIFT
+				| din);
+		if (ret < 0)
+			return ret;
+		if (data_out) {
+			ret = dm_i2c_reg_read(dev, REG_UFM_CTRL);
+			if (ret < 0)
+				return ret;
+			if (ret & UFM_CTRL_DOUT)
+				data |= (1 << i);
+		}
+		ret = dm_i2c_reg_write(dev, REG_UFM_CTRL,
+				       UFM_CTRL_DSHIFT | UFM_CTRL_DCLK | din);
+		if (ret < 0)
+			return ret;
+	}
+
+	/* deassert drshift */
+	ret = dm_i2c_reg_write(dev, REG_UFM_CTRL, UFM_CTRL_DCLK);
+	if (ret < 0)
+		return ret;
+
+	if (data_out)
+		*data_out = data;
+
+	return ret;
+}
+
+static int ufm_erase(struct udevice *dev)
+{
+	int ret;
+
+	/* erase, tEPMX is 500ms */
+	ret = dm_i2c_reg_write(dev, REG_UFM_CTRL,
+			       UFM_CTRL_DCLK | UFM_CTRL_ERASE);
+	if (ret < 0)
+		return ret;
+	ret = dm_i2c_reg_write(dev, REG_UFM_CTRL, UFM_CTRL_DCLK);
+	if (ret < 0)
+		return ret;
+	mdelay(500);
+
+	return 0;
+}
+
+static int ufm_program(struct udevice *dev)
+{
+	int ret;
+
+	/* program, tPPMX is 100us */
+	ret = dm_i2c_reg_write(dev, REG_UFM_CTRL,
+			       UFM_CTRL_DCLK | UFM_CTRL_PROGRAM);
+	if (ret < 0)
+		return ret;
+	ret = dm_i2c_reg_write(dev, REG_UFM_CTRL, UFM_CTRL_DCLK);
+	if (ret < 0)
+		return ret;
+	udelay(100);
+
+	return 0;
+}
+
+static int ufm_write(struct udevice *dev, u16 data)
+{
+	int ret;
+
+	ret = ufm_shift_data(dev, data, NULL);
+	if (ret < 0)
+		return ret;
+
+	ret = ufm_erase(dev);
+	if (ret < 0)
+		return ret;
+
+	return ufm_program(dev);
+}
+
+static int ufm_read(struct udevice *dev, u16 *data)
+{
+	return ufm_shift_data(dev, 0, data);
+}
+
+static int do_sl28_nvm(struct cmd_tbl *cmdtp, int flag, int argc,
+		       char *const argv[])
+{
+	struct udevice *dev;
+	u16 nvm;
+	int ret;
+	char *endp;
+
+	if (i2c_get_chip_for_busnum(0, CPLD_I2C_ADDR, 1, &dev))
+		return CMD_RET_FAILURE;
+
+	if (argc > 1) {
+		nvm = simple_strtoul(argv[1], &endp, 16);
+		if (*endp != '\0') {
+			printf("ERROR: argument is not a valid number\n");
+			ret = -EINVAL;
+			goto out;
+		}
+
+		/*
+		 * We swap all bits, because the a zero bit in hardware means the
+		 * feature is enabled. But this is hard for the user.
+		 */
+		nvm ^= 0xffff;
+
+		ret = ufm_write(dev, nvm);
+		if (ret)
+			goto out;
+		printf("New settings will be activated after the next power cycle!\n");
+	} else {
+		ret = ufm_read(dev, &nvm);
+		if (ret)
+			goto out;
+		nvm ^= 0xffff;
+
+		printf("%04hx\n", nvm);
+	}
+
+	return CMD_RET_SUCCESS;
+
+out:
+	printf("command failed (%d)\n", ret);
+	return CMD_RET_FAILURE;
+}
+
+static char sl28_help_text[] =
+	"nvm [<hex>] - display/set the 16 non-volatile bits\n";
+
+U_BOOT_CMD_WITH_SUBCMDS(sl28, "SMARC-sAL28 specific", sl28_help_text,
+			U_BOOT_SUBCMD_MKENT(nvm, 2, 1, do_sl28_nvm));
-- 
2.20.1

^ permalink raw reply related	[flat|nested] 3+ messages in thread
end of thread, other threads:[~2020-09-25 11:51 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-09-25 11:51 [PATCH v8 0/2] Basic Kontron SMARC-sAL28 board support Michael Walle
2020-09-25 11:51 ` [PATCH v8 1/2] board: kontron: add sl28 support Michael Walle
2020-09-25 11:51 ` [PATCH v8 2/2] board: sl28: add board specific nvm command Michael Walle

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