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From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: vandita.kulkarni@intel.com, uma.shankar@intel.com,
	dri-devel@lists.freedesktop.org, swati2.sharma@intel.com
Subject: [RFC 2/7] drm/edid: Parse MAX_FRL field from HFVSDB block
Date: Fri, 25 Sep 2020 17:43:35 +0530	[thread overview]
Message-ID: <20200925121340.29497-3-ankit.k.nautiyal@intel.com> (raw)
In-Reply-To: <20200925121340.29497-1-ankit.k.nautiyal@intel.com>

From: Swati Sharma <swati2.sharma@intel.com>

This patch parses MAX_FRL field to get the MAX rate in Gbps that
the HDMI 2.1 panel can support in FRL mode. Source need this
field to determine the optimal rate between the source and sink
during FRL training.

Signed-off-by: Sharma, Swati2 <swati2.sharma@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/drm_edid.c  | 50 +++++++++++++++++++++++++++++++++++++
 include/drm/drm_connector.h |  6 +++++
 2 files changed, 56 insertions(+)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 631125b46e04..d468ac91abb6 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -4849,6 +4849,51 @@ static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
 		info->rgb_quant_range_selectable = true;
 }
 
+static void drm_parse_hdmi_21_additional_fields(struct drm_connector *connector,
+						const u8 *db)
+{
+     /* hf_vsdb 7:14 support needs to be added */
+
+    u8 max_frl_rate_per_lane;
+    struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
+
+    max_frl_rate_per_lane = (db[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4;
+
+    switch(max_frl_rate_per_lane) {
+    case 0:
+	    hdmi->max_lane = 0;
+	    hdmi->max_frl_rate_per_lane = 0;
+	    break;
+    case 1:
+	    hdmi->max_lane = 3;
+	    hdmi->max_frl_rate_per_lane = 3;
+	    break;
+    case 2:
+	    hdmi->max_lane = 3;
+	    hdmi->max_frl_rate_per_lane = 6;
+	    break;
+    case 3:
+	    hdmi->max_lane = 4;
+	    hdmi->max_frl_rate_per_lane = 6;
+	    break;
+    case 4:
+	    hdmi->max_lane = 4;
+	    hdmi->max_frl_rate_per_lane = 8;
+	    break;
+    case 5:
+	    hdmi->max_lane = 4;
+	    hdmi->max_frl_rate_per_lane = 10;
+	    break;
+    case 6:
+	    hdmi->max_lane = 4;
+	    hdmi->max_frl_rate_per_lane = 12;
+	    break;
+    default:
+	    DRM_DEBUG_KMS("max frl rate per lane 0x%x, reserved\n", max_frl_rate_per_lane);
+	    break;
+    }
+}
+
 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
 					       const u8 *db)
 {
@@ -4902,6 +4947,11 @@ static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
 		}
 	}
 
+	if (hf_vsdb[7]) {
+		    DRM_DEBUG_KMS("hdmi_21 sink detected. parsing edid\n");
+		    drm_parse_hdmi_21_additional_fields(connector, hf_vsdb);
+	}
+
 	drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);
 }
 
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 928136556174..aa6ae9c17ca4 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -207,6 +207,12 @@ struct drm_hdmi_info {
 
 	/** @y420_dc_modes: bitmap of deep color support index */
 	u8 y420_dc_modes;
+
+	/** @max_frl_rate_per_lane: support fixed rate link */
+	u8 max_frl_rate_per_lane;
+
+	/** @max_lane: supported by sink */
+	u8 max_lane;
 };
 
 /**
-- 
2.17.1

_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

WARNING: multiple messages have this Message-ID (diff)
From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Subject: [Intel-gfx] [RFC 2/7] drm/edid: Parse MAX_FRL field from HFVSDB block
Date: Fri, 25 Sep 2020 17:43:35 +0530	[thread overview]
Message-ID: <20200925121340.29497-3-ankit.k.nautiyal@intel.com> (raw)
In-Reply-To: <20200925121340.29497-1-ankit.k.nautiyal@intel.com>

From: Swati Sharma <swati2.sharma@intel.com>

This patch parses MAX_FRL field to get the MAX rate in Gbps that
the HDMI 2.1 panel can support in FRL mode. Source need this
field to determine the optimal rate between the source and sink
during FRL training.

Signed-off-by: Sharma, Swati2 <swati2.sharma@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/drm_edid.c  | 50 +++++++++++++++++++++++++++++++++++++
 include/drm/drm_connector.h |  6 +++++
 2 files changed, 56 insertions(+)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 631125b46e04..d468ac91abb6 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -4849,6 +4849,51 @@ static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
 		info->rgb_quant_range_selectable = true;
 }
 
+static void drm_parse_hdmi_21_additional_fields(struct drm_connector *connector,
+						const u8 *db)
+{
+     /* hf_vsdb 7:14 support needs to be added */
+
+    u8 max_frl_rate_per_lane;
+    struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
+
+    max_frl_rate_per_lane = (db[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4;
+
+    switch(max_frl_rate_per_lane) {
+    case 0:
+	    hdmi->max_lane = 0;
+	    hdmi->max_frl_rate_per_lane = 0;
+	    break;
+    case 1:
+	    hdmi->max_lane = 3;
+	    hdmi->max_frl_rate_per_lane = 3;
+	    break;
+    case 2:
+	    hdmi->max_lane = 3;
+	    hdmi->max_frl_rate_per_lane = 6;
+	    break;
+    case 3:
+	    hdmi->max_lane = 4;
+	    hdmi->max_frl_rate_per_lane = 6;
+	    break;
+    case 4:
+	    hdmi->max_lane = 4;
+	    hdmi->max_frl_rate_per_lane = 8;
+	    break;
+    case 5:
+	    hdmi->max_lane = 4;
+	    hdmi->max_frl_rate_per_lane = 10;
+	    break;
+    case 6:
+	    hdmi->max_lane = 4;
+	    hdmi->max_frl_rate_per_lane = 12;
+	    break;
+    default:
+	    DRM_DEBUG_KMS("max frl rate per lane 0x%x, reserved\n", max_frl_rate_per_lane);
+	    break;
+    }
+}
+
 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
 					       const u8 *db)
 {
@@ -4902,6 +4947,11 @@ static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
 		}
 	}
 
+	if (hf_vsdb[7]) {
+		    DRM_DEBUG_KMS("hdmi_21 sink detected. parsing edid\n");
+		    drm_parse_hdmi_21_additional_fields(connector, hf_vsdb);
+	}
+
 	drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);
 }
 
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 928136556174..aa6ae9c17ca4 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -207,6 +207,12 @@ struct drm_hdmi_info {
 
 	/** @y420_dc_modes: bitmap of deep color support index */
 	u8 y420_dc_modes;
+
+	/** @max_frl_rate_per_lane: support fixed rate link */
+	u8 max_frl_rate_per_lane;
+
+	/** @max_lane: supported by sink */
+	u8 max_lane;
 };
 
 /**
-- 
2.17.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2020-09-25 12:21 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-25 12:13 [RFC 0/7] Add support for DP-HDMI2.1 PCON Ankit Nautiyal
2020-09-25 12:13 ` [Intel-gfx] " Ankit Nautiyal
2020-09-25 12:13 ` [RFC 1/7] drm/edid: Add additional HFVSDB fields for HDMI2.1 Ankit Nautiyal
2020-09-25 12:13   ` [Intel-gfx] " Ankit Nautiyal
2020-09-25 12:13 ` Ankit Nautiyal [this message]
2020-09-25 12:13   ` [Intel-gfx] [RFC 2/7] drm/edid: Parse MAX_FRL field from HFVSDB block Ankit Nautiyal
2020-09-25 12:13 ` [RFC 3/7] drm/dp_helper: Add FRL training support for a DP-HDMI2.1 PCON Ankit Nautiyal
2020-09-25 12:13   ` [Intel-gfx] " Ankit Nautiyal
2020-09-25 12:13 ` [RFC 4/7] drm/i915: Add support for starting FRL training for HDMI2.1 via PCON Ankit Nautiyal
2020-09-25 12:13   ` [Intel-gfx] " Ankit Nautiyal
2020-09-25 12:13 ` [RFC 5/7] drm/i915: Check for FRL training before DP Link training Ankit Nautiyal
2020-09-25 12:13   ` [Intel-gfx] " Ankit Nautiyal
2020-09-25 12:13 ` [RFC 6/7] drm/dp_helper: Add support for link status and link recovery Ankit Nautiyal
2020-09-25 12:13   ` [Intel-gfx] " Ankit Nautiyal
2020-09-25 18:22   ` kernel test robot
2020-09-25 12:13 ` [RFC 7/7] drm/i915: Add support for enabling link status and recovery Ankit Nautiyal
2020-09-25 12:13   ` [Intel-gfx] " Ankit Nautiyal
2020-09-25 12:59 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add support for DP-HDMI2.1 PCON Patchwork
2020-09-25 13:01 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-09-25 13:21 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-09-25 18:31 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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