[PATCH v2 0/9] s390x/tcg: Implement some z14 facilities

[PATCH v2 0/9] s390x/tcg: Implement some z14 facilities

[David Hildenbrand]

With this patchset, I can boot a kernel compiled for z14 (requiring
Miscellaneous-Instruction-Extensions Facility 2) (using -cpu max).

I am currently working on "vector-enhancements facility 1", I have most
stuff in place except:
- VECTOR FP (MAXIMUM|MINIMUM): needs some manual work to cover all types of
                               comparisons.

Once we have that in place, we can convert the QEMU machine to a
stripped-down z14.

v1 -> v2:
- "s390x/cpu_model: S390_FEAT_MISC_INSTRUCTION_EXT ->
   S390_FEAT_MISC_INSTRUCTION_EXT2"
-- Added
- "s390x/tcg: Implement BRANCH INDIRECT ON CONDITION (BIC)"
-- Use new helper instead
- "s390x/tcg: Implement MULTIPLY SINGLE (MSC, MSGC, MSGRKC, MSRKC)"
-- Tune comparisons in CC computation

David Hildenbrand (9):
  s390x/cpu_model: S390_FEAT_MISC_INSTRUCTION_EXT ->
    S390_FEAT_MISC_INSTRUCTION_EXT2
  s390x/tcg: Implement ADD HALFWORD (AGH)
  s390x/tcg: Implement SUBTRACT HALFWORD (SGH)
  s390x/tcg: Implement MULTIPLY (MG, MGRK)
  s390x/tcg: Implement MULTIPLY HALFWORD (MGH)
  s390x/tcg: Implement BRANCH INDIRECT ON CONDITION (BIC)
  s390x/tcg: Implement MULTIPLY SINGLE (MSC, MSGC, MSGRKC, MSRKC)
  s390x/tcg: We support Miscellaneous-Instruction-Extensions Facility 2
  s390x/tcg: Implement CIPHER MESSAGE WITH AUTHENTICATION (KMA)

 target/s390x/cc_helper.c            | 32 +++++++++++++++++++
 target/s390x/cpu_features_def.h.inc |  2 +-
 target/s390x/gen-features.c         |  4 ++-
 target/s390x/helper.c               |  2 ++
 target/s390x/insn-data.def          | 12 ++++++++
 target/s390x/internal.h             |  2 ++
 target/s390x/translate.c            | 48 +++++++++++++++++++++++++++++
 7 files changed, 100 insertions(+), 2 deletions(-)

-- 
2.26.2

[PATCH v2 1/9] s390x/cpu_model: S390_FEAT_MISC_INSTRUCTION_EXT -> S390_FEAT_MISC_INSTRUCTION_EXT2

[David Hildenbrand]

Let's avoid confusion with the "Miscellaneous-Instruction-Extensions
Facility 1"

Suggested-by: Thomas Huth <thuth@redhat.com>
Cc: Christian Borntraeger <borntraeger@de.ibm.com>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
 target/s390x/cpu_features_def.h.inc | 2 +-
 target/s390x/gen-features.c         | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/s390x/cpu_features_def.h.inc b/target/s390x/cpu_features_def.h.inc
index 5942f81f16..6cc776e121 100644
--- a/target/s390x/cpu_features_def.h.inc
+++ b/target/s390x/cpu_features_def.h.inc
@@ -72,7 +72,7 @@ DEF_FEAT(INTERLOCKED_ACCESS_2, "iacc2", STFL, 52, "Interlocked-access facility 2
 DEF_FEAT(STFLE_53, "stfle53", STFL, 53, "Various facilities introduced with z13")
 DEF_FEAT(ENTROPY_ENC_COMP, "eec", STFL, 54, "Entropy encoding compression facility")
 DEF_FEAT(MSA_EXT_5, "msa5-base", STFL, 57, "Message-security-assist-extension-5 facility (excluding subfunctions)")
-DEF_FEAT(MISC_INSTRUCTION_EXT, "minste2", STFL, 58, "Miscellaneous-instruction-extensions facility 2")
+DEF_FEAT(MISC_INSTRUCTION_EXT2, "minste2", STFL, 58, "Miscellaneous-instruction-extensions facility 2")
 DEF_FEAT(SEMAPHORE_ASSIST, "sema", STFL, 59, "Semaphore-assist facility")
 DEF_FEAT(TIME_SLICE_INSTRUMENTATION, "tsi", STFL, 60, "Time-slice Instrumentation facility")
 DEF_FEAT(MISC_INSTRUCTION_EXT3, "minste3", STFL, 61, "Miscellaneous-Instruction-Extensions Facility 3")
diff --git a/target/s390x/gen-features.c b/target/s390x/gen-features.c
index 8ddeebc544..210cee65f3 100644
--- a/target/s390x/gen-features.c
+++ b/target/s390x/gen-features.c
@@ -412,7 +412,7 @@ static uint16_t base_GEN13_GA1[] = {
 
 static uint16_t base_GEN14_GA1[] = {
     S390_FEAT_ENTROPY_ENC_COMP,
-    S390_FEAT_MISC_INSTRUCTION_EXT,
+    S390_FEAT_MISC_INSTRUCTION_EXT2,
     S390_FEAT_SEMAPHORE_ASSIST,
     S390_FEAT_TIME_SLICE_INSTRUMENTATION,
     S390_FEAT_ORDER_PRESERVING_COMPRESSION,
-- 
2.26.2

[PATCH v2 2/9] s390x/tcg: Implement ADD HALFWORD (AGH)

[David Hildenbrand]

Easy, just like ADD HALFWORD IMMEDIATE (AGHI).

Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
 target/s390x/insn-data.def | 1 +
 target/s390x/translate.c   | 1 +
 2 files changed, 2 insertions(+)

diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index d79ae9e3f1..8dbeaf8c49 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -52,6 +52,7 @@
 /* ADD HALFWORD */
     C(0x4a00, AH,      RX_a,  Z,   r1, m2_16s, new, r1_32, add, adds32)
     C(0xe37a, AHY,     RXY_a, LD,  r1, m2_16s, new, r1_32, add, adds32)
+    C(0xe338, AGH,     RXY_a, MIE2,r1, m2_16s, r1, 0, add, adds64)
 /* ADD HALFWORD IMMEDIATE */
     C(0xa70a, AHI,     RI_a,  Z,   r1, i2, new, r1_32, add, adds32)
     C(0xa70b, AGHI,    RI_a,  Z,   r1, i2, r1, 0, add, adds64)
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index a777343821..3b433caf46 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -6098,6 +6098,7 @@ enum DisasInsnEnum {
 #define FAC_AIS         S390_FEAT_ADAPTER_INT_SUPPRESSION
 #define FAC_V           S390_FEAT_VECTOR /* vector facility */
 #define FAC_VE          S390_FEAT_VECTOR_ENH /* vector enhancements facility 1 */
+#define FAC_MIE2        S390_FEAT_MISC_INSTRUCTION_EXT2 /* miscellaneous-instruction-extensions facility 2 */
 
 static const DisasInsn insn_info[] = {
 #include "insn-data.def"
-- 
2.26.2

[PATCH v2 3/9] s390x/tcg: Implement SUBTRACT HALFWORD (SGH)

[David Hildenbrand]

Easy to wire up.

Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
 target/s390x/insn-data.def | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 8dbeaf8c49..e851e9df5e 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -883,6 +883,7 @@
 /* SUBTRACT HALFWORD */
     C(0x4b00, SH,      RX_a,  Z,   r1, m2_16s, new, r1_32, sub, subs32)
     C(0xe37b, SHY,     RXY_a, LD,  r1, m2_16s, new, r1_32, sub, subs32)
+    C(0xe339, SGH,     RXY_a, MIE2,r1, m2_16s, r1, 0, sub, subs64)
 /* SUBTRACT HIGH */
     C(0xb9c9, SHHHR,   RRF_a, HW,  r2_sr32, r3_sr32, new, r1_32h, sub, subs32)
     C(0xb9d9, SHHLR,   RRF_a, HW,  r2_sr32, r3, new, r1_32h, sub, subs32)
-- 
2.26.2

[PATCH v2 4/9] s390x/tcg: Implement MULTIPLY (MG, MGRK)

[David Hildenbrand]

Multiply two signed 64bit values and store the 128bit result in r1 (0-63)
and r1 + 1 (64-127).

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
 target/s390x/insn-data.def |  2 ++
 target/s390x/translate.c   | 13 +++++++++++++
 2 files changed, 15 insertions(+)

diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index e851e9df5e..2b4ad1530d 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -650,8 +650,10 @@
 
 /* MULTIPLY */
     C(0x1c00, MR,      RR_a,  Z,   r1p1_32s, r2_32s, new, r1_D32, mul, 0)
+    C(0xb9ec, MGRK,    RRF_a, MIE2,r3_o, r2_o, r1_P, 0, muls128, 0)
     C(0x5c00, M,       RX_a,  Z,   r1p1_32s, m2_32s, new, r1_D32, mul, 0)
     C(0xe35c, MFY,     RXY_a, GIE, r1p1_32s, m2_32s, new, r1_D32, mul, 0)
+    C(0xe384, MG,      RXY_a, MIE2,r1p1_o, m2_64, r1_P, 0, muls128, 0)
     F(0xb317, MEEBR,   RRE,   Z,   e1, e2, new, e1, meeb, 0, IF_BFP)
     F(0xb31c, MDBR,    RRE,   Z,   f1, f2, new, f1, mdb, 0, IF_BFP)
     F(0xb34c, MXBR,    RRE,   Z,   x2h, x2l, x1, x1, mxb, 0, IF_BFP)
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index 3b433caf46..f20ebd7c6a 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -3518,6 +3518,12 @@ static DisasJumpType op_mul128(DisasContext *s, DisasOps *o)
     return DISAS_NEXT;
 }
 
+static DisasJumpType op_muls128(DisasContext *s, DisasOps *o)
+{
+    tcg_gen_muls2_i64(o->out2, o->out, o->in1, o->in2);
+    return DISAS_NEXT;
+}
+
 static DisasJumpType op_meeb(DisasContext *s, DisasOps *o)
 {
     gen_helper_meeb(o->out, cpu_env, o->in1, o->in2);
@@ -5542,6 +5548,13 @@ static void in1_r1p1(DisasContext *s, DisasOps *o)
 }
 #define SPEC_in1_r1p1 SPEC_r1_even
 
+static void in1_r1p1_o(DisasContext *s, DisasOps *o)
+{
+    o->in1 = regs[get_field(s, r1) + 1];
+    o->g_in1 = true;
+}
+#define SPEC_in1_r1p1_o SPEC_r1_even
+
 static void in1_r1p1_32s(DisasContext *s, DisasOps *o)
 {
     o->in1 = tcg_temp_new_i64();
-- 
2.26.2

[PATCH v2 5/9] s390x/tcg: Implement MULTIPLY HALFWORD (MGH)

[David Hildenbrand]

Just like MULTIPLY HALFWORD IMMEDIATE (MGHI), only the second operand
(signed 16 bit) comes from memory.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
 target/s390x/insn-data.def | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 2b4ad1530d..455efe73da 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -666,6 +666,7 @@
 /* MULTIPLY HALFWORD */
     C(0x4c00, MH,      RX_a,  Z,   r1_o, m2_16s, new, r1_32, mul, 0)
     C(0xe37c, MHY,     RXY_a, GIE, r1_o, m2_16s, new, r1_32, mul, 0)
+    C(0xe33c, MGH,     RXY_a, MIE2,r1_o, m2_16s, r1, 0, mul, 0)
 /* MULTIPLY HALFWORD IMMEDIATE */
     C(0xa70c, MHI,     RI_a,  Z,   r1_o, i2, new, r1_32, mul, 0)
     C(0xa70d, MGHI,    RI_a,  Z,   r1_o, i2, r1, 0, mul, 0)
-- 
2.26.2

[PATCH v2 6/9] s390x/tcg: Implement BRANCH INDIRECT ON CONDITION (BIC)

[David Hildenbrand]

Just like BRANCH ON CONDITION - however the address is read from memory
(always 8 bytes are read), we have to wrap the address manually. The
address is read using current CPU DAT/address-space controls, just like
ordinary data.

Signed-off-by: David Hildenbrand <david@redhat.com>
---
 target/s390x/insn-data.def | 2 ++
 target/s390x/translate.c   | 8 ++++++++
 2 files changed, 10 insertions(+)

diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 455efe73da..cb40aea9a3 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -115,6 +115,8 @@
 /* BRANCH RELATIVE AND SAVE */
     C(0xa705, BRAS,    RI_b,  Z,   0, 0, r1, 0, basi, 0)
     C(0xc005, BRASL,   RIL_b, Z,   0, 0, r1, 0, basi, 0)
+/* BRANCH INDIRECT ON CONDITION */
+    C(0xe347, BIC,     RXY_b, MIE2,0, m2_64w, 0, 0, bc, 0)
 /* BRANCH ON CONDITION */
     C(0x0700, BCR,     RR_b,  Z,   0, r2_nz, 0, 0, bc, 0)
     C(0x4700, BC,      RX_b,  Z,   0, a2, 0, 0, bc, 0)
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index f20ebd7c6a..893b1f54a8 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -5935,6 +5935,14 @@ static void in2_m2_64(DisasContext *s, DisasOps *o)
 }
 #define SPEC_in2_m2_64 0
 
+static void in2_m2_64w(DisasContext *s, DisasOps *o)
+{
+    in2_a2(s, o);
+    tcg_gen_qemu_ld64(o->in2, o->in2, get_mem_index(s));
+    gen_addi_and_wrap_i64(s, o->in2, o->in2, 0);
+}
+#define SPEC_in2_m2_64w 0
+
 #ifndef CONFIG_USER_ONLY
 static void in2_m2_64a(DisasContext *s, DisasOps *o)
 {
-- 
2.26.2

[PATCH v2 7/9] s390x/tcg: Implement MULTIPLY SINGLE (MSC, MSGC, MSGRKC, MSRKC)

[David Hildenbrand]

We need new CC handling, determining the CC based on the intermediate
result (64bit for MSC and MSRKC, 128bit for MSGC and MSGRKC).

We want to store out2 ("low") after muls128 to r1, so add
"wout_out2_r1".

Signed-off-by: David Hildenbrand <david@redhat.com>
---
 target/s390x/cc_helper.c   | 32 ++++++++++++++++++++++++++++++++
 target/s390x/helper.c      |  2 ++
 target/s390x/insn-data.def |  4 ++++
 target/s390x/internal.h    |  2 ++
 target/s390x/translate.c   | 19 +++++++++++++++++++
 5 files changed, 59 insertions(+)

diff --git a/target/s390x/cc_helper.c b/target/s390x/cc_helper.c
index 44731e4a85..5432aeeed4 100644
--- a/target/s390x/cc_helper.c
+++ b/target/s390x/cc_helper.c
@@ -417,6 +417,32 @@ static uint32_t cc_calc_vc(uint64_t low, uint64_t high)
     }
 }
 
+static uint32_t cc_calc_muls_32(int64_t res)
+{
+    const int64_t tmp = res >> 31;
+
+    if (!res) {
+        return 0;
+    } else if (tmp && tmp != -1) {
+        return 3;
+    } else if (res < 0) {
+        return 1;
+    }
+    return 2;
+}
+
+static uint64_t cc_calc_muls_64(int64_t res_high, uint64_t res_low)
+{
+    if (!res_high && !res_low) {
+        return 0;
+    } else if (res_high + (res_low >> 63) != 0) {
+        return 3;
+    } else if (res_high < 0) {
+        return 1;
+    }
+    return 2;
+}
+
 static uint32_t do_calc_cc(CPUS390XState *env, uint32_t cc_op,
                                   uint64_t src, uint64_t dst, uint64_t vr)
 {
@@ -484,6 +510,9 @@ static uint32_t do_calc_cc(CPUS390XState *env, uint32_t cc_op,
     case CC_OP_COMP_64:
         r =  cc_calc_comp_64(dst);
         break;
+    case CC_OP_MULS_64:
+        r = cc_calc_muls_64(src, dst);
+        break;
 
     case CC_OP_ADD_32:
         r =  cc_calc_add_32(src, dst, vr);
@@ -512,6 +541,9 @@ static uint32_t do_calc_cc(CPUS390XState *env, uint32_t cc_op,
     case CC_OP_COMP_32:
         r =  cc_calc_comp_32(dst);
         break;
+    case CC_OP_MULS_32:
+        r = cc_calc_muls_32(dst);
+        break;
 
     case CC_OP_ICM:
         r =  cc_calc_icm(src, dst);
diff --git a/target/s390x/helper.c b/target/s390x/helper.c
index 9257d388ba..b877690845 100644
--- a/target/s390x/helper.c
+++ b/target/s390x/helper.c
@@ -430,6 +430,8 @@ const char *cc_name(enum cc_op cc_op)
         [CC_OP_FLOGR]     = "CC_OP_FLOGR",
         [CC_OP_LCBB]      = "CC_OP_LCBB",
         [CC_OP_VC]        = "CC_OP_VC",
+        [CC_OP_MULS_32]   = "CC_OP_MULS_32",
+        [CC_OP_MULS_64]   = "CC_OP_MULS_64",
     };
 
     return cc_names[cc_op];
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index cb40aea9a3..d068708404 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -679,11 +679,15 @@
     C(0xe386, MLG,     RXY_a, Z,   r1p1, m2_64, r1_P, 0, mul128, 0)
 /* MULTIPLY SINGLE */
     C(0xb252, MSR,     RRE,   Z,   r1_o, r2_o, new, r1_32, mul, 0)
+    C(0xb9fd, MSRKC,   RRF_a, MIE2,r3_32s, r2_32s, new, r1_32, mul, muls32)
     C(0x7100, MS,      RX_a,  Z,   r1_o, m2_32s, new, r1_32, mul, 0)
     C(0xe351, MSY,     RXY_a, LD,  r1_o, m2_32s, new, r1_32, mul, 0)
+    C(0xe353, MSC,     RXY_a, MIE2,r1_32s, m2_32s, new, r1_32, mul, muls32)
     C(0xb90c, MSGR,    RRE,   Z,   r1_o, r2_o, r1, 0, mul, 0)
+    C(0xb9ed, MSGRKC,  RRF_a, MIE2,r3_o, r2_o, new_P, out2_r1, muls128, muls64)
     C(0xb91c, MSGFR,   RRE,   Z,   r1_o, r2_32s, r1, 0, mul, 0)
     C(0xe30c, MSG,     RXY_a, Z,   r1_o, m2_64, r1, 0, mul, 0)
+    C(0xe383, MSGC,    RXY_a, MIE2,r1_o, m2_64, new_P, out2_r1, muls128, muls64)
     C(0xe31c, MSGF,    RXY_a, Z,   r1_o, m2_32s, r1, 0, mul, 0)
 /* MULTIPLY SINGLE IMMEDIATE */
     C(0xc201, MSFI,    RIL_a, GIE, r1_o, i2, new, r1_32, mul, 0)
diff --git a/target/s390x/internal.h b/target/s390x/internal.h
index bac0d3c67b..64602660ae 100644
--- a/target/s390x/internal.h
+++ b/target/s390x/internal.h
@@ -175,6 +175,7 @@ enum cc_op {
     CC_OP_SUBB_64,              /* overflow on unsigned sub-borrow (64bit) */
     CC_OP_ABS_64,               /* sign eval on abs (64bit) */
     CC_OP_NABS_64,              /* sign eval on nabs (64bit) */
+    CC_OP_MULS_64,              /* overflow on signed multiply (64bit) */
 
     CC_OP_ADD_32,               /* overflow on add (32bit) */
     CC_OP_ADDU_32,              /* overflow on unsigned add (32bit) */
@@ -184,6 +185,7 @@ enum cc_op {
     CC_OP_SUBB_32,              /* overflow on unsigned sub-borrow (32bit) */
     CC_OP_ABS_32,               /* sign eval on abs (64bit) */
     CC_OP_NABS_32,              /* sign eval on nabs (64bit) */
+    CC_OP_MULS_32,              /* overflow on signed multiply (32bit) */
 
     CC_OP_COMP_32,              /* complement */
     CC_OP_COMP_64,              /* complement */
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index 893b1f54a8..b4e6174244 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -646,6 +646,7 @@ static void gen_op_calc_cc(DisasContext *s)
     case CC_OP_NZ_F64:
     case CC_OP_FLOGR:
     case CC_OP_LCBB:
+    case CC_OP_MULS_32:
         /* 1 argument */
         gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, dummy, cc_dst, dummy);
         break;
@@ -660,6 +661,7 @@ static void gen_op_calc_cc(DisasContext *s)
     case CC_OP_SLA_64:
     case CC_OP_NZ_F128:
     case CC_OP_VC:
+    case CC_OP_MULS_64:
         /* 2 arguments */
         gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, dummy);
         break;
@@ -5289,6 +5291,17 @@ static void cout_tm64(DisasContext *s, DisasOps *o)
     gen_op_update2_cc_i64(s, CC_OP_TM_64, o->in1, o->in2);
 }
 
+static void cout_muls32(DisasContext *s, DisasOps *o)
+{
+    gen_op_update1_cc_i64(s, CC_OP_MULS_32, o->out);
+}
+
+static void cout_muls64(DisasContext *s, DisasOps *o)
+{
+    /* out contains "high" part, out2 contains "low" part of 128 bit result */
+    gen_op_update2_cc_i64(s, CC_OP_MULS_64, o->out, o->out2);
+}
+
 /* ====================================================================== */
 /* The "PREParation" generators.  These initialize the DisasOps.OUT fields
    with the TCG register to which we will write.  Used in combination with
@@ -5344,6 +5357,12 @@ static void wout_r1(DisasContext *s, DisasOps *o)
 }
 #define SPEC_wout_r1 0
 
+static void wout_out2_r1(DisasContext *s, DisasOps *o)
+{
+    store_reg(get_field(s, r1), o->out2);
+}
+#define SPEC_wout_out2_r1 0
+
 static void wout_r1_8(DisasContext *s, DisasOps *o)
 {
     int r1 = get_field(s, r1);
-- 
2.26.2

[PATCH v2 8/9] s390x/tcg: We support Miscellaneous-Instruction-Extensions Facility 2

[David Hildenbrand]

We implement all relevant instructions.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
 target/s390x/gen-features.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/s390x/gen-features.c b/target/s390x/gen-features.c
index 210cee65f3..00af4f95bd 100644
--- a/target/s390x/gen-features.c
+++ b/target/s390x/gen-features.c
@@ -716,6 +716,7 @@ static uint16_t qemu_MAX[] = {
     S390_FEAT_MSA_EXT_5,
     /* features introduced after the z13 */
     S390_FEAT_INSTRUCTION_EXEC_PROT,
+    S390_FEAT_MISC_INSTRUCTION_EXT2,
 };
 
 /****** END FEATURE DEFS ******/
-- 
2.26.2

[PATCH v2 9/9] s390x/tcg: Implement CIPHER MESSAGE WITH AUTHENTICATION (KMA)

[David Hildenbrand]

As with the other crypto functions, we only implement subcode 0 (query)
and no actual encryption/decryption. We now implement S390_FEAT_MSA_EXT_8.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
 target/s390x/gen-features.c | 1 +
 target/s390x/insn-data.def  | 1 +
 target/s390x/translate.c    | 7 +++++++
 3 files changed, 9 insertions(+)

diff --git a/target/s390x/gen-features.c b/target/s390x/gen-features.c
index 00af4f95bd..21c1e912fd 100644
--- a/target/s390x/gen-features.c
+++ b/target/s390x/gen-features.c
@@ -717,6 +717,7 @@ static uint16_t qemu_MAX[] = {
     /* features introduced after the z13 */
     S390_FEAT_INSTRUCTION_EXEC_PROT,
     S390_FEAT_MISC_INSTRUCTION_EXT2,
+    S390_FEAT_MSA_EXT_8,
 };
 
 /****** END FEATURE DEFS ******/
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index d068708404..8ccf54895e 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -979,6 +979,7 @@
     D(0xb92d, KMCTR,   RRF_b, MSA4, 0, 0, 0, 0, msa, 0, S390_FEAT_TYPE_KMCTR)
     D(0xb92e, KM,      RRE,   MSA,  0, 0, 0, 0, msa, 0, S390_FEAT_TYPE_KM)
     D(0xb92f, KMC,     RRE,   MSA,  0, 0, 0, 0, msa, 0, S390_FEAT_TYPE_KMC)
+    D(0xb929, KMA,     RRF_b, MSA8, 0, 0, 0, 0, msa, 0, S390_FEAT_TYPE_KMA)
     D(0xb93c, PPNO,    RRE,   MSA5, 0, 0, 0, 0, msa, 0, S390_FEAT_TYPE_PPNO)
     D(0xb93e, KIMD,    RRE,   MSA,  0, 0, 0, 0, msa, 0, S390_FEAT_TYPE_KIMD)
     D(0xb93f, KLMD,    RRE,   MSA,  0, 0, 0, 0, msa, 0, S390_FEAT_TYPE_KLMD)
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index b4e6174244..f2dc24d71f 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -2710,6 +2710,12 @@ static DisasJumpType op_msa(DisasContext *s, DisasOps *o)
     TCGv_i32 t_r1, t_r2, t_r3, type;
 
     switch (s->insn->data) {
+    case S390_FEAT_TYPE_KMA:
+        if (r3 == r1 || r3 == r2) {
+            gen_program_exception(s, PGM_SPECIFICATION);
+            return DISAS_NORETURN;
+        }
+        /* FALL THROUGH */
     case S390_FEAT_TYPE_KMCTR:
         if (r3 & 1 || !r3) {
             gen_program_exception(s, PGM_SPECIFICATION);
@@ -6133,6 +6139,7 @@ enum DisasInsnEnum {
 #define FAC_MSA3        S390_FEAT_MSA_EXT_3 /* msa-extension-3 facility */
 #define FAC_MSA4        S390_FEAT_MSA_EXT_4 /* msa-extension-4 facility */
 #define FAC_MSA5        S390_FEAT_MSA_EXT_5 /* msa-extension-5 facility */
+#define FAC_MSA8        S390_FEAT_MSA_EXT_8 /* msa-extension-8 facility */
 #define FAC_ECT         S390_FEAT_EXTRACT_CPU_TIME
 #define FAC_PCI         S390_FEAT_ZPCI /* z/PCI facility */
 #define FAC_AIS         S390_FEAT_ADAPTER_INT_SUPPRESSION
-- 
2.26.2

Re: [PATCH v2 1/9] s390x/cpu_model: S390_FEAT_MISC_INSTRUCTION_EXT -> S390_FEAT_MISC_INSTRUCTION_EXT2

[Christian Borntraeger]

On 28.09.20 14:27, David Hildenbrand wrote:
> Let's avoid confusion with the "Miscellaneous-Instruction-Extensions
> Facility 1"
> 
> Suggested-by: Thomas Huth <thuth@redhat.com>
> Cc: Christian Borntraeger <borntraeger@de.ibm.com>
> Signed-off-by: David Hildenbrand <david@redhat.com>
> ---
>  target/s390x/cpu_features_def.h.inc | 2 +-

strange this is target/s390x/cpu_features_def.inc.h in my repo?

>  target/s390x/gen-features.c         | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/target/s390x/cpu_features_def.h.inc b/target/s390x/cpu_features_def.h.inc
> index 5942f81f16..6cc776e121 100644
> --- a/target/s390x/cpu_features_def.h.inc
> +++ b/target/s390x/cpu_features_def.h.inc
> @@ -72,7 +72,7 @@ DEF_FEAT(INTERLOCKED_ACCESS_2, "iacc2", STFL, 52, "Interlocked-access facility 2
>  DEF_FEAT(STFLE_53, "stfle53", STFL, 53, "Various facilities introduced with z13")
>  DEF_FEAT(ENTROPY_ENC_COMP, "eec", STFL, 54, "Entropy encoding compression facility")
>  DEF_FEAT(MSA_EXT_5, "msa5-base", STFL, 57, "Message-security-assist-extension-5 facility (excluding subfunctions)")
> -DEF_FEAT(MISC_INSTRUCTION_EXT, "minste2", STFL, 58, "Miscellaneous-instruction-extensions facility 2")
> +DEF_FEAT(MISC_INSTRUCTION_EXT2, "minste2", STFL, 58, "Miscellaneous-instruction-extensions facility 2")

Right, the 1 variant is part of STFLE_49 and thus not mentioned directly, but as everything else uses the 2 in that
line it makes sense to also rename the define. 


>  DEF_FEAT(SEMAPHORE_ASSIST, "sema", STFL, 59, "Semaphore-assist facility")
>  DEF_FEAT(TIME_SLICE_INSTRUMENTATION, "tsi", STFL, 60, "Time-slice Instrumentation facility")
>  DEF_FEAT(MISC_INSTRUCTION_EXT3, "minste3", STFL, 61, "Miscellaneous-Instruction-Extensions Facility 3")
> diff --git a/target/s390x/gen-features.c b/target/s390x/gen-features.c
> index 8ddeebc544..210cee65f3 100644
> --- a/target/s390x/gen-features.c
> +++ b/target/s390x/gen-features.c
> @@ -412,7 +412,7 @@ static uint16_t base_GEN13_GA1[] = {
>  
>  static uint16_t base_GEN14_GA1[] = {
>      S390_FEAT_ENTROPY_ENC_COMP,
> -    S390_FEAT_MISC_INSTRUCTION_EXT,
> +    S390_FEAT_MISC_INSTRUCTION_EXT2,
>      S390_FEAT_SEMAPHORE_ASSIST,
>      S390_FEAT_TIME_SLICE_INSTRUMENTATION,
>      S390_FEAT_ORDER_PRESERVING_COMPRESSION,
> 

Re: [PATCH v2 1/9] s390x/cpu_model: S390_FEAT_MISC_INSTRUCTION_EXT -> S390_FEAT_MISC_INSTRUCTION_EXT2

[David Hildenbrand]

On 28.09.20 14:50, Christian Borntraeger wrote:
> 
> 
> On 28.09.20 14:27, David Hildenbrand wrote:
>> Let's avoid confusion with the "Miscellaneous-Instruction-Extensions
>> Facility 1"
>>
>> Suggested-by: Thomas Huth <thuth@redhat.com>
>> Cc: Christian Borntraeger <borntraeger@de.ibm.com>
>> Signed-off-by: David Hildenbrand <david@redhat.com>
>> ---
>>  target/s390x/cpu_features_def.h.inc | 2 +-
> 
> strange this is target/s390x/cpu_features_def.inc.h in my repo?

Seems to be due to upstream

commit 0979ed017f093ead3c011513a3a79517ed75bd00
Author: Paolo Bonzini <pbonzini@redhat.com>
Date:   Tue Feb 4 12:41:01 2020 +0100

    meson: rename .inc.h files to .h.inc

    Make it consistent with '.c.inc' and '.rst.inc'.


-- 
Thanks,

David / dhildenb

Re: [PATCH v2 0/9] s390x/tcg: Implement some z14 facilities

[no-reply]

Patchew URL: https://patchew.org/QEMU/20200928122717.30586-1-david@redhat.com/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20200928122717.30586-1-david@redhat.com
Subject: [PATCH v2 0/9] s390x/tcg: Implement some z14 facilities

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 - [tag update]      patchew/20200925162316.21205-1-peter.maydell@linaro.org -> patchew/20200925162316.21205-1-peter.maydell@linaro.org
 * [new tag]         patchew/20200928061201.1601-1-wangzhiqiang.bj@bytedance.com -> patchew/20200928061201.1601-1-wangzhiqiang.bj@bytedance.com
 * [new tag]         patchew/20200928092705.3730-1-wangzhiqiang.bj@bytedance.com -> patchew/20200928092705.3730-1-wangzhiqiang.bj@bytedance.com
 * [new tag]         patchew/20200928125859.734287-1-philmd@redhat.com -> patchew/20200928125859.734287-1-philmd@redhat.com
 * [new tag]         patchew/20200928131934.739451-1-philmd@redhat.com -> patchew/20200928131934.739451-1-philmd@redhat.com
Switched to a new branch 'test'
9d42c6b s390x/tcg: Implement CIPHER MESSAGE WITH AUTHENTICATION (KMA)
33bb426 s390x/tcg: We support Miscellaneous-Instruction-Extensions Facility 2
749f183 s390x/tcg: Implement MULTIPLY SINGLE (MSC, MSGC, MSGRKC, MSRKC)
48d85e6 s390x/tcg: Implement BRANCH INDIRECT ON CONDITION (BIC)
ce04e77 s390x/tcg: Implement MULTIPLY HALFWORD (MGH)
96f9c9c s390x/tcg: Implement MULTIPLY (MG, MGRK)
ff5b047 s390x/tcg: Implement SUBTRACT HALFWORD (SGH)
18f2055 s390x/tcg: Implement ADD HALFWORD (AGH)
7533d8f s390x/cpu_model: S390_FEAT_MISC_INSTRUCTION_EXT -> S390_FEAT_MISC_INSTRUCTION_EXT2

=== OUTPUT BEGIN ===
1/9 Checking commit 7533d8fd7ca1 (s390x/cpu_model: S390_FEAT_MISC_INSTRUCTION_EXT -> S390_FEAT_MISC_INSTRUCTION_EXT2)
2/9 Checking commit 18f20555ed6f (s390x/tcg: Implement ADD HALFWORD (AGH))
ERROR: line over 90 characters
#34: FILE: target/s390x/translate.c:6101:
+#define FAC_MIE2        S390_FEAT_MISC_INSTRUCTION_EXT2 /* miscellaneous-instruction-extensions facility 2 */

total: 1 errors, 0 warnings, 14 lines checked

Patch 2/9 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

3/9 Checking commit ff5b0476125c (s390x/tcg: Implement SUBTRACT HALFWORD (SGH))
4/9 Checking commit 96f9c9cac0e7 (s390x/tcg: Implement MULTIPLY (MG, MGRK))
5/9 Checking commit ce04e77373db (s390x/tcg: Implement MULTIPLY HALFWORD (MGH))
6/9 Checking commit 48d85e6436bb (s390x/tcg: Implement BRANCH INDIRECT ON CONDITION (BIC))
7/9 Checking commit 749f183b9be4 (s390x/tcg: Implement MULTIPLY SINGLE (MSC, MSGC, MSGRKC, MSRKC))
8/9 Checking commit 33bb426469fd (s390x/tcg: We support Miscellaneous-Instruction-Extensions Facility 2)
9/9 Checking commit 9d42c6b7f1f8 (s390x/tcg: Implement CIPHER MESSAGE WITH AUTHENTICATION (KMA))
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20200928122717.30586-1-david@redhat.com/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com

Re: [PATCH v2 0/9] s390x/tcg: Implement some z14 facilities

[Cornelia Huck]

On Mon, 28 Sep 2020 14:27:08 +0200
David Hildenbrand <david@redhat.com> wrote:

> With this patchset, I can boot a kernel compiled for z14 (requiring
> Miscellaneous-Instruction-Extensions Facility 2) (using -cpu max).
> 
> I am currently working on "vector-enhancements facility 1", I have most
> stuff in place except:
> - VECTOR FP (MAXIMUM|MINIMUM): needs some manual work to cover all types of
>                                comparisons.
> 
> Once we have that in place, we can convert the QEMU machine to a
> stripped-down z14.
> 
> v1 -> v2:
> - "s390x/cpu_model: S390_FEAT_MISC_INSTRUCTION_EXT ->
>    S390_FEAT_MISC_INSTRUCTION_EXT2"
> -- Added
> - "s390x/tcg: Implement BRANCH INDIRECT ON CONDITION (BIC)"
> -- Use new helper instead
> - "s390x/tcg: Implement MULTIPLY SINGLE (MSC, MSGC, MSGRKC, MSRKC)"
> -- Tune comparisons in CC computation
> 
> David Hildenbrand (9):
>   s390x/cpu_model: S390_FEAT_MISC_INSTRUCTION_EXT ->
>     S390_FEAT_MISC_INSTRUCTION_EXT2
>   s390x/tcg: Implement ADD HALFWORD (AGH)
>   s390x/tcg: Implement SUBTRACT HALFWORD (SGH)
>   s390x/tcg: Implement MULTIPLY (MG, MGRK)
>   s390x/tcg: Implement MULTIPLY HALFWORD (MGH)
>   s390x/tcg: Implement BRANCH INDIRECT ON CONDITION (BIC)
>   s390x/tcg: Implement MULTIPLY SINGLE (MSC, MSGC, MSGRKC, MSRKC)
>   s390x/tcg: We support Miscellaneous-Instruction-Extensions Facility 2
>   s390x/tcg: Implement CIPHER MESSAGE WITH AUTHENTICATION (KMA)
> 
>  target/s390x/cc_helper.c            | 32 +++++++++++++++++++
>  target/s390x/cpu_features_def.h.inc |  2 +-
>  target/s390x/gen-features.c         |  4 ++-
>  target/s390x/helper.c               |  2 ++
>  target/s390x/insn-data.def          | 12 ++++++++
>  target/s390x/internal.h             |  2 ++
>  target/s390x/translate.c            | 48 +++++++++++++++++++++++++++++
>  7 files changed, 100 insertions(+), 2 deletions(-)

Working on preparing a pull request... I think this still misses review
on two patches?

Re: [PATCH v2 6/9] s390x/tcg: Implement BRANCH INDIRECT ON CONDITION (BIC)

[Richard Henderson]

On 9/28/20 7:27 AM, David Hildenbrand wrote:
> Just like BRANCH ON CONDITION - however the address is read from memory
> (always 8 bytes are read), we have to wrap the address manually. The
> address is read using current CPU DAT/address-space controls, just like
> ordinary data.
> 
> Signed-off-by: David Hildenbrand <david@redhat.com>
> ---
>  target/s390x/insn-data.def | 2 ++
>  target/s390x/translate.c   | 8 ++++++++
>  2 files changed, 10 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH v2 7/9] s390x/tcg: Implement MULTIPLY SINGLE (MSC, MSGC, MSGRKC, MSRKC)

[Richard Henderson]

On 9/28/20 7:27 AM, David Hildenbrand wrote:
> We need new CC handling, determining the CC based on the intermediate
> result (64bit for MSC and MSRKC, 128bit for MSGC and MSGRKC).
> 
> We want to store out2 ("low") after muls128 to r1, so add
> "wout_out2_r1".
> 
> Signed-off-by: David Hildenbrand <david@redhat.com>
> ---
>  target/s390x/cc_helper.c   | 32 ++++++++++++++++++++++++++++++++
>  target/s390x/helper.c      |  2 ++
>  target/s390x/insn-data.def |  4 ++++
>  target/s390x/internal.h    |  2 ++
>  target/s390x/translate.c   | 19 +++++++++++++++++++
>  5 files changed, 59 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH v2 0/9] s390x/tcg: Implement some z14 facilities

[Cornelia Huck]

On Mon, 28 Sep 2020 14:27:08 +0200
David Hildenbrand <david@redhat.com> wrote:

> With this patchset, I can boot a kernel compiled for z14 (requiring
> Miscellaneous-Instruction-Extensions Facility 2) (using -cpu max).
> 
> I am currently working on "vector-enhancements facility 1", I have most
> stuff in place except:
> - VECTOR FP (MAXIMUM|MINIMUM): needs some manual work to cover all types of
>                                comparisons.
> 
> Once we have that in place, we can convert the QEMU machine to a
> stripped-down z14.
> 
> v1 -> v2:
> - "s390x/cpu_model: S390_FEAT_MISC_INSTRUCTION_EXT ->
>    S390_FEAT_MISC_INSTRUCTION_EXT2"
> -- Added
> - "s390x/tcg: Implement BRANCH INDIRECT ON CONDITION (BIC)"
> -- Use new helper instead
> - "s390x/tcg: Implement MULTIPLY SINGLE (MSC, MSGC, MSGRKC, MSRKC)"
> -- Tune comparisons in CC computation
> 
> David Hildenbrand (9):
>   s390x/cpu_model: S390_FEAT_MISC_INSTRUCTION_EXT ->
>     S390_FEAT_MISC_INSTRUCTION_EXT2
>   s390x/tcg: Implement ADD HALFWORD (AGH)
>   s390x/tcg: Implement SUBTRACT HALFWORD (SGH)
>   s390x/tcg: Implement MULTIPLY (MG, MGRK)
>   s390x/tcg: Implement MULTIPLY HALFWORD (MGH)
>   s390x/tcg: Implement BRANCH INDIRECT ON CONDITION (BIC)
>   s390x/tcg: Implement MULTIPLY SINGLE (MSC, MSGC, MSGRKC, MSRKC)
>   s390x/tcg: We support Miscellaneous-Instruction-Extensions Facility 2
>   s390x/tcg: Implement CIPHER MESSAGE WITH AUTHENTICATION (KMA)
> 
>  target/s390x/cc_helper.c            | 32 +++++++++++++++++++
>  target/s390x/cpu_features_def.h.inc |  2 +-
>  target/s390x/gen-features.c         |  4 ++-
>  target/s390x/helper.c               |  2 ++
>  target/s390x/insn-data.def          | 12 ++++++++
>  target/s390x/internal.h             |  2 ++
>  target/s390x/translate.c            | 48 +++++++++++++++++++++++++++++
>  7 files changed, 100 insertions(+), 2 deletions(-)
> 

Thanks, applied.

Re: [PATCH v2 0/9] s390x/tcg: Implement some z14 facilities

[David Hildenbrand]

On 01.10.20 19:02, Cornelia Huck wrote:
> On Mon, 28 Sep 2020 14:27:08 +0200
> David Hildenbrand <david@redhat.com> wrote:
> 
>> With this patchset, I can boot a kernel compiled for z14 (requiring
>> Miscellaneous-Instruction-Extensions Facility 2) (using -cpu max).
>>
>> I am currently working on "vector-enhancements facility 1", I have most
>> stuff in place except:
>> - VECTOR FP (MAXIMUM|MINIMUM): needs some manual work to cover all types of
>>                                comparisons.
>>
>> Once we have that in place, we can convert the QEMU machine to a
>> stripped-down z14.
>>
>> v1 -> v2:
>> - "s390x/cpu_model: S390_FEAT_MISC_INSTRUCTION_EXT ->
>>    S390_FEAT_MISC_INSTRUCTION_EXT2"
>> -- Added
>> - "s390x/tcg: Implement BRANCH INDIRECT ON CONDITION (BIC)"
>> -- Use new helper instead
>> - "s390x/tcg: Implement MULTIPLY SINGLE (MSC, MSGC, MSGRKC, MSRKC)"
>> -- Tune comparisons in CC computation
>>
>> David Hildenbrand (9):
>>   s390x/cpu_model: S390_FEAT_MISC_INSTRUCTION_EXT ->
>>     S390_FEAT_MISC_INSTRUCTION_EXT2
>>   s390x/tcg: Implement ADD HALFWORD (AGH)
>>   s390x/tcg: Implement SUBTRACT HALFWORD (SGH)
>>   s390x/tcg: Implement MULTIPLY (MG, MGRK)
>>   s390x/tcg: Implement MULTIPLY HALFWORD (MGH)
>>   s390x/tcg: Implement BRANCH INDIRECT ON CONDITION (BIC)
>>   s390x/tcg: Implement MULTIPLY SINGLE (MSC, MSGC, MSGRKC, MSRKC)
>>   s390x/tcg: We support Miscellaneous-Instruction-Extensions Facility 2
>>   s390x/tcg: Implement CIPHER MESSAGE WITH AUTHENTICATION (KMA)
>>
>>  target/s390x/cc_helper.c            | 32 +++++++++++++++++++
>>  target/s390x/cpu_features_def.h.inc |  2 +-
>>  target/s390x/gen-features.c         |  4 ++-
>>  target/s390x/helper.c               |  2 ++
>>  target/s390x/insn-data.def          | 12 ++++++++
>>  target/s390x/internal.h             |  2 ++
>>  target/s390x/translate.c            | 48 +++++++++++++++++++++++++++++
>>  7 files changed, 100 insertions(+), 2 deletions(-)
>>
> 
> Thanks, applied.
> 

Can you rename in patch #1 subject "s390x/cpu_model" ->
"s390x/cpumodel"? Thanks!


-- 
Thanks,

David / dhildenb

Re: [PATCH v2 0/9] s390x/tcg: Implement some z14 facilities

[Cornelia Huck]

On Thu, 1 Oct 2020 19:03:39 +0200
David Hildenbrand <david@redhat.com> wrote:

> On 01.10.20 19:02, Cornelia Huck wrote:
> > On Mon, 28 Sep 2020 14:27:08 +0200
> > David Hildenbrand <david@redhat.com> wrote:
> >   
> >> With this patchset, I can boot a kernel compiled for z14 (requiring
> >> Miscellaneous-Instruction-Extensions Facility 2) (using -cpu max).
> >>
> >> I am currently working on "vector-enhancements facility 1", I have most
> >> stuff in place except:
> >> - VECTOR FP (MAXIMUM|MINIMUM): needs some manual work to cover all types of
> >>                                comparisons.
> >>
> >> Once we have that in place, we can convert the QEMU machine to a
> >> stripped-down z14.
> >>
> >> v1 -> v2:
> >> - "s390x/cpu_model: S390_FEAT_MISC_INSTRUCTION_EXT ->
> >>    S390_FEAT_MISC_INSTRUCTION_EXT2"
> >> -- Added
> >> - "s390x/tcg: Implement BRANCH INDIRECT ON CONDITION (BIC)"
> >> -- Use new helper instead
> >> - "s390x/tcg: Implement MULTIPLY SINGLE (MSC, MSGC, MSGRKC, MSRKC)"
> >> -- Tune comparisons in CC computation
> >>
> >> David Hildenbrand (9):
> >>   s390x/cpu_model: S390_FEAT_MISC_INSTRUCTION_EXT ->
> >>     S390_FEAT_MISC_INSTRUCTION_EXT2
> >>   s390x/tcg: Implement ADD HALFWORD (AGH)
> >>   s390x/tcg: Implement SUBTRACT HALFWORD (SGH)
> >>   s390x/tcg: Implement MULTIPLY (MG, MGRK)
> >>   s390x/tcg: Implement MULTIPLY HALFWORD (MGH)
> >>   s390x/tcg: Implement BRANCH INDIRECT ON CONDITION (BIC)
> >>   s390x/tcg: Implement MULTIPLY SINGLE (MSC, MSGC, MSGRKC, MSRKC)
> >>   s390x/tcg: We support Miscellaneous-Instruction-Extensions Facility 2
> >>   s390x/tcg: Implement CIPHER MESSAGE WITH AUTHENTICATION (KMA)
> >>
> >>  target/s390x/cc_helper.c            | 32 +++++++++++++++++++
> >>  target/s390x/cpu_features_def.h.inc |  2 +-
> >>  target/s390x/gen-features.c         |  4 ++-
> >>  target/s390x/helper.c               |  2 ++
> >>  target/s390x/insn-data.def          | 12 ++++++++
> >>  target/s390x/internal.h             |  2 ++
> >>  target/s390x/translate.c            | 48 +++++++++++++++++++++++++++++
> >>  7 files changed, 100 insertions(+), 2 deletions(-)
> >>  
> > 
> > Thanks, applied.
> >   
> 
> Can you rename in patch #1 subject "s390x/cpu_model" ->
> "s390x/cpumodel"? Thanks!

As you wish :) Pushed out.