* [PATCH 05/45] drm/amdgpu: add vangogh_reg_base_init function for van gogh
@ 2020-09-29 15:27 Alex Deucher
2020-09-29 15:27 ` [PATCH 06/45] drm/amdgpu: add nv common ip block support " Alex Deucher
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Alex Deucher @ 2020-09-29 15:27 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
This patch adds vangogh_reg_base_init function to init the register base for
van gogh.
v2: make vangogh_reg_base_init void, align equality sign
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
drivers/gpu/drm/amd/amdgpu/nv.h | 1 +
drivers/gpu/drm/amd/amdgpu/vangogh_reg_init.c | 50 +
.../gpu/drm/amd/include/vangogh_ip_offset.h | 1516 +++++++++++++++++
4 files changed, 1568 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/vangogh_reg_init.c
create mode 100644 drivers/gpu/drm/amd/include/vangogh_ip_offset.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index 39976c7b100c..7866e4666a43 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -69,7 +69,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce
amdgpu-y += \
vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \
vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o navi10_reg_init.o navi14_reg_init.o \
- arct_reg_init.o navi12_reg_init.o mxgpu_nv.o sienna_cichlid_reg_init.o
+ arct_reg_init.o navi12_reg_init.o mxgpu_nv.o sienna_cichlid_reg_init.o vangogh_reg_init.o
# add DF block
amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.h b/drivers/gpu/drm/amd/amdgpu/nv.h
index aeef50a6a54b..bb17e0f434c9 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.h
+++ b/drivers/gpu/drm/amd/amdgpu/nv.h
@@ -34,4 +34,5 @@ int navi10_reg_base_init(struct amdgpu_device *adev);
int navi14_reg_base_init(struct amdgpu_device *adev);
int navi12_reg_base_init(struct amdgpu_device *adev);
int sienna_cichlid_reg_base_init(struct amdgpu_device *adev);
+void vangogh_reg_base_init(struct amdgpu_device *adev);
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/vangogh_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vangogh_reg_init.c
new file mode 100644
index 000000000000..d64d681a05dc
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/vangogh_reg_init.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include "amdgpu.h"
+#include "nv.h"
+
+#include "soc15_common.h"
+#include "soc15_hw_ip.h"
+#include "vangogh_ip_offset.h"
+
+void vangogh_reg_base_init(struct amdgpu_device *adev)
+{
+ /* HW has more IP blocks, only initialized the blocke needed by driver */
+ uint32_t i;
+ for (i = 0 ; i < MAX_INSTANCE ; ++i) {
+ adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
+ adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
+ adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
+ adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
+ adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
+ adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
+ adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
+ adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i]));
+ adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
+ adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCN_BASE.instance[i]));
+ adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));
+ adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
+ adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
+ adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
+ }
+}
diff --git a/drivers/gpu/drm/amd/include/vangogh_ip_offset.h b/drivers/gpu/drm/amd/include/vangogh_ip_offset.h
new file mode 100644
index 000000000000..2875574b060e
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/vangogh_ip_offset.h
@@ -0,0 +1,1516 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __VANGOGH_IP_OFFSET_H__
+#define __VANGOGH_IP_OFFSET_H__
+
+#define MAX_INSTANCE 8
+#define MAX_SEGMENT 6
+
+
+struct IP_BASE_INSTANCE
+{
+ unsigned int segment[MAX_SEGMENT];
+};
+
+struct IP_BASE
+{
+ struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
+};
+
+
+static const struct IP_BASE ACP_BASE = { { { { 0x02403800, 0x00480000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C00, 0x00013300, 0x02408C00, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } },
+ { { 0x00016E00, 0x02401C00, 0, 0, 0, 0 } },
+ { { 0x00017000, 0x02402000, 0, 0, 0, 0 } },
+ { { 0x00017200, 0x02402400, 0, 0, 0, 0 } },
+ { { 0x0001B000, 0x0242D800, 0, 0, 0, 0 } },
+ { { 0x0001B200, 0x0242DC00, 0, 0, 0, 0 } },
+ { { 0x0001B400, 0x0242E000, 0, 0, 0, 0 } },
+ { { 0x00017E00, 0x0240BC00, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0x0240B800, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DPCS_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE FCH_BASE = { { { { 0x0240C000, 0x00B40000, 0x11000000, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0x02401400, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE GC_BASE = { { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0x0240A400, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE ISP_BASE = { { { { 0x00018000, 0x0240B000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MMHUB_BASE = { { { { 0x00013200, 0x0001A000, 0x02408800, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x0243FC00, 0x00DC0000, 0x00E00000, 0x00E40000, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0x0243FC00, 0x00DC0000, 0x00E00000, 0x00E40000, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MP2_BASE = { { { { 0x00016400, 0x02400800, 0x00F40000, 0x00F80000, 0x00FC0000, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0x0240A000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE PCIE0_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0x00016A00, 0x02401000, 0x00440000, 0, 0 } },
+ { { 0x0001BC00, 0x0242D400, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0x02400C00, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0x02425800, 0, 0, 0, 0 } },
+ { { 0x00054000, 0x02425C00, 0, 0, 0, 0 } },
+ { { 0x00094000, 0x02426000, 0, 0, 0, 0 } },
+ { { 0x000D4000, 0x02426400, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE USB_BASE = { { { { 0x0242A800, 0x05B00000, 0, 0, 0, 0 } },
+ { { 0x0242AC00, 0x05B80000, 0, 0, 0, 0 } },
+ { { 0x0242B000, 0x05C00000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE VCN_BASE = { { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+
+
+#define ACP_BASE__INST0_SEG0 0x02403800
+#define ACP_BASE__INST0_SEG1 0x00480000
+#define ACP_BASE__INST0_SEG2 0
+#define ACP_BASE__INST0_SEG3 0
+#define ACP_BASE__INST0_SEG4 0
+#define ACP_BASE__INST0_SEG5 0
+
+#define ACP_BASE__INST1_SEG0 0
+#define ACP_BASE__INST1_SEG1 0
+#define ACP_BASE__INST1_SEG2 0
+#define ACP_BASE__INST1_SEG3 0
+#define ACP_BASE__INST1_SEG4 0
+#define ACP_BASE__INST1_SEG5 0
+
+#define ACP_BASE__INST2_SEG0 0
+#define ACP_BASE__INST2_SEG1 0
+#define ACP_BASE__INST2_SEG2 0
+#define ACP_BASE__INST2_SEG3 0
+#define ACP_BASE__INST2_SEG4 0
+#define ACP_BASE__INST2_SEG5 0
+
+#define ACP_BASE__INST3_SEG0 0
+#define ACP_BASE__INST3_SEG1 0
+#define ACP_BASE__INST3_SEG2 0
+#define ACP_BASE__INST3_SEG3 0
+#define ACP_BASE__INST3_SEG4 0
+#define ACP_BASE__INST3_SEG5 0
+
+#define ACP_BASE__INST4_SEG0 0
+#define ACP_BASE__INST4_SEG1 0
+#define ACP_BASE__INST4_SEG2 0
+#define ACP_BASE__INST4_SEG3 0
+#define ACP_BASE__INST4_SEG4 0
+#define ACP_BASE__INST4_SEG5 0
+
+#define ACP_BASE__INST5_SEG0 0
+#define ACP_BASE__INST5_SEG1 0
+#define ACP_BASE__INST5_SEG2 0
+#define ACP_BASE__INST5_SEG3 0
+#define ACP_BASE__INST5_SEG4 0
+#define ACP_BASE__INST5_SEG5 0
+
+#define ACP_BASE__INST6_SEG0 0
+#define ACP_BASE__INST6_SEG1 0
+#define ACP_BASE__INST6_SEG2 0
+#define ACP_BASE__INST6_SEG3 0
+#define ACP_BASE__INST6_SEG4 0
+#define ACP_BASE__INST6_SEG5 0
+
+#define ACP_BASE__INST7_SEG0 0
+#define ACP_BASE__INST7_SEG1 0
+#define ACP_BASE__INST7_SEG2 0
+#define ACP_BASE__INST7_SEG3 0
+#define ACP_BASE__INST7_SEG4 0
+#define ACP_BASE__INST7_SEG5 0
+
+#define ATHUB_BASE__INST0_SEG0 0x00000C00
+#define ATHUB_BASE__INST0_SEG1 0x00013300
+#define ATHUB_BASE__INST0_SEG2 0x02408C00
+#define ATHUB_BASE__INST0_SEG3 0
+#define ATHUB_BASE__INST0_SEG4 0
+#define ATHUB_BASE__INST0_SEG5 0
+
+#define ATHUB_BASE__INST1_SEG0 0
+#define ATHUB_BASE__INST1_SEG1 0
+#define ATHUB_BASE__INST1_SEG2 0
+#define ATHUB_BASE__INST1_SEG3 0
+#define ATHUB_BASE__INST1_SEG4 0
+#define ATHUB_BASE__INST1_SEG5 0
+
+#define ATHUB_BASE__INST2_SEG0 0
+#define ATHUB_BASE__INST2_SEG1 0
+#define ATHUB_BASE__INST2_SEG2 0
+#define ATHUB_BASE__INST2_SEG3 0
+#define ATHUB_BASE__INST2_SEG4 0
+#define ATHUB_BASE__INST2_SEG5 0
+
+#define ATHUB_BASE__INST3_SEG0 0
+#define ATHUB_BASE__INST3_SEG1 0
+#define ATHUB_BASE__INST3_SEG2 0
+#define ATHUB_BASE__INST3_SEG3 0
+#define ATHUB_BASE__INST3_SEG4 0
+#define ATHUB_BASE__INST3_SEG5 0
+
+#define ATHUB_BASE__INST4_SEG0 0
+#define ATHUB_BASE__INST4_SEG1 0
+#define ATHUB_BASE__INST4_SEG2 0
+#define ATHUB_BASE__INST4_SEG3 0
+#define ATHUB_BASE__INST4_SEG4 0
+#define ATHUB_BASE__INST4_SEG5 0
+
+#define ATHUB_BASE__INST5_SEG0 0
+#define ATHUB_BASE__INST5_SEG1 0
+#define ATHUB_BASE__INST5_SEG2 0
+#define ATHUB_BASE__INST5_SEG3 0
+#define ATHUB_BASE__INST5_SEG4 0
+#define ATHUB_BASE__INST5_SEG5 0
+
+#define ATHUB_BASE__INST6_SEG0 0
+#define ATHUB_BASE__INST6_SEG1 0
+#define ATHUB_BASE__INST6_SEG2 0
+#define ATHUB_BASE__INST6_SEG3 0
+#define ATHUB_BASE__INST6_SEG4 0
+#define ATHUB_BASE__INST6_SEG5 0
+
+#define ATHUB_BASE__INST7_SEG0 0
+#define ATHUB_BASE__INST7_SEG1 0
+#define ATHUB_BASE__INST7_SEG2 0
+#define ATHUB_BASE__INST7_SEG3 0
+#define ATHUB_BASE__INST7_SEG4 0
+#define ATHUB_BASE__INST7_SEG5 0
+
+#define CLK_BASE__INST0_SEG0 0x00016C00
+#define CLK_BASE__INST0_SEG1 0x02401800
+#define CLK_BASE__INST0_SEG2 0
+#define CLK_BASE__INST0_SEG3 0
+#define CLK_BASE__INST0_SEG4 0
+#define CLK_BASE__INST0_SEG5 0
+
+#define CLK_BASE__INST1_SEG0 0x00016E00
+#define CLK_BASE__INST1_SEG1 0x02401C00
+#define CLK_BASE__INST1_SEG2 0
+#define CLK_BASE__INST1_SEG3 0
+#define CLK_BASE__INST1_SEG4 0
+#define CLK_BASE__INST1_SEG5 0
+
+#define CLK_BASE__INST2_SEG0 0x00017000
+#define CLK_BASE__INST2_SEG1 0x02402000
+#define CLK_BASE__INST2_SEG2 0
+#define CLK_BASE__INST2_SEG3 0
+#define CLK_BASE__INST2_SEG4 0
+#define CLK_BASE__INST2_SEG5 0
+
+#define CLK_BASE__INST3_SEG0 0x00017200
+#define CLK_BASE__INST3_SEG1 0x02402400
+#define CLK_BASE__INST3_SEG2 0
+#define CLK_BASE__INST3_SEG3 0
+#define CLK_BASE__INST3_SEG4 0
+#define CLK_BASE__INST3_SEG5 0
+
+#define CLK_BASE__INST4_SEG0 0x0001B000
+#define CLK_BASE__INST4_SEG1 0x0242D800
+#define CLK_BASE__INST4_SEG2 0
+#define CLK_BASE__INST4_SEG3 0
+#define CLK_BASE__INST4_SEG4 0
+#define CLK_BASE__INST4_SEG5 0
+
+#define CLK_BASE__INST5_SEG0 0x0001B200
+#define CLK_BASE__INST5_SEG1 0x0242DC00
+#define CLK_BASE__INST5_SEG2 0
+#define CLK_BASE__INST5_SEG3 0
+#define CLK_BASE__INST5_SEG4 0
+#define CLK_BASE__INST5_SEG5 0
+
+#define CLK_BASE__INST6_SEG0 0x0001B400
+#define CLK_BASE__INST6_SEG1 0x0242E000
+#define CLK_BASE__INST6_SEG2 0
+#define CLK_BASE__INST6_SEG3 0
+#define CLK_BASE__INST6_SEG4 0
+#define CLK_BASE__INST6_SEG5 0
+
+#define CLK_BASE__INST7_SEG0 0x00017E00
+#define CLK_BASE__INST7_SEG1 0x0240BC00
+#define CLK_BASE__INST7_SEG2 0
+#define CLK_BASE__INST7_SEG3 0
+#define CLK_BASE__INST7_SEG4 0
+#define CLK_BASE__INST7_SEG5 0
+
+#define DF_BASE__INST0_SEG0 0x00007000
+#define DF_BASE__INST0_SEG1 0x0240B800
+#define DF_BASE__INST0_SEG2 0
+#define DF_BASE__INST0_SEG3 0
+#define DF_BASE__INST0_SEG4 0
+#define DF_BASE__INST0_SEG5 0
+
+#define DF_BASE__INST1_SEG0 0
+#define DF_BASE__INST1_SEG1 0
+#define DF_BASE__INST1_SEG2 0
+#define DF_BASE__INST1_SEG3 0
+#define DF_BASE__INST1_SEG4 0
+#define DF_BASE__INST1_SEG5 0
+
+#define DF_BASE__INST2_SEG0 0
+#define DF_BASE__INST2_SEG1 0
+#define DF_BASE__INST2_SEG2 0
+#define DF_BASE__INST2_SEG3 0
+#define DF_BASE__INST2_SEG4 0
+#define DF_BASE__INST2_SEG5 0
+
+#define DF_BASE__INST3_SEG0 0
+#define DF_BASE__INST3_SEG1 0
+#define DF_BASE__INST3_SEG2 0
+#define DF_BASE__INST3_SEG3 0
+#define DF_BASE__INST3_SEG4 0
+#define DF_BASE__INST3_SEG5 0
+
+#define DF_BASE__INST4_SEG0 0
+#define DF_BASE__INST4_SEG1 0
+#define DF_BASE__INST4_SEG2 0
+#define DF_BASE__INST4_SEG3 0
+#define DF_BASE__INST4_SEG4 0
+#define DF_BASE__INST4_SEG5 0
+
+#define DF_BASE__INST5_SEG0 0
+#define DF_BASE__INST5_SEG1 0
+#define DF_BASE__INST5_SEG2 0
+#define DF_BASE__INST5_SEG3 0
+#define DF_BASE__INST5_SEG4 0
+#define DF_BASE__INST5_SEG5 0
+
+#define DF_BASE__INST6_SEG0 0
+#define DF_BASE__INST6_SEG1 0
+#define DF_BASE__INST6_SEG2 0
+#define DF_BASE__INST6_SEG3 0
+#define DF_BASE__INST6_SEG4 0
+#define DF_BASE__INST6_SEG5 0
+
+#define DF_BASE__INST7_SEG0 0
+#define DF_BASE__INST7_SEG1 0
+#define DF_BASE__INST7_SEG2 0
+#define DF_BASE__INST7_SEG3 0
+#define DF_BASE__INST7_SEG4 0
+#define DF_BASE__INST7_SEG5 0
+
+#define DCN_BASE__INST0_SEG0 0x00000012
+#define DCN_BASE__INST0_SEG1 0x000000C0
+#define DCN_BASE__INST0_SEG2 0x000034C0
+#define DCN_BASE__INST0_SEG3 0x00009000
+#define DCN_BASE__INST0_SEG4 0x02403C00
+#define DCN_BASE__INST0_SEG5 0
+
+#define DCN_BASE__INST1_SEG0 0
+#define DCN_BASE__INST1_SEG1 0
+#define DCN_BASE__INST1_SEG2 0
+#define DCN_BASE__INST1_SEG3 0
+#define DCN_BASE__INST1_SEG4 0
+#define DCN_BASE__INST1_SEG5 0
+
+#define DCN_BASE__INST2_SEG0 0
+#define DCN_BASE__INST2_SEG1 0
+#define DCN_BASE__INST2_SEG2 0
+#define DCN_BASE__INST2_SEG3 0
+#define DCN_BASE__INST2_SEG4 0
+#define DCN_BASE__INST2_SEG5 0
+
+#define DCN_BASE__INST3_SEG0 0
+#define DCN_BASE__INST3_SEG1 0
+#define DCN_BASE__INST3_SEG2 0
+#define DCN_BASE__INST3_SEG3 0
+#define DCN_BASE__INST3_SEG4 0
+#define DCN_BASE__INST3_SEG5 0
+
+#define DCN_BASE__INST4_SEG0 0
+#define DCN_BASE__INST4_SEG1 0
+#define DCN_BASE__INST4_SEG2 0
+#define DCN_BASE__INST4_SEG3 0
+#define DCN_BASE__INST4_SEG4 0
+#define DCN_BASE__INST4_SEG5 0
+
+#define DCN_BASE__INST5_SEG0 0
+#define DCN_BASE__INST5_SEG1 0
+#define DCN_BASE__INST5_SEG2 0
+#define DCN_BASE__INST5_SEG3 0
+#define DCN_BASE__INST5_SEG4 0
+#define DCN_BASE__INST5_SEG5 0
+
+#define DCN_BASE__INST6_SEG0 0
+#define DCN_BASE__INST6_SEG1 0
+#define DCN_BASE__INST6_SEG2 0
+#define DCN_BASE__INST6_SEG3 0
+#define DCN_BASE__INST6_SEG4 0
+#define DCN_BASE__INST6_SEG5 0
+
+#define DCN_BASE__INST7_SEG0 0
+#define DCN_BASE__INST7_SEG1 0
+#define DCN_BASE__INST7_SEG2 0
+#define DCN_BASE__INST7_SEG3 0
+#define DCN_BASE__INST7_SEG4 0
+#define DCN_BASE__INST7_SEG5 0
+
+#define DPCS_BASE__INST0_SEG0 0x00000012
+#define DPCS_BASE__INST0_SEG1 0x000000C0
+#define DPCS_BASE__INST0_SEG2 0x000034C0
+#define DPCS_BASE__INST0_SEG3 0x00009000
+#define DPCS_BASE__INST0_SEG4 0x02403C00
+#define DPCS_BASE__INST0_SEG5 0
+
+#define DPCS_BASE__INST1_SEG0 0
+#define DPCS_BASE__INST1_SEG1 0
+#define DPCS_BASE__INST1_SEG2 0
+#define DPCS_BASE__INST1_SEG3 0
+#define DPCS_BASE__INST1_SEG4 0
+#define DPCS_BASE__INST1_SEG5 0
+
+#define DPCS_BASE__INST2_SEG0 0
+#define DPCS_BASE__INST2_SEG1 0
+#define DPCS_BASE__INST2_SEG2 0
+#define DPCS_BASE__INST2_SEG3 0
+#define DPCS_BASE__INST2_SEG4 0
+#define DPCS_BASE__INST2_SEG5 0
+
+#define DPCS_BASE__INST3_SEG0 0
+#define DPCS_BASE__INST3_SEG1 0
+#define DPCS_BASE__INST3_SEG2 0
+#define DPCS_BASE__INST3_SEG3 0
+#define DPCS_BASE__INST3_SEG4 0
+#define DPCS_BASE__INST3_SEG5 0
+
+#define DPCS_BASE__INST4_SEG0 0
+#define DPCS_BASE__INST4_SEG1 0
+#define DPCS_BASE__INST4_SEG2 0
+#define DPCS_BASE__INST4_SEG3 0
+#define DPCS_BASE__INST4_SEG4 0
+#define DPCS_BASE__INST4_SEG5 0
+
+#define DPCS_BASE__INST5_SEG0 0
+#define DPCS_BASE__INST5_SEG1 0
+#define DPCS_BASE__INST5_SEG2 0
+#define DPCS_BASE__INST5_SEG3 0
+#define DPCS_BASE__INST5_SEG4 0
+#define DPCS_BASE__INST5_SEG5 0
+
+#define DPCS_BASE__INST6_SEG0 0
+#define DPCS_BASE__INST6_SEG1 0
+#define DPCS_BASE__INST6_SEG2 0
+#define DPCS_BASE__INST6_SEG3 0
+#define DPCS_BASE__INST6_SEG4 0
+#define DPCS_BASE__INST6_SEG5 0
+
+#define DPCS_BASE__INST7_SEG0 0
+#define DPCS_BASE__INST7_SEG1 0
+#define DPCS_BASE__INST7_SEG2 0
+#define DPCS_BASE__INST7_SEG3 0
+#define DPCS_BASE__INST7_SEG4 0
+#define DPCS_BASE__INST7_SEG5 0
+
+#define FCH_BASE__INST0_SEG0 0x0240C000
+#define FCH_BASE__INST0_SEG1 0x00B40000
+#define FCH_BASE__INST0_SEG2 0x11000000
+#define FCH_BASE__INST0_SEG3 0
+#define FCH_BASE__INST0_SEG4 0
+#define FCH_BASE__INST0_SEG5 0
+
+#define FCH_BASE__INST1_SEG0 0
+#define FCH_BASE__INST1_SEG1 0
+#define FCH_BASE__INST1_SEG2 0
+#define FCH_BASE__INST1_SEG3 0
+#define FCH_BASE__INST1_SEG4 0
+#define FCH_BASE__INST1_SEG5 0
+
+#define FCH_BASE__INST2_SEG0 0
+#define FCH_BASE__INST2_SEG1 0
+#define FCH_BASE__INST2_SEG2 0
+#define FCH_BASE__INST2_SEG3 0
+#define FCH_BASE__INST2_SEG4 0
+#define FCH_BASE__INST2_SEG5 0
+
+#define FCH_BASE__INST3_SEG0 0
+#define FCH_BASE__INST3_SEG1 0
+#define FCH_BASE__INST3_SEG2 0
+#define FCH_BASE__INST3_SEG3 0
+#define FCH_BASE__INST3_SEG4 0
+#define FCH_BASE__INST3_SEG5 0
+
+#define FCH_BASE__INST4_SEG0 0
+#define FCH_BASE__INST4_SEG1 0
+#define FCH_BASE__INST4_SEG2 0
+#define FCH_BASE__INST4_SEG3 0
+#define FCH_BASE__INST4_SEG4 0
+#define FCH_BASE__INST4_SEG5 0
+
+#define FCH_BASE__INST5_SEG0 0
+#define FCH_BASE__INST5_SEG1 0
+#define FCH_BASE__INST5_SEG2 0
+#define FCH_BASE__INST5_SEG3 0
+#define FCH_BASE__INST5_SEG4 0
+#define FCH_BASE__INST5_SEG5 0
+
+#define FCH_BASE__INST6_SEG0 0
+#define FCH_BASE__INST6_SEG1 0
+#define FCH_BASE__INST6_SEG2 0
+#define FCH_BASE__INST6_SEG3 0
+#define FCH_BASE__INST6_SEG4 0
+#define FCH_BASE__INST6_SEG5 0
+
+#define FCH_BASE__INST7_SEG0 0
+#define FCH_BASE__INST7_SEG1 0
+#define FCH_BASE__INST7_SEG2 0
+#define FCH_BASE__INST7_SEG3 0
+#define FCH_BASE__INST7_SEG4 0
+#define FCH_BASE__INST7_SEG5 0
+
+#define FUSE_BASE__INST0_SEG0 0x00017400
+#define FUSE_BASE__INST0_SEG1 0x02401400
+#define FUSE_BASE__INST0_SEG2 0
+#define FUSE_BASE__INST0_SEG3 0
+#define FUSE_BASE__INST0_SEG4 0
+#define FUSE_BASE__INST0_SEG5 0
+
+#define FUSE_BASE__INST1_SEG0 0
+#define FUSE_BASE__INST1_SEG1 0
+#define FUSE_BASE__INST1_SEG2 0
+#define FUSE_BASE__INST1_SEG3 0
+#define FUSE_BASE__INST1_SEG4 0
+#define FUSE_BASE__INST1_SEG5 0
+
+#define FUSE_BASE__INST2_SEG0 0
+#define FUSE_BASE__INST2_SEG1 0
+#define FUSE_BASE__INST2_SEG2 0
+#define FUSE_BASE__INST2_SEG3 0
+#define FUSE_BASE__INST2_SEG4 0
+#define FUSE_BASE__INST2_SEG5 0
+
+#define FUSE_BASE__INST3_SEG0 0
+#define FUSE_BASE__INST3_SEG1 0
+#define FUSE_BASE__INST3_SEG2 0
+#define FUSE_BASE__INST3_SEG3 0
+#define FUSE_BASE__INST3_SEG4 0
+#define FUSE_BASE__INST3_SEG5 0
+
+#define FUSE_BASE__INST4_SEG0 0
+#define FUSE_BASE__INST4_SEG1 0
+#define FUSE_BASE__INST4_SEG2 0
+#define FUSE_BASE__INST4_SEG3 0
+#define FUSE_BASE__INST4_SEG4 0
+#define FUSE_BASE__INST4_SEG5 0
+
+#define FUSE_BASE__INST5_SEG0 0
+#define FUSE_BASE__INST5_SEG1 0
+#define FUSE_BASE__INST5_SEG2 0
+#define FUSE_BASE__INST5_SEG3 0
+#define FUSE_BASE__INST5_SEG4 0
+#define FUSE_BASE__INST5_SEG5 0
+
+#define FUSE_BASE__INST6_SEG0 0
+#define FUSE_BASE__INST6_SEG1 0
+#define FUSE_BASE__INST6_SEG2 0
+#define FUSE_BASE__INST6_SEG3 0
+#define FUSE_BASE__INST6_SEG4 0
+#define FUSE_BASE__INST6_SEG5 0
+
+#define FUSE_BASE__INST7_SEG0 0
+#define FUSE_BASE__INST7_SEG1 0
+#define FUSE_BASE__INST7_SEG2 0
+#define FUSE_BASE__INST7_SEG3 0
+#define FUSE_BASE__INST7_SEG4 0
+#define FUSE_BASE__INST7_SEG5 0
+
+#define GC_BASE__INST0_SEG0 0x00001260
+#define GC_BASE__INST0_SEG1 0x0000A000
+#define GC_BASE__INST0_SEG2 0x02402C00
+#define GC_BASE__INST0_SEG3 0
+#define GC_BASE__INST0_SEG4 0
+#define GC_BASE__INST0_SEG5 0
+
+#define GC_BASE__INST1_SEG0 0
+#define GC_BASE__INST1_SEG1 0
+#define GC_BASE__INST1_SEG2 0
+#define GC_BASE__INST1_SEG3 0
+#define GC_BASE__INST1_SEG4 0
+#define GC_BASE__INST1_SEG5 0
+
+#define GC_BASE__INST2_SEG0 0
+#define GC_BASE__INST2_SEG1 0
+#define GC_BASE__INST2_SEG2 0
+#define GC_BASE__INST2_SEG3 0
+#define GC_BASE__INST2_SEG4 0
+#define GC_BASE__INST2_SEG5 0
+
+#define GC_BASE__INST3_SEG0 0
+#define GC_BASE__INST3_SEG1 0
+#define GC_BASE__INST3_SEG2 0
+#define GC_BASE__INST3_SEG3 0
+#define GC_BASE__INST3_SEG4 0
+#define GC_BASE__INST3_SEG5 0
+
+#define GC_BASE__INST4_SEG0 0
+#define GC_BASE__INST4_SEG1 0
+#define GC_BASE__INST4_SEG2 0
+#define GC_BASE__INST4_SEG3 0
+#define GC_BASE__INST4_SEG4 0
+#define GC_BASE__INST4_SEG5 0
+
+#define GC_BASE__INST5_SEG0 0
+#define GC_BASE__INST5_SEG1 0
+#define GC_BASE__INST5_SEG2 0
+#define GC_BASE__INST5_SEG3 0
+#define GC_BASE__INST5_SEG4 0
+#define GC_BASE__INST5_SEG5 0
+
+#define GC_BASE__INST6_SEG0 0
+#define GC_BASE__INST6_SEG1 0
+#define GC_BASE__INST6_SEG2 0
+#define GC_BASE__INST6_SEG3 0
+#define GC_BASE__INST6_SEG4 0
+#define GC_BASE__INST6_SEG5 0
+
+#define GC_BASE__INST7_SEG0 0
+#define GC_BASE__INST7_SEG1 0
+#define GC_BASE__INST7_SEG2 0
+#define GC_BASE__INST7_SEG3 0
+#define GC_BASE__INST7_SEG4 0
+#define GC_BASE__INST7_SEG5 0
+
+#define HDP_BASE__INST0_SEG0 0x00000F20
+#define HDP_BASE__INST0_SEG1 0x0240A400
+#define HDP_BASE__INST0_SEG2 0
+#define HDP_BASE__INST0_SEG3 0
+#define HDP_BASE__INST0_SEG4 0
+#define HDP_BASE__INST0_SEG5 0
+
+#define HDP_BASE__INST1_SEG0 0
+#define HDP_BASE__INST1_SEG1 0
+#define HDP_BASE__INST1_SEG2 0
+#define HDP_BASE__INST1_SEG3 0
+#define HDP_BASE__INST1_SEG4 0
+#define HDP_BASE__INST1_SEG5 0
+
+#define HDP_BASE__INST2_SEG0 0
+#define HDP_BASE__INST2_SEG1 0
+#define HDP_BASE__INST2_SEG2 0
+#define HDP_BASE__INST2_SEG3 0
+#define HDP_BASE__INST2_SEG4 0
+#define HDP_BASE__INST2_SEG5 0
+
+#define HDP_BASE__INST3_SEG0 0
+#define HDP_BASE__INST3_SEG1 0
+#define HDP_BASE__INST3_SEG2 0
+#define HDP_BASE__INST3_SEG3 0
+#define HDP_BASE__INST3_SEG4 0
+#define HDP_BASE__INST3_SEG5 0
+
+#define HDP_BASE__INST4_SEG0 0
+#define HDP_BASE__INST4_SEG1 0
+#define HDP_BASE__INST4_SEG2 0
+#define HDP_BASE__INST4_SEG3 0
+#define HDP_BASE__INST4_SEG4 0
+#define HDP_BASE__INST4_SEG5 0
+
+#define HDP_BASE__INST5_SEG0 0
+#define HDP_BASE__INST5_SEG1 0
+#define HDP_BASE__INST5_SEG2 0
+#define HDP_BASE__INST5_SEG3 0
+#define HDP_BASE__INST5_SEG4 0
+#define HDP_BASE__INST5_SEG5 0
+
+#define HDP_BASE__INST6_SEG0 0
+#define HDP_BASE__INST6_SEG1 0
+#define HDP_BASE__INST6_SEG2 0
+#define HDP_BASE__INST6_SEG3 0
+#define HDP_BASE__INST6_SEG4 0
+#define HDP_BASE__INST6_SEG5 0
+
+#define HDP_BASE__INST7_SEG0 0
+#define HDP_BASE__INST7_SEG1 0
+#define HDP_BASE__INST7_SEG2 0
+#define HDP_BASE__INST7_SEG3 0
+#define HDP_BASE__INST7_SEG4 0
+#define HDP_BASE__INST7_SEG5 0
+
+#define ISP_BASE__INST0_SEG0 0x00018000
+#define ISP_BASE__INST0_SEG1 0x0240B000
+#define ISP_BASE__INST0_SEG2 0
+#define ISP_BASE__INST0_SEG3 0
+#define ISP_BASE__INST0_SEG4 0
+#define ISP_BASE__INST0_SEG5 0
+
+#define ISP_BASE__INST1_SEG0 0
+#define ISP_BASE__INST1_SEG1 0
+#define ISP_BASE__INST1_SEG2 0
+#define ISP_BASE__INST1_SEG3 0
+#define ISP_BASE__INST1_SEG4 0
+#define ISP_BASE__INST1_SEG5 0
+
+#define ISP_BASE__INST2_SEG0 0
+#define ISP_BASE__INST2_SEG1 0
+#define ISP_BASE__INST2_SEG2 0
+#define ISP_BASE__INST2_SEG3 0
+#define ISP_BASE__INST2_SEG4 0
+#define ISP_BASE__INST2_SEG5 0
+
+#define ISP_BASE__INST3_SEG0 0
+#define ISP_BASE__INST3_SEG1 0
+#define ISP_BASE__INST3_SEG2 0
+#define ISP_BASE__INST3_SEG3 0
+#define ISP_BASE__INST3_SEG4 0
+#define ISP_BASE__INST3_SEG5 0
+
+#define ISP_BASE__INST4_SEG0 0
+#define ISP_BASE__INST4_SEG1 0
+#define ISP_BASE__INST4_SEG2 0
+#define ISP_BASE__INST4_SEG3 0
+#define ISP_BASE__INST4_SEG4 0
+#define ISP_BASE__INST4_SEG5 0
+
+#define ISP_BASE__INST5_SEG0 0
+#define ISP_BASE__INST5_SEG1 0
+#define ISP_BASE__INST5_SEG2 0
+#define ISP_BASE__INST5_SEG3 0
+#define ISP_BASE__INST5_SEG4 0
+#define ISP_BASE__INST5_SEG5 0
+
+#define ISP_BASE__INST6_SEG0 0
+#define ISP_BASE__INST6_SEG1 0
+#define ISP_BASE__INST6_SEG2 0
+#define ISP_BASE__INST6_SEG3 0
+#define ISP_BASE__INST6_SEG4 0
+#define ISP_BASE__INST6_SEG5 0
+
+#define ISP_BASE__INST7_SEG0 0
+#define ISP_BASE__INST7_SEG1 0
+#define ISP_BASE__INST7_SEG2 0
+#define ISP_BASE__INST7_SEG3 0
+#define ISP_BASE__INST7_SEG4 0
+#define ISP_BASE__INST7_SEG5 0
+
+#define MMHUB_BASE__INST0_SEG0 0x00013200
+#define MMHUB_BASE__INST0_SEG1 0x0001A000
+#define MMHUB_BASE__INST0_SEG2 0x02408800
+#define MMHUB_BASE__INST0_SEG3 0
+#define MMHUB_BASE__INST0_SEG4 0
+#define MMHUB_BASE__INST0_SEG5 0
+
+#define MMHUB_BASE__INST1_SEG0 0
+#define MMHUB_BASE__INST1_SEG1 0
+#define MMHUB_BASE__INST1_SEG2 0
+#define MMHUB_BASE__INST1_SEG3 0
+#define MMHUB_BASE__INST1_SEG4 0
+#define MMHUB_BASE__INST1_SEG5 0
+
+#define MMHUB_BASE__INST2_SEG0 0
+#define MMHUB_BASE__INST2_SEG1 0
+#define MMHUB_BASE__INST2_SEG2 0
+#define MMHUB_BASE__INST2_SEG3 0
+#define MMHUB_BASE__INST2_SEG4 0
+#define MMHUB_BASE__INST2_SEG5 0
+
+#define MMHUB_BASE__INST3_SEG0 0
+#define MMHUB_BASE__INST3_SEG1 0
+#define MMHUB_BASE__INST3_SEG2 0
+#define MMHUB_BASE__INST3_SEG3 0
+#define MMHUB_BASE__INST3_SEG4 0
+#define MMHUB_BASE__INST3_SEG5 0
+
+#define MMHUB_BASE__INST4_SEG0 0
+#define MMHUB_BASE__INST4_SEG1 0
+#define MMHUB_BASE__INST4_SEG2 0
+#define MMHUB_BASE__INST4_SEG3 0
+#define MMHUB_BASE__INST4_SEG4 0
+#define MMHUB_BASE__INST4_SEG5 0
+
+#define MMHUB_BASE__INST5_SEG0 0
+#define MMHUB_BASE__INST5_SEG1 0
+#define MMHUB_BASE__INST5_SEG2 0
+#define MMHUB_BASE__INST5_SEG3 0
+#define MMHUB_BASE__INST5_SEG4 0
+#define MMHUB_BASE__INST5_SEG5 0
+
+#define MMHUB_BASE__INST6_SEG0 0
+#define MMHUB_BASE__INST6_SEG1 0
+#define MMHUB_BASE__INST6_SEG2 0
+#define MMHUB_BASE__INST6_SEG3 0
+#define MMHUB_BASE__INST6_SEG4 0
+#define MMHUB_BASE__INST6_SEG5 0
+
+#define MMHUB_BASE__INST7_SEG0 0
+#define MMHUB_BASE__INST7_SEG1 0
+#define MMHUB_BASE__INST7_SEG2 0
+#define MMHUB_BASE__INST7_SEG3 0
+#define MMHUB_BASE__INST7_SEG4 0
+#define MMHUB_BASE__INST7_SEG5 0
+
+#define MP0_BASE__INST0_SEG0 0x00016000
+#define MP0_BASE__INST0_SEG1 0x0243FC00
+#define MP0_BASE__INST0_SEG2 0x00DC0000
+#define MP0_BASE__INST0_SEG3 0x00E00000
+#define MP0_BASE__INST0_SEG4 0x00E40000
+#define MP0_BASE__INST0_SEG5 0
+
+#define MP0_BASE__INST1_SEG0 0
+#define MP0_BASE__INST1_SEG1 0
+#define MP0_BASE__INST1_SEG2 0
+#define MP0_BASE__INST1_SEG3 0
+#define MP0_BASE__INST1_SEG4 0
+#define MP0_BASE__INST1_SEG5 0
+
+#define MP0_BASE__INST2_SEG0 0
+#define MP0_BASE__INST2_SEG1 0
+#define MP0_BASE__INST2_SEG2 0
+#define MP0_BASE__INST2_SEG3 0
+#define MP0_BASE__INST2_SEG4 0
+#define MP0_BASE__INST2_SEG5 0
+
+#define MP0_BASE__INST3_SEG0 0
+#define MP0_BASE__INST3_SEG1 0
+#define MP0_BASE__INST3_SEG2 0
+#define MP0_BASE__INST3_SEG3 0
+#define MP0_BASE__INST3_SEG4 0
+#define MP0_BASE__INST3_SEG5 0
+
+#define MP0_BASE__INST4_SEG0 0
+#define MP0_BASE__INST4_SEG1 0
+#define MP0_BASE__INST4_SEG2 0
+#define MP0_BASE__INST4_SEG3 0
+#define MP0_BASE__INST4_SEG4 0
+#define MP0_BASE__INST4_SEG5 0
+
+#define MP0_BASE__INST5_SEG0 0
+#define MP0_BASE__INST5_SEG1 0
+#define MP0_BASE__INST5_SEG2 0
+#define MP0_BASE__INST5_SEG3 0
+#define MP0_BASE__INST5_SEG4 0
+#define MP0_BASE__INST5_SEG5 0
+
+#define MP0_BASE__INST6_SEG0 0
+#define MP0_BASE__INST6_SEG1 0
+#define MP0_BASE__INST6_SEG2 0
+#define MP0_BASE__INST6_SEG3 0
+#define MP0_BASE__INST6_SEG4 0
+#define MP0_BASE__INST6_SEG5 0
+
+#define MP0_BASE__INST7_SEG0 0
+#define MP0_BASE__INST7_SEG1 0
+#define MP0_BASE__INST7_SEG2 0
+#define MP0_BASE__INST7_SEG3 0
+#define MP0_BASE__INST7_SEG4 0
+#define MP0_BASE__INST7_SEG5 0
+
+#define MP1_BASE__INST0_SEG0 0x00016000
+#define MP1_BASE__INST0_SEG1 0x0243FC00
+#define MP1_BASE__INST0_SEG2 0x00DC0000
+#define MP1_BASE__INST0_SEG3 0x00E00000
+#define MP1_BASE__INST0_SEG4 0x00E40000
+#define MP1_BASE__INST0_SEG5 0
+
+#define MP1_BASE__INST1_SEG0 0
+#define MP1_BASE__INST1_SEG1 0
+#define MP1_BASE__INST1_SEG2 0
+#define MP1_BASE__INST1_SEG3 0
+#define MP1_BASE__INST1_SEG4 0
+#define MP1_BASE__INST1_SEG5 0
+
+#define MP1_BASE__INST2_SEG0 0
+#define MP1_BASE__INST2_SEG1 0
+#define MP1_BASE__INST2_SEG2 0
+#define MP1_BASE__INST2_SEG3 0
+#define MP1_BASE__INST2_SEG4 0
+#define MP1_BASE__INST2_SEG5 0
+
+#define MP1_BASE__INST3_SEG0 0
+#define MP1_BASE__INST3_SEG1 0
+#define MP1_BASE__INST3_SEG2 0
+#define MP1_BASE__INST3_SEG3 0
+#define MP1_BASE__INST3_SEG4 0
+#define MP1_BASE__INST3_SEG5 0
+
+#define MP1_BASE__INST4_SEG0 0
+#define MP1_BASE__INST4_SEG1 0
+#define MP1_BASE__INST4_SEG2 0
+#define MP1_BASE__INST4_SEG3 0
+#define MP1_BASE__INST4_SEG4 0
+#define MP1_BASE__INST4_SEG5 0
+
+#define MP1_BASE__INST5_SEG0 0
+#define MP1_BASE__INST5_SEG1 0
+#define MP1_BASE__INST5_SEG2 0
+#define MP1_BASE__INST5_SEG3 0
+#define MP1_BASE__INST5_SEG4 0
+#define MP1_BASE__INST5_SEG5 0
+
+#define MP1_BASE__INST6_SEG0 0
+#define MP1_BASE__INST6_SEG1 0
+#define MP1_BASE__INST6_SEG2 0
+#define MP1_BASE__INST6_SEG3 0
+#define MP1_BASE__INST6_SEG4 0
+#define MP1_BASE__INST6_SEG5 0
+
+#define MP1_BASE__INST7_SEG0 0
+#define MP1_BASE__INST7_SEG1 0
+#define MP1_BASE__INST7_SEG2 0
+#define MP1_BASE__INST7_SEG3 0
+#define MP1_BASE__INST7_SEG4 0
+#define MP1_BASE__INST7_SEG5 0
+
+#define MP2_BASE__INST0_SEG0 0x00016400
+#define MP2_BASE__INST0_SEG1 0x02400800
+#define MP2_BASE__INST0_SEG2 0x00F40000
+#define MP2_BASE__INST0_SEG3 0x00F80000
+#define MP2_BASE__INST0_SEG4 0x00FC0000
+#define MP2_BASE__INST0_SEG5 0
+
+#define MP2_BASE__INST1_SEG0 0
+#define MP2_BASE__INST1_SEG1 0
+#define MP2_BASE__INST1_SEG2 0
+#define MP2_BASE__INST1_SEG3 0
+#define MP2_BASE__INST1_SEG4 0
+#define MP2_BASE__INST1_SEG5 0
+
+#define MP2_BASE__INST2_SEG0 0
+#define MP2_BASE__INST2_SEG1 0
+#define MP2_BASE__INST2_SEG2 0
+#define MP2_BASE__INST2_SEG3 0
+#define MP2_BASE__INST2_SEG4 0
+#define MP2_BASE__INST2_SEG5 0
+
+#define MP2_BASE__INST3_SEG0 0
+#define MP2_BASE__INST3_SEG1 0
+#define MP2_BASE__INST3_SEG2 0
+#define MP2_BASE__INST3_SEG3 0
+#define MP2_BASE__INST3_SEG4 0
+#define MP2_BASE__INST3_SEG5 0
+
+#define MP2_BASE__INST4_SEG0 0
+#define MP2_BASE__INST4_SEG1 0
+#define MP2_BASE__INST4_SEG2 0
+#define MP2_BASE__INST4_SEG3 0
+#define MP2_BASE__INST4_SEG4 0
+#define MP2_BASE__INST4_SEG5 0
+
+#define MP2_BASE__INST5_SEG0 0
+#define MP2_BASE__INST5_SEG1 0
+#define MP2_BASE__INST5_SEG2 0
+#define MP2_BASE__INST5_SEG3 0
+#define MP2_BASE__INST5_SEG4 0
+#define MP2_BASE__INST5_SEG5 0
+
+#define MP2_BASE__INST6_SEG0 0
+#define MP2_BASE__INST6_SEG1 0
+#define MP2_BASE__INST6_SEG2 0
+#define MP2_BASE__INST6_SEG3 0
+#define MP2_BASE__INST6_SEG4 0
+#define MP2_BASE__INST6_SEG5 0
+
+#define MP2_BASE__INST7_SEG0 0
+#define MP2_BASE__INST7_SEG1 0
+#define MP2_BASE__INST7_SEG2 0
+#define MP2_BASE__INST7_SEG3 0
+#define MP2_BASE__INST7_SEG4 0
+#define MP2_BASE__INST7_SEG5 0
+
+#define NBIO_BASE__INST0_SEG0 0x00000000
+#define NBIO_BASE__INST0_SEG1 0x00000014
+#define NBIO_BASE__INST0_SEG2 0x00000D20
+#define NBIO_BASE__INST0_SEG3 0x00010400
+#define NBIO_BASE__INST0_SEG4 0x0241B000
+#define NBIO_BASE__INST0_SEG5 0x04040000
+
+#define NBIO_BASE__INST1_SEG0 0
+#define NBIO_BASE__INST1_SEG1 0
+#define NBIO_BASE__INST1_SEG2 0
+#define NBIO_BASE__INST1_SEG3 0
+#define NBIO_BASE__INST1_SEG4 0
+#define NBIO_BASE__INST1_SEG5 0
+
+#define NBIO_BASE__INST2_SEG0 0
+#define NBIO_BASE__INST2_SEG1 0
+#define NBIO_BASE__INST2_SEG2 0
+#define NBIO_BASE__INST2_SEG3 0
+#define NBIO_BASE__INST2_SEG4 0
+#define NBIO_BASE__INST2_SEG5 0
+
+#define NBIO_BASE__INST3_SEG0 0
+#define NBIO_BASE__INST3_SEG1 0
+#define NBIO_BASE__INST3_SEG2 0
+#define NBIO_BASE__INST3_SEG3 0
+#define NBIO_BASE__INST3_SEG4 0
+#define NBIO_BASE__INST3_SEG5 0
+
+#define NBIO_BASE__INST4_SEG0 0
+#define NBIO_BASE__INST4_SEG1 0
+#define NBIO_BASE__INST4_SEG2 0
+#define NBIO_BASE__INST4_SEG3 0
+#define NBIO_BASE__INST4_SEG4 0
+#define NBIO_BASE__INST4_SEG5 0
+
+#define NBIO_BASE__INST5_SEG0 0
+#define NBIO_BASE__INST5_SEG1 0
+#define NBIO_BASE__INST5_SEG2 0
+#define NBIO_BASE__INST5_SEG3 0
+#define NBIO_BASE__INST5_SEG4 0
+#define NBIO_BASE__INST5_SEG5 0
+
+#define NBIO_BASE__INST6_SEG0 0
+#define NBIO_BASE__INST6_SEG1 0
+#define NBIO_BASE__INST6_SEG2 0
+#define NBIO_BASE__INST6_SEG3 0
+#define NBIO_BASE__INST6_SEG4 0
+#define NBIO_BASE__INST6_SEG5 0
+
+#define NBIO_BASE__INST7_SEG0 0
+#define NBIO_BASE__INST7_SEG1 0
+#define NBIO_BASE__INST7_SEG2 0
+#define NBIO_BASE__INST7_SEG3 0
+#define NBIO_BASE__INST7_SEG4 0
+#define NBIO_BASE__INST7_SEG5 0
+
+#define OSSSYS_BASE__INST0_SEG0 0x000010A0
+#define OSSSYS_BASE__INST0_SEG1 0x0240A000
+#define OSSSYS_BASE__INST0_SEG2 0
+#define OSSSYS_BASE__INST0_SEG3 0
+#define OSSSYS_BASE__INST0_SEG4 0
+#define OSSSYS_BASE__INST0_SEG5 0
+
+#define OSSSYS_BASE__INST1_SEG0 0
+#define OSSSYS_BASE__INST1_SEG1 0
+#define OSSSYS_BASE__INST1_SEG2 0
+#define OSSSYS_BASE__INST1_SEG3 0
+#define OSSSYS_BASE__INST1_SEG4 0
+#define OSSSYS_BASE__INST1_SEG5 0
+
+#define OSSSYS_BASE__INST2_SEG0 0
+#define OSSSYS_BASE__INST2_SEG1 0
+#define OSSSYS_BASE__INST2_SEG2 0
+#define OSSSYS_BASE__INST2_SEG3 0
+#define OSSSYS_BASE__INST2_SEG4 0
+#define OSSSYS_BASE__INST2_SEG5 0
+
+#define OSSSYS_BASE__INST3_SEG0 0
+#define OSSSYS_BASE__INST3_SEG1 0
+#define OSSSYS_BASE__INST3_SEG2 0
+#define OSSSYS_BASE__INST3_SEG3 0
+#define OSSSYS_BASE__INST3_SEG4 0
+#define OSSSYS_BASE__INST3_SEG5 0
+
+#define OSSSYS_BASE__INST4_SEG0 0
+#define OSSSYS_BASE__INST4_SEG1 0
+#define OSSSYS_BASE__INST4_SEG2 0
+#define OSSSYS_BASE__INST4_SEG3 0
+#define OSSSYS_BASE__INST4_SEG4 0
+#define OSSSYS_BASE__INST4_SEG5 0
+
+#define OSSSYS_BASE__INST5_SEG0 0
+#define OSSSYS_BASE__INST5_SEG1 0
+#define OSSSYS_BASE__INST5_SEG2 0
+#define OSSSYS_BASE__INST5_SEG3 0
+#define OSSSYS_BASE__INST5_SEG4 0
+#define OSSSYS_BASE__INST5_SEG5 0
+
+#define OSSSYS_BASE__INST6_SEG0 0
+#define OSSSYS_BASE__INST6_SEG1 0
+#define OSSSYS_BASE__INST6_SEG2 0
+#define OSSSYS_BASE__INST6_SEG3 0
+#define OSSSYS_BASE__INST6_SEG4 0
+#define OSSSYS_BASE__INST6_SEG5 0
+
+#define OSSSYS_BASE__INST7_SEG0 0
+#define OSSSYS_BASE__INST7_SEG1 0
+#define OSSSYS_BASE__INST7_SEG2 0
+#define OSSSYS_BASE__INST7_SEG3 0
+#define OSSSYS_BASE__INST7_SEG4 0
+#define OSSSYS_BASE__INST7_SEG5 0
+
+#define PCIE0_BASE__INST0_SEG0 0x00000000
+#define PCIE0_BASE__INST0_SEG1 0x00000014
+#define PCIE0_BASE__INST0_SEG2 0x00000D20
+#define PCIE0_BASE__INST0_SEG3 0x00010400
+#define PCIE0_BASE__INST0_SEG4 0x0241B000
+#define PCIE0_BASE__INST0_SEG5 0x04040000
+
+#define PCIE0_BASE__INST1_SEG0 0
+#define PCIE0_BASE__INST1_SEG1 0
+#define PCIE0_BASE__INST1_SEG2 0
+#define PCIE0_BASE__INST1_SEG3 0
+#define PCIE0_BASE__INST1_SEG4 0
+#define PCIE0_BASE__INST1_SEG5 0
+
+#define PCIE0_BASE__INST2_SEG0 0
+#define PCIE0_BASE__INST2_SEG1 0
+#define PCIE0_BASE__INST2_SEG2 0
+#define PCIE0_BASE__INST2_SEG3 0
+#define PCIE0_BASE__INST2_SEG4 0
+#define PCIE0_BASE__INST2_SEG5 0
+
+#define PCIE0_BASE__INST3_SEG0 0
+#define PCIE0_BASE__INST3_SEG1 0
+#define PCIE0_BASE__INST3_SEG2 0
+#define PCIE0_BASE__INST3_SEG3 0
+#define PCIE0_BASE__INST3_SEG4 0
+#define PCIE0_BASE__INST3_SEG5 0
+
+#define PCIE0_BASE__INST4_SEG0 0
+#define PCIE0_BASE__INST4_SEG1 0
+#define PCIE0_BASE__INST4_SEG2 0
+#define PCIE0_BASE__INST4_SEG3 0
+#define PCIE0_BASE__INST4_SEG4 0
+#define PCIE0_BASE__INST4_SEG5 0
+
+#define PCIE0_BASE__INST5_SEG0 0
+#define PCIE0_BASE__INST5_SEG1 0
+#define PCIE0_BASE__INST5_SEG2 0
+#define PCIE0_BASE__INST5_SEG3 0
+#define PCIE0_BASE__INST5_SEG4 0
+#define PCIE0_BASE__INST5_SEG5 0
+
+#define PCIE0_BASE__INST6_SEG0 0
+#define PCIE0_BASE__INST6_SEG1 0
+#define PCIE0_BASE__INST6_SEG2 0
+#define PCIE0_BASE__INST6_SEG3 0
+#define PCIE0_BASE__INST6_SEG4 0
+#define PCIE0_BASE__INST6_SEG5 0
+
+#define PCIE0_BASE__INST7_SEG0 0
+#define PCIE0_BASE__INST7_SEG1 0
+#define PCIE0_BASE__INST7_SEG2 0
+#define PCIE0_BASE__INST7_SEG3 0
+#define PCIE0_BASE__INST7_SEG4 0
+#define PCIE0_BASE__INST7_SEG5 0
+
+#define SMUIO_BASE__INST0_SEG0 0x00016800
+#define SMUIO_BASE__INST0_SEG1 0x00016A00
+#define SMUIO_BASE__INST0_SEG2 0x02401000
+#define SMUIO_BASE__INST0_SEG3 0x00440000
+#define SMUIO_BASE__INST0_SEG4 0
+#define SMUIO_BASE__INST0_SEG5 0
+
+#define SMUIO_BASE__INST1_SEG0 0x0001BC00
+#define SMUIO_BASE__INST1_SEG1 0x0242D400
+#define SMUIO_BASE__INST1_SEG2 0
+#define SMUIO_BASE__INST1_SEG3 0
+#define SMUIO_BASE__INST1_SEG4 0
+#define SMUIO_BASE__INST1_SEG5 0
+
+#define SMUIO_BASE__INST2_SEG0 0
+#define SMUIO_BASE__INST2_SEG1 0
+#define SMUIO_BASE__INST2_SEG2 0
+#define SMUIO_BASE__INST2_SEG3 0
+#define SMUIO_BASE__INST2_SEG4 0
+#define SMUIO_BASE__INST2_SEG5 0
+
+#define SMUIO_BASE__INST3_SEG0 0
+#define SMUIO_BASE__INST3_SEG1 0
+#define SMUIO_BASE__INST3_SEG2 0
+#define SMUIO_BASE__INST3_SEG3 0
+#define SMUIO_BASE__INST3_SEG4 0
+#define SMUIO_BASE__INST3_SEG5 0
+
+#define SMUIO_BASE__INST4_SEG0 0
+#define SMUIO_BASE__INST4_SEG1 0
+#define SMUIO_BASE__INST4_SEG2 0
+#define SMUIO_BASE__INST4_SEG3 0
+#define SMUIO_BASE__INST4_SEG4 0
+#define SMUIO_BASE__INST4_SEG5 0
+
+#define SMUIO_BASE__INST5_SEG0 0
+#define SMUIO_BASE__INST5_SEG1 0
+#define SMUIO_BASE__INST5_SEG2 0
+#define SMUIO_BASE__INST5_SEG3 0
+#define SMUIO_BASE__INST5_SEG4 0
+#define SMUIO_BASE__INST5_SEG5 0
+
+#define SMUIO_BASE__INST6_SEG0 0
+#define SMUIO_BASE__INST6_SEG1 0
+#define SMUIO_BASE__INST6_SEG2 0
+#define SMUIO_BASE__INST6_SEG3 0
+#define SMUIO_BASE__INST6_SEG4 0
+#define SMUIO_BASE__INST6_SEG5 0
+
+#define SMUIO_BASE__INST7_SEG0 0
+#define SMUIO_BASE__INST7_SEG1 0
+#define SMUIO_BASE__INST7_SEG2 0
+#define SMUIO_BASE__INST7_SEG3 0
+#define SMUIO_BASE__INST7_SEG4 0
+#define SMUIO_BASE__INST7_SEG5 0
+
+#define THM_BASE__INST0_SEG0 0x00016600
+#define THM_BASE__INST0_SEG1 0x02400C00
+#define THM_BASE__INST0_SEG2 0
+#define THM_BASE__INST0_SEG3 0
+#define THM_BASE__INST0_SEG4 0
+#define THM_BASE__INST0_SEG5 0
+
+#define THM_BASE__INST1_SEG0 0
+#define THM_BASE__INST1_SEG1 0
+#define THM_BASE__INST1_SEG2 0
+#define THM_BASE__INST1_SEG3 0
+#define THM_BASE__INST1_SEG4 0
+#define THM_BASE__INST1_SEG5 0
+
+#define THM_BASE__INST2_SEG0 0
+#define THM_BASE__INST2_SEG1 0
+#define THM_BASE__INST2_SEG2 0
+#define THM_BASE__INST2_SEG3 0
+#define THM_BASE__INST2_SEG4 0
+#define THM_BASE__INST2_SEG5 0
+
+#define THM_BASE__INST3_SEG0 0
+#define THM_BASE__INST3_SEG1 0
+#define THM_BASE__INST3_SEG2 0
+#define THM_BASE__INST3_SEG3 0
+#define THM_BASE__INST3_SEG4 0
+#define THM_BASE__INST3_SEG5 0
+
+#define THM_BASE__INST4_SEG0 0
+#define THM_BASE__INST4_SEG1 0
+#define THM_BASE__INST4_SEG2 0
+#define THM_BASE__INST4_SEG3 0
+#define THM_BASE__INST4_SEG4 0
+#define THM_BASE__INST4_SEG5 0
+
+#define THM_BASE__INST5_SEG0 0
+#define THM_BASE__INST5_SEG1 0
+#define THM_BASE__INST5_SEG2 0
+#define THM_BASE__INST5_SEG3 0
+#define THM_BASE__INST5_SEG4 0
+#define THM_BASE__INST5_SEG5 0
+
+#define THM_BASE__INST6_SEG0 0
+#define THM_BASE__INST6_SEG1 0
+#define THM_BASE__INST6_SEG2 0
+#define THM_BASE__INST6_SEG3 0
+#define THM_BASE__INST6_SEG4 0
+#define THM_BASE__INST6_SEG5 0
+
+#define THM_BASE__INST7_SEG0 0
+#define THM_BASE__INST7_SEG1 0
+#define THM_BASE__INST7_SEG2 0
+#define THM_BASE__INST7_SEG3 0
+#define THM_BASE__INST7_SEG4 0
+#define THM_BASE__INST7_SEG5 0
+
+#define UMC_BASE__INST0_SEG0 0x00014000
+#define UMC_BASE__INST0_SEG1 0x02425800
+#define UMC_BASE__INST0_SEG2 0
+#define UMC_BASE__INST0_SEG3 0
+#define UMC_BASE__INST0_SEG4 0
+#define UMC_BASE__INST0_SEG5 0
+
+#define UMC_BASE__INST1_SEG0 0x00054000
+#define UMC_BASE__INST1_SEG1 0x02425C00
+#define UMC_BASE__INST1_SEG2 0
+#define UMC_BASE__INST1_SEG3 0
+#define UMC_BASE__INST1_SEG4 0
+#define UMC_BASE__INST1_SEG5 0
+
+#define UMC_BASE__INST2_SEG0 0x00094000
+#define UMC_BASE__INST2_SEG1 0x02426000
+#define UMC_BASE__INST2_SEG2 0
+#define UMC_BASE__INST2_SEG3 0
+#define UMC_BASE__INST2_SEG4 0
+#define UMC_BASE__INST2_SEG5 0
+
+#define UMC_BASE__INST3_SEG0 0x000D4000
+#define UMC_BASE__INST3_SEG1 0x02426400
+#define UMC_BASE__INST3_SEG2 0
+#define UMC_BASE__INST3_SEG3 0
+#define UMC_BASE__INST3_SEG4 0
+#define UMC_BASE__INST3_SEG5 0
+
+#define UMC_BASE__INST4_SEG0 0
+#define UMC_BASE__INST4_SEG1 0
+#define UMC_BASE__INST4_SEG2 0
+#define UMC_BASE__INST4_SEG3 0
+#define UMC_BASE__INST4_SEG4 0
+#define UMC_BASE__INST4_SEG5 0
+
+#define UMC_BASE__INST5_SEG0 0
+#define UMC_BASE__INST5_SEG1 0
+#define UMC_BASE__INST5_SEG2 0
+#define UMC_BASE__INST5_SEG3 0
+#define UMC_BASE__INST5_SEG4 0
+#define UMC_BASE__INST5_SEG5 0
+
+#define UMC_BASE__INST6_SEG0 0
+#define UMC_BASE__INST6_SEG1 0
+#define UMC_BASE__INST6_SEG2 0
+#define UMC_BASE__INST6_SEG3 0
+#define UMC_BASE__INST6_SEG4 0
+#define UMC_BASE__INST6_SEG5 0
+
+#define UMC_BASE__INST7_SEG0 0
+#define UMC_BASE__INST7_SEG1 0
+#define UMC_BASE__INST7_SEG2 0
+#define UMC_BASE__INST7_SEG3 0
+#define UMC_BASE__INST7_SEG4 0
+#define UMC_BASE__INST7_SEG5 0
+
+#define USB_BASE__INST0_SEG0 0x0242A800
+#define USB_BASE__INST0_SEG1 0x05B00000
+#define USB_BASE__INST0_SEG2 0
+#define USB_BASE__INST0_SEG3 0
+#define USB_BASE__INST0_SEG4 0
+#define USB_BASE__INST0_SEG5 0
+
+#define USB_BASE__INST1_SEG0 0x0242AC00
+#define USB_BASE__INST1_SEG1 0x05B80000
+#define USB_BASE__INST1_SEG2 0
+#define USB_BASE__INST1_SEG3 0
+#define USB_BASE__INST1_SEG4 0
+#define USB_BASE__INST1_SEG5 0
+
+#define USB_BASE__INST2_SEG0 0x0242B000
+#define USB_BASE__INST2_SEG1 0x05C00000
+#define USB_BASE__INST2_SEG2 0
+#define USB_BASE__INST2_SEG3 0
+#define USB_BASE__INST2_SEG4 0
+#define USB_BASE__INST2_SEG5 0
+
+#define USB_BASE__INST3_SEG0 0
+#define USB_BASE__INST3_SEG1 0
+#define USB_BASE__INST3_SEG2 0
+#define USB_BASE__INST3_SEG3 0
+#define USB_BASE__INST3_SEG4 0
+#define USB_BASE__INST3_SEG5 0
+
+#define USB_BASE__INST4_SEG0 0
+#define USB_BASE__INST4_SEG1 0
+#define USB_BASE__INST4_SEG2 0
+#define USB_BASE__INST4_SEG3 0
+#define USB_BASE__INST4_SEG4 0
+#define USB_BASE__INST4_SEG5 0
+
+#define USB_BASE__INST5_SEG0 0
+#define USB_BASE__INST5_SEG1 0
+#define USB_BASE__INST5_SEG2 0
+#define USB_BASE__INST5_SEG3 0
+#define USB_BASE__INST5_SEG4 0
+#define USB_BASE__INST5_SEG5 0
+
+#define USB_BASE__INST6_SEG0 0
+#define USB_BASE__INST6_SEG1 0
+#define USB_BASE__INST6_SEG2 0
+#define USB_BASE__INST6_SEG3 0
+#define USB_BASE__INST6_SEG4 0
+#define USB_BASE__INST6_SEG5 0
+
+#define USB_BASE__INST7_SEG0 0
+#define USB_BASE__INST7_SEG1 0
+#define USB_BASE__INST7_SEG2 0
+#define USB_BASE__INST7_SEG3 0
+#define USB_BASE__INST7_SEG4 0
+#define USB_BASE__INST7_SEG5 0
+
+#define VCN_BASE__INST0_SEG0 0x00007800
+#define VCN_BASE__INST0_SEG1 0x00007E00
+#define VCN_BASE__INST0_SEG2 0x02403000
+#define VCN_BASE__INST0_SEG3 0
+#define VCN_BASE__INST0_SEG4 0
+#define VCN_BASE__INST0_SEG5 0
+
+#define VCN_BASE__INST1_SEG0 0
+#define VCN_BASE__INST1_SEG1 0
+#define VCN_BASE__INST1_SEG2 0
+#define VCN_BASE__INST1_SEG3 0
+#define VCN_BASE__INST1_SEG4 0
+#define VCN_BASE__INST1_SEG5 0
+
+#define VCN_BASE__INST2_SEG0 0
+#define VCN_BASE__INST2_SEG1 0
+#define VCN_BASE__INST2_SEG2 0
+#define VCN_BASE__INST2_SEG3 0
+#define VCN_BASE__INST2_SEG4 0
+#define VCN_BASE__INST2_SEG5 0
+
+#define VCN_BASE__INST3_SEG0 0
+#define VCN_BASE__INST3_SEG1 0
+#define VCN_BASE__INST3_SEG2 0
+#define VCN_BASE__INST3_SEG3 0
+#define VCN_BASE__INST3_SEG4 0
+#define VCN_BASE__INST3_SEG5 0
+
+#define VCN_BASE__INST4_SEG0 0
+#define VCN_BASE__INST4_SEG1 0
+#define VCN_BASE__INST4_SEG2 0
+#define VCN_BASE__INST4_SEG3 0
+#define VCN_BASE__INST4_SEG4 0
+#define VCN_BASE__INST4_SEG5 0
+
+#define VCN_BASE__INST5_SEG0 0
+#define VCN_BASE__INST5_SEG1 0
+#define VCN_BASE__INST5_SEG2 0
+#define VCN_BASE__INST5_SEG3 0
+#define VCN_BASE__INST5_SEG4 0
+#define VCN_BASE__INST5_SEG5 0
+
+#define VCN_BASE__INST6_SEG0 0
+#define VCN_BASE__INST6_SEG1 0
+#define VCN_BASE__INST6_SEG2 0
+#define VCN_BASE__INST6_SEG3 0
+#define VCN_BASE__INST6_SEG4 0
+#define VCN_BASE__INST6_SEG5 0
+
+#define VCN_BASE__INST7_SEG0 0
+#define VCN_BASE__INST7_SEG1 0
+#define VCN_BASE__INST7_SEG2 0
+#define VCN_BASE__INST7_SEG3 0
+#define VCN_BASE__INST7_SEG4 0
+#define VCN_BASE__INST7_SEG5 0
+
+#endif
--
2.25.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 06/45] drm/amdgpu: add nv common ip block support for van gogh
2020-09-29 15:27 [PATCH 05/45] drm/amdgpu: add vangogh_reg_base_init function for van gogh Alex Deucher
@ 2020-09-29 15:27 ` Alex Deucher
2020-09-29 15:27 ` [PATCH 09/45] drm/amdgpu: use gpu virtual address for interrupt packet write space for vangogh Alex Deucher
2020-09-29 15:27 ` [PATCH 36/45] drm/amdgpu: add TOC firmware support for apu (v3) Alex Deucher
2 siblings, 0 replies; 9+ messages in thread
From: Alex Deucher @ 2020-09-29 15:27 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
This patch adds common ip support for van gogh.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/nv.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index bc894cfba60c..2077f897d6eb 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -478,6 +478,9 @@ static int nv_reg_base_init(struct amdgpu_device *adev)
case CHIP_NAVY_FLOUNDER:
sienna_cichlid_reg_base_init(adev);
break;
+ case CHIP_VANGOGH:
+ vangogh_reg_base_init(adev);
+ break;
default:
return -EINVAL;
}
@@ -858,6 +861,11 @@ static int nv_common_early_init(void *handle)
adev->external_rev_id = adev->rev_id + 0x32;
break;
+ case CHIP_VANGOGH:
+ adev->cg_flags = 0;
+ adev->pg_flags = 0;
+ adev->external_rev_id = adev->rev_id + 0x01;
+ break;
default:
/* FIXME: not supported yet */
return -EINVAL;
--
2.25.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 09/45] drm/amdgpu: use gpu virtual address for interrupt packet write space for vangogh
2020-09-29 15:27 [PATCH 05/45] drm/amdgpu: add vangogh_reg_base_init function for van gogh Alex Deucher
2020-09-29 15:27 ` [PATCH 06/45] drm/amdgpu: add nv common ip block support " Alex Deucher
@ 2020-09-29 15:27 ` Alex Deucher
2020-09-29 15:27 ` [PATCH 36/45] drm/amdgpu: add TOC firmware support for apu (v3) Alex Deucher
2 siblings, 0 replies; 9+ messages in thread
From: Alex Deucher @ 2020-09-29 15:27 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
The interrupts are not stable while uses guest physical address (GPA)
for interrupt packet write space even on direct loading case.
v2: make condition more readable
Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index ce4a974ab777..53ea83c08e8e 100644
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
@@ -661,8 +661,11 @@ static int navi10_ih_sw_init(void *handle)
/* use gpu virtual address for ih ring
* until ih_checken is programmed to allow
* use bus address for ih ring by psp bl */
- use_bus_addr =
- (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) ? false : true;
+ if ((adev->flags & AMD_IS_APU) ||
+ (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
+ use_bus_addr = false;
+ else
+ use_bus_addr = true;
r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr);
if (r)
return r;
--
2.25.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 36/45] drm/amdgpu: add TOC firmware support for apu (v3)
2020-09-29 15:27 [PATCH 05/45] drm/amdgpu: add vangogh_reg_base_init function for van gogh Alex Deucher
2020-09-29 15:27 ` [PATCH 06/45] drm/amdgpu: add nv common ip block support " Alex Deucher
2020-09-29 15:27 ` [PATCH 09/45] drm/amdgpu: use gpu virtual address for interrupt packet write space for vangogh Alex Deucher
@ 2020-09-29 15:27 ` Alex Deucher
2 siblings, 0 replies; 9+ messages in thread
From: Alex Deucher @ 2020-09-29 15:27 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
APU needs load toc firmware for gfx10 series on psp front door loading.
v2: rebase against latest code
v3: clarify error message
Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 11 ++++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 36 +++++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 7 +++++
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 33 ++++++++++++++++-------
4 files changed, 77 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index bd0d14419841..26caa8d43483 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -325,6 +325,10 @@ static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
fw_info->ver = adev->dm.dmcub_fw_version;
fw_info->feature = 0;
break;
+ case AMDGPU_INFO_FW_TOC:
+ fw_info->ver = adev->psp.toc_fw_version;
+ fw_info->feature = adev->psp.toc_feature_version;
+ break;
default:
return -EINVAL;
}
@@ -1464,6 +1468,13 @@ static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data)
seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n",
fw_info.feature, fw_info.ver);
+ /* TOC */
+ query_fw.fw_type = AMDGPU_INFO_FW_TOC;
+ ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
+ if (ret)
+ return ret;
+ seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n",
+ fw_info.feature, fw_info.ver);
seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 18be544d8c1e..62ae7b4ff275 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -2415,6 +2415,42 @@ int psp_init_asd_microcode(struct psp_context *psp,
return err;
}
+int psp_init_toc_microcode(struct psp_context *psp,
+ const char *chip_name)
+{
+ struct amdgpu_device *adev = psp->adev;
+ char fw_name[30];
+ const struct psp_firmware_header_v1_0 *toc_hdr;
+ int err = 0;
+
+ if (!chip_name) {
+ dev_err(adev->dev, "invalid chip name for toc microcode\n");
+ return -EINVAL;
+ }
+
+ snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name);
+ err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev);
+ if (err)
+ goto out;
+
+ err = amdgpu_ucode_validate(adev->psp.toc_fw);
+ if (err)
+ goto out;
+
+ toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
+ adev->psp.toc_fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
+ adev->psp.toc_feature_version = le32_to_cpu(toc_hdr->ucode_feature_version);
+ adev->psp.toc_bin_size = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
+ adev->psp.toc_start_addr = (uint8_t *)toc_hdr +
+ le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
+ return 0;
+out:
+ dev_err(adev->dev, "fail to request/validate toc microcode\n");
+ release_firmware(adev->psp.toc_fw);
+ adev->psp.toc_fw = NULL;
+ return err;
+}
+
int psp_init_sos_microcode(struct psp_context *psp,
const char *chip_name)
{
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 919d2fb7427b..13f56618660a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -253,6 +253,11 @@ struct psp_context
uint32_t asd_ucode_size;
uint8_t *asd_start_addr;
+ /* toc firmware */
+ const struct firmware *toc_fw;
+ uint32_t toc_fw_version;
+ uint32_t toc_feature_version;
+
/* fence buffer */
struct amdgpu_bo *fence_buf_bo;
uint64_t fence_buf_mc_addr;
@@ -386,6 +391,8 @@ int psp_ring_cmd_submit(struct psp_context *psp,
int index);
int psp_init_asd_microcode(struct psp_context *psp,
const char *chip_name);
+int psp_init_toc_microcode(struct psp_context *psp,
+ const char *chip_name);
int psp_init_sos_microcode(struct psp_context *psp,
const char *chip_name);
int psp_init_ta_microcode(struct psp_context *psp,
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index 6c5d9612abcb..f2d6b2518eee 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -109,20 +109,16 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
BUG();
}
- err = psp_init_sos_microcode(psp, chip_name);
- if (err)
- return err;
-
- if (adev->asic_type != CHIP_SIENNA_CICHLID &&
- adev->asic_type != CHIP_NAVY_FLOUNDER) {
- err = psp_init_asd_microcode(psp, chip_name);
- if (err)
- return err;
- }
switch (adev->asic_type) {
case CHIP_VEGA20:
case CHIP_ARCTURUS:
+ err = psp_init_sos_microcode(psp, chip_name);
+ if (err)
+ return err;
+ err = psp_init_asd_microcode(psp, chip_name);
+ if (err)
+ return err;
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
if (err) {
@@ -150,6 +146,12 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
case CHIP_NAVI10:
case CHIP_NAVI14:
case CHIP_NAVI12:
+ err = psp_init_sos_microcode(psp, chip_name);
+ if (err)
+ return err;
+ err = psp_init_asd_microcode(psp, chip_name);
+ if (err)
+ return err;
if (amdgpu_sriov_vf(adev))
break;
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
@@ -180,10 +182,21 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
break;
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ err = psp_init_sos_microcode(psp, chip_name);
+ if (err)
+ return err;
err = psp_init_ta_microcode(&adev->psp, chip_name);
if (err)
return err;
break;
+ case CHIP_VANGOGH:
+ err = psp_init_asd_microcode(psp, chip_name);
+ if (err)
+ return err;
+ err = psp_init_toc_microcode(psp, chip_name);
+ if (err)
+ return err;
+ break;
default:
BUG();
}
--
2.25.4
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 05/45] drm/amdgpu: add vangogh_reg_base_init function for van gogh
2020-09-29 18:59 ` Luben Tuikov
@ 2020-09-29 20:15 ` Alex Deucher
0 siblings, 0 replies; 9+ messages in thread
From: Alex Deucher @ 2020-09-29 20:15 UTC (permalink / raw)
To: Luben Tuikov; +Cc: Alex Deucher, Huang Rui, amd-gfx list
On Tue, Sep 29, 2020 at 2:59 PM Luben Tuikov <luben.tuikov@amd.com> wrote:
>
> On 2020-09-29 10:57 a.m., Alex Deucher wrote:
> >>> +#ifndef __VANGOGH_IP_OFFSET_H__
> >>> +#define __VANGOGH_IP_OFFSET_H__
> >>> +
> >>> +#define MAX_INSTANCE 8
> >>> +#define MAX_SEGMENT 6
> >> No. No "max". Use "num" instead, as:
> >>
> >> #define NUM_INSTANCE 8
> >> #define NUM_SEGMENT 6
> >>
> >> To mean, the _number_ of instances and the _number_ of
> >> segments. (Their count is a number.)
> >>
> >> A "maximum" (similarly "minimum") value is an _attainable_ value,
> >> i.e. something you can get, use, etc. But array indices are 0 to arraysize-1,
> >> and thus max instance can never be attained.
> >>
> >> It is the count, the number of instances (segments, wlg),
> >> not the maximum instance. The maximum instance is 7,
> >> the minimum instance is 0. Similarly for segments.
> > Valid point, but this file is shared across components so I'd like to
> > minimize the differences.
> >
>
> Is it possible to educate the organization?
>
> Is it possible for knowledge to flow backwards,
> i.e. from the Linux team back in?
>
> As a mathematician, this really, really bothers me.
>
> It leaves traces of badly named objects and new people reading
> it would pick this bad naming up, and experienced people would
> either be confused or find it incorrect.
>
> Let's fix this at the source.
We can take it up with the internal teams that generate these files.
Alex
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 05/45] drm/amdgpu: add vangogh_reg_base_init function for van gogh
2020-09-29 14:57 ` Alex Deucher
@ 2020-09-29 18:59 ` Luben Tuikov
2020-09-29 20:15 ` Alex Deucher
0 siblings, 1 reply; 9+ messages in thread
From: Luben Tuikov @ 2020-09-29 18:59 UTC (permalink / raw)
To: Alex Deucher; +Cc: Alex Deucher, Huang Rui, amd-gfx list
On 2020-09-29 10:57 a.m., Alex Deucher wrote:
>>> +#ifndef __VANGOGH_IP_OFFSET_H__
>>> +#define __VANGOGH_IP_OFFSET_H__
>>> +
>>> +#define MAX_INSTANCE 8
>>> +#define MAX_SEGMENT 6
>> No. No "max". Use "num" instead, as:
>>
>> #define NUM_INSTANCE 8
>> #define NUM_SEGMENT 6
>>
>> To mean, the _number_ of instances and the _number_ of
>> segments. (Their count is a number.)
>>
>> A "maximum" (similarly "minimum") value is an _attainable_ value,
>> i.e. something you can get, use, etc. But array indices are 0 to arraysize-1,
>> and thus max instance can never be attained.
>>
>> It is the count, the number of instances (segments, wlg),
>> not the maximum instance. The maximum instance is 7,
>> the minimum instance is 0. Similarly for segments.
> Valid point, but this file is shared across components so I'd like to
> minimize the differences.
>
Is it possible to educate the organization?
Is it possible for knowledge to flow backwards,
i.e. from the Linux team back in?
As a mathematician, this really, really bothers me.
It leaves traces of badly named objects and new people reading
it would pick this bad naming up, and experienced people would
either be confused or find it incorrect.
Let's fix this at the source.
Regards,
Luben
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 05/45] drm/amdgpu: add vangogh_reg_base_init function for van gogh
2020-09-28 20:48 ` Luben Tuikov
@ 2020-09-29 14:57 ` Alex Deucher
2020-09-29 18:59 ` Luben Tuikov
0 siblings, 1 reply; 9+ messages in thread
From: Alex Deucher @ 2020-09-29 14:57 UTC (permalink / raw)
To: Luben Tuikov; +Cc: Alex Deucher, Huang Rui, amd-gfx list
On Mon, Sep 28, 2020 at 4:49 PM Luben Tuikov <luben.tuikov@amd.com> wrote:
>
> On 2020-09-25 4:09 p.m., Alex Deucher wrote:
> > From: Huang Rui <ray.huang@amd.com>
> >
> > This patch adds vangogh_reg_base_init function to init the register base for
> > van gogh.
> >
> > Signed-off-by: Huang Rui <ray.huang@amd.com>
> > Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > ---
> > drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
> > drivers/gpu/drm/amd/amdgpu/nv.h | 1 +
> > drivers/gpu/drm/amd/amdgpu/vangogh_reg_init.c | 51 +
> > .../gpu/drm/amd/include/vangogh_ip_offset.h | 1516 +++++++++++++++++
> > 4 files changed, 1569 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/gpu/drm/amd/amdgpu/vangogh_reg_init.c
> > create mode 100644 drivers/gpu/drm/amd/include/vangogh_ip_offset.h
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
> > index 39976c7b100c..7866e4666a43 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/Makefile
> > +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
> > @@ -69,7 +69,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce
> > amdgpu-y += \
> > vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \
> > vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o navi10_reg_init.o navi14_reg_init.o \
> > - arct_reg_init.o navi12_reg_init.o mxgpu_nv.o sienna_cichlid_reg_init.o
> > + arct_reg_init.o navi12_reg_init.o mxgpu_nv.o sienna_cichlid_reg_init.o vangogh_reg_init.o
> >
> > # add DF block
> > amdgpu-y += \
> > diff --git a/drivers/gpu/drm/amd/amdgpu/nv.h b/drivers/gpu/drm/amd/amdgpu/nv.h
> > index aeef50a6a54b..8a3bf476b18f 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/nv.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/nv.h
> > @@ -34,4 +34,5 @@ int navi10_reg_base_init(struct amdgpu_device *adev);
> > int navi14_reg_base_init(struct amdgpu_device *adev);
> > int navi12_reg_base_init(struct amdgpu_device *adev);
> > int sienna_cichlid_reg_base_init(struct amdgpu_device *adev);
> > +int vangogh_reg_base_init(struct amdgpu_device *adev);
> > #endif
> > diff --git a/drivers/gpu/drm/amd/amdgpu/vangogh_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vangogh_reg_init.c
> > new file mode 100644
> > index 000000000000..4c6c3b415e7b
> > --- /dev/null
> > +++ b/drivers/gpu/drm/amd/amdgpu/vangogh_reg_init.c
> > @@ -0,0 +1,51 @@
> > +/*
> > + * Copyright 2019 Advanced Micro Devices, Inc.
> > + *
> > + * Permission is hereby granted, free of charge, to any person obtaining a
> > + * copy of this software and associated documentation files (the "Software"),
> > + * to deal in the Software without restriction, including without limitation
> > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice shall be included in
> > + * all copies or substantial portions of the Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> > + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> > + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> > + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > + * OTHER DEALINGS IN THE SOFTWARE.
> > + *
> > + */
> > +#include "amdgpu.h"
> > +#include "nv.h"
> > +
> > +#include "soc15_common.h"
> > +#include "soc15_hw_ip.h"
> > +#include "vangogh_ip_offset.h"
> > +
> > +int vangogh_reg_base_init(struct amdgpu_device *adev)
> > +{
> > + /* HW has more IP blocks, only initialized the blocke needed by driver */
> > + uint32_t i;
> > + for (i = 0 ; i < MAX_INSTANCE ; ++i) {
> > + adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
> > + adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
> > + adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
> > + adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
> > + adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
> > + adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
> > + adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
> > + adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i]));
> > + adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
> > + adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCN_BASE.instance[i]));
> > + adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));
> > + adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
> > + adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
> > + adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
>
> I'd align the equality sign for presentation.
>
Updated.
> > + }
> > + return 0;
> > +}
>
> This function should be "void", else the compiler will throw a warning
> when you compile nv.c.
>
Fixed.
> > diff --git a/drivers/gpu/drm/amd/include/vangogh_ip_offset.h b/drivers/gpu/drm/amd/include/vangogh_ip_offset.h
> > new file mode 100644
> > index 000000000000..2875574b060e
> > --- /dev/null
> > +++ b/drivers/gpu/drm/amd/include/vangogh_ip_offset.h
> > @@ -0,0 +1,1516 @@
> > +/*
> > + * Copyright 2019 Advanced Micro Devices, Inc.
> > + *
> > + * Permission is hereby granted, free of charge, to any person obtaining a
> > + * copy of this software and associated documentation files (the "Software"),
> > + * to deal in the Software without restriction, including without limitation
> > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice shall be included in
> > + * all copies or substantial portions of the Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> > + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> > + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> > + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > + * OTHER DEALINGS IN THE SOFTWARE.
> > + *
> > + */
> > +
> > +#ifndef __VANGOGH_IP_OFFSET_H__
> > +#define __VANGOGH_IP_OFFSET_H__
> > +
> > +#define MAX_INSTANCE 8
> > +#define MAX_SEGMENT 6
>
> No. No "max". Use "num" instead, as:
>
> #define NUM_INSTANCE 8
> #define NUM_SEGMENT 6
>
> To mean, the _number_ of instances and the _number_ of
> segments. (Their count is a number.)
>
> A "maximum" (similarly "minimum") value is an _attainable_ value,
> i.e. something you can get, use, etc. But array indices are 0 to arraysize-1,
> and thus max instance can never be attained.
>
> It is the count, the number of instances (segments, wlg),
> not the maximum instance. The maximum instance is 7,
> the minimum instance is 0. Similarly for segments.
Valid point, but this file is shared across components so I'd like to
minimize the differences.
Alex
>
> > +
> > +
> > +struct IP_BASE_INSTANCE
> > +{
> > + unsigned int segment[MAX_SEGMENT];
> > +};
>
> So, here if you used NUM_SEGMENT, it is very clear
> what is intended: an array of number of segments,
> i.e. their count, whose array index would be 0 to
> NUM_SEGMENTS-1.
>
> Similarly for "instance" below.
>
> Regards,
> Luben
>
> > +
> > +struct IP_BASE
> > +{
> > + struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
> > +};
> > +
> > +
> > +static const struct IP_BASE ACP_BASE = { { { { 0x02403800, 0x00480000, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } } } };
> > +static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C00, 0x00013300, 0x02408C00, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } } } };
> > +static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } },
> > + { { 0x00016E00, 0x02401C00, 0, 0, 0, 0 } },
> > + { { 0x00017000, 0x02402000, 0, 0, 0, 0 } },
> > + { { 0x00017200, 0x02402400, 0, 0, 0, 0 } },
> > + { { 0x0001B000, 0x0242D800, 0, 0, 0, 0 } },
> > + { { 0x0001B200, 0x0242DC00, 0, 0, 0, 0 } },
> > + { { 0x0001B400, 0x0242E000, 0, 0, 0, 0 } },
> > + { { 0x00017E00, 0x0240BC00, 0, 0, 0, 0 } } } };
> > +static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0x0240B800, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } } } };
> > +static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } } } };
> > +static const struct IP_BASE DPCS_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } } } };
> > +static const struct IP_BASE FCH_BASE = { { { { 0x0240C000, 0x00B40000, 0x11000000, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } } } };
> > +static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0x02401400, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } } } };
> > +static const struct IP_BASE GC_BASE = { { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } } } };
> > +static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0x0240A400, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } } } };
> > +static const struct IP_BASE ISP_BASE = { { { { 0x00018000, 0x0240B000, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } } } };
> > +static const struct IP_BASE MMHUB_BASE = { { { { 0x00013200, 0x0001A000, 0x02408800, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } } } };
> > +static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x0243FC00, 0x00DC0000, 0x00E00000, 0x00E40000, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } } } };
> > +static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0x0243FC00, 0x00DC0000, 0x00E00000, 0x00E40000, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } } } };
> > +static const struct IP_BASE MP2_BASE = { { { { 0x00016400, 0x02400800, 0x00F40000, 0x00F80000, 0x00FC0000, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } } } };
> > +static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } } } };
> > +static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0x0240A000, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } } } };
> > +static const struct IP_BASE PCIE0_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } } } };
> > +static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0x00016A00, 0x02401000, 0x00440000, 0, 0 } },
> > + { { 0x0001BC00, 0x0242D400, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } } } };
> > +static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0x02400C00, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } } } };
> > +static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0x02425800, 0, 0, 0, 0 } },
> > + { { 0x00054000, 0x02425C00, 0, 0, 0, 0 } },
> > + { { 0x00094000, 0x02426000, 0, 0, 0, 0 } },
> > + { { 0x000D4000, 0x02426400, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } } } };
> > +static const struct IP_BASE USB_BASE = { { { { 0x0242A800, 0x05B00000, 0, 0, 0, 0 } },
> > + { { 0x0242AC00, 0x05B80000, 0, 0, 0, 0 } },
> > + { { 0x0242B000, 0x05C00000, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } } } };
> > +static const struct IP_BASE VCN_BASE = { { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } },
> > + { { 0, 0, 0, 0, 0, 0 } } } };
> > +
> > +
> > +#define ACP_BASE__INST0_SEG0 0x02403800
> > +#define ACP_BASE__INST0_SEG1 0x00480000
> > +#define ACP_BASE__INST0_SEG2 0
> > +#define ACP_BASE__INST0_SEG3 0
> > +#define ACP_BASE__INST0_SEG4 0
> > +#define ACP_BASE__INST0_SEG5 0
> > +
> > +#define ACP_BASE__INST1_SEG0 0
> > +#define ACP_BASE__INST1_SEG1 0
> > +#define ACP_BASE__INST1_SEG2 0
> > +#define ACP_BASE__INST1_SEG3 0
> > +#define ACP_BASE__INST1_SEG4 0
> > +#define ACP_BASE__INST1_SEG5 0
> > +
> > +#define ACP_BASE__INST2_SEG0 0
> > +#define ACP_BASE__INST2_SEG1 0
> > +#define ACP_BASE__INST2_SEG2 0
> > +#define ACP_BASE__INST2_SEG3 0
> > +#define ACP_BASE__INST2_SEG4 0
> > +#define ACP_BASE__INST2_SEG5 0
> > +
> > +#define ACP_BASE__INST3_SEG0 0
> > +#define ACP_BASE__INST3_SEG1 0
> > +#define ACP_BASE__INST3_SEG2 0
> > +#define ACP_BASE__INST3_SEG3 0
> > +#define ACP_BASE__INST3_SEG4 0
> > +#define ACP_BASE__INST3_SEG5 0
> > +
> > +#define ACP_BASE__INST4_SEG0 0
> > +#define ACP_BASE__INST4_SEG1 0
> > +#define ACP_BASE__INST4_SEG2 0
> > +#define ACP_BASE__INST4_SEG3 0
> > +#define ACP_BASE__INST4_SEG4 0
> > +#define ACP_BASE__INST4_SEG5 0
> > +
> > +#define ACP_BASE__INST5_SEG0 0
> > +#define ACP_BASE__INST5_SEG1 0
> > +#define ACP_BASE__INST5_SEG2 0
> > +#define ACP_BASE__INST5_SEG3 0
> > +#define ACP_BASE__INST5_SEG4 0
> > +#define ACP_BASE__INST5_SEG5 0
> > +
> > +#define ACP_BASE__INST6_SEG0 0
> > +#define ACP_BASE__INST6_SEG1 0
> > +#define ACP_BASE__INST6_SEG2 0
> > +#define ACP_BASE__INST6_SEG3 0
> > +#define ACP_BASE__INST6_SEG4 0
> > +#define ACP_BASE__INST6_SEG5 0
> > +
> > +#define ACP_BASE__INST7_SEG0 0
> > +#define ACP_BASE__INST7_SEG1 0
> > +#define ACP_BASE__INST7_SEG2 0
> > +#define ACP_BASE__INST7_SEG3 0
> > +#define ACP_BASE__INST7_SEG4 0
> > +#define ACP_BASE__INST7_SEG5 0
> > +
> > +#define ATHUB_BASE__INST0_SEG0 0x00000C00
> > +#define ATHUB_BASE__INST0_SEG1 0x00013300
> > +#define ATHUB_BASE__INST0_SEG2 0x02408C00
> > +#define ATHUB_BASE__INST0_SEG3 0
> > +#define ATHUB_BASE__INST0_SEG4 0
> > +#define ATHUB_BASE__INST0_SEG5 0
> > +
> > +#define ATHUB_BASE__INST1_SEG0 0
> > +#define ATHUB_BASE__INST1_SEG1 0
> > +#define ATHUB_BASE__INST1_SEG2 0
> > +#define ATHUB_BASE__INST1_SEG3 0
> > +#define ATHUB_BASE__INST1_SEG4 0
> > +#define ATHUB_BASE__INST1_SEG5 0
> > +
> > +#define ATHUB_BASE__INST2_SEG0 0
> > +#define ATHUB_BASE__INST2_SEG1 0
> > +#define ATHUB_BASE__INST2_SEG2 0
> > +#define ATHUB_BASE__INST2_SEG3 0
> > +#define ATHUB_BASE__INST2_SEG4 0
> > +#define ATHUB_BASE__INST2_SEG5 0
> > +
> > +#define ATHUB_BASE__INST3_SEG0 0
> > +#define ATHUB_BASE__INST3_SEG1 0
> > +#define ATHUB_BASE__INST3_SEG2 0
> > +#define ATHUB_BASE__INST3_SEG3 0
> > +#define ATHUB_BASE__INST3_SEG4 0
> > +#define ATHUB_BASE__INST3_SEG5 0
> > +
> > +#define ATHUB_BASE__INST4_SEG0 0
> > +#define ATHUB_BASE__INST4_SEG1 0
> > +#define ATHUB_BASE__INST4_SEG2 0
> > +#define ATHUB_BASE__INST4_SEG3 0
> > +#define ATHUB_BASE__INST4_SEG4 0
> > +#define ATHUB_BASE__INST4_SEG5 0
> > +
> > +#define ATHUB_BASE__INST5_SEG0 0
> > +#define ATHUB_BASE__INST5_SEG1 0
> > +#define ATHUB_BASE__INST5_SEG2 0
> > +#define ATHUB_BASE__INST5_SEG3 0
> > +#define ATHUB_BASE__INST5_SEG4 0
> > +#define ATHUB_BASE__INST5_SEG5 0
> > +
> > +#define ATHUB_BASE__INST6_SEG0 0
> > +#define ATHUB_BASE__INST6_SEG1 0
> > +#define ATHUB_BASE__INST6_SEG2 0
> > +#define ATHUB_BASE__INST6_SEG3 0
> > +#define ATHUB_BASE__INST6_SEG4 0
> > +#define ATHUB_BASE__INST6_SEG5 0
> > +
> > +#define ATHUB_BASE__INST7_SEG0 0
> > +#define ATHUB_BASE__INST7_SEG1 0
> > +#define ATHUB_BASE__INST7_SEG2 0
> > +#define ATHUB_BASE__INST7_SEG3 0
> > +#define ATHUB_BASE__INST7_SEG4 0
> > +#define ATHUB_BASE__INST7_SEG5 0
> > +
> > +#define CLK_BASE__INST0_SEG0 0x00016C00
> > +#define CLK_BASE__INST0_SEG1 0x02401800
> > +#define CLK_BASE__INST0_SEG2 0
> > +#define CLK_BASE__INST0_SEG3 0
> > +#define CLK_BASE__INST0_SEG4 0
> > +#define CLK_BASE__INST0_SEG5 0
> > +
> > +#define CLK_BASE__INST1_SEG0 0x00016E00
> > +#define CLK_BASE__INST1_SEG1 0x02401C00
> > +#define CLK_BASE__INST1_SEG2 0
> > +#define CLK_BASE__INST1_SEG3 0
> > +#define CLK_BASE__INST1_SEG4 0
> > +#define CLK_BASE__INST1_SEG5 0
> > +
> > +#define CLK_BASE__INST2_SEG0 0x00017000
> > +#define CLK_BASE__INST2_SEG1 0x02402000
> > +#define CLK_BASE__INST2_SEG2 0
> > +#define CLK_BASE__INST2_SEG3 0
> > +#define CLK_BASE__INST2_SEG4 0
> > +#define CLK_BASE__INST2_SEG5 0
> > +
> > +#define CLK_BASE__INST3_SEG0 0x00017200
> > +#define CLK_BASE__INST3_SEG1 0x02402400
> > +#define CLK_BASE__INST3_SEG2 0
> > +#define CLK_BASE__INST3_SEG3 0
> > +#define CLK_BASE__INST3_SEG4 0
> > +#define CLK_BASE__INST3_SEG5 0
> > +
> > +#define CLK_BASE__INST4_SEG0 0x0001B000
> > +#define CLK_BASE__INST4_SEG1 0x0242D800
> > +#define CLK_BASE__INST4_SEG2 0
> > +#define CLK_BASE__INST4_SEG3 0
> > +#define CLK_BASE__INST4_SEG4 0
> > +#define CLK_BASE__INST4_SEG5 0
> > +
> > +#define CLK_BASE__INST5_SEG0 0x0001B200
> > +#define CLK_BASE__INST5_SEG1 0x0242DC00
> > +#define CLK_BASE__INST5_SEG2 0
> > +#define CLK_BASE__INST5_SEG3 0
> > +#define CLK_BASE__INST5_SEG4 0
> > +#define CLK_BASE__INST5_SEG5 0
> > +
> > +#define CLK_BASE__INST6_SEG0 0x0001B400
> > +#define CLK_BASE__INST6_SEG1 0x0242E000
> > +#define CLK_BASE__INST6_SEG2 0
> > +#define CLK_BASE__INST6_SEG3 0
> > +#define CLK_BASE__INST6_SEG4 0
> > +#define CLK_BASE__INST6_SEG5 0
> > +
> > +#define CLK_BASE__INST7_SEG0 0x00017E00
> > +#define CLK_BASE__INST7_SEG1 0x0240BC00
> > +#define CLK_BASE__INST7_SEG2 0
> > +#define CLK_BASE__INST7_SEG3 0
> > +#define CLK_BASE__INST7_SEG4 0
> > +#define CLK_BASE__INST7_SEG5 0
> > +
> > +#define DF_BASE__INST0_SEG0 0x00007000
> > +#define DF_BASE__INST0_SEG1 0x0240B800
> > +#define DF_BASE__INST0_SEG2 0
> > +#define DF_BASE__INST0_SEG3 0
> > +#define DF_BASE__INST0_SEG4 0
> > +#define DF_BASE__INST0_SEG5 0
> > +
> > +#define DF_BASE__INST1_SEG0 0
> > +#define DF_BASE__INST1_SEG1 0
> > +#define DF_BASE__INST1_SEG2 0
> > +#define DF_BASE__INST1_SEG3 0
> > +#define DF_BASE__INST1_SEG4 0
> > +#define DF_BASE__INST1_SEG5 0
> > +
> > +#define DF_BASE__INST2_SEG0 0
> > +#define DF_BASE__INST2_SEG1 0
> > +#define DF_BASE__INST2_SEG2 0
> > +#define DF_BASE__INST2_SEG3 0
> > +#define DF_BASE__INST2_SEG4 0
> > +#define DF_BASE__INST2_SEG5 0
> > +
> > +#define DF_BASE__INST3_SEG0 0
> > +#define DF_BASE__INST3_SEG1 0
> > +#define DF_BASE__INST3_SEG2 0
> > +#define DF_BASE__INST3_SEG3 0
> > +#define DF_BASE__INST3_SEG4 0
> > +#define DF_BASE__INST3_SEG5 0
> > +
> > +#define DF_BASE__INST4_SEG0 0
> > +#define DF_BASE__INST4_SEG1 0
> > +#define DF_BASE__INST4_SEG2 0
> > +#define DF_BASE__INST4_SEG3 0
> > +#define DF_BASE__INST4_SEG4 0
> > +#define DF_BASE__INST4_SEG5 0
> > +
> > +#define DF_BASE__INST5_SEG0 0
> > +#define DF_BASE__INST5_SEG1 0
> > +#define DF_BASE__INST5_SEG2 0
> > +#define DF_BASE__INST5_SEG3 0
> > +#define DF_BASE__INST5_SEG4 0
> > +#define DF_BASE__INST5_SEG5 0
> > +
> > +#define DF_BASE__INST6_SEG0 0
> > +#define DF_BASE__INST6_SEG1 0
> > +#define DF_BASE__INST6_SEG2 0
> > +#define DF_BASE__INST6_SEG3 0
> > +#define DF_BASE__INST6_SEG4 0
> > +#define DF_BASE__INST6_SEG5 0
> > +
> > +#define DF_BASE__INST7_SEG0 0
> > +#define DF_BASE__INST7_SEG1 0
> > +#define DF_BASE__INST7_SEG2 0
> > +#define DF_BASE__INST7_SEG3 0
> > +#define DF_BASE__INST7_SEG4 0
> > +#define DF_BASE__INST7_SEG5 0
> > +
> > +#define DCN_BASE__INST0_SEG0 0x00000012
> > +#define DCN_BASE__INST0_SEG1 0x000000C0
> > +#define DCN_BASE__INST0_SEG2 0x000034C0
> > +#define DCN_BASE__INST0_SEG3 0x00009000
> > +#define DCN_BASE__INST0_SEG4 0x02403C00
> > +#define DCN_BASE__INST0_SEG5 0
> > +
> > +#define DCN_BASE__INST1_SEG0 0
> > +#define DCN_BASE__INST1_SEG1 0
> > +#define DCN_BASE__INST1_SEG2 0
> > +#define DCN_BASE__INST1_SEG3 0
> > +#define DCN_BASE__INST1_SEG4 0
> > +#define DCN_BASE__INST1_SEG5 0
> > +
> > +#define DCN_BASE__INST2_SEG0 0
> > +#define DCN_BASE__INST2_SEG1 0
> > +#define DCN_BASE__INST2_SEG2 0
> > +#define DCN_BASE__INST2_SEG3 0
> > +#define DCN_BASE__INST2_SEG4 0
> > +#define DCN_BASE__INST2_SEG5 0
> > +
> > +#define DCN_BASE__INST3_SEG0 0
> > +#define DCN_BASE__INST3_SEG1 0
> > +#define DCN_BASE__INST3_SEG2 0
> > +#define DCN_BASE__INST3_SEG3 0
> > +#define DCN_BASE__INST3_SEG4 0
> > +#define DCN_BASE__INST3_SEG5 0
> > +
> > +#define DCN_BASE__INST4_SEG0 0
> > +#define DCN_BASE__INST4_SEG1 0
> > +#define DCN_BASE__INST4_SEG2 0
> > +#define DCN_BASE__INST4_SEG3 0
> > +#define DCN_BASE__INST4_SEG4 0
> > +#define DCN_BASE__INST4_SEG5 0
> > +
> > +#define DCN_BASE__INST5_SEG0 0
> > +#define DCN_BASE__INST5_SEG1 0
> > +#define DCN_BASE__INST5_SEG2 0
> > +#define DCN_BASE__INST5_SEG3 0
> > +#define DCN_BASE__INST5_SEG4 0
> > +#define DCN_BASE__INST5_SEG5 0
> > +
> > +#define DCN_BASE__INST6_SEG0 0
> > +#define DCN_BASE__INST6_SEG1 0
> > +#define DCN_BASE__INST6_SEG2 0
> > +#define DCN_BASE__INST6_SEG3 0
> > +#define DCN_BASE__INST6_SEG4 0
> > +#define DCN_BASE__INST6_SEG5 0
> > +
> > +#define DCN_BASE__INST7_SEG0 0
> > +#define DCN_BASE__INST7_SEG1 0
> > +#define DCN_BASE__INST7_SEG2 0
> > +#define DCN_BASE__INST7_SEG3 0
> > +#define DCN_BASE__INST7_SEG4 0
> > +#define DCN_BASE__INST7_SEG5 0
> > +
> > +#define DPCS_BASE__INST0_SEG0 0x00000012
> > +#define DPCS_BASE__INST0_SEG1 0x000000C0
> > +#define DPCS_BASE__INST0_SEG2 0x000034C0
> > +#define DPCS_BASE__INST0_SEG3 0x00009000
> > +#define DPCS_BASE__INST0_SEG4 0x02403C00
> > +#define DPCS_BASE__INST0_SEG5 0
> > +
> > +#define DPCS_BASE__INST1_SEG0 0
> > +#define DPCS_BASE__INST1_SEG1 0
> > +#define DPCS_BASE__INST1_SEG2 0
> > +#define DPCS_BASE__INST1_SEG3 0
> > +#define DPCS_BASE__INST1_SEG4 0
> > +#define DPCS_BASE__INST1_SEG5 0
> > +
> > +#define DPCS_BASE__INST2_SEG0 0
> > +#define DPCS_BASE__INST2_SEG1 0
> > +#define DPCS_BASE__INST2_SEG2 0
> > +#define DPCS_BASE__INST2_SEG3 0
> > +#define DPCS_BASE__INST2_SEG4 0
> > +#define DPCS_BASE__INST2_SEG5 0
> > +
> > +#define DPCS_BASE__INST3_SEG0 0
> > +#define DPCS_BASE__INST3_SEG1 0
> > +#define DPCS_BASE__INST3_SEG2 0
> > +#define DPCS_BASE__INST3_SEG3 0
> > +#define DPCS_BASE__INST3_SEG4 0
> > +#define DPCS_BASE__INST3_SEG5 0
> > +
> > +#define DPCS_BASE__INST4_SEG0 0
> > +#define DPCS_BASE__INST4_SEG1 0
> > +#define DPCS_BASE__INST4_SEG2 0
> > +#define DPCS_BASE__INST4_SEG3 0
> > +#define DPCS_BASE__INST4_SEG4 0
> > +#define DPCS_BASE__INST4_SEG5 0
> > +
> > +#define DPCS_BASE__INST5_SEG0 0
> > +#define DPCS_BASE__INST5_SEG1 0
> > +#define DPCS_BASE__INST5_SEG2 0
> > +#define DPCS_BASE__INST5_SEG3 0
> > +#define DPCS_BASE__INST5_SEG4 0
> > +#define DPCS_BASE__INST5_SEG5 0
> > +
> > +#define DPCS_BASE__INST6_SEG0 0
> > +#define DPCS_BASE__INST6_SEG1 0
> > +#define DPCS_BASE__INST6_SEG2 0
> > +#define DPCS_BASE__INST6_SEG3 0
> > +#define DPCS_BASE__INST6_SEG4 0
> > +#define DPCS_BASE__INST6_SEG5 0
> > +
> > +#define DPCS_BASE__INST7_SEG0 0
> > +#define DPCS_BASE__INST7_SEG1 0
> > +#define DPCS_BASE__INST7_SEG2 0
> > +#define DPCS_BASE__INST7_SEG3 0
> > +#define DPCS_BASE__INST7_SEG4 0
> > +#define DPCS_BASE__INST7_SEG5 0
> > +
> > +#define FCH_BASE__INST0_SEG0 0x0240C000
> > +#define FCH_BASE__INST0_SEG1 0x00B40000
> > +#define FCH_BASE__INST0_SEG2 0x11000000
> > +#define FCH_BASE__INST0_SEG3 0
> > +#define FCH_BASE__INST0_SEG4 0
> > +#define FCH_BASE__INST0_SEG5 0
> > +
> > +#define FCH_BASE__INST1_SEG0 0
> > +#define FCH_BASE__INST1_SEG1 0
> > +#define FCH_BASE__INST1_SEG2 0
> > +#define FCH_BASE__INST1_SEG3 0
> > +#define FCH_BASE__INST1_SEG4 0
> > +#define FCH_BASE__INST1_SEG5 0
> > +
> > +#define FCH_BASE__INST2_SEG0 0
> > +#define FCH_BASE__INST2_SEG1 0
> > +#define FCH_BASE__INST2_SEG2 0
> > +#define FCH_BASE__INST2_SEG3 0
> > +#define FCH_BASE__INST2_SEG4 0
> > +#define FCH_BASE__INST2_SEG5 0
> > +
> > +#define FCH_BASE__INST3_SEG0 0
> > +#define FCH_BASE__INST3_SEG1 0
> > +#define FCH_BASE__INST3_SEG2 0
> > +#define FCH_BASE__INST3_SEG3 0
> > +#define FCH_BASE__INST3_SEG4 0
> > +#define FCH_BASE__INST3_SEG5 0
> > +
> > +#define FCH_BASE__INST4_SEG0 0
> > +#define FCH_BASE__INST4_SEG1 0
> > +#define FCH_BASE__INST4_SEG2 0
> > +#define FCH_BASE__INST4_SEG3 0
> > +#define FCH_BASE__INST4_SEG4 0
> > +#define FCH_BASE__INST4_SEG5 0
> > +
> > +#define FCH_BASE__INST5_SEG0 0
> > +#define FCH_BASE__INST5_SEG1 0
> > +#define FCH_BASE__INST5_SEG2 0
> > +#define FCH_BASE__INST5_SEG3 0
> > +#define FCH_BASE__INST5_SEG4 0
> > +#define FCH_BASE__INST5_SEG5 0
> > +
> > +#define FCH_BASE__INST6_SEG0 0
> > +#define FCH_BASE__INST6_SEG1 0
> > +#define FCH_BASE__INST6_SEG2 0
> > +#define FCH_BASE__INST6_SEG3 0
> > +#define FCH_BASE__INST6_SEG4 0
> > +#define FCH_BASE__INST6_SEG5 0
> > +
> > +#define FCH_BASE__INST7_SEG0 0
> > +#define FCH_BASE__INST7_SEG1 0
> > +#define FCH_BASE__INST7_SEG2 0
> > +#define FCH_BASE__INST7_SEG3 0
> > +#define FCH_BASE__INST7_SEG4 0
> > +#define FCH_BASE__INST7_SEG5 0
> > +
> > +#define FUSE_BASE__INST0_SEG0 0x00017400
> > +#define FUSE_BASE__INST0_SEG1 0x02401400
> > +#define FUSE_BASE__INST0_SEG2 0
> > +#define FUSE_BASE__INST0_SEG3 0
> > +#define FUSE_BASE__INST0_SEG4 0
> > +#define FUSE_BASE__INST0_SEG5 0
> > +
> > +#define FUSE_BASE__INST1_SEG0 0
> > +#define FUSE_BASE__INST1_SEG1 0
> > +#define FUSE_BASE__INST1_SEG2 0
> > +#define FUSE_BASE__INST1_SEG3 0
> > +#define FUSE_BASE__INST1_SEG4 0
> > +#define FUSE_BASE__INST1_SEG5 0
> > +
> > +#define FUSE_BASE__INST2_SEG0 0
> > +#define FUSE_BASE__INST2_SEG1 0
> > +#define FUSE_BASE__INST2_SEG2 0
> > +#define FUSE_BASE__INST2_SEG3 0
> > +#define FUSE_BASE__INST2_SEG4 0
> > +#define FUSE_BASE__INST2_SEG5 0
> > +
> > +#define FUSE_BASE__INST3_SEG0 0
> > +#define FUSE_BASE__INST3_SEG1 0
> > +#define FUSE_BASE__INST3_SEG2 0
> > +#define FUSE_BASE__INST3_SEG3 0
> > +#define FUSE_BASE__INST3_SEG4 0
> > +#define FUSE_BASE__INST3_SEG5 0
> > +
> > +#define FUSE_BASE__INST4_SEG0 0
> > +#define FUSE_BASE__INST4_SEG1 0
> > +#define FUSE_BASE__INST4_SEG2 0
> > +#define FUSE_BASE__INST4_SEG3 0
> > +#define FUSE_BASE__INST4_SEG4 0
> > +#define FUSE_BASE__INST4_SEG5 0
> > +
> > +#define FUSE_BASE__INST5_SEG0 0
> > +#define FUSE_BASE__INST5_SEG1 0
> > +#define FUSE_BASE__INST5_SEG2 0
> > +#define FUSE_BASE__INST5_SEG3 0
> > +#define FUSE_BASE__INST5_SEG4 0
> > +#define FUSE_BASE__INST5_SEG5 0
> > +
> > +#define FUSE_BASE__INST6_SEG0 0
> > +#define FUSE_BASE__INST6_SEG1 0
> > +#define FUSE_BASE__INST6_SEG2 0
> > +#define FUSE_BASE__INST6_SEG3 0
> > +#define FUSE_BASE__INST6_SEG4 0
> > +#define FUSE_BASE__INST6_SEG5 0
> > +
> > +#define FUSE_BASE__INST7_SEG0 0
> > +#define FUSE_BASE__INST7_SEG1 0
> > +#define FUSE_BASE__INST7_SEG2 0
> > +#define FUSE_BASE__INST7_SEG3 0
> > +#define FUSE_BASE__INST7_SEG4 0
> > +#define FUSE_BASE__INST7_SEG5 0
> > +
> > +#define GC_BASE__INST0_SEG0 0x00001260
> > +#define GC_BASE__INST0_SEG1 0x0000A000
> > +#define GC_BASE__INST0_SEG2 0x02402C00
> > +#define GC_BASE__INST0_SEG3 0
> > +#define GC_BASE__INST0_SEG4 0
> > +#define GC_BASE__INST0_SEG5 0
> > +
> > +#define GC_BASE__INST1_SEG0 0
> > +#define GC_BASE__INST1_SEG1 0
> > +#define GC_BASE__INST1_SEG2 0
> > +#define GC_BASE__INST1_SEG3 0
> > +#define GC_BASE__INST1_SEG4 0
> > +#define GC_BASE__INST1_SEG5 0
> > +
> > +#define GC_BASE__INST2_SEG0 0
> > +#define GC_BASE__INST2_SEG1 0
> > +#define GC_BASE__INST2_SEG2 0
> > +#define GC_BASE__INST2_SEG3 0
> > +#define GC_BASE__INST2_SEG4 0
> > +#define GC_BASE__INST2_SEG5 0
> > +
> > +#define GC_BASE__INST3_SEG0 0
> > +#define GC_BASE__INST3_SEG1 0
> > +#define GC_BASE__INST3_SEG2 0
> > +#define GC_BASE__INST3_SEG3 0
> > +#define GC_BASE__INST3_SEG4 0
> > +#define GC_BASE__INST3_SEG5 0
> > +
> > +#define GC_BASE__INST4_SEG0 0
> > +#define GC_BASE__INST4_SEG1 0
> > +#define GC_BASE__INST4_SEG2 0
> > +#define GC_BASE__INST4_SEG3 0
> > +#define GC_BASE__INST4_SEG4 0
> > +#define GC_BASE__INST4_SEG5 0
> > +
> > +#define GC_BASE__INST5_SEG0 0
> > +#define GC_BASE__INST5_SEG1 0
> > +#define GC_BASE__INST5_SEG2 0
> > +#define GC_BASE__INST5_SEG3 0
> > +#define GC_BASE__INST5_SEG4 0
> > +#define GC_BASE__INST5_SEG5 0
> > +
> > +#define GC_BASE__INST6_SEG0 0
> > +#define GC_BASE__INST6_SEG1 0
> > +#define GC_BASE__INST6_SEG2 0
> > +#define GC_BASE__INST6_SEG3 0
> > +#define GC_BASE__INST6_SEG4 0
> > +#define GC_BASE__INST6_SEG5 0
> > +
> > +#define GC_BASE__INST7_SEG0 0
> > +#define GC_BASE__INST7_SEG1 0
> > +#define GC_BASE__INST7_SEG2 0
> > +#define GC_BASE__INST7_SEG3 0
> > +#define GC_BASE__INST7_SEG4 0
> > +#define GC_BASE__INST7_SEG5 0
> > +
> > +#define HDP_BASE__INST0_SEG0 0x00000F20
> > +#define HDP_BASE__INST0_SEG1 0x0240A400
> > +#define HDP_BASE__INST0_SEG2 0
> > +#define HDP_BASE__INST0_SEG3 0
> > +#define HDP_BASE__INST0_SEG4 0
> > +#define HDP_BASE__INST0_SEG5 0
> > +
> > +#define HDP_BASE__INST1_SEG0 0
> > +#define HDP_BASE__INST1_SEG1 0
> > +#define HDP_BASE__INST1_SEG2 0
> > +#define HDP_BASE__INST1_SEG3 0
> > +#define HDP_BASE__INST1_SEG4 0
> > +#define HDP_BASE__INST1_SEG5 0
> > +
> > +#define HDP_BASE__INST2_SEG0 0
> > +#define HDP_BASE__INST2_SEG1 0
> > +#define HDP_BASE__INST2_SEG2 0
> > +#define HDP_BASE__INST2_SEG3 0
> > +#define HDP_BASE__INST2_SEG4 0
> > +#define HDP_BASE__INST2_SEG5 0
> > +
> > +#define HDP_BASE__INST3_SEG0 0
> > +#define HDP_BASE__INST3_SEG1 0
> > +#define HDP_BASE__INST3_SEG2 0
> > +#define HDP_BASE__INST3_SEG3 0
> > +#define HDP_BASE__INST3_SEG4 0
> > +#define HDP_BASE__INST3_SEG5 0
> > +
> > +#define HDP_BASE__INST4_SEG0 0
> > +#define HDP_BASE__INST4_SEG1 0
> > +#define HDP_BASE__INST4_SEG2 0
> > +#define HDP_BASE__INST4_SEG3 0
> > +#define HDP_BASE__INST4_SEG4 0
> > +#define HDP_BASE__INST4_SEG5 0
> > +
> > +#define HDP_BASE__INST5_SEG0 0
> > +#define HDP_BASE__INST5_SEG1 0
> > +#define HDP_BASE__INST5_SEG2 0
> > +#define HDP_BASE__INST5_SEG3 0
> > +#define HDP_BASE__INST5_SEG4 0
> > +#define HDP_BASE__INST5_SEG5 0
> > +
> > +#define HDP_BASE__INST6_SEG0 0
> > +#define HDP_BASE__INST6_SEG1 0
> > +#define HDP_BASE__INST6_SEG2 0
> > +#define HDP_BASE__INST6_SEG3 0
> > +#define HDP_BASE__INST6_SEG4 0
> > +#define HDP_BASE__INST6_SEG5 0
> > +
> > +#define HDP_BASE__INST7_SEG0 0
> > +#define HDP_BASE__INST7_SEG1 0
> > +#define HDP_BASE__INST7_SEG2 0
> > +#define HDP_BASE__INST7_SEG3 0
> > +#define HDP_BASE__INST7_SEG4 0
> > +#define HDP_BASE__INST7_SEG5 0
> > +
> > +#define ISP_BASE__INST0_SEG0 0x00018000
> > +#define ISP_BASE__INST0_SEG1 0x0240B000
> > +#define ISP_BASE__INST0_SEG2 0
> > +#define ISP_BASE__INST0_SEG3 0
> > +#define ISP_BASE__INST0_SEG4 0
> > +#define ISP_BASE__INST0_SEG5 0
> > +
> > +#define ISP_BASE__INST1_SEG0 0
> > +#define ISP_BASE__INST1_SEG1 0
> > +#define ISP_BASE__INST1_SEG2 0
> > +#define ISP_BASE__INST1_SEG3 0
> > +#define ISP_BASE__INST1_SEG4 0
> > +#define ISP_BASE__INST1_SEG5 0
> > +
> > +#define ISP_BASE__INST2_SEG0 0
> > +#define ISP_BASE__INST2_SEG1 0
> > +#define ISP_BASE__INST2_SEG2 0
> > +#define ISP_BASE__INST2_SEG3 0
> > +#define ISP_BASE__INST2_SEG4 0
> > +#define ISP_BASE__INST2_SEG5 0
> > +
> > +#define ISP_BASE__INST3_SEG0 0
> > +#define ISP_BASE__INST3_SEG1 0
> > +#define ISP_BASE__INST3_SEG2 0
> > +#define ISP_BASE__INST3_SEG3 0
> > +#define ISP_BASE__INST3_SEG4 0
> > +#define ISP_BASE__INST3_SEG5 0
> > +
> > +#define ISP_BASE__INST4_SEG0 0
> > +#define ISP_BASE__INST4_SEG1 0
> > +#define ISP_BASE__INST4_SEG2 0
> > +#define ISP_BASE__INST4_SEG3 0
> > +#define ISP_BASE__INST4_SEG4 0
> > +#define ISP_BASE__INST4_SEG5 0
> > +
> > +#define ISP_BASE__INST5_SEG0 0
> > +#define ISP_BASE__INST5_SEG1 0
> > +#define ISP_BASE__INST5_SEG2 0
> > +#define ISP_BASE__INST5_SEG3 0
> > +#define ISP_BASE__INST5_SEG4 0
> > +#define ISP_BASE__INST5_SEG5 0
> > +
> > +#define ISP_BASE__INST6_SEG0 0
> > +#define ISP_BASE__INST6_SEG1 0
> > +#define ISP_BASE__INST6_SEG2 0
> > +#define ISP_BASE__INST6_SEG3 0
> > +#define ISP_BASE__INST6_SEG4 0
> > +#define ISP_BASE__INST6_SEG5 0
> > +
> > +#define ISP_BASE__INST7_SEG0 0
> > +#define ISP_BASE__INST7_SEG1 0
> > +#define ISP_BASE__INST7_SEG2 0
> > +#define ISP_BASE__INST7_SEG3 0
> > +#define ISP_BASE__INST7_SEG4 0
> > +#define ISP_BASE__INST7_SEG5 0
> > +
> > +#define MMHUB_BASE__INST0_SEG0 0x00013200
> > +#define MMHUB_BASE__INST0_SEG1 0x0001A000
> > +#define MMHUB_BASE__INST0_SEG2 0x02408800
> > +#define MMHUB_BASE__INST0_SEG3 0
> > +#define MMHUB_BASE__INST0_SEG4 0
> > +#define MMHUB_BASE__INST0_SEG5 0
> > +
> > +#define MMHUB_BASE__INST1_SEG0 0
> > +#define MMHUB_BASE__INST1_SEG1 0
> > +#define MMHUB_BASE__INST1_SEG2 0
> > +#define MMHUB_BASE__INST1_SEG3 0
> > +#define MMHUB_BASE__INST1_SEG4 0
> > +#define MMHUB_BASE__INST1_SEG5 0
> > +
> > +#define MMHUB_BASE__INST2_SEG0 0
> > +#define MMHUB_BASE__INST2_SEG1 0
> > +#define MMHUB_BASE__INST2_SEG2 0
> > +#define MMHUB_BASE__INST2_SEG3 0
> > +#define MMHUB_BASE__INST2_SEG4 0
> > +#define MMHUB_BASE__INST2_SEG5 0
> > +
> > +#define MMHUB_BASE__INST3_SEG0 0
> > +#define MMHUB_BASE__INST3_SEG1 0
> > +#define MMHUB_BASE__INST3_SEG2 0
> > +#define MMHUB_BASE__INST3_SEG3 0
> > +#define MMHUB_BASE__INST3_SEG4 0
> > +#define MMHUB_BASE__INST3_SEG5 0
> > +
> > +#define MMHUB_BASE__INST4_SEG0 0
> > +#define MMHUB_BASE__INST4_SEG1 0
> > +#define MMHUB_BASE__INST4_SEG2 0
> > +#define MMHUB_BASE__INST4_SEG3 0
> > +#define MMHUB_BASE__INST4_SEG4 0
> > +#define MMHUB_BASE__INST4_SEG5 0
> > +
> > +#define MMHUB_BASE__INST5_SEG0 0
> > +#define MMHUB_BASE__INST5_SEG1 0
> > +#define MMHUB_BASE__INST5_SEG2 0
> > +#define MMHUB_BASE__INST5_SEG3 0
> > +#define MMHUB_BASE__INST5_SEG4 0
> > +#define MMHUB_BASE__INST5_SEG5 0
> > +
> > +#define MMHUB_BASE__INST6_SEG0 0
> > +#define MMHUB_BASE__INST6_SEG1 0
> > +#define MMHUB_BASE__INST6_SEG2 0
> > +#define MMHUB_BASE__INST6_SEG3 0
> > +#define MMHUB_BASE__INST6_SEG4 0
> > +#define MMHUB_BASE__INST6_SEG5 0
> > +
> > +#define MMHUB_BASE__INST7_SEG0 0
> > +#define MMHUB_BASE__INST7_SEG1 0
> > +#define MMHUB_BASE__INST7_SEG2 0
> > +#define MMHUB_BASE__INST7_SEG3 0
> > +#define MMHUB_BASE__INST7_SEG4 0
> > +#define MMHUB_BASE__INST7_SEG5 0
> > +
> > +#define MP0_BASE__INST0_SEG0 0x00016000
> > +#define MP0_BASE__INST0_SEG1 0x0243FC00
> > +#define MP0_BASE__INST0_SEG2 0x00DC0000
> > +#define MP0_BASE__INST0_SEG3 0x00E00000
> > +#define MP0_BASE__INST0_SEG4 0x00E40000
> > +#define MP0_BASE__INST0_SEG5 0
> > +
> > +#define MP0_BASE__INST1_SEG0 0
> > +#define MP0_BASE__INST1_SEG1 0
> > +#define MP0_BASE__INST1_SEG2 0
> > +#define MP0_BASE__INST1_SEG3 0
> > +#define MP0_BASE__INST1_SEG4 0
> > +#define MP0_BASE__INST1_SEG5 0
> > +
> > +#define MP0_BASE__INST2_SEG0 0
> > +#define MP0_BASE__INST2_SEG1 0
> > +#define MP0_BASE__INST2_SEG2 0
> > +#define MP0_BASE__INST2_SEG3 0
> > +#define MP0_BASE__INST2_SEG4 0
> > +#define MP0_BASE__INST2_SEG5 0
> > +
> > +#define MP0_BASE__INST3_SEG0 0
> > +#define MP0_BASE__INST3_SEG1 0
> > +#define MP0_BASE__INST3_SEG2 0
> > +#define MP0_BASE__INST3_SEG3 0
> > +#define MP0_BASE__INST3_SEG4 0
> > +#define MP0_BASE__INST3_SEG5 0
> > +
> > +#define MP0_BASE__INST4_SEG0 0
> > +#define MP0_BASE__INST4_SEG1 0
> > +#define MP0_BASE__INST4_SEG2 0
> > +#define MP0_BASE__INST4_SEG3 0
> > +#define MP0_BASE__INST4_SEG4 0
> > +#define MP0_BASE__INST4_SEG5 0
> > +
> > +#define MP0_BASE__INST5_SEG0 0
> > +#define MP0_BASE__INST5_SEG1 0
> > +#define MP0_BASE__INST5_SEG2 0
> > +#define MP0_BASE__INST5_SEG3 0
> > +#define MP0_BASE__INST5_SEG4 0
> > +#define MP0_BASE__INST5_SEG5 0
> > +
> > +#define MP0_BASE__INST6_SEG0 0
> > +#define MP0_BASE__INST6_SEG1 0
> > +#define MP0_BASE__INST6_SEG2 0
> > +#define MP0_BASE__INST6_SEG3 0
> > +#define MP0_BASE__INST6_SEG4 0
> > +#define MP0_BASE__INST6_SEG5 0
> > +
> > +#define MP0_BASE__INST7_SEG0 0
> > +#define MP0_BASE__INST7_SEG1 0
> > +#define MP0_BASE__INST7_SEG2 0
> > +#define MP0_BASE__INST7_SEG3 0
> > +#define MP0_BASE__INST7_SEG4 0
> > +#define MP0_BASE__INST7_SEG5 0
> > +
> > +#define MP1_BASE__INST0_SEG0 0x00016000
> > +#define MP1_BASE__INST0_SEG1 0x0243FC00
> > +#define MP1_BASE__INST0_SEG2 0x00DC0000
> > +#define MP1_BASE__INST0_SEG3 0x00E00000
> > +#define MP1_BASE__INST0_SEG4 0x00E40000
> > +#define MP1_BASE__INST0_SEG5 0
> > +
> > +#define MP1_BASE__INST1_SEG0 0
> > +#define MP1_BASE__INST1_SEG1 0
> > +#define MP1_BASE__INST1_SEG2 0
> > +#define MP1_BASE__INST1_SEG3 0
> > +#define MP1_BASE__INST1_SEG4 0
> > +#define MP1_BASE__INST1_SEG5 0
> > +
> > +#define MP1_BASE__INST2_SEG0 0
> > +#define MP1_BASE__INST2_SEG1 0
> > +#define MP1_BASE__INST2_SEG2 0
> > +#define MP1_BASE__INST2_SEG3 0
> > +#define MP1_BASE__INST2_SEG4 0
> > +#define MP1_BASE__INST2_SEG5 0
> > +
> > +#define MP1_BASE__INST3_SEG0 0
> > +#define MP1_BASE__INST3_SEG1 0
> > +#define MP1_BASE__INST3_SEG2 0
> > +#define MP1_BASE__INST3_SEG3 0
> > +#define MP1_BASE__INST3_SEG4 0
> > +#define MP1_BASE__INST3_SEG5 0
> > +
> > +#define MP1_BASE__INST4_SEG0 0
> > +#define MP1_BASE__INST4_SEG1 0
> > +#define MP1_BASE__INST4_SEG2 0
> > +#define MP1_BASE__INST4_SEG3 0
> > +#define MP1_BASE__INST4_SEG4 0
> > +#define MP1_BASE__INST4_SEG5 0
> > +
> > +#define MP1_BASE__INST5_SEG0 0
> > +#define MP1_BASE__INST5_SEG1 0
> > +#define MP1_BASE__INST5_SEG2 0
> > +#define MP1_BASE__INST5_SEG3 0
> > +#define MP1_BASE__INST5_SEG4 0
> > +#define MP1_BASE__INST5_SEG5 0
> > +
> > +#define MP1_BASE__INST6_SEG0 0
> > +#define MP1_BASE__INST6_SEG1 0
> > +#define MP1_BASE__INST6_SEG2 0
> > +#define MP1_BASE__INST6_SEG3 0
> > +#define MP1_BASE__INST6_SEG4 0
> > +#define MP1_BASE__INST6_SEG5 0
> > +
> > +#define MP1_BASE__INST7_SEG0 0
> > +#define MP1_BASE__INST7_SEG1 0
> > +#define MP1_BASE__INST7_SEG2 0
> > +#define MP1_BASE__INST7_SEG3 0
> > +#define MP1_BASE__INST7_SEG4 0
> > +#define MP1_BASE__INST7_SEG5 0
> > +
> > +#define MP2_BASE__INST0_SEG0 0x00016400
> > +#define MP2_BASE__INST0_SEG1 0x02400800
> > +#define MP2_BASE__INST0_SEG2 0x00F40000
> > +#define MP2_BASE__INST0_SEG3 0x00F80000
> > +#define MP2_BASE__INST0_SEG4 0x00FC0000
> > +#define MP2_BASE__INST0_SEG5 0
> > +
> > +#define MP2_BASE__INST1_SEG0 0
> > +#define MP2_BASE__INST1_SEG1 0
> > +#define MP2_BASE__INST1_SEG2 0
> > +#define MP2_BASE__INST1_SEG3 0
> > +#define MP2_BASE__INST1_SEG4 0
> > +#define MP2_BASE__INST1_SEG5 0
> > +
> > +#define MP2_BASE__INST2_SEG0 0
> > +#define MP2_BASE__INST2_SEG1 0
> > +#define MP2_BASE__INST2_SEG2 0
> > +#define MP2_BASE__INST2_SEG3 0
> > +#define MP2_BASE__INST2_SEG4 0
> > +#define MP2_BASE__INST2_SEG5 0
> > +
> > +#define MP2_BASE__INST3_SEG0 0
> > +#define MP2_BASE__INST3_SEG1 0
> > +#define MP2_BASE__INST3_SEG2 0
> > +#define MP2_BASE__INST3_SEG3 0
> > +#define MP2_BASE__INST3_SEG4 0
> > +#define MP2_BASE__INST3_SEG5 0
> > +
> > +#define MP2_BASE__INST4_SEG0 0
> > +#define MP2_BASE__INST4_SEG1 0
> > +#define MP2_BASE__INST4_SEG2 0
> > +#define MP2_BASE__INST4_SEG3 0
> > +#define MP2_BASE__INST4_SEG4 0
> > +#define MP2_BASE__INST4_SEG5 0
> > +
> > +#define MP2_BASE__INST5_SEG0 0
> > +#define MP2_BASE__INST5_SEG1 0
> > +#define MP2_BASE__INST5_SEG2 0
> > +#define MP2_BASE__INST5_SEG3 0
> > +#define MP2_BASE__INST5_SEG4 0
> > +#define MP2_BASE__INST5_SEG5 0
> > +
> > +#define MP2_BASE__INST6_SEG0 0
> > +#define MP2_BASE__INST6_SEG1 0
> > +#define MP2_BASE__INST6_SEG2 0
> > +#define MP2_BASE__INST6_SEG3 0
> > +#define MP2_BASE__INST6_SEG4 0
> > +#define MP2_BASE__INST6_SEG5 0
> > +
> > +#define MP2_BASE__INST7_SEG0 0
> > +#define MP2_BASE__INST7_SEG1 0
> > +#define MP2_BASE__INST7_SEG2 0
> > +#define MP2_BASE__INST7_SEG3 0
> > +#define MP2_BASE__INST7_SEG4 0
> > +#define MP2_BASE__INST7_SEG5 0
> > +
> > +#define NBIO_BASE__INST0_SEG0 0x00000000
> > +#define NBIO_BASE__INST0_SEG1 0x00000014
> > +#define NBIO_BASE__INST0_SEG2 0x00000D20
> > +#define NBIO_BASE__INST0_SEG3 0x00010400
> > +#define NBIO_BASE__INST0_SEG4 0x0241B000
> > +#define NBIO_BASE__INST0_SEG5 0x04040000
> > +
> > +#define NBIO_BASE__INST1_SEG0 0
> > +#define NBIO_BASE__INST1_SEG1 0
> > +#define NBIO_BASE__INST1_SEG2 0
> > +#define NBIO_BASE__INST1_SEG3 0
> > +#define NBIO_BASE__INST1_SEG4 0
> > +#define NBIO_BASE__INST1_SEG5 0
> > +
> > +#define NBIO_BASE__INST2_SEG0 0
> > +#define NBIO_BASE__INST2_SEG1 0
> > +#define NBIO_BASE__INST2_SEG2 0
> > +#define NBIO_BASE__INST2_SEG3 0
> > +#define NBIO_BASE__INST2_SEG4 0
> > +#define NBIO_BASE__INST2_SEG5 0
> > +
> > +#define NBIO_BASE__INST3_SEG0 0
> > +#define NBIO_BASE__INST3_SEG1 0
> > +#define NBIO_BASE__INST3_SEG2 0
> > +#define NBIO_BASE__INST3_SEG3 0
> > +#define NBIO_BASE__INST3_SEG4 0
> > +#define NBIO_BASE__INST3_SEG5 0
> > +
> > +#define NBIO_BASE__INST4_SEG0 0
> > +#define NBIO_BASE__INST4_SEG1 0
> > +#define NBIO_BASE__INST4_SEG2 0
> > +#define NBIO_BASE__INST4_SEG3 0
> > +#define NBIO_BASE__INST4_SEG4 0
> > +#define NBIO_BASE__INST4_SEG5 0
> > +
> > +#define NBIO_BASE__INST5_SEG0 0
> > +#define NBIO_BASE__INST5_SEG1 0
> > +#define NBIO_BASE__INST5_SEG2 0
> > +#define NBIO_BASE__INST5_SEG3 0
> > +#define NBIO_BASE__INST5_SEG4 0
> > +#define NBIO_BASE__INST5_SEG5 0
> > +
> > +#define NBIO_BASE__INST6_SEG0 0
> > +#define NBIO_BASE__INST6_SEG1 0
> > +#define NBIO_BASE__INST6_SEG2 0
> > +#define NBIO_BASE__INST6_SEG3 0
> > +#define NBIO_BASE__INST6_SEG4 0
> > +#define NBIO_BASE__INST6_SEG5 0
> > +
> > +#define NBIO_BASE__INST7_SEG0 0
> > +#define NBIO_BASE__INST7_SEG1 0
> > +#define NBIO_BASE__INST7_SEG2 0
> > +#define NBIO_BASE__INST7_SEG3 0
> > +#define NBIO_BASE__INST7_SEG4 0
> > +#define NBIO_BASE__INST7_SEG5 0
> > +
> > +#define OSSSYS_BASE__INST0_SEG0 0x000010A0
> > +#define OSSSYS_BASE__INST0_SEG1 0x0240A000
> > +#define OSSSYS_BASE__INST0_SEG2 0
> > +#define OSSSYS_BASE__INST0_SEG3 0
> > +#define OSSSYS_BASE__INST0_SEG4 0
> > +#define OSSSYS_BASE__INST0_SEG5 0
> > +
> > +#define OSSSYS_BASE__INST1_SEG0 0
> > +#define OSSSYS_BASE__INST1_SEG1 0
> > +#define OSSSYS_BASE__INST1_SEG2 0
> > +#define OSSSYS_BASE__INST1_SEG3 0
> > +#define OSSSYS_BASE__INST1_SEG4 0
> > +#define OSSSYS_BASE__INST1_SEG5 0
> > +
> > +#define OSSSYS_BASE__INST2_SEG0 0
> > +#define OSSSYS_BASE__INST2_SEG1 0
> > +#define OSSSYS_BASE__INST2_SEG2 0
> > +#define OSSSYS_BASE__INST2_SEG3 0
> > +#define OSSSYS_BASE__INST2_SEG4 0
> > +#define OSSSYS_BASE__INST2_SEG5 0
> > +
> > +#define OSSSYS_BASE__INST3_SEG0 0
> > +#define OSSSYS_BASE__INST3_SEG1 0
> > +#define OSSSYS_BASE__INST3_SEG2 0
> > +#define OSSSYS_BASE__INST3_SEG3 0
> > +#define OSSSYS_BASE__INST3_SEG4 0
> > +#define OSSSYS_BASE__INST3_SEG5 0
> > +
> > +#define OSSSYS_BASE__INST4_SEG0 0
> > +#define OSSSYS_BASE__INST4_SEG1 0
> > +#define OSSSYS_BASE__INST4_SEG2 0
> > +#define OSSSYS_BASE__INST4_SEG3 0
> > +#define OSSSYS_BASE__INST4_SEG4 0
> > +#define OSSSYS_BASE__INST4_SEG5 0
> > +
> > +#define OSSSYS_BASE__INST5_SEG0 0
> > +#define OSSSYS_BASE__INST5_SEG1 0
> > +#define OSSSYS_BASE__INST5_SEG2 0
> > +#define OSSSYS_BASE__INST5_SEG3 0
> > +#define OSSSYS_BASE__INST5_SEG4 0
> > +#define OSSSYS_BASE__INST5_SEG5 0
> > +
> > +#define OSSSYS_BASE__INST6_SEG0 0
> > +#define OSSSYS_BASE__INST6_SEG1 0
> > +#define OSSSYS_BASE__INST6_SEG2 0
> > +#define OSSSYS_BASE__INST6_SEG3 0
> > +#define OSSSYS_BASE__INST6_SEG4 0
> > +#define OSSSYS_BASE__INST6_SEG5 0
> > +
> > +#define OSSSYS_BASE__INST7_SEG0 0
> > +#define OSSSYS_BASE__INST7_SEG1 0
> > +#define OSSSYS_BASE__INST7_SEG2 0
> > +#define OSSSYS_BASE__INST7_SEG3 0
> > +#define OSSSYS_BASE__INST7_SEG4 0
> > +#define OSSSYS_BASE__INST7_SEG5 0
> > +
> > +#define PCIE0_BASE__INST0_SEG0 0x00000000
> > +#define PCIE0_BASE__INST0_SEG1 0x00000014
> > +#define PCIE0_BASE__INST0_SEG2 0x00000D20
> > +#define PCIE0_BASE__INST0_SEG3 0x00010400
> > +#define PCIE0_BASE__INST0_SEG4 0x0241B000
> > +#define PCIE0_BASE__INST0_SEG5 0x04040000
> > +
> > +#define PCIE0_BASE__INST1_SEG0 0
> > +#define PCIE0_BASE__INST1_SEG1 0
> > +#define PCIE0_BASE__INST1_SEG2 0
> > +#define PCIE0_BASE__INST1_SEG3 0
> > +#define PCIE0_BASE__INST1_SEG4 0
> > +#define PCIE0_BASE__INST1_SEG5 0
> > +
> > +#define PCIE0_BASE__INST2_SEG0 0
> > +#define PCIE0_BASE__INST2_SEG1 0
> > +#define PCIE0_BASE__INST2_SEG2 0
> > +#define PCIE0_BASE__INST2_SEG3 0
> > +#define PCIE0_BASE__INST2_SEG4 0
> > +#define PCIE0_BASE__INST2_SEG5 0
> > +
> > +#define PCIE0_BASE__INST3_SEG0 0
> > +#define PCIE0_BASE__INST3_SEG1 0
> > +#define PCIE0_BASE__INST3_SEG2 0
> > +#define PCIE0_BASE__INST3_SEG3 0
> > +#define PCIE0_BASE__INST3_SEG4 0
> > +#define PCIE0_BASE__INST3_SEG5 0
> > +
> > +#define PCIE0_BASE__INST4_SEG0 0
> > +#define PCIE0_BASE__INST4_SEG1 0
> > +#define PCIE0_BASE__INST4_SEG2 0
> > +#define PCIE0_BASE__INST4_SEG3 0
> > +#define PCIE0_BASE__INST4_SEG4 0
> > +#define PCIE0_BASE__INST4_SEG5 0
> > +
> > +#define PCIE0_BASE__INST5_SEG0 0
> > +#define PCIE0_BASE__INST5_SEG1 0
> > +#define PCIE0_BASE__INST5_SEG2 0
> > +#define PCIE0_BASE__INST5_SEG3 0
> > +#define PCIE0_BASE__INST5_SEG4 0
> > +#define PCIE0_BASE__INST5_SEG5 0
> > +
> > +#define PCIE0_BASE__INST6_SEG0 0
> > +#define PCIE0_BASE__INST6_SEG1 0
> > +#define PCIE0_BASE__INST6_SEG2 0
> > +#define PCIE0_BASE__INST6_SEG3 0
> > +#define PCIE0_BASE__INST6_SEG4 0
> > +#define PCIE0_BASE__INST6_SEG5 0
> > +
> > +#define PCIE0_BASE__INST7_SEG0 0
> > +#define PCIE0_BASE__INST7_SEG1 0
> > +#define PCIE0_BASE__INST7_SEG2 0
> > +#define PCIE0_BASE__INST7_SEG3 0
> > +#define PCIE0_BASE__INST7_SEG4 0
> > +#define PCIE0_BASE__INST7_SEG5 0
> > +
> > +#define SMUIO_BASE__INST0_SEG0 0x00016800
> > +#define SMUIO_BASE__INST0_SEG1 0x00016A00
> > +#define SMUIO_BASE__INST0_SEG2 0x02401000
> > +#define SMUIO_BASE__INST0_SEG3 0x00440000
> > +#define SMUIO_BASE__INST0_SEG4 0
> > +#define SMUIO_BASE__INST0_SEG5 0
> > +
> > +#define SMUIO_BASE__INST1_SEG0 0x0001BC00
> > +#define SMUIO_BASE__INST1_SEG1 0x0242D400
> > +#define SMUIO_BASE__INST1_SEG2 0
> > +#define SMUIO_BASE__INST1_SEG3 0
> > +#define SMUIO_BASE__INST1_SEG4 0
> > +#define SMUIO_BASE__INST1_SEG5 0
> > +
> > +#define SMUIO_BASE__INST2_SEG0 0
> > +#define SMUIO_BASE__INST2_SEG1 0
> > +#define SMUIO_BASE__INST2_SEG2 0
> > +#define SMUIO_BASE__INST2_SEG3 0
> > +#define SMUIO_BASE__INST2_SEG4 0
> > +#define SMUIO_BASE__INST2_SEG5 0
> > +
> > +#define SMUIO_BASE__INST3_SEG0 0
> > +#define SMUIO_BASE__INST3_SEG1 0
> > +#define SMUIO_BASE__INST3_SEG2 0
> > +#define SMUIO_BASE__INST3_SEG3 0
> > +#define SMUIO_BASE__INST3_SEG4 0
> > +#define SMUIO_BASE__INST3_SEG5 0
> > +
> > +#define SMUIO_BASE__INST4_SEG0 0
> > +#define SMUIO_BASE__INST4_SEG1 0
> > +#define SMUIO_BASE__INST4_SEG2 0
> > +#define SMUIO_BASE__INST4_SEG3 0
> > +#define SMUIO_BASE__INST4_SEG4 0
> > +#define SMUIO_BASE__INST4_SEG5 0
> > +
> > +#define SMUIO_BASE__INST5_SEG0 0
> > +#define SMUIO_BASE__INST5_SEG1 0
> > +#define SMUIO_BASE__INST5_SEG2 0
> > +#define SMUIO_BASE__INST5_SEG3 0
> > +#define SMUIO_BASE__INST5_SEG4 0
> > +#define SMUIO_BASE__INST5_SEG5 0
> > +
> > +#define SMUIO_BASE__INST6_SEG0 0
> > +#define SMUIO_BASE__INST6_SEG1 0
> > +#define SMUIO_BASE__INST6_SEG2 0
> > +#define SMUIO_BASE__INST6_SEG3 0
> > +#define SMUIO_BASE__INST6_SEG4 0
> > +#define SMUIO_BASE__INST6_SEG5 0
> > +
> > +#define SMUIO_BASE__INST7_SEG0 0
> > +#define SMUIO_BASE__INST7_SEG1 0
> > +#define SMUIO_BASE__INST7_SEG2 0
> > +#define SMUIO_BASE__INST7_SEG3 0
> > +#define SMUIO_BASE__INST7_SEG4 0
> > +#define SMUIO_BASE__INST7_SEG5 0
> > +
> > +#define THM_BASE__INST0_SEG0 0x00016600
> > +#define THM_BASE__INST0_SEG1 0x02400C00
> > +#define THM_BASE__INST0_SEG2 0
> > +#define THM_BASE__INST0_SEG3 0
> > +#define THM_BASE__INST0_SEG4 0
> > +#define THM_BASE__INST0_SEG5 0
> > +
> > +#define THM_BASE__INST1_SEG0 0
> > +#define THM_BASE__INST1_SEG1 0
> > +#define THM_BASE__INST1_SEG2 0
> > +#define THM_BASE__INST1_SEG3 0
> > +#define THM_BASE__INST1_SEG4 0
> > +#define THM_BASE__INST1_SEG5 0
> > +
> > +#define THM_BASE__INST2_SEG0 0
> > +#define THM_BASE__INST2_SEG1 0
> > +#define THM_BASE__INST2_SEG2 0
> > +#define THM_BASE__INST2_SEG3 0
> > +#define THM_BASE__INST2_SEG4 0
> > +#define THM_BASE__INST2_SEG5 0
> > +
> > +#define THM_BASE__INST3_SEG0 0
> > +#define THM_BASE__INST3_SEG1 0
> > +#define THM_BASE__INST3_SEG2 0
> > +#define THM_BASE__INST3_SEG3 0
> > +#define THM_BASE__INST3_SEG4 0
> > +#define THM_BASE__INST3_SEG5 0
> > +
> > +#define THM_BASE__INST4_SEG0 0
> > +#define THM_BASE__INST4_SEG1 0
> > +#define THM_BASE__INST4_SEG2 0
> > +#define THM_BASE__INST4_SEG3 0
> > +#define THM_BASE__INST4_SEG4 0
> > +#define THM_BASE__INST4_SEG5 0
> > +
> > +#define THM_BASE__INST5_SEG0 0
> > +#define THM_BASE__INST5_SEG1 0
> > +#define THM_BASE__INST5_SEG2 0
> > +#define THM_BASE__INST5_SEG3 0
> > +#define THM_BASE__INST5_SEG4 0
> > +#define THM_BASE__INST5_SEG5 0
> > +
> > +#define THM_BASE__INST6_SEG0 0
> > +#define THM_BASE__INST6_SEG1 0
> > +#define THM_BASE__INST6_SEG2 0
> > +#define THM_BASE__INST6_SEG3 0
> > +#define THM_BASE__INST6_SEG4 0
> > +#define THM_BASE__INST6_SEG5 0
> > +
> > +#define THM_BASE__INST7_SEG0 0
> > +#define THM_BASE__INST7_SEG1 0
> > +#define THM_BASE__INST7_SEG2 0
> > +#define THM_BASE__INST7_SEG3 0
> > +#define THM_BASE__INST7_SEG4 0
> > +#define THM_BASE__INST7_SEG5 0
> > +
> > +#define UMC_BASE__INST0_SEG0 0x00014000
> > +#define UMC_BASE__INST0_SEG1 0x02425800
> > +#define UMC_BASE__INST0_SEG2 0
> > +#define UMC_BASE__INST0_SEG3 0
> > +#define UMC_BASE__INST0_SEG4 0
> > +#define UMC_BASE__INST0_SEG5 0
> > +
> > +#define UMC_BASE__INST1_SEG0 0x00054000
> > +#define UMC_BASE__INST1_SEG1 0x02425C00
> > +#define UMC_BASE__INST1_SEG2 0
> > +#define UMC_BASE__INST1_SEG3 0
> > +#define UMC_BASE__INST1_SEG4 0
> > +#define UMC_BASE__INST1_SEG5 0
> > +
> > +#define UMC_BASE__INST2_SEG0 0x00094000
> > +#define UMC_BASE__INST2_SEG1 0x02426000
> > +#define UMC_BASE__INST2_SEG2 0
> > +#define UMC_BASE__INST2_SEG3 0
> > +#define UMC_BASE__INST2_SEG4 0
> > +#define UMC_BASE__INST2_SEG5 0
> > +
> > +#define UMC_BASE__INST3_SEG0 0x000D4000
> > +#define UMC_BASE__INST3_SEG1 0x02426400
> > +#define UMC_BASE__INST3_SEG2 0
> > +#define UMC_BASE__INST3_SEG3 0
> > +#define UMC_BASE__INST3_SEG4 0
> > +#define UMC_BASE__INST3_SEG5 0
> > +
> > +#define UMC_BASE__INST4_SEG0 0
> > +#define UMC_BASE__INST4_SEG1 0
> > +#define UMC_BASE__INST4_SEG2 0
> > +#define UMC_BASE__INST4_SEG3 0
> > +#define UMC_BASE__INST4_SEG4 0
> > +#define UMC_BASE__INST4_SEG5 0
> > +
> > +#define UMC_BASE__INST5_SEG0 0
> > +#define UMC_BASE__INST5_SEG1 0
> > +#define UMC_BASE__INST5_SEG2 0
> > +#define UMC_BASE__INST5_SEG3 0
> > +#define UMC_BASE__INST5_SEG4 0
> > +#define UMC_BASE__INST5_SEG5 0
> > +
> > +#define UMC_BASE__INST6_SEG0 0
> > +#define UMC_BASE__INST6_SEG1 0
> > +#define UMC_BASE__INST6_SEG2 0
> > +#define UMC_BASE__INST6_SEG3 0
> > +#define UMC_BASE__INST6_SEG4 0
> > +#define UMC_BASE__INST6_SEG5 0
> > +
> > +#define UMC_BASE__INST7_SEG0 0
> > +#define UMC_BASE__INST7_SEG1 0
> > +#define UMC_BASE__INST7_SEG2 0
> > +#define UMC_BASE__INST7_SEG3 0
> > +#define UMC_BASE__INST7_SEG4 0
> > +#define UMC_BASE__INST7_SEG5 0
> > +
> > +#define USB_BASE__INST0_SEG0 0x0242A800
> > +#define USB_BASE__INST0_SEG1 0x05B00000
> > +#define USB_BASE__INST0_SEG2 0
> > +#define USB_BASE__INST0_SEG3 0
> > +#define USB_BASE__INST0_SEG4 0
> > +#define USB_BASE__INST0_SEG5 0
> > +
> > +#define USB_BASE__INST1_SEG0 0x0242AC00
> > +#define USB_BASE__INST1_SEG1 0x05B80000
> > +#define USB_BASE__INST1_SEG2 0
> > +#define USB_BASE__INST1_SEG3 0
> > +#define USB_BASE__INST1_SEG4 0
> > +#define USB_BASE__INST1_SEG5 0
> > +
> > +#define USB_BASE__INST2_SEG0 0x0242B000
> > +#define USB_BASE__INST2_SEG1 0x05C00000
> > +#define USB_BASE__INST2_SEG2 0
> > +#define USB_BASE__INST2_SEG3 0
> > +#define USB_BASE__INST2_SEG4 0
> > +#define USB_BASE__INST2_SEG5 0
> > +
> > +#define USB_BASE__INST3_SEG0 0
> > +#define USB_BASE__INST3_SEG1 0
> > +#define USB_BASE__INST3_SEG2 0
> > +#define USB_BASE__INST3_SEG3 0
> > +#define USB_BASE__INST3_SEG4 0
> > +#define USB_BASE__INST3_SEG5 0
> > +
> > +#define USB_BASE__INST4_SEG0 0
> > +#define USB_BASE__INST4_SEG1 0
> > +#define USB_BASE__INST4_SEG2 0
> > +#define USB_BASE__INST4_SEG3 0
> > +#define USB_BASE__INST4_SEG4 0
> > +#define USB_BASE__INST4_SEG5 0
> > +
> > +#define USB_BASE__INST5_SEG0 0
> > +#define USB_BASE__INST5_SEG1 0
> > +#define USB_BASE__INST5_SEG2 0
> > +#define USB_BASE__INST5_SEG3 0
> > +#define USB_BASE__INST5_SEG4 0
> > +#define USB_BASE__INST5_SEG5 0
> > +
> > +#define USB_BASE__INST6_SEG0 0
> > +#define USB_BASE__INST6_SEG1 0
> > +#define USB_BASE__INST6_SEG2 0
> > +#define USB_BASE__INST6_SEG3 0
> > +#define USB_BASE__INST6_SEG4 0
> > +#define USB_BASE__INST6_SEG5 0
> > +
> > +#define USB_BASE__INST7_SEG0 0
> > +#define USB_BASE__INST7_SEG1 0
> > +#define USB_BASE__INST7_SEG2 0
> > +#define USB_BASE__INST7_SEG3 0
> > +#define USB_BASE__INST7_SEG4 0
> > +#define USB_BASE__INST7_SEG5 0
> > +
> > +#define VCN_BASE__INST0_SEG0 0x00007800
> > +#define VCN_BASE__INST0_SEG1 0x00007E00
> > +#define VCN_BASE__INST0_SEG2 0x02403000
> > +#define VCN_BASE__INST0_SEG3 0
> > +#define VCN_BASE__INST0_SEG4 0
> > +#define VCN_BASE__INST0_SEG5 0
> > +
> > +#define VCN_BASE__INST1_SEG0 0
> > +#define VCN_BASE__INST1_SEG1 0
> > +#define VCN_BASE__INST1_SEG2 0
> > +#define VCN_BASE__INST1_SEG3 0
> > +#define VCN_BASE__INST1_SEG4 0
> > +#define VCN_BASE__INST1_SEG5 0
> > +
> > +#define VCN_BASE__INST2_SEG0 0
> > +#define VCN_BASE__INST2_SEG1 0
> > +#define VCN_BASE__INST2_SEG2 0
> > +#define VCN_BASE__INST2_SEG3 0
> > +#define VCN_BASE__INST2_SEG4 0
> > +#define VCN_BASE__INST2_SEG5 0
> > +
> > +#define VCN_BASE__INST3_SEG0 0
> > +#define VCN_BASE__INST3_SEG1 0
> > +#define VCN_BASE__INST3_SEG2 0
> > +#define VCN_BASE__INST3_SEG3 0
> > +#define VCN_BASE__INST3_SEG4 0
> > +#define VCN_BASE__INST3_SEG5 0
> > +
> > +#define VCN_BASE__INST4_SEG0 0
> > +#define VCN_BASE__INST4_SEG1 0
> > +#define VCN_BASE__INST4_SEG2 0
> > +#define VCN_BASE__INST4_SEG3 0
> > +#define VCN_BASE__INST4_SEG4 0
> > +#define VCN_BASE__INST4_SEG5 0
> > +
> > +#define VCN_BASE__INST5_SEG0 0
> > +#define VCN_BASE__INST5_SEG1 0
> > +#define VCN_BASE__INST5_SEG2 0
> > +#define VCN_BASE__INST5_SEG3 0
> > +#define VCN_BASE__INST5_SEG4 0
> > +#define VCN_BASE__INST5_SEG5 0
> > +
> > +#define VCN_BASE__INST6_SEG0 0
> > +#define VCN_BASE__INST6_SEG1 0
> > +#define VCN_BASE__INST6_SEG2 0
> > +#define VCN_BASE__INST6_SEG3 0
> > +#define VCN_BASE__INST6_SEG4 0
> > +#define VCN_BASE__INST6_SEG5 0
> > +
> > +#define VCN_BASE__INST7_SEG0 0
> > +#define VCN_BASE__INST7_SEG1 0
> > +#define VCN_BASE__INST7_SEG2 0
> > +#define VCN_BASE__INST7_SEG3 0
> > +#define VCN_BASE__INST7_SEG4 0
> > +#define VCN_BASE__INST7_SEG5 0
> > +
> > +#endif
> >
>
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 05/45] drm/amdgpu: add vangogh_reg_base_init function for van gogh
2020-09-25 20:09 ` [PATCH 05/45] drm/amdgpu: add vangogh_reg_base_init function for van gogh Alex Deucher
@ 2020-09-28 20:48 ` Luben Tuikov
2020-09-29 14:57 ` Alex Deucher
0 siblings, 1 reply; 9+ messages in thread
From: Luben Tuikov @ 2020-09-28 20:48 UTC (permalink / raw)
To: Alex Deucher, amd-gfx; +Cc: Alex Deucher, Huang Rui
On 2020-09-25 4:09 p.m., Alex Deucher wrote:
> From: Huang Rui <ray.huang@amd.com>
>
> This patch adds vangogh_reg_base_init function to init the register base for
> van gogh.
>
> Signed-off-by: Huang Rui <ray.huang@amd.com>
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
> drivers/gpu/drm/amd/amdgpu/nv.h | 1 +
> drivers/gpu/drm/amd/amdgpu/vangogh_reg_init.c | 51 +
> .../gpu/drm/amd/include/vangogh_ip_offset.h | 1516 +++++++++++++++++
> 4 files changed, 1569 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/amd/amdgpu/vangogh_reg_init.c
> create mode 100644 drivers/gpu/drm/amd/include/vangogh_ip_offset.h
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
> index 39976c7b100c..7866e4666a43 100644
> --- a/drivers/gpu/drm/amd/amdgpu/Makefile
> +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
> @@ -69,7 +69,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce
> amdgpu-y += \
> vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \
> vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o navi10_reg_init.o navi14_reg_init.o \
> - arct_reg_init.o navi12_reg_init.o mxgpu_nv.o sienna_cichlid_reg_init.o
> + arct_reg_init.o navi12_reg_init.o mxgpu_nv.o sienna_cichlid_reg_init.o vangogh_reg_init.o
>
> # add DF block
> amdgpu-y += \
> diff --git a/drivers/gpu/drm/amd/amdgpu/nv.h b/drivers/gpu/drm/amd/amdgpu/nv.h
> index aeef50a6a54b..8a3bf476b18f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nv.h
> +++ b/drivers/gpu/drm/amd/amdgpu/nv.h
> @@ -34,4 +34,5 @@ int navi10_reg_base_init(struct amdgpu_device *adev);
> int navi14_reg_base_init(struct amdgpu_device *adev);
> int navi12_reg_base_init(struct amdgpu_device *adev);
> int sienna_cichlid_reg_base_init(struct amdgpu_device *adev);
> +int vangogh_reg_base_init(struct amdgpu_device *adev);
> #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/vangogh_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vangogh_reg_init.c
> new file mode 100644
> index 000000000000..4c6c3b415e7b
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/amdgpu/vangogh_reg_init.c
> @@ -0,0 +1,51 @@
> +/*
> + * Copyright 2019 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + */
> +#include "amdgpu.h"
> +#include "nv.h"
> +
> +#include "soc15_common.h"
> +#include "soc15_hw_ip.h"
> +#include "vangogh_ip_offset.h"
> +
> +int vangogh_reg_base_init(struct amdgpu_device *adev)
> +{
> + /* HW has more IP blocks, only initialized the blocke needed by driver */
> + uint32_t i;
> + for (i = 0 ; i < MAX_INSTANCE ; ++i) {
> + adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
> + adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
> + adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
> + adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
> + adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
> + adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
> + adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
> + adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i]));
> + adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
> + adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCN_BASE.instance[i]));
> + adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));
> + adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
> + adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
> + adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
I'd align the equality sign for presentation.
> + }
> + return 0;
> +}
This function should be "void", else the compiler will throw a warning
when you compile nv.c.
> diff --git a/drivers/gpu/drm/amd/include/vangogh_ip_offset.h b/drivers/gpu/drm/amd/include/vangogh_ip_offset.h
> new file mode 100644
> index 000000000000..2875574b060e
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/include/vangogh_ip_offset.h
> @@ -0,0 +1,1516 @@
> +/*
> + * Copyright 2019 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + */
> +
> +#ifndef __VANGOGH_IP_OFFSET_H__
> +#define __VANGOGH_IP_OFFSET_H__
> +
> +#define MAX_INSTANCE 8
> +#define MAX_SEGMENT 6
No. No "max". Use "num" instead, as:
#define NUM_INSTANCE 8
#define NUM_SEGMENT 6
To mean, the _number_ of instances and the _number_ of
segments. (Their count is a number.)
A "maximum" (similarly "minimum") value is an _attainable_ value,
i.e. something you can get, use, etc. But array indices are 0 to arraysize-1,
and thus max instance can never be attained.
It is the count, the number of instances (segments, wlg),
not the maximum instance. The maximum instance is 7,
the minimum instance is 0. Similarly for segments.
> +
> +
> +struct IP_BASE_INSTANCE
> +{
> + unsigned int segment[MAX_SEGMENT];
> +};
So, here if you used NUM_SEGMENT, it is very clear
what is intended: an array of number of segments,
i.e. their count, whose array index would be 0 to
NUM_SEGMENTS-1.
Similarly for "instance" below.
Regards,
Luben
> +
> +struct IP_BASE
> +{
> + struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
> +};
> +
> +
> +static const struct IP_BASE ACP_BASE = { { { { 0x02403800, 0x00480000, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C00, 0x00013300, 0x02408C00, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } },
> + { { 0x00016E00, 0x02401C00, 0, 0, 0, 0 } },
> + { { 0x00017000, 0x02402000, 0, 0, 0, 0 } },
> + { { 0x00017200, 0x02402400, 0, 0, 0, 0 } },
> + { { 0x0001B000, 0x0242D800, 0, 0, 0, 0 } },
> + { { 0x0001B200, 0x0242DC00, 0, 0, 0, 0 } },
> + { { 0x0001B400, 0x0242E000, 0, 0, 0, 0 } },
> + { { 0x00017E00, 0x0240BC00, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0x0240B800, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE DPCS_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE FCH_BASE = { { { { 0x0240C000, 0x00B40000, 0x11000000, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0x02401400, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE GC_BASE = { { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0x0240A400, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE ISP_BASE = { { { { 0x00018000, 0x0240B000, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE MMHUB_BASE = { { { { 0x00013200, 0x0001A000, 0x02408800, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x0243FC00, 0x00DC0000, 0x00E00000, 0x00E40000, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0x0243FC00, 0x00DC0000, 0x00E00000, 0x00E40000, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE MP2_BASE = { { { { 0x00016400, 0x02400800, 0x00F40000, 0x00F80000, 0x00FC0000, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0x0240A000, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE PCIE0_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0x00016A00, 0x02401000, 0x00440000, 0, 0 } },
> + { { 0x0001BC00, 0x0242D400, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0x02400C00, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0x02425800, 0, 0, 0, 0 } },
> + { { 0x00054000, 0x02425C00, 0, 0, 0, 0 } },
> + { { 0x00094000, 0x02426000, 0, 0, 0, 0 } },
> + { { 0x000D4000, 0x02426400, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE USB_BASE = { { { { 0x0242A800, 0x05B00000, 0, 0, 0, 0 } },
> + { { 0x0242AC00, 0x05B80000, 0, 0, 0, 0 } },
> + { { 0x0242B000, 0x05C00000, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE VCN_BASE = { { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } } } };
> +
> +
> +#define ACP_BASE__INST0_SEG0 0x02403800
> +#define ACP_BASE__INST0_SEG1 0x00480000
> +#define ACP_BASE__INST0_SEG2 0
> +#define ACP_BASE__INST0_SEG3 0
> +#define ACP_BASE__INST0_SEG4 0
> +#define ACP_BASE__INST0_SEG5 0
> +
> +#define ACP_BASE__INST1_SEG0 0
> +#define ACP_BASE__INST1_SEG1 0
> +#define ACP_BASE__INST1_SEG2 0
> +#define ACP_BASE__INST1_SEG3 0
> +#define ACP_BASE__INST1_SEG4 0
> +#define ACP_BASE__INST1_SEG5 0
> +
> +#define ACP_BASE__INST2_SEG0 0
> +#define ACP_BASE__INST2_SEG1 0
> +#define ACP_BASE__INST2_SEG2 0
> +#define ACP_BASE__INST2_SEG3 0
> +#define ACP_BASE__INST2_SEG4 0
> +#define ACP_BASE__INST2_SEG5 0
> +
> +#define ACP_BASE__INST3_SEG0 0
> +#define ACP_BASE__INST3_SEG1 0
> +#define ACP_BASE__INST3_SEG2 0
> +#define ACP_BASE__INST3_SEG3 0
> +#define ACP_BASE__INST3_SEG4 0
> +#define ACP_BASE__INST3_SEG5 0
> +
> +#define ACP_BASE__INST4_SEG0 0
> +#define ACP_BASE__INST4_SEG1 0
> +#define ACP_BASE__INST4_SEG2 0
> +#define ACP_BASE__INST4_SEG3 0
> +#define ACP_BASE__INST4_SEG4 0
> +#define ACP_BASE__INST4_SEG5 0
> +
> +#define ACP_BASE__INST5_SEG0 0
> +#define ACP_BASE__INST5_SEG1 0
> +#define ACP_BASE__INST5_SEG2 0
> +#define ACP_BASE__INST5_SEG3 0
> +#define ACP_BASE__INST5_SEG4 0
> +#define ACP_BASE__INST5_SEG5 0
> +
> +#define ACP_BASE__INST6_SEG0 0
> +#define ACP_BASE__INST6_SEG1 0
> +#define ACP_BASE__INST6_SEG2 0
> +#define ACP_BASE__INST6_SEG3 0
> +#define ACP_BASE__INST6_SEG4 0
> +#define ACP_BASE__INST6_SEG5 0
> +
> +#define ACP_BASE__INST7_SEG0 0
> +#define ACP_BASE__INST7_SEG1 0
> +#define ACP_BASE__INST7_SEG2 0
> +#define ACP_BASE__INST7_SEG3 0
> +#define ACP_BASE__INST7_SEG4 0
> +#define ACP_BASE__INST7_SEG5 0
> +
> +#define ATHUB_BASE__INST0_SEG0 0x00000C00
> +#define ATHUB_BASE__INST0_SEG1 0x00013300
> +#define ATHUB_BASE__INST0_SEG2 0x02408C00
> +#define ATHUB_BASE__INST0_SEG3 0
> +#define ATHUB_BASE__INST0_SEG4 0
> +#define ATHUB_BASE__INST0_SEG5 0
> +
> +#define ATHUB_BASE__INST1_SEG0 0
> +#define ATHUB_BASE__INST1_SEG1 0
> +#define ATHUB_BASE__INST1_SEG2 0
> +#define ATHUB_BASE__INST1_SEG3 0
> +#define ATHUB_BASE__INST1_SEG4 0
> +#define ATHUB_BASE__INST1_SEG5 0
> +
> +#define ATHUB_BASE__INST2_SEG0 0
> +#define ATHUB_BASE__INST2_SEG1 0
> +#define ATHUB_BASE__INST2_SEG2 0
> +#define ATHUB_BASE__INST2_SEG3 0
> +#define ATHUB_BASE__INST2_SEG4 0
> +#define ATHUB_BASE__INST2_SEG5 0
> +
> +#define ATHUB_BASE__INST3_SEG0 0
> +#define ATHUB_BASE__INST3_SEG1 0
> +#define ATHUB_BASE__INST3_SEG2 0
> +#define ATHUB_BASE__INST3_SEG3 0
> +#define ATHUB_BASE__INST3_SEG4 0
> +#define ATHUB_BASE__INST3_SEG5 0
> +
> +#define ATHUB_BASE__INST4_SEG0 0
> +#define ATHUB_BASE__INST4_SEG1 0
> +#define ATHUB_BASE__INST4_SEG2 0
> +#define ATHUB_BASE__INST4_SEG3 0
> +#define ATHUB_BASE__INST4_SEG4 0
> +#define ATHUB_BASE__INST4_SEG5 0
> +
> +#define ATHUB_BASE__INST5_SEG0 0
> +#define ATHUB_BASE__INST5_SEG1 0
> +#define ATHUB_BASE__INST5_SEG2 0
> +#define ATHUB_BASE__INST5_SEG3 0
> +#define ATHUB_BASE__INST5_SEG4 0
> +#define ATHUB_BASE__INST5_SEG5 0
> +
> +#define ATHUB_BASE__INST6_SEG0 0
> +#define ATHUB_BASE__INST6_SEG1 0
> +#define ATHUB_BASE__INST6_SEG2 0
> +#define ATHUB_BASE__INST6_SEG3 0
> +#define ATHUB_BASE__INST6_SEG4 0
> +#define ATHUB_BASE__INST6_SEG5 0
> +
> +#define ATHUB_BASE__INST7_SEG0 0
> +#define ATHUB_BASE__INST7_SEG1 0
> +#define ATHUB_BASE__INST7_SEG2 0
> +#define ATHUB_BASE__INST7_SEG3 0
> +#define ATHUB_BASE__INST7_SEG4 0
> +#define ATHUB_BASE__INST7_SEG5 0
> +
> +#define CLK_BASE__INST0_SEG0 0x00016C00
> +#define CLK_BASE__INST0_SEG1 0x02401800
> +#define CLK_BASE__INST0_SEG2 0
> +#define CLK_BASE__INST0_SEG3 0
> +#define CLK_BASE__INST0_SEG4 0
> +#define CLK_BASE__INST0_SEG5 0
> +
> +#define CLK_BASE__INST1_SEG0 0x00016E00
> +#define CLK_BASE__INST1_SEG1 0x02401C00
> +#define CLK_BASE__INST1_SEG2 0
> +#define CLK_BASE__INST1_SEG3 0
> +#define CLK_BASE__INST1_SEG4 0
> +#define CLK_BASE__INST1_SEG5 0
> +
> +#define CLK_BASE__INST2_SEG0 0x00017000
> +#define CLK_BASE__INST2_SEG1 0x02402000
> +#define CLK_BASE__INST2_SEG2 0
> +#define CLK_BASE__INST2_SEG3 0
> +#define CLK_BASE__INST2_SEG4 0
> +#define CLK_BASE__INST2_SEG5 0
> +
> +#define CLK_BASE__INST3_SEG0 0x00017200
> +#define CLK_BASE__INST3_SEG1 0x02402400
> +#define CLK_BASE__INST3_SEG2 0
> +#define CLK_BASE__INST3_SEG3 0
> +#define CLK_BASE__INST3_SEG4 0
> +#define CLK_BASE__INST3_SEG5 0
> +
> +#define CLK_BASE__INST4_SEG0 0x0001B000
> +#define CLK_BASE__INST4_SEG1 0x0242D800
> +#define CLK_BASE__INST4_SEG2 0
> +#define CLK_BASE__INST4_SEG3 0
> +#define CLK_BASE__INST4_SEG4 0
> +#define CLK_BASE__INST4_SEG5 0
> +
> +#define CLK_BASE__INST5_SEG0 0x0001B200
> +#define CLK_BASE__INST5_SEG1 0x0242DC00
> +#define CLK_BASE__INST5_SEG2 0
> +#define CLK_BASE__INST5_SEG3 0
> +#define CLK_BASE__INST5_SEG4 0
> +#define CLK_BASE__INST5_SEG5 0
> +
> +#define CLK_BASE__INST6_SEG0 0x0001B400
> +#define CLK_BASE__INST6_SEG1 0x0242E000
> +#define CLK_BASE__INST6_SEG2 0
> +#define CLK_BASE__INST6_SEG3 0
> +#define CLK_BASE__INST6_SEG4 0
> +#define CLK_BASE__INST6_SEG5 0
> +
> +#define CLK_BASE__INST7_SEG0 0x00017E00
> +#define CLK_BASE__INST7_SEG1 0x0240BC00
> +#define CLK_BASE__INST7_SEG2 0
> +#define CLK_BASE__INST7_SEG3 0
> +#define CLK_BASE__INST7_SEG4 0
> +#define CLK_BASE__INST7_SEG5 0
> +
> +#define DF_BASE__INST0_SEG0 0x00007000
> +#define DF_BASE__INST0_SEG1 0x0240B800
> +#define DF_BASE__INST0_SEG2 0
> +#define DF_BASE__INST0_SEG3 0
> +#define DF_BASE__INST0_SEG4 0
> +#define DF_BASE__INST0_SEG5 0
> +
> +#define DF_BASE__INST1_SEG0 0
> +#define DF_BASE__INST1_SEG1 0
> +#define DF_BASE__INST1_SEG2 0
> +#define DF_BASE__INST1_SEG3 0
> +#define DF_BASE__INST1_SEG4 0
> +#define DF_BASE__INST1_SEG5 0
> +
> +#define DF_BASE__INST2_SEG0 0
> +#define DF_BASE__INST2_SEG1 0
> +#define DF_BASE__INST2_SEG2 0
> +#define DF_BASE__INST2_SEG3 0
> +#define DF_BASE__INST2_SEG4 0
> +#define DF_BASE__INST2_SEG5 0
> +
> +#define DF_BASE__INST3_SEG0 0
> +#define DF_BASE__INST3_SEG1 0
> +#define DF_BASE__INST3_SEG2 0
> +#define DF_BASE__INST3_SEG3 0
> +#define DF_BASE__INST3_SEG4 0
> +#define DF_BASE__INST3_SEG5 0
> +
> +#define DF_BASE__INST4_SEG0 0
> +#define DF_BASE__INST4_SEG1 0
> +#define DF_BASE__INST4_SEG2 0
> +#define DF_BASE__INST4_SEG3 0
> +#define DF_BASE__INST4_SEG4 0
> +#define DF_BASE__INST4_SEG5 0
> +
> +#define DF_BASE__INST5_SEG0 0
> +#define DF_BASE__INST5_SEG1 0
> +#define DF_BASE__INST5_SEG2 0
> +#define DF_BASE__INST5_SEG3 0
> +#define DF_BASE__INST5_SEG4 0
> +#define DF_BASE__INST5_SEG5 0
> +
> +#define DF_BASE__INST6_SEG0 0
> +#define DF_BASE__INST6_SEG1 0
> +#define DF_BASE__INST6_SEG2 0
> +#define DF_BASE__INST6_SEG3 0
> +#define DF_BASE__INST6_SEG4 0
> +#define DF_BASE__INST6_SEG5 0
> +
> +#define DF_BASE__INST7_SEG0 0
> +#define DF_BASE__INST7_SEG1 0
> +#define DF_BASE__INST7_SEG2 0
> +#define DF_BASE__INST7_SEG3 0
> +#define DF_BASE__INST7_SEG4 0
> +#define DF_BASE__INST7_SEG5 0
> +
> +#define DCN_BASE__INST0_SEG0 0x00000012
> +#define DCN_BASE__INST0_SEG1 0x000000C0
> +#define DCN_BASE__INST0_SEG2 0x000034C0
> +#define DCN_BASE__INST0_SEG3 0x00009000
> +#define DCN_BASE__INST0_SEG4 0x02403C00
> +#define DCN_BASE__INST0_SEG5 0
> +
> +#define DCN_BASE__INST1_SEG0 0
> +#define DCN_BASE__INST1_SEG1 0
> +#define DCN_BASE__INST1_SEG2 0
> +#define DCN_BASE__INST1_SEG3 0
> +#define DCN_BASE__INST1_SEG4 0
> +#define DCN_BASE__INST1_SEG5 0
> +
> +#define DCN_BASE__INST2_SEG0 0
> +#define DCN_BASE__INST2_SEG1 0
> +#define DCN_BASE__INST2_SEG2 0
> +#define DCN_BASE__INST2_SEG3 0
> +#define DCN_BASE__INST2_SEG4 0
> +#define DCN_BASE__INST2_SEG5 0
> +
> +#define DCN_BASE__INST3_SEG0 0
> +#define DCN_BASE__INST3_SEG1 0
> +#define DCN_BASE__INST3_SEG2 0
> +#define DCN_BASE__INST3_SEG3 0
> +#define DCN_BASE__INST3_SEG4 0
> +#define DCN_BASE__INST3_SEG5 0
> +
> +#define DCN_BASE__INST4_SEG0 0
> +#define DCN_BASE__INST4_SEG1 0
> +#define DCN_BASE__INST4_SEG2 0
> +#define DCN_BASE__INST4_SEG3 0
> +#define DCN_BASE__INST4_SEG4 0
> +#define DCN_BASE__INST4_SEG5 0
> +
> +#define DCN_BASE__INST5_SEG0 0
> +#define DCN_BASE__INST5_SEG1 0
> +#define DCN_BASE__INST5_SEG2 0
> +#define DCN_BASE__INST5_SEG3 0
> +#define DCN_BASE__INST5_SEG4 0
> +#define DCN_BASE__INST5_SEG5 0
> +
> +#define DCN_BASE__INST6_SEG0 0
> +#define DCN_BASE__INST6_SEG1 0
> +#define DCN_BASE__INST6_SEG2 0
> +#define DCN_BASE__INST6_SEG3 0
> +#define DCN_BASE__INST6_SEG4 0
> +#define DCN_BASE__INST6_SEG5 0
> +
> +#define DCN_BASE__INST7_SEG0 0
> +#define DCN_BASE__INST7_SEG1 0
> +#define DCN_BASE__INST7_SEG2 0
> +#define DCN_BASE__INST7_SEG3 0
> +#define DCN_BASE__INST7_SEG4 0
> +#define DCN_BASE__INST7_SEG5 0
> +
> +#define DPCS_BASE__INST0_SEG0 0x00000012
> +#define DPCS_BASE__INST0_SEG1 0x000000C0
> +#define DPCS_BASE__INST0_SEG2 0x000034C0
> +#define DPCS_BASE__INST0_SEG3 0x00009000
> +#define DPCS_BASE__INST0_SEG4 0x02403C00
> +#define DPCS_BASE__INST0_SEG5 0
> +
> +#define DPCS_BASE__INST1_SEG0 0
> +#define DPCS_BASE__INST1_SEG1 0
> +#define DPCS_BASE__INST1_SEG2 0
> +#define DPCS_BASE__INST1_SEG3 0
> +#define DPCS_BASE__INST1_SEG4 0
> +#define DPCS_BASE__INST1_SEG5 0
> +
> +#define DPCS_BASE__INST2_SEG0 0
> +#define DPCS_BASE__INST2_SEG1 0
> +#define DPCS_BASE__INST2_SEG2 0
> +#define DPCS_BASE__INST2_SEG3 0
> +#define DPCS_BASE__INST2_SEG4 0
> +#define DPCS_BASE__INST2_SEG5 0
> +
> +#define DPCS_BASE__INST3_SEG0 0
> +#define DPCS_BASE__INST3_SEG1 0
> +#define DPCS_BASE__INST3_SEG2 0
> +#define DPCS_BASE__INST3_SEG3 0
> +#define DPCS_BASE__INST3_SEG4 0
> +#define DPCS_BASE__INST3_SEG5 0
> +
> +#define DPCS_BASE__INST4_SEG0 0
> +#define DPCS_BASE__INST4_SEG1 0
> +#define DPCS_BASE__INST4_SEG2 0
> +#define DPCS_BASE__INST4_SEG3 0
> +#define DPCS_BASE__INST4_SEG4 0
> +#define DPCS_BASE__INST4_SEG5 0
> +
> +#define DPCS_BASE__INST5_SEG0 0
> +#define DPCS_BASE__INST5_SEG1 0
> +#define DPCS_BASE__INST5_SEG2 0
> +#define DPCS_BASE__INST5_SEG3 0
> +#define DPCS_BASE__INST5_SEG4 0
> +#define DPCS_BASE__INST5_SEG5 0
> +
> +#define DPCS_BASE__INST6_SEG0 0
> +#define DPCS_BASE__INST6_SEG1 0
> +#define DPCS_BASE__INST6_SEG2 0
> +#define DPCS_BASE__INST6_SEG3 0
> +#define DPCS_BASE__INST6_SEG4 0
> +#define DPCS_BASE__INST6_SEG5 0
> +
> +#define DPCS_BASE__INST7_SEG0 0
> +#define DPCS_BASE__INST7_SEG1 0
> +#define DPCS_BASE__INST7_SEG2 0
> +#define DPCS_BASE__INST7_SEG3 0
> +#define DPCS_BASE__INST7_SEG4 0
> +#define DPCS_BASE__INST7_SEG5 0
> +
> +#define FCH_BASE__INST0_SEG0 0x0240C000
> +#define FCH_BASE__INST0_SEG1 0x00B40000
> +#define FCH_BASE__INST0_SEG2 0x11000000
> +#define FCH_BASE__INST0_SEG3 0
> +#define FCH_BASE__INST0_SEG4 0
> +#define FCH_BASE__INST0_SEG5 0
> +
> +#define FCH_BASE__INST1_SEG0 0
> +#define FCH_BASE__INST1_SEG1 0
> +#define FCH_BASE__INST1_SEG2 0
> +#define FCH_BASE__INST1_SEG3 0
> +#define FCH_BASE__INST1_SEG4 0
> +#define FCH_BASE__INST1_SEG5 0
> +
> +#define FCH_BASE__INST2_SEG0 0
> +#define FCH_BASE__INST2_SEG1 0
> +#define FCH_BASE__INST2_SEG2 0
> +#define FCH_BASE__INST2_SEG3 0
> +#define FCH_BASE__INST2_SEG4 0
> +#define FCH_BASE__INST2_SEG5 0
> +
> +#define FCH_BASE__INST3_SEG0 0
> +#define FCH_BASE__INST3_SEG1 0
> +#define FCH_BASE__INST3_SEG2 0
> +#define FCH_BASE__INST3_SEG3 0
> +#define FCH_BASE__INST3_SEG4 0
> +#define FCH_BASE__INST3_SEG5 0
> +
> +#define FCH_BASE__INST4_SEG0 0
> +#define FCH_BASE__INST4_SEG1 0
> +#define FCH_BASE__INST4_SEG2 0
> +#define FCH_BASE__INST4_SEG3 0
> +#define FCH_BASE__INST4_SEG4 0
> +#define FCH_BASE__INST4_SEG5 0
> +
> +#define FCH_BASE__INST5_SEG0 0
> +#define FCH_BASE__INST5_SEG1 0
> +#define FCH_BASE__INST5_SEG2 0
> +#define FCH_BASE__INST5_SEG3 0
> +#define FCH_BASE__INST5_SEG4 0
> +#define FCH_BASE__INST5_SEG5 0
> +
> +#define FCH_BASE__INST6_SEG0 0
> +#define FCH_BASE__INST6_SEG1 0
> +#define FCH_BASE__INST6_SEG2 0
> +#define FCH_BASE__INST6_SEG3 0
> +#define FCH_BASE__INST6_SEG4 0
> +#define FCH_BASE__INST6_SEG5 0
> +
> +#define FCH_BASE__INST7_SEG0 0
> +#define FCH_BASE__INST7_SEG1 0
> +#define FCH_BASE__INST7_SEG2 0
> +#define FCH_BASE__INST7_SEG3 0
> +#define FCH_BASE__INST7_SEG4 0
> +#define FCH_BASE__INST7_SEG5 0
> +
> +#define FUSE_BASE__INST0_SEG0 0x00017400
> +#define FUSE_BASE__INST0_SEG1 0x02401400
> +#define FUSE_BASE__INST0_SEG2 0
> +#define FUSE_BASE__INST0_SEG3 0
> +#define FUSE_BASE__INST0_SEG4 0
> +#define FUSE_BASE__INST0_SEG5 0
> +
> +#define FUSE_BASE__INST1_SEG0 0
> +#define FUSE_BASE__INST1_SEG1 0
> +#define FUSE_BASE__INST1_SEG2 0
> +#define FUSE_BASE__INST1_SEG3 0
> +#define FUSE_BASE__INST1_SEG4 0
> +#define FUSE_BASE__INST1_SEG5 0
> +
> +#define FUSE_BASE__INST2_SEG0 0
> +#define FUSE_BASE__INST2_SEG1 0
> +#define FUSE_BASE__INST2_SEG2 0
> +#define FUSE_BASE__INST2_SEG3 0
> +#define FUSE_BASE__INST2_SEG4 0
> +#define FUSE_BASE__INST2_SEG5 0
> +
> +#define FUSE_BASE__INST3_SEG0 0
> +#define FUSE_BASE__INST3_SEG1 0
> +#define FUSE_BASE__INST3_SEG2 0
> +#define FUSE_BASE__INST3_SEG3 0
> +#define FUSE_BASE__INST3_SEG4 0
> +#define FUSE_BASE__INST3_SEG5 0
> +
> +#define FUSE_BASE__INST4_SEG0 0
> +#define FUSE_BASE__INST4_SEG1 0
> +#define FUSE_BASE__INST4_SEG2 0
> +#define FUSE_BASE__INST4_SEG3 0
> +#define FUSE_BASE__INST4_SEG4 0
> +#define FUSE_BASE__INST4_SEG5 0
> +
> +#define FUSE_BASE__INST5_SEG0 0
> +#define FUSE_BASE__INST5_SEG1 0
> +#define FUSE_BASE__INST5_SEG2 0
> +#define FUSE_BASE__INST5_SEG3 0
> +#define FUSE_BASE__INST5_SEG4 0
> +#define FUSE_BASE__INST5_SEG5 0
> +
> +#define FUSE_BASE__INST6_SEG0 0
> +#define FUSE_BASE__INST6_SEG1 0
> +#define FUSE_BASE__INST6_SEG2 0
> +#define FUSE_BASE__INST6_SEG3 0
> +#define FUSE_BASE__INST6_SEG4 0
> +#define FUSE_BASE__INST6_SEG5 0
> +
> +#define FUSE_BASE__INST7_SEG0 0
> +#define FUSE_BASE__INST7_SEG1 0
> +#define FUSE_BASE__INST7_SEG2 0
> +#define FUSE_BASE__INST7_SEG3 0
> +#define FUSE_BASE__INST7_SEG4 0
> +#define FUSE_BASE__INST7_SEG5 0
> +
> +#define GC_BASE__INST0_SEG0 0x00001260
> +#define GC_BASE__INST0_SEG1 0x0000A000
> +#define GC_BASE__INST0_SEG2 0x02402C00
> +#define GC_BASE__INST0_SEG3 0
> +#define GC_BASE__INST0_SEG4 0
> +#define GC_BASE__INST0_SEG5 0
> +
> +#define GC_BASE__INST1_SEG0 0
> +#define GC_BASE__INST1_SEG1 0
> +#define GC_BASE__INST1_SEG2 0
> +#define GC_BASE__INST1_SEG3 0
> +#define GC_BASE__INST1_SEG4 0
> +#define GC_BASE__INST1_SEG5 0
> +
> +#define GC_BASE__INST2_SEG0 0
> +#define GC_BASE__INST2_SEG1 0
> +#define GC_BASE__INST2_SEG2 0
> +#define GC_BASE__INST2_SEG3 0
> +#define GC_BASE__INST2_SEG4 0
> +#define GC_BASE__INST2_SEG5 0
> +
> +#define GC_BASE__INST3_SEG0 0
> +#define GC_BASE__INST3_SEG1 0
> +#define GC_BASE__INST3_SEG2 0
> +#define GC_BASE__INST3_SEG3 0
> +#define GC_BASE__INST3_SEG4 0
> +#define GC_BASE__INST3_SEG5 0
> +
> +#define GC_BASE__INST4_SEG0 0
> +#define GC_BASE__INST4_SEG1 0
> +#define GC_BASE__INST4_SEG2 0
> +#define GC_BASE__INST4_SEG3 0
> +#define GC_BASE__INST4_SEG4 0
> +#define GC_BASE__INST4_SEG5 0
> +
> +#define GC_BASE__INST5_SEG0 0
> +#define GC_BASE__INST5_SEG1 0
> +#define GC_BASE__INST5_SEG2 0
> +#define GC_BASE__INST5_SEG3 0
> +#define GC_BASE__INST5_SEG4 0
> +#define GC_BASE__INST5_SEG5 0
> +
> +#define GC_BASE__INST6_SEG0 0
> +#define GC_BASE__INST6_SEG1 0
> +#define GC_BASE__INST6_SEG2 0
> +#define GC_BASE__INST6_SEG3 0
> +#define GC_BASE__INST6_SEG4 0
> +#define GC_BASE__INST6_SEG5 0
> +
> +#define GC_BASE__INST7_SEG0 0
> +#define GC_BASE__INST7_SEG1 0
> +#define GC_BASE__INST7_SEG2 0
> +#define GC_BASE__INST7_SEG3 0
> +#define GC_BASE__INST7_SEG4 0
> +#define GC_BASE__INST7_SEG5 0
> +
> +#define HDP_BASE__INST0_SEG0 0x00000F20
> +#define HDP_BASE__INST0_SEG1 0x0240A400
> +#define HDP_BASE__INST0_SEG2 0
> +#define HDP_BASE__INST0_SEG3 0
> +#define HDP_BASE__INST0_SEG4 0
> +#define HDP_BASE__INST0_SEG5 0
> +
> +#define HDP_BASE__INST1_SEG0 0
> +#define HDP_BASE__INST1_SEG1 0
> +#define HDP_BASE__INST1_SEG2 0
> +#define HDP_BASE__INST1_SEG3 0
> +#define HDP_BASE__INST1_SEG4 0
> +#define HDP_BASE__INST1_SEG5 0
> +
> +#define HDP_BASE__INST2_SEG0 0
> +#define HDP_BASE__INST2_SEG1 0
> +#define HDP_BASE__INST2_SEG2 0
> +#define HDP_BASE__INST2_SEG3 0
> +#define HDP_BASE__INST2_SEG4 0
> +#define HDP_BASE__INST2_SEG5 0
> +
> +#define HDP_BASE__INST3_SEG0 0
> +#define HDP_BASE__INST3_SEG1 0
> +#define HDP_BASE__INST3_SEG2 0
> +#define HDP_BASE__INST3_SEG3 0
> +#define HDP_BASE__INST3_SEG4 0
> +#define HDP_BASE__INST3_SEG5 0
> +
> +#define HDP_BASE__INST4_SEG0 0
> +#define HDP_BASE__INST4_SEG1 0
> +#define HDP_BASE__INST4_SEG2 0
> +#define HDP_BASE__INST4_SEG3 0
> +#define HDP_BASE__INST4_SEG4 0
> +#define HDP_BASE__INST4_SEG5 0
> +
> +#define HDP_BASE__INST5_SEG0 0
> +#define HDP_BASE__INST5_SEG1 0
> +#define HDP_BASE__INST5_SEG2 0
> +#define HDP_BASE__INST5_SEG3 0
> +#define HDP_BASE__INST5_SEG4 0
> +#define HDP_BASE__INST5_SEG5 0
> +
> +#define HDP_BASE__INST6_SEG0 0
> +#define HDP_BASE__INST6_SEG1 0
> +#define HDP_BASE__INST6_SEG2 0
> +#define HDP_BASE__INST6_SEG3 0
> +#define HDP_BASE__INST6_SEG4 0
> +#define HDP_BASE__INST6_SEG5 0
> +
> +#define HDP_BASE__INST7_SEG0 0
> +#define HDP_BASE__INST7_SEG1 0
> +#define HDP_BASE__INST7_SEG2 0
> +#define HDP_BASE__INST7_SEG3 0
> +#define HDP_BASE__INST7_SEG4 0
> +#define HDP_BASE__INST7_SEG5 0
> +
> +#define ISP_BASE__INST0_SEG0 0x00018000
> +#define ISP_BASE__INST0_SEG1 0x0240B000
> +#define ISP_BASE__INST0_SEG2 0
> +#define ISP_BASE__INST0_SEG3 0
> +#define ISP_BASE__INST0_SEG4 0
> +#define ISP_BASE__INST0_SEG5 0
> +
> +#define ISP_BASE__INST1_SEG0 0
> +#define ISP_BASE__INST1_SEG1 0
> +#define ISP_BASE__INST1_SEG2 0
> +#define ISP_BASE__INST1_SEG3 0
> +#define ISP_BASE__INST1_SEG4 0
> +#define ISP_BASE__INST1_SEG5 0
> +
> +#define ISP_BASE__INST2_SEG0 0
> +#define ISP_BASE__INST2_SEG1 0
> +#define ISP_BASE__INST2_SEG2 0
> +#define ISP_BASE__INST2_SEG3 0
> +#define ISP_BASE__INST2_SEG4 0
> +#define ISP_BASE__INST2_SEG5 0
> +
> +#define ISP_BASE__INST3_SEG0 0
> +#define ISP_BASE__INST3_SEG1 0
> +#define ISP_BASE__INST3_SEG2 0
> +#define ISP_BASE__INST3_SEG3 0
> +#define ISP_BASE__INST3_SEG4 0
> +#define ISP_BASE__INST3_SEG5 0
> +
> +#define ISP_BASE__INST4_SEG0 0
> +#define ISP_BASE__INST4_SEG1 0
> +#define ISP_BASE__INST4_SEG2 0
> +#define ISP_BASE__INST4_SEG3 0
> +#define ISP_BASE__INST4_SEG4 0
> +#define ISP_BASE__INST4_SEG5 0
> +
> +#define ISP_BASE__INST5_SEG0 0
> +#define ISP_BASE__INST5_SEG1 0
> +#define ISP_BASE__INST5_SEG2 0
> +#define ISP_BASE__INST5_SEG3 0
> +#define ISP_BASE__INST5_SEG4 0
> +#define ISP_BASE__INST5_SEG5 0
> +
> +#define ISP_BASE__INST6_SEG0 0
> +#define ISP_BASE__INST6_SEG1 0
> +#define ISP_BASE__INST6_SEG2 0
> +#define ISP_BASE__INST6_SEG3 0
> +#define ISP_BASE__INST6_SEG4 0
> +#define ISP_BASE__INST6_SEG5 0
> +
> +#define ISP_BASE__INST7_SEG0 0
> +#define ISP_BASE__INST7_SEG1 0
> +#define ISP_BASE__INST7_SEG2 0
> +#define ISP_BASE__INST7_SEG3 0
> +#define ISP_BASE__INST7_SEG4 0
> +#define ISP_BASE__INST7_SEG5 0
> +
> +#define MMHUB_BASE__INST0_SEG0 0x00013200
> +#define MMHUB_BASE__INST0_SEG1 0x0001A000
> +#define MMHUB_BASE__INST0_SEG2 0x02408800
> +#define MMHUB_BASE__INST0_SEG3 0
> +#define MMHUB_BASE__INST0_SEG4 0
> +#define MMHUB_BASE__INST0_SEG5 0
> +
> +#define MMHUB_BASE__INST1_SEG0 0
> +#define MMHUB_BASE__INST1_SEG1 0
> +#define MMHUB_BASE__INST1_SEG2 0
> +#define MMHUB_BASE__INST1_SEG3 0
> +#define MMHUB_BASE__INST1_SEG4 0
> +#define MMHUB_BASE__INST1_SEG5 0
> +
> +#define MMHUB_BASE__INST2_SEG0 0
> +#define MMHUB_BASE__INST2_SEG1 0
> +#define MMHUB_BASE__INST2_SEG2 0
> +#define MMHUB_BASE__INST2_SEG3 0
> +#define MMHUB_BASE__INST2_SEG4 0
> +#define MMHUB_BASE__INST2_SEG5 0
> +
> +#define MMHUB_BASE__INST3_SEG0 0
> +#define MMHUB_BASE__INST3_SEG1 0
> +#define MMHUB_BASE__INST3_SEG2 0
> +#define MMHUB_BASE__INST3_SEG3 0
> +#define MMHUB_BASE__INST3_SEG4 0
> +#define MMHUB_BASE__INST3_SEG5 0
> +
> +#define MMHUB_BASE__INST4_SEG0 0
> +#define MMHUB_BASE__INST4_SEG1 0
> +#define MMHUB_BASE__INST4_SEG2 0
> +#define MMHUB_BASE__INST4_SEG3 0
> +#define MMHUB_BASE__INST4_SEG4 0
> +#define MMHUB_BASE__INST4_SEG5 0
> +
> +#define MMHUB_BASE__INST5_SEG0 0
> +#define MMHUB_BASE__INST5_SEG1 0
> +#define MMHUB_BASE__INST5_SEG2 0
> +#define MMHUB_BASE__INST5_SEG3 0
> +#define MMHUB_BASE__INST5_SEG4 0
> +#define MMHUB_BASE__INST5_SEG5 0
> +
> +#define MMHUB_BASE__INST6_SEG0 0
> +#define MMHUB_BASE__INST6_SEG1 0
> +#define MMHUB_BASE__INST6_SEG2 0
> +#define MMHUB_BASE__INST6_SEG3 0
> +#define MMHUB_BASE__INST6_SEG4 0
> +#define MMHUB_BASE__INST6_SEG5 0
> +
> +#define MMHUB_BASE__INST7_SEG0 0
> +#define MMHUB_BASE__INST7_SEG1 0
> +#define MMHUB_BASE__INST7_SEG2 0
> +#define MMHUB_BASE__INST7_SEG3 0
> +#define MMHUB_BASE__INST7_SEG4 0
> +#define MMHUB_BASE__INST7_SEG5 0
> +
> +#define MP0_BASE__INST0_SEG0 0x00016000
> +#define MP0_BASE__INST0_SEG1 0x0243FC00
> +#define MP0_BASE__INST0_SEG2 0x00DC0000
> +#define MP0_BASE__INST0_SEG3 0x00E00000
> +#define MP0_BASE__INST0_SEG4 0x00E40000
> +#define MP0_BASE__INST0_SEG5 0
> +
> +#define MP0_BASE__INST1_SEG0 0
> +#define MP0_BASE__INST1_SEG1 0
> +#define MP0_BASE__INST1_SEG2 0
> +#define MP0_BASE__INST1_SEG3 0
> +#define MP0_BASE__INST1_SEG4 0
> +#define MP0_BASE__INST1_SEG5 0
> +
> +#define MP0_BASE__INST2_SEG0 0
> +#define MP0_BASE__INST2_SEG1 0
> +#define MP0_BASE__INST2_SEG2 0
> +#define MP0_BASE__INST2_SEG3 0
> +#define MP0_BASE__INST2_SEG4 0
> +#define MP0_BASE__INST2_SEG5 0
> +
> +#define MP0_BASE__INST3_SEG0 0
> +#define MP0_BASE__INST3_SEG1 0
> +#define MP0_BASE__INST3_SEG2 0
> +#define MP0_BASE__INST3_SEG3 0
> +#define MP0_BASE__INST3_SEG4 0
> +#define MP0_BASE__INST3_SEG5 0
> +
> +#define MP0_BASE__INST4_SEG0 0
> +#define MP0_BASE__INST4_SEG1 0
> +#define MP0_BASE__INST4_SEG2 0
> +#define MP0_BASE__INST4_SEG3 0
> +#define MP0_BASE__INST4_SEG4 0
> +#define MP0_BASE__INST4_SEG5 0
> +
> +#define MP0_BASE__INST5_SEG0 0
> +#define MP0_BASE__INST5_SEG1 0
> +#define MP0_BASE__INST5_SEG2 0
> +#define MP0_BASE__INST5_SEG3 0
> +#define MP0_BASE__INST5_SEG4 0
> +#define MP0_BASE__INST5_SEG5 0
> +
> +#define MP0_BASE__INST6_SEG0 0
> +#define MP0_BASE__INST6_SEG1 0
> +#define MP0_BASE__INST6_SEG2 0
> +#define MP0_BASE__INST6_SEG3 0
> +#define MP0_BASE__INST6_SEG4 0
> +#define MP0_BASE__INST6_SEG5 0
> +
> +#define MP0_BASE__INST7_SEG0 0
> +#define MP0_BASE__INST7_SEG1 0
> +#define MP0_BASE__INST7_SEG2 0
> +#define MP0_BASE__INST7_SEG3 0
> +#define MP0_BASE__INST7_SEG4 0
> +#define MP0_BASE__INST7_SEG5 0
> +
> +#define MP1_BASE__INST0_SEG0 0x00016000
> +#define MP1_BASE__INST0_SEG1 0x0243FC00
> +#define MP1_BASE__INST0_SEG2 0x00DC0000
> +#define MP1_BASE__INST0_SEG3 0x00E00000
> +#define MP1_BASE__INST0_SEG4 0x00E40000
> +#define MP1_BASE__INST0_SEG5 0
> +
> +#define MP1_BASE__INST1_SEG0 0
> +#define MP1_BASE__INST1_SEG1 0
> +#define MP1_BASE__INST1_SEG2 0
> +#define MP1_BASE__INST1_SEG3 0
> +#define MP1_BASE__INST1_SEG4 0
> +#define MP1_BASE__INST1_SEG5 0
> +
> +#define MP1_BASE__INST2_SEG0 0
> +#define MP1_BASE__INST2_SEG1 0
> +#define MP1_BASE__INST2_SEG2 0
> +#define MP1_BASE__INST2_SEG3 0
> +#define MP1_BASE__INST2_SEG4 0
> +#define MP1_BASE__INST2_SEG5 0
> +
> +#define MP1_BASE__INST3_SEG0 0
> +#define MP1_BASE__INST3_SEG1 0
> +#define MP1_BASE__INST3_SEG2 0
> +#define MP1_BASE__INST3_SEG3 0
> +#define MP1_BASE__INST3_SEG4 0
> +#define MP1_BASE__INST3_SEG5 0
> +
> +#define MP1_BASE__INST4_SEG0 0
> +#define MP1_BASE__INST4_SEG1 0
> +#define MP1_BASE__INST4_SEG2 0
> +#define MP1_BASE__INST4_SEG3 0
> +#define MP1_BASE__INST4_SEG4 0
> +#define MP1_BASE__INST4_SEG5 0
> +
> +#define MP1_BASE__INST5_SEG0 0
> +#define MP1_BASE__INST5_SEG1 0
> +#define MP1_BASE__INST5_SEG2 0
> +#define MP1_BASE__INST5_SEG3 0
> +#define MP1_BASE__INST5_SEG4 0
> +#define MP1_BASE__INST5_SEG5 0
> +
> +#define MP1_BASE__INST6_SEG0 0
> +#define MP1_BASE__INST6_SEG1 0
> +#define MP1_BASE__INST6_SEG2 0
> +#define MP1_BASE__INST6_SEG3 0
> +#define MP1_BASE__INST6_SEG4 0
> +#define MP1_BASE__INST6_SEG5 0
> +
> +#define MP1_BASE__INST7_SEG0 0
> +#define MP1_BASE__INST7_SEG1 0
> +#define MP1_BASE__INST7_SEG2 0
> +#define MP1_BASE__INST7_SEG3 0
> +#define MP1_BASE__INST7_SEG4 0
> +#define MP1_BASE__INST7_SEG5 0
> +
> +#define MP2_BASE__INST0_SEG0 0x00016400
> +#define MP2_BASE__INST0_SEG1 0x02400800
> +#define MP2_BASE__INST0_SEG2 0x00F40000
> +#define MP2_BASE__INST0_SEG3 0x00F80000
> +#define MP2_BASE__INST0_SEG4 0x00FC0000
> +#define MP2_BASE__INST0_SEG5 0
> +
> +#define MP2_BASE__INST1_SEG0 0
> +#define MP2_BASE__INST1_SEG1 0
> +#define MP2_BASE__INST1_SEG2 0
> +#define MP2_BASE__INST1_SEG3 0
> +#define MP2_BASE__INST1_SEG4 0
> +#define MP2_BASE__INST1_SEG5 0
> +
> +#define MP2_BASE__INST2_SEG0 0
> +#define MP2_BASE__INST2_SEG1 0
> +#define MP2_BASE__INST2_SEG2 0
> +#define MP2_BASE__INST2_SEG3 0
> +#define MP2_BASE__INST2_SEG4 0
> +#define MP2_BASE__INST2_SEG5 0
> +
> +#define MP2_BASE__INST3_SEG0 0
> +#define MP2_BASE__INST3_SEG1 0
> +#define MP2_BASE__INST3_SEG2 0
> +#define MP2_BASE__INST3_SEG3 0
> +#define MP2_BASE__INST3_SEG4 0
> +#define MP2_BASE__INST3_SEG5 0
> +
> +#define MP2_BASE__INST4_SEG0 0
> +#define MP2_BASE__INST4_SEG1 0
> +#define MP2_BASE__INST4_SEG2 0
> +#define MP2_BASE__INST4_SEG3 0
> +#define MP2_BASE__INST4_SEG4 0
> +#define MP2_BASE__INST4_SEG5 0
> +
> +#define MP2_BASE__INST5_SEG0 0
> +#define MP2_BASE__INST5_SEG1 0
> +#define MP2_BASE__INST5_SEG2 0
> +#define MP2_BASE__INST5_SEG3 0
> +#define MP2_BASE__INST5_SEG4 0
> +#define MP2_BASE__INST5_SEG5 0
> +
> +#define MP2_BASE__INST6_SEG0 0
> +#define MP2_BASE__INST6_SEG1 0
> +#define MP2_BASE__INST6_SEG2 0
> +#define MP2_BASE__INST6_SEG3 0
> +#define MP2_BASE__INST6_SEG4 0
> +#define MP2_BASE__INST6_SEG5 0
> +
> +#define MP2_BASE__INST7_SEG0 0
> +#define MP2_BASE__INST7_SEG1 0
> +#define MP2_BASE__INST7_SEG2 0
> +#define MP2_BASE__INST7_SEG3 0
> +#define MP2_BASE__INST7_SEG4 0
> +#define MP2_BASE__INST7_SEG5 0
> +
> +#define NBIO_BASE__INST0_SEG0 0x00000000
> +#define NBIO_BASE__INST0_SEG1 0x00000014
> +#define NBIO_BASE__INST0_SEG2 0x00000D20
> +#define NBIO_BASE__INST0_SEG3 0x00010400
> +#define NBIO_BASE__INST0_SEG4 0x0241B000
> +#define NBIO_BASE__INST0_SEG5 0x04040000
> +
> +#define NBIO_BASE__INST1_SEG0 0
> +#define NBIO_BASE__INST1_SEG1 0
> +#define NBIO_BASE__INST1_SEG2 0
> +#define NBIO_BASE__INST1_SEG3 0
> +#define NBIO_BASE__INST1_SEG4 0
> +#define NBIO_BASE__INST1_SEG5 0
> +
> +#define NBIO_BASE__INST2_SEG0 0
> +#define NBIO_BASE__INST2_SEG1 0
> +#define NBIO_BASE__INST2_SEG2 0
> +#define NBIO_BASE__INST2_SEG3 0
> +#define NBIO_BASE__INST2_SEG4 0
> +#define NBIO_BASE__INST2_SEG5 0
> +
> +#define NBIO_BASE__INST3_SEG0 0
> +#define NBIO_BASE__INST3_SEG1 0
> +#define NBIO_BASE__INST3_SEG2 0
> +#define NBIO_BASE__INST3_SEG3 0
> +#define NBIO_BASE__INST3_SEG4 0
> +#define NBIO_BASE__INST3_SEG5 0
> +
> +#define NBIO_BASE__INST4_SEG0 0
> +#define NBIO_BASE__INST4_SEG1 0
> +#define NBIO_BASE__INST4_SEG2 0
> +#define NBIO_BASE__INST4_SEG3 0
> +#define NBIO_BASE__INST4_SEG4 0
> +#define NBIO_BASE__INST4_SEG5 0
> +
> +#define NBIO_BASE__INST5_SEG0 0
> +#define NBIO_BASE__INST5_SEG1 0
> +#define NBIO_BASE__INST5_SEG2 0
> +#define NBIO_BASE__INST5_SEG3 0
> +#define NBIO_BASE__INST5_SEG4 0
> +#define NBIO_BASE__INST5_SEG5 0
> +
> +#define NBIO_BASE__INST6_SEG0 0
> +#define NBIO_BASE__INST6_SEG1 0
> +#define NBIO_BASE__INST6_SEG2 0
> +#define NBIO_BASE__INST6_SEG3 0
> +#define NBIO_BASE__INST6_SEG4 0
> +#define NBIO_BASE__INST6_SEG5 0
> +
> +#define NBIO_BASE__INST7_SEG0 0
> +#define NBIO_BASE__INST7_SEG1 0
> +#define NBIO_BASE__INST7_SEG2 0
> +#define NBIO_BASE__INST7_SEG3 0
> +#define NBIO_BASE__INST7_SEG4 0
> +#define NBIO_BASE__INST7_SEG5 0
> +
> +#define OSSSYS_BASE__INST0_SEG0 0x000010A0
> +#define OSSSYS_BASE__INST0_SEG1 0x0240A000
> +#define OSSSYS_BASE__INST0_SEG2 0
> +#define OSSSYS_BASE__INST0_SEG3 0
> +#define OSSSYS_BASE__INST0_SEG4 0
> +#define OSSSYS_BASE__INST0_SEG5 0
> +
> +#define OSSSYS_BASE__INST1_SEG0 0
> +#define OSSSYS_BASE__INST1_SEG1 0
> +#define OSSSYS_BASE__INST1_SEG2 0
> +#define OSSSYS_BASE__INST1_SEG3 0
> +#define OSSSYS_BASE__INST1_SEG4 0
> +#define OSSSYS_BASE__INST1_SEG5 0
> +
> +#define OSSSYS_BASE__INST2_SEG0 0
> +#define OSSSYS_BASE__INST2_SEG1 0
> +#define OSSSYS_BASE__INST2_SEG2 0
> +#define OSSSYS_BASE__INST2_SEG3 0
> +#define OSSSYS_BASE__INST2_SEG4 0
> +#define OSSSYS_BASE__INST2_SEG5 0
> +
> +#define OSSSYS_BASE__INST3_SEG0 0
> +#define OSSSYS_BASE__INST3_SEG1 0
> +#define OSSSYS_BASE__INST3_SEG2 0
> +#define OSSSYS_BASE__INST3_SEG3 0
> +#define OSSSYS_BASE__INST3_SEG4 0
> +#define OSSSYS_BASE__INST3_SEG5 0
> +
> +#define OSSSYS_BASE__INST4_SEG0 0
> +#define OSSSYS_BASE__INST4_SEG1 0
> +#define OSSSYS_BASE__INST4_SEG2 0
> +#define OSSSYS_BASE__INST4_SEG3 0
> +#define OSSSYS_BASE__INST4_SEG4 0
> +#define OSSSYS_BASE__INST4_SEG5 0
> +
> +#define OSSSYS_BASE__INST5_SEG0 0
> +#define OSSSYS_BASE__INST5_SEG1 0
> +#define OSSSYS_BASE__INST5_SEG2 0
> +#define OSSSYS_BASE__INST5_SEG3 0
> +#define OSSSYS_BASE__INST5_SEG4 0
> +#define OSSSYS_BASE__INST5_SEG5 0
> +
> +#define OSSSYS_BASE__INST6_SEG0 0
> +#define OSSSYS_BASE__INST6_SEG1 0
> +#define OSSSYS_BASE__INST6_SEG2 0
> +#define OSSSYS_BASE__INST6_SEG3 0
> +#define OSSSYS_BASE__INST6_SEG4 0
> +#define OSSSYS_BASE__INST6_SEG5 0
> +
> +#define OSSSYS_BASE__INST7_SEG0 0
> +#define OSSSYS_BASE__INST7_SEG1 0
> +#define OSSSYS_BASE__INST7_SEG2 0
> +#define OSSSYS_BASE__INST7_SEG3 0
> +#define OSSSYS_BASE__INST7_SEG4 0
> +#define OSSSYS_BASE__INST7_SEG5 0
> +
> +#define PCIE0_BASE__INST0_SEG0 0x00000000
> +#define PCIE0_BASE__INST0_SEG1 0x00000014
> +#define PCIE0_BASE__INST0_SEG2 0x00000D20
> +#define PCIE0_BASE__INST0_SEG3 0x00010400
> +#define PCIE0_BASE__INST0_SEG4 0x0241B000
> +#define PCIE0_BASE__INST0_SEG5 0x04040000
> +
> +#define PCIE0_BASE__INST1_SEG0 0
> +#define PCIE0_BASE__INST1_SEG1 0
> +#define PCIE0_BASE__INST1_SEG2 0
> +#define PCIE0_BASE__INST1_SEG3 0
> +#define PCIE0_BASE__INST1_SEG4 0
> +#define PCIE0_BASE__INST1_SEG5 0
> +
> +#define PCIE0_BASE__INST2_SEG0 0
> +#define PCIE0_BASE__INST2_SEG1 0
> +#define PCIE0_BASE__INST2_SEG2 0
> +#define PCIE0_BASE__INST2_SEG3 0
> +#define PCIE0_BASE__INST2_SEG4 0
> +#define PCIE0_BASE__INST2_SEG5 0
> +
> +#define PCIE0_BASE__INST3_SEG0 0
> +#define PCIE0_BASE__INST3_SEG1 0
> +#define PCIE0_BASE__INST3_SEG2 0
> +#define PCIE0_BASE__INST3_SEG3 0
> +#define PCIE0_BASE__INST3_SEG4 0
> +#define PCIE0_BASE__INST3_SEG5 0
> +
> +#define PCIE0_BASE__INST4_SEG0 0
> +#define PCIE0_BASE__INST4_SEG1 0
> +#define PCIE0_BASE__INST4_SEG2 0
> +#define PCIE0_BASE__INST4_SEG3 0
> +#define PCIE0_BASE__INST4_SEG4 0
> +#define PCIE0_BASE__INST4_SEG5 0
> +
> +#define PCIE0_BASE__INST5_SEG0 0
> +#define PCIE0_BASE__INST5_SEG1 0
> +#define PCIE0_BASE__INST5_SEG2 0
> +#define PCIE0_BASE__INST5_SEG3 0
> +#define PCIE0_BASE__INST5_SEG4 0
> +#define PCIE0_BASE__INST5_SEG5 0
> +
> +#define PCIE0_BASE__INST6_SEG0 0
> +#define PCIE0_BASE__INST6_SEG1 0
> +#define PCIE0_BASE__INST6_SEG2 0
> +#define PCIE0_BASE__INST6_SEG3 0
> +#define PCIE0_BASE__INST6_SEG4 0
> +#define PCIE0_BASE__INST6_SEG5 0
> +
> +#define PCIE0_BASE__INST7_SEG0 0
> +#define PCIE0_BASE__INST7_SEG1 0
> +#define PCIE0_BASE__INST7_SEG2 0
> +#define PCIE0_BASE__INST7_SEG3 0
> +#define PCIE0_BASE__INST7_SEG4 0
> +#define PCIE0_BASE__INST7_SEG5 0
> +
> +#define SMUIO_BASE__INST0_SEG0 0x00016800
> +#define SMUIO_BASE__INST0_SEG1 0x00016A00
> +#define SMUIO_BASE__INST0_SEG2 0x02401000
> +#define SMUIO_BASE__INST0_SEG3 0x00440000
> +#define SMUIO_BASE__INST0_SEG4 0
> +#define SMUIO_BASE__INST0_SEG5 0
> +
> +#define SMUIO_BASE__INST1_SEG0 0x0001BC00
> +#define SMUIO_BASE__INST1_SEG1 0x0242D400
> +#define SMUIO_BASE__INST1_SEG2 0
> +#define SMUIO_BASE__INST1_SEG3 0
> +#define SMUIO_BASE__INST1_SEG4 0
> +#define SMUIO_BASE__INST1_SEG5 0
> +
> +#define SMUIO_BASE__INST2_SEG0 0
> +#define SMUIO_BASE__INST2_SEG1 0
> +#define SMUIO_BASE__INST2_SEG2 0
> +#define SMUIO_BASE__INST2_SEG3 0
> +#define SMUIO_BASE__INST2_SEG4 0
> +#define SMUIO_BASE__INST2_SEG5 0
> +
> +#define SMUIO_BASE__INST3_SEG0 0
> +#define SMUIO_BASE__INST3_SEG1 0
> +#define SMUIO_BASE__INST3_SEG2 0
> +#define SMUIO_BASE__INST3_SEG3 0
> +#define SMUIO_BASE__INST3_SEG4 0
> +#define SMUIO_BASE__INST3_SEG5 0
> +
> +#define SMUIO_BASE__INST4_SEG0 0
> +#define SMUIO_BASE__INST4_SEG1 0
> +#define SMUIO_BASE__INST4_SEG2 0
> +#define SMUIO_BASE__INST4_SEG3 0
> +#define SMUIO_BASE__INST4_SEG4 0
> +#define SMUIO_BASE__INST4_SEG5 0
> +
> +#define SMUIO_BASE__INST5_SEG0 0
> +#define SMUIO_BASE__INST5_SEG1 0
> +#define SMUIO_BASE__INST5_SEG2 0
> +#define SMUIO_BASE__INST5_SEG3 0
> +#define SMUIO_BASE__INST5_SEG4 0
> +#define SMUIO_BASE__INST5_SEG5 0
> +
> +#define SMUIO_BASE__INST6_SEG0 0
> +#define SMUIO_BASE__INST6_SEG1 0
> +#define SMUIO_BASE__INST6_SEG2 0
> +#define SMUIO_BASE__INST6_SEG3 0
> +#define SMUIO_BASE__INST6_SEG4 0
> +#define SMUIO_BASE__INST6_SEG5 0
> +
> +#define SMUIO_BASE__INST7_SEG0 0
> +#define SMUIO_BASE__INST7_SEG1 0
> +#define SMUIO_BASE__INST7_SEG2 0
> +#define SMUIO_BASE__INST7_SEG3 0
> +#define SMUIO_BASE__INST7_SEG4 0
> +#define SMUIO_BASE__INST7_SEG5 0
> +
> +#define THM_BASE__INST0_SEG0 0x00016600
> +#define THM_BASE__INST0_SEG1 0x02400C00
> +#define THM_BASE__INST0_SEG2 0
> +#define THM_BASE__INST0_SEG3 0
> +#define THM_BASE__INST0_SEG4 0
> +#define THM_BASE__INST0_SEG5 0
> +
> +#define THM_BASE__INST1_SEG0 0
> +#define THM_BASE__INST1_SEG1 0
> +#define THM_BASE__INST1_SEG2 0
> +#define THM_BASE__INST1_SEG3 0
> +#define THM_BASE__INST1_SEG4 0
> +#define THM_BASE__INST1_SEG5 0
> +
> +#define THM_BASE__INST2_SEG0 0
> +#define THM_BASE__INST2_SEG1 0
> +#define THM_BASE__INST2_SEG2 0
> +#define THM_BASE__INST2_SEG3 0
> +#define THM_BASE__INST2_SEG4 0
> +#define THM_BASE__INST2_SEG5 0
> +
> +#define THM_BASE__INST3_SEG0 0
> +#define THM_BASE__INST3_SEG1 0
> +#define THM_BASE__INST3_SEG2 0
> +#define THM_BASE__INST3_SEG3 0
> +#define THM_BASE__INST3_SEG4 0
> +#define THM_BASE__INST3_SEG5 0
> +
> +#define THM_BASE__INST4_SEG0 0
> +#define THM_BASE__INST4_SEG1 0
> +#define THM_BASE__INST4_SEG2 0
> +#define THM_BASE__INST4_SEG3 0
> +#define THM_BASE__INST4_SEG4 0
> +#define THM_BASE__INST4_SEG5 0
> +
> +#define THM_BASE__INST5_SEG0 0
> +#define THM_BASE__INST5_SEG1 0
> +#define THM_BASE__INST5_SEG2 0
> +#define THM_BASE__INST5_SEG3 0
> +#define THM_BASE__INST5_SEG4 0
> +#define THM_BASE__INST5_SEG5 0
> +
> +#define THM_BASE__INST6_SEG0 0
> +#define THM_BASE__INST6_SEG1 0
> +#define THM_BASE__INST6_SEG2 0
> +#define THM_BASE__INST6_SEG3 0
> +#define THM_BASE__INST6_SEG4 0
> +#define THM_BASE__INST6_SEG5 0
> +
> +#define THM_BASE__INST7_SEG0 0
> +#define THM_BASE__INST7_SEG1 0
> +#define THM_BASE__INST7_SEG2 0
> +#define THM_BASE__INST7_SEG3 0
> +#define THM_BASE__INST7_SEG4 0
> +#define THM_BASE__INST7_SEG5 0
> +
> +#define UMC_BASE__INST0_SEG0 0x00014000
> +#define UMC_BASE__INST0_SEG1 0x02425800
> +#define UMC_BASE__INST0_SEG2 0
> +#define UMC_BASE__INST0_SEG3 0
> +#define UMC_BASE__INST0_SEG4 0
> +#define UMC_BASE__INST0_SEG5 0
> +
> +#define UMC_BASE__INST1_SEG0 0x00054000
> +#define UMC_BASE__INST1_SEG1 0x02425C00
> +#define UMC_BASE__INST1_SEG2 0
> +#define UMC_BASE__INST1_SEG3 0
> +#define UMC_BASE__INST1_SEG4 0
> +#define UMC_BASE__INST1_SEG5 0
> +
> +#define UMC_BASE__INST2_SEG0 0x00094000
> +#define UMC_BASE__INST2_SEG1 0x02426000
> +#define UMC_BASE__INST2_SEG2 0
> +#define UMC_BASE__INST2_SEG3 0
> +#define UMC_BASE__INST2_SEG4 0
> +#define UMC_BASE__INST2_SEG5 0
> +
> +#define UMC_BASE__INST3_SEG0 0x000D4000
> +#define UMC_BASE__INST3_SEG1 0x02426400
> +#define UMC_BASE__INST3_SEG2 0
> +#define UMC_BASE__INST3_SEG3 0
> +#define UMC_BASE__INST3_SEG4 0
> +#define UMC_BASE__INST3_SEG5 0
> +
> +#define UMC_BASE__INST4_SEG0 0
> +#define UMC_BASE__INST4_SEG1 0
> +#define UMC_BASE__INST4_SEG2 0
> +#define UMC_BASE__INST4_SEG3 0
> +#define UMC_BASE__INST4_SEG4 0
> +#define UMC_BASE__INST4_SEG5 0
> +
> +#define UMC_BASE__INST5_SEG0 0
> +#define UMC_BASE__INST5_SEG1 0
> +#define UMC_BASE__INST5_SEG2 0
> +#define UMC_BASE__INST5_SEG3 0
> +#define UMC_BASE__INST5_SEG4 0
> +#define UMC_BASE__INST5_SEG5 0
> +
> +#define UMC_BASE__INST6_SEG0 0
> +#define UMC_BASE__INST6_SEG1 0
> +#define UMC_BASE__INST6_SEG2 0
> +#define UMC_BASE__INST6_SEG3 0
> +#define UMC_BASE__INST6_SEG4 0
> +#define UMC_BASE__INST6_SEG5 0
> +
> +#define UMC_BASE__INST7_SEG0 0
> +#define UMC_BASE__INST7_SEG1 0
> +#define UMC_BASE__INST7_SEG2 0
> +#define UMC_BASE__INST7_SEG3 0
> +#define UMC_BASE__INST7_SEG4 0
> +#define UMC_BASE__INST7_SEG5 0
> +
> +#define USB_BASE__INST0_SEG0 0x0242A800
> +#define USB_BASE__INST0_SEG1 0x05B00000
> +#define USB_BASE__INST0_SEG2 0
> +#define USB_BASE__INST0_SEG3 0
> +#define USB_BASE__INST0_SEG4 0
> +#define USB_BASE__INST0_SEG5 0
> +
> +#define USB_BASE__INST1_SEG0 0x0242AC00
> +#define USB_BASE__INST1_SEG1 0x05B80000
> +#define USB_BASE__INST1_SEG2 0
> +#define USB_BASE__INST1_SEG3 0
> +#define USB_BASE__INST1_SEG4 0
> +#define USB_BASE__INST1_SEG5 0
> +
> +#define USB_BASE__INST2_SEG0 0x0242B000
> +#define USB_BASE__INST2_SEG1 0x05C00000
> +#define USB_BASE__INST2_SEG2 0
> +#define USB_BASE__INST2_SEG3 0
> +#define USB_BASE__INST2_SEG4 0
> +#define USB_BASE__INST2_SEG5 0
> +
> +#define USB_BASE__INST3_SEG0 0
> +#define USB_BASE__INST3_SEG1 0
> +#define USB_BASE__INST3_SEG2 0
> +#define USB_BASE__INST3_SEG3 0
> +#define USB_BASE__INST3_SEG4 0
> +#define USB_BASE__INST3_SEG5 0
> +
> +#define USB_BASE__INST4_SEG0 0
> +#define USB_BASE__INST4_SEG1 0
> +#define USB_BASE__INST4_SEG2 0
> +#define USB_BASE__INST4_SEG3 0
> +#define USB_BASE__INST4_SEG4 0
> +#define USB_BASE__INST4_SEG5 0
> +
> +#define USB_BASE__INST5_SEG0 0
> +#define USB_BASE__INST5_SEG1 0
> +#define USB_BASE__INST5_SEG2 0
> +#define USB_BASE__INST5_SEG3 0
> +#define USB_BASE__INST5_SEG4 0
> +#define USB_BASE__INST5_SEG5 0
> +
> +#define USB_BASE__INST6_SEG0 0
> +#define USB_BASE__INST6_SEG1 0
> +#define USB_BASE__INST6_SEG2 0
> +#define USB_BASE__INST6_SEG3 0
> +#define USB_BASE__INST6_SEG4 0
> +#define USB_BASE__INST6_SEG5 0
> +
> +#define USB_BASE__INST7_SEG0 0
> +#define USB_BASE__INST7_SEG1 0
> +#define USB_BASE__INST7_SEG2 0
> +#define USB_BASE__INST7_SEG3 0
> +#define USB_BASE__INST7_SEG4 0
> +#define USB_BASE__INST7_SEG5 0
> +
> +#define VCN_BASE__INST0_SEG0 0x00007800
> +#define VCN_BASE__INST0_SEG1 0x00007E00
> +#define VCN_BASE__INST0_SEG2 0x02403000
> +#define VCN_BASE__INST0_SEG3 0
> +#define VCN_BASE__INST0_SEG4 0
> +#define VCN_BASE__INST0_SEG5 0
> +
> +#define VCN_BASE__INST1_SEG0 0
> +#define VCN_BASE__INST1_SEG1 0
> +#define VCN_BASE__INST1_SEG2 0
> +#define VCN_BASE__INST1_SEG3 0
> +#define VCN_BASE__INST1_SEG4 0
> +#define VCN_BASE__INST1_SEG5 0
> +
> +#define VCN_BASE__INST2_SEG0 0
> +#define VCN_BASE__INST2_SEG1 0
> +#define VCN_BASE__INST2_SEG2 0
> +#define VCN_BASE__INST2_SEG3 0
> +#define VCN_BASE__INST2_SEG4 0
> +#define VCN_BASE__INST2_SEG5 0
> +
> +#define VCN_BASE__INST3_SEG0 0
> +#define VCN_BASE__INST3_SEG1 0
> +#define VCN_BASE__INST3_SEG2 0
> +#define VCN_BASE__INST3_SEG3 0
> +#define VCN_BASE__INST3_SEG4 0
> +#define VCN_BASE__INST3_SEG5 0
> +
> +#define VCN_BASE__INST4_SEG0 0
> +#define VCN_BASE__INST4_SEG1 0
> +#define VCN_BASE__INST4_SEG2 0
> +#define VCN_BASE__INST4_SEG3 0
> +#define VCN_BASE__INST4_SEG4 0
> +#define VCN_BASE__INST4_SEG5 0
> +
> +#define VCN_BASE__INST5_SEG0 0
> +#define VCN_BASE__INST5_SEG1 0
> +#define VCN_BASE__INST5_SEG2 0
> +#define VCN_BASE__INST5_SEG3 0
> +#define VCN_BASE__INST5_SEG4 0
> +#define VCN_BASE__INST5_SEG5 0
> +
> +#define VCN_BASE__INST6_SEG0 0
> +#define VCN_BASE__INST6_SEG1 0
> +#define VCN_BASE__INST6_SEG2 0
> +#define VCN_BASE__INST6_SEG3 0
> +#define VCN_BASE__INST6_SEG4 0
> +#define VCN_BASE__INST6_SEG5 0
> +
> +#define VCN_BASE__INST7_SEG0 0
> +#define VCN_BASE__INST7_SEG1 0
> +#define VCN_BASE__INST7_SEG2 0
> +#define VCN_BASE__INST7_SEG3 0
> +#define VCN_BASE__INST7_SEG4 0
> +#define VCN_BASE__INST7_SEG5 0
> +
> +#endif
>
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^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 05/45] drm/amdgpu: add vangogh_reg_base_init function for van gogh
2020-09-25 20:09 [PATCH 00/45] Add support for vangoh Alex Deucher
@ 2020-09-25 20:09 ` Alex Deucher
2020-09-28 20:48 ` Luben Tuikov
0 siblings, 1 reply; 9+ messages in thread
From: Alex Deucher @ 2020-09-25 20:09 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
This patch adds vangogh_reg_base_init function to init the register base for
van gogh.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
drivers/gpu/drm/amd/amdgpu/nv.h | 1 +
drivers/gpu/drm/amd/amdgpu/vangogh_reg_init.c | 51 +
.../gpu/drm/amd/include/vangogh_ip_offset.h | 1516 +++++++++++++++++
4 files changed, 1569 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/vangogh_reg_init.c
create mode 100644 drivers/gpu/drm/amd/include/vangogh_ip_offset.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index 39976c7b100c..7866e4666a43 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -69,7 +69,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce
amdgpu-y += \
vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \
vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o navi10_reg_init.o navi14_reg_init.o \
- arct_reg_init.o navi12_reg_init.o mxgpu_nv.o sienna_cichlid_reg_init.o
+ arct_reg_init.o navi12_reg_init.o mxgpu_nv.o sienna_cichlid_reg_init.o vangogh_reg_init.o
# add DF block
amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.h b/drivers/gpu/drm/amd/amdgpu/nv.h
index aeef50a6a54b..8a3bf476b18f 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.h
+++ b/drivers/gpu/drm/amd/amdgpu/nv.h
@@ -34,4 +34,5 @@ int navi10_reg_base_init(struct amdgpu_device *adev);
int navi14_reg_base_init(struct amdgpu_device *adev);
int navi12_reg_base_init(struct amdgpu_device *adev);
int sienna_cichlid_reg_base_init(struct amdgpu_device *adev);
+int vangogh_reg_base_init(struct amdgpu_device *adev);
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/vangogh_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vangogh_reg_init.c
new file mode 100644
index 000000000000..4c6c3b415e7b
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/vangogh_reg_init.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include "amdgpu.h"
+#include "nv.h"
+
+#include "soc15_common.h"
+#include "soc15_hw_ip.h"
+#include "vangogh_ip_offset.h"
+
+int vangogh_reg_base_init(struct amdgpu_device *adev)
+{
+ /* HW has more IP blocks, only initialized the blocke needed by driver */
+ uint32_t i;
+ for (i = 0 ; i < MAX_INSTANCE ; ++i) {
+ adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
+ adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
+ adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
+ adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
+ adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
+ adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
+ adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
+ adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i]));
+ adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
+ adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCN_BASE.instance[i]));
+ adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));
+ adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
+ adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
+ adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
+ }
+ return 0;
+}
diff --git a/drivers/gpu/drm/amd/include/vangogh_ip_offset.h b/drivers/gpu/drm/amd/include/vangogh_ip_offset.h
new file mode 100644
index 000000000000..2875574b060e
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/vangogh_ip_offset.h
@@ -0,0 +1,1516 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __VANGOGH_IP_OFFSET_H__
+#define __VANGOGH_IP_OFFSET_H__
+
+#define MAX_INSTANCE 8
+#define MAX_SEGMENT 6
+
+
+struct IP_BASE_INSTANCE
+{
+ unsigned int segment[MAX_SEGMENT];
+};
+
+struct IP_BASE
+{
+ struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
+};
+
+
+static const struct IP_BASE ACP_BASE = { { { { 0x02403800, 0x00480000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C00, 0x00013300, 0x02408C00, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } },
+ { { 0x00016E00, 0x02401C00, 0, 0, 0, 0 } },
+ { { 0x00017000, 0x02402000, 0, 0, 0, 0 } },
+ { { 0x00017200, 0x02402400, 0, 0, 0, 0 } },
+ { { 0x0001B000, 0x0242D800, 0, 0, 0, 0 } },
+ { { 0x0001B200, 0x0242DC00, 0, 0, 0, 0 } },
+ { { 0x0001B400, 0x0242E000, 0, 0, 0, 0 } },
+ { { 0x00017E00, 0x0240BC00, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0x0240B800, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DPCS_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE FCH_BASE = { { { { 0x0240C000, 0x00B40000, 0x11000000, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0x02401400, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE GC_BASE = { { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0x0240A400, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE ISP_BASE = { { { { 0x00018000, 0x0240B000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MMHUB_BASE = { { { { 0x00013200, 0x0001A000, 0x02408800, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x0243FC00, 0x00DC0000, 0x00E00000, 0x00E40000, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0x0243FC00, 0x00DC0000, 0x00E00000, 0x00E40000, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MP2_BASE = { { { { 0x00016400, 0x02400800, 0x00F40000, 0x00F80000, 0x00FC0000, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0x0240A000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE PCIE0_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0x00016A00, 0x02401000, 0x00440000, 0, 0 } },
+ { { 0x0001BC00, 0x0242D400, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0x02400C00, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0x02425800, 0, 0, 0, 0 } },
+ { { 0x00054000, 0x02425C00, 0, 0, 0, 0 } },
+ { { 0x00094000, 0x02426000, 0, 0, 0, 0 } },
+ { { 0x000D4000, 0x02426400, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE USB_BASE = { { { { 0x0242A800, 0x05B00000, 0, 0, 0, 0 } },
+ { { 0x0242AC00, 0x05B80000, 0, 0, 0, 0 } },
+ { { 0x0242B000, 0x05C00000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE VCN_BASE = { { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+
+
+#define ACP_BASE__INST0_SEG0 0x02403800
+#define ACP_BASE__INST0_SEG1 0x00480000
+#define ACP_BASE__INST0_SEG2 0
+#define ACP_BASE__INST0_SEG3 0
+#define ACP_BASE__INST0_SEG4 0
+#define ACP_BASE__INST0_SEG5 0
+
+#define ACP_BASE__INST1_SEG0 0
+#define ACP_BASE__INST1_SEG1 0
+#define ACP_BASE__INST1_SEG2 0
+#define ACP_BASE__INST1_SEG3 0
+#define ACP_BASE__INST1_SEG4 0
+#define ACP_BASE__INST1_SEG5 0
+
+#define ACP_BASE__INST2_SEG0 0
+#define ACP_BASE__INST2_SEG1 0
+#define ACP_BASE__INST2_SEG2 0
+#define ACP_BASE__INST2_SEG3 0
+#define ACP_BASE__INST2_SEG4 0
+#define ACP_BASE__INST2_SEG5 0
+
+#define ACP_BASE__INST3_SEG0 0
+#define ACP_BASE__INST3_SEG1 0
+#define ACP_BASE__INST3_SEG2 0
+#define ACP_BASE__INST3_SEG3 0
+#define ACP_BASE__INST3_SEG4 0
+#define ACP_BASE__INST3_SEG5 0
+
+#define ACP_BASE__INST4_SEG0 0
+#define ACP_BASE__INST4_SEG1 0
+#define ACP_BASE__INST4_SEG2 0
+#define ACP_BASE__INST4_SEG3 0
+#define ACP_BASE__INST4_SEG4 0
+#define ACP_BASE__INST4_SEG5 0
+
+#define ACP_BASE__INST5_SEG0 0
+#define ACP_BASE__INST5_SEG1 0
+#define ACP_BASE__INST5_SEG2 0
+#define ACP_BASE__INST5_SEG3 0
+#define ACP_BASE__INST5_SEG4 0
+#define ACP_BASE__INST5_SEG5 0
+
+#define ACP_BASE__INST6_SEG0 0
+#define ACP_BASE__INST6_SEG1 0
+#define ACP_BASE__INST6_SEG2 0
+#define ACP_BASE__INST6_SEG3 0
+#define ACP_BASE__INST6_SEG4 0
+#define ACP_BASE__INST6_SEG5 0
+
+#define ACP_BASE__INST7_SEG0 0
+#define ACP_BASE__INST7_SEG1 0
+#define ACP_BASE__INST7_SEG2 0
+#define ACP_BASE__INST7_SEG3 0
+#define ACP_BASE__INST7_SEG4 0
+#define ACP_BASE__INST7_SEG5 0
+
+#define ATHUB_BASE__INST0_SEG0 0x00000C00
+#define ATHUB_BASE__INST0_SEG1 0x00013300
+#define ATHUB_BASE__INST0_SEG2 0x02408C00
+#define ATHUB_BASE__INST0_SEG3 0
+#define ATHUB_BASE__INST0_SEG4 0
+#define ATHUB_BASE__INST0_SEG5 0
+
+#define ATHUB_BASE__INST1_SEG0 0
+#define ATHUB_BASE__INST1_SEG1 0
+#define ATHUB_BASE__INST1_SEG2 0
+#define ATHUB_BASE__INST1_SEG3 0
+#define ATHUB_BASE__INST1_SEG4 0
+#define ATHUB_BASE__INST1_SEG5 0
+
+#define ATHUB_BASE__INST2_SEG0 0
+#define ATHUB_BASE__INST2_SEG1 0
+#define ATHUB_BASE__INST2_SEG2 0
+#define ATHUB_BASE__INST2_SEG3 0
+#define ATHUB_BASE__INST2_SEG4 0
+#define ATHUB_BASE__INST2_SEG5 0
+
+#define ATHUB_BASE__INST3_SEG0 0
+#define ATHUB_BASE__INST3_SEG1 0
+#define ATHUB_BASE__INST3_SEG2 0
+#define ATHUB_BASE__INST3_SEG3 0
+#define ATHUB_BASE__INST3_SEG4 0
+#define ATHUB_BASE__INST3_SEG5 0
+
+#define ATHUB_BASE__INST4_SEG0 0
+#define ATHUB_BASE__INST4_SEG1 0
+#define ATHUB_BASE__INST4_SEG2 0
+#define ATHUB_BASE__INST4_SEG3 0
+#define ATHUB_BASE__INST4_SEG4 0
+#define ATHUB_BASE__INST4_SEG5 0
+
+#define ATHUB_BASE__INST5_SEG0 0
+#define ATHUB_BASE__INST5_SEG1 0
+#define ATHUB_BASE__INST5_SEG2 0
+#define ATHUB_BASE__INST5_SEG3 0
+#define ATHUB_BASE__INST5_SEG4 0
+#define ATHUB_BASE__INST5_SEG5 0
+
+#define ATHUB_BASE__INST6_SEG0 0
+#define ATHUB_BASE__INST6_SEG1 0
+#define ATHUB_BASE__INST6_SEG2 0
+#define ATHUB_BASE__INST6_SEG3 0
+#define ATHUB_BASE__INST6_SEG4 0
+#define ATHUB_BASE__INST6_SEG5 0
+
+#define ATHUB_BASE__INST7_SEG0 0
+#define ATHUB_BASE__INST7_SEG1 0
+#define ATHUB_BASE__INST7_SEG2 0
+#define ATHUB_BASE__INST7_SEG3 0
+#define ATHUB_BASE__INST7_SEG4 0
+#define ATHUB_BASE__INST7_SEG5 0
+
+#define CLK_BASE__INST0_SEG0 0x00016C00
+#define CLK_BASE__INST0_SEG1 0x02401800
+#define CLK_BASE__INST0_SEG2 0
+#define CLK_BASE__INST0_SEG3 0
+#define CLK_BASE__INST0_SEG4 0
+#define CLK_BASE__INST0_SEG5 0
+
+#define CLK_BASE__INST1_SEG0 0x00016E00
+#define CLK_BASE__INST1_SEG1 0x02401C00
+#define CLK_BASE__INST1_SEG2 0
+#define CLK_BASE__INST1_SEG3 0
+#define CLK_BASE__INST1_SEG4 0
+#define CLK_BASE__INST1_SEG5 0
+
+#define CLK_BASE__INST2_SEG0 0x00017000
+#define CLK_BASE__INST2_SEG1 0x02402000
+#define CLK_BASE__INST2_SEG2 0
+#define CLK_BASE__INST2_SEG3 0
+#define CLK_BASE__INST2_SEG4 0
+#define CLK_BASE__INST2_SEG5 0
+
+#define CLK_BASE__INST3_SEG0 0x00017200
+#define CLK_BASE__INST3_SEG1 0x02402400
+#define CLK_BASE__INST3_SEG2 0
+#define CLK_BASE__INST3_SEG3 0
+#define CLK_BASE__INST3_SEG4 0
+#define CLK_BASE__INST3_SEG5 0
+
+#define CLK_BASE__INST4_SEG0 0x0001B000
+#define CLK_BASE__INST4_SEG1 0x0242D800
+#define CLK_BASE__INST4_SEG2 0
+#define CLK_BASE__INST4_SEG3 0
+#define CLK_BASE__INST4_SEG4 0
+#define CLK_BASE__INST4_SEG5 0
+
+#define CLK_BASE__INST5_SEG0 0x0001B200
+#define CLK_BASE__INST5_SEG1 0x0242DC00
+#define CLK_BASE__INST5_SEG2 0
+#define CLK_BASE__INST5_SEG3 0
+#define CLK_BASE__INST5_SEG4 0
+#define CLK_BASE__INST5_SEG5 0
+
+#define CLK_BASE__INST6_SEG0 0x0001B400
+#define CLK_BASE__INST6_SEG1 0x0242E000
+#define CLK_BASE__INST6_SEG2 0
+#define CLK_BASE__INST6_SEG3 0
+#define CLK_BASE__INST6_SEG4 0
+#define CLK_BASE__INST6_SEG5 0
+
+#define CLK_BASE__INST7_SEG0 0x00017E00
+#define CLK_BASE__INST7_SEG1 0x0240BC00
+#define CLK_BASE__INST7_SEG2 0
+#define CLK_BASE__INST7_SEG3 0
+#define CLK_BASE__INST7_SEG4 0
+#define CLK_BASE__INST7_SEG5 0
+
+#define DF_BASE__INST0_SEG0 0x00007000
+#define DF_BASE__INST0_SEG1 0x0240B800
+#define DF_BASE__INST0_SEG2 0
+#define DF_BASE__INST0_SEG3 0
+#define DF_BASE__INST0_SEG4 0
+#define DF_BASE__INST0_SEG5 0
+
+#define DF_BASE__INST1_SEG0 0
+#define DF_BASE__INST1_SEG1 0
+#define DF_BASE__INST1_SEG2 0
+#define DF_BASE__INST1_SEG3 0
+#define DF_BASE__INST1_SEG4 0
+#define DF_BASE__INST1_SEG5 0
+
+#define DF_BASE__INST2_SEG0 0
+#define DF_BASE__INST2_SEG1 0
+#define DF_BASE__INST2_SEG2 0
+#define DF_BASE__INST2_SEG3 0
+#define DF_BASE__INST2_SEG4 0
+#define DF_BASE__INST2_SEG5 0
+
+#define DF_BASE__INST3_SEG0 0
+#define DF_BASE__INST3_SEG1 0
+#define DF_BASE__INST3_SEG2 0
+#define DF_BASE__INST3_SEG3 0
+#define DF_BASE__INST3_SEG4 0
+#define DF_BASE__INST3_SEG5 0
+
+#define DF_BASE__INST4_SEG0 0
+#define DF_BASE__INST4_SEG1 0
+#define DF_BASE__INST4_SEG2 0
+#define DF_BASE__INST4_SEG3 0
+#define DF_BASE__INST4_SEG4 0
+#define DF_BASE__INST4_SEG5 0
+
+#define DF_BASE__INST5_SEG0 0
+#define DF_BASE__INST5_SEG1 0
+#define DF_BASE__INST5_SEG2 0
+#define DF_BASE__INST5_SEG3 0
+#define DF_BASE__INST5_SEG4 0
+#define DF_BASE__INST5_SEG5 0
+
+#define DF_BASE__INST6_SEG0 0
+#define DF_BASE__INST6_SEG1 0
+#define DF_BASE__INST6_SEG2 0
+#define DF_BASE__INST6_SEG3 0
+#define DF_BASE__INST6_SEG4 0
+#define DF_BASE__INST6_SEG5 0
+
+#define DF_BASE__INST7_SEG0 0
+#define DF_BASE__INST7_SEG1 0
+#define DF_BASE__INST7_SEG2 0
+#define DF_BASE__INST7_SEG3 0
+#define DF_BASE__INST7_SEG4 0
+#define DF_BASE__INST7_SEG5 0
+
+#define DCN_BASE__INST0_SEG0 0x00000012
+#define DCN_BASE__INST0_SEG1 0x000000C0
+#define DCN_BASE__INST0_SEG2 0x000034C0
+#define DCN_BASE__INST0_SEG3 0x00009000
+#define DCN_BASE__INST0_SEG4 0x02403C00
+#define DCN_BASE__INST0_SEG5 0
+
+#define DCN_BASE__INST1_SEG0 0
+#define DCN_BASE__INST1_SEG1 0
+#define DCN_BASE__INST1_SEG2 0
+#define DCN_BASE__INST1_SEG3 0
+#define DCN_BASE__INST1_SEG4 0
+#define DCN_BASE__INST1_SEG5 0
+
+#define DCN_BASE__INST2_SEG0 0
+#define DCN_BASE__INST2_SEG1 0
+#define DCN_BASE__INST2_SEG2 0
+#define DCN_BASE__INST2_SEG3 0
+#define DCN_BASE__INST2_SEG4 0
+#define DCN_BASE__INST2_SEG5 0
+
+#define DCN_BASE__INST3_SEG0 0
+#define DCN_BASE__INST3_SEG1 0
+#define DCN_BASE__INST3_SEG2 0
+#define DCN_BASE__INST3_SEG3 0
+#define DCN_BASE__INST3_SEG4 0
+#define DCN_BASE__INST3_SEG5 0
+
+#define DCN_BASE__INST4_SEG0 0
+#define DCN_BASE__INST4_SEG1 0
+#define DCN_BASE__INST4_SEG2 0
+#define DCN_BASE__INST4_SEG3 0
+#define DCN_BASE__INST4_SEG4 0
+#define DCN_BASE__INST4_SEG5 0
+
+#define DCN_BASE__INST5_SEG0 0
+#define DCN_BASE__INST5_SEG1 0
+#define DCN_BASE__INST5_SEG2 0
+#define DCN_BASE__INST5_SEG3 0
+#define DCN_BASE__INST5_SEG4 0
+#define DCN_BASE__INST5_SEG5 0
+
+#define DCN_BASE__INST6_SEG0 0
+#define DCN_BASE__INST6_SEG1 0
+#define DCN_BASE__INST6_SEG2 0
+#define DCN_BASE__INST6_SEG3 0
+#define DCN_BASE__INST6_SEG4 0
+#define DCN_BASE__INST6_SEG5 0
+
+#define DCN_BASE__INST7_SEG0 0
+#define DCN_BASE__INST7_SEG1 0
+#define DCN_BASE__INST7_SEG2 0
+#define DCN_BASE__INST7_SEG3 0
+#define DCN_BASE__INST7_SEG4 0
+#define DCN_BASE__INST7_SEG5 0
+
+#define DPCS_BASE__INST0_SEG0 0x00000012
+#define DPCS_BASE__INST0_SEG1 0x000000C0
+#define DPCS_BASE__INST0_SEG2 0x000034C0
+#define DPCS_BASE__INST0_SEG3 0x00009000
+#define DPCS_BASE__INST0_SEG4 0x02403C00
+#define DPCS_BASE__INST0_SEG5 0
+
+#define DPCS_BASE__INST1_SEG0 0
+#define DPCS_BASE__INST1_SEG1 0
+#define DPCS_BASE__INST1_SEG2 0
+#define DPCS_BASE__INST1_SEG3 0
+#define DPCS_BASE__INST1_SEG4 0
+#define DPCS_BASE__INST1_SEG5 0
+
+#define DPCS_BASE__INST2_SEG0 0
+#define DPCS_BASE__INST2_SEG1 0
+#define DPCS_BASE__INST2_SEG2 0
+#define DPCS_BASE__INST2_SEG3 0
+#define DPCS_BASE__INST2_SEG4 0
+#define DPCS_BASE__INST2_SEG5 0
+
+#define DPCS_BASE__INST3_SEG0 0
+#define DPCS_BASE__INST3_SEG1 0
+#define DPCS_BASE__INST3_SEG2 0
+#define DPCS_BASE__INST3_SEG3 0
+#define DPCS_BASE__INST3_SEG4 0
+#define DPCS_BASE__INST3_SEG5 0
+
+#define DPCS_BASE__INST4_SEG0 0
+#define DPCS_BASE__INST4_SEG1 0
+#define DPCS_BASE__INST4_SEG2 0
+#define DPCS_BASE__INST4_SEG3 0
+#define DPCS_BASE__INST4_SEG4 0
+#define DPCS_BASE__INST4_SEG5 0
+
+#define DPCS_BASE__INST5_SEG0 0
+#define DPCS_BASE__INST5_SEG1 0
+#define DPCS_BASE__INST5_SEG2 0
+#define DPCS_BASE__INST5_SEG3 0
+#define DPCS_BASE__INST5_SEG4 0
+#define DPCS_BASE__INST5_SEG5 0
+
+#define DPCS_BASE__INST6_SEG0 0
+#define DPCS_BASE__INST6_SEG1 0
+#define DPCS_BASE__INST6_SEG2 0
+#define DPCS_BASE__INST6_SEG3 0
+#define DPCS_BASE__INST6_SEG4 0
+#define DPCS_BASE__INST6_SEG5 0
+
+#define DPCS_BASE__INST7_SEG0 0
+#define DPCS_BASE__INST7_SEG1 0
+#define DPCS_BASE__INST7_SEG2 0
+#define DPCS_BASE__INST7_SEG3 0
+#define DPCS_BASE__INST7_SEG4 0
+#define DPCS_BASE__INST7_SEG5 0
+
+#define FCH_BASE__INST0_SEG0 0x0240C000
+#define FCH_BASE__INST0_SEG1 0x00B40000
+#define FCH_BASE__INST0_SEG2 0x11000000
+#define FCH_BASE__INST0_SEG3 0
+#define FCH_BASE__INST0_SEG4 0
+#define FCH_BASE__INST0_SEG5 0
+
+#define FCH_BASE__INST1_SEG0 0
+#define FCH_BASE__INST1_SEG1 0
+#define FCH_BASE__INST1_SEG2 0
+#define FCH_BASE__INST1_SEG3 0
+#define FCH_BASE__INST1_SEG4 0
+#define FCH_BASE__INST1_SEG5 0
+
+#define FCH_BASE__INST2_SEG0 0
+#define FCH_BASE__INST2_SEG1 0
+#define FCH_BASE__INST2_SEG2 0
+#define FCH_BASE__INST2_SEG3 0
+#define FCH_BASE__INST2_SEG4 0
+#define FCH_BASE__INST2_SEG5 0
+
+#define FCH_BASE__INST3_SEG0 0
+#define FCH_BASE__INST3_SEG1 0
+#define FCH_BASE__INST3_SEG2 0
+#define FCH_BASE__INST3_SEG3 0
+#define FCH_BASE__INST3_SEG4 0
+#define FCH_BASE__INST3_SEG5 0
+
+#define FCH_BASE__INST4_SEG0 0
+#define FCH_BASE__INST4_SEG1 0
+#define FCH_BASE__INST4_SEG2 0
+#define FCH_BASE__INST4_SEG3 0
+#define FCH_BASE__INST4_SEG4 0
+#define FCH_BASE__INST4_SEG5 0
+
+#define FCH_BASE__INST5_SEG0 0
+#define FCH_BASE__INST5_SEG1 0
+#define FCH_BASE__INST5_SEG2 0
+#define FCH_BASE__INST5_SEG3 0
+#define FCH_BASE__INST5_SEG4 0
+#define FCH_BASE__INST5_SEG5 0
+
+#define FCH_BASE__INST6_SEG0 0
+#define FCH_BASE__INST6_SEG1 0
+#define FCH_BASE__INST6_SEG2 0
+#define FCH_BASE__INST6_SEG3 0
+#define FCH_BASE__INST6_SEG4 0
+#define FCH_BASE__INST6_SEG5 0
+
+#define FCH_BASE__INST7_SEG0 0
+#define FCH_BASE__INST7_SEG1 0
+#define FCH_BASE__INST7_SEG2 0
+#define FCH_BASE__INST7_SEG3 0
+#define FCH_BASE__INST7_SEG4 0
+#define FCH_BASE__INST7_SEG5 0
+
+#define FUSE_BASE__INST0_SEG0 0x00017400
+#define FUSE_BASE__INST0_SEG1 0x02401400
+#define FUSE_BASE__INST0_SEG2 0
+#define FUSE_BASE__INST0_SEG3 0
+#define FUSE_BASE__INST0_SEG4 0
+#define FUSE_BASE__INST0_SEG5 0
+
+#define FUSE_BASE__INST1_SEG0 0
+#define FUSE_BASE__INST1_SEG1 0
+#define FUSE_BASE__INST1_SEG2 0
+#define FUSE_BASE__INST1_SEG3 0
+#define FUSE_BASE__INST1_SEG4 0
+#define FUSE_BASE__INST1_SEG5 0
+
+#define FUSE_BASE__INST2_SEG0 0
+#define FUSE_BASE__INST2_SEG1 0
+#define FUSE_BASE__INST2_SEG2 0
+#define FUSE_BASE__INST2_SEG3 0
+#define FUSE_BASE__INST2_SEG4 0
+#define FUSE_BASE__INST2_SEG5 0
+
+#define FUSE_BASE__INST3_SEG0 0
+#define FUSE_BASE__INST3_SEG1 0
+#define FUSE_BASE__INST3_SEG2 0
+#define FUSE_BASE__INST3_SEG3 0
+#define FUSE_BASE__INST3_SEG4 0
+#define FUSE_BASE__INST3_SEG5 0
+
+#define FUSE_BASE__INST4_SEG0 0
+#define FUSE_BASE__INST4_SEG1 0
+#define FUSE_BASE__INST4_SEG2 0
+#define FUSE_BASE__INST4_SEG3 0
+#define FUSE_BASE__INST4_SEG4 0
+#define FUSE_BASE__INST4_SEG5 0
+
+#define FUSE_BASE__INST5_SEG0 0
+#define FUSE_BASE__INST5_SEG1 0
+#define FUSE_BASE__INST5_SEG2 0
+#define FUSE_BASE__INST5_SEG3 0
+#define FUSE_BASE__INST5_SEG4 0
+#define FUSE_BASE__INST5_SEG5 0
+
+#define FUSE_BASE__INST6_SEG0 0
+#define FUSE_BASE__INST6_SEG1 0
+#define FUSE_BASE__INST6_SEG2 0
+#define FUSE_BASE__INST6_SEG3 0
+#define FUSE_BASE__INST6_SEG4 0
+#define FUSE_BASE__INST6_SEG5 0
+
+#define FUSE_BASE__INST7_SEG0 0
+#define FUSE_BASE__INST7_SEG1 0
+#define FUSE_BASE__INST7_SEG2 0
+#define FUSE_BASE__INST7_SEG3 0
+#define FUSE_BASE__INST7_SEG4 0
+#define FUSE_BASE__INST7_SEG5 0
+
+#define GC_BASE__INST0_SEG0 0x00001260
+#define GC_BASE__INST0_SEG1 0x0000A000
+#define GC_BASE__INST0_SEG2 0x02402C00
+#define GC_BASE__INST0_SEG3 0
+#define GC_BASE__INST0_SEG4 0
+#define GC_BASE__INST0_SEG5 0
+
+#define GC_BASE__INST1_SEG0 0
+#define GC_BASE__INST1_SEG1 0
+#define GC_BASE__INST1_SEG2 0
+#define GC_BASE__INST1_SEG3 0
+#define GC_BASE__INST1_SEG4 0
+#define GC_BASE__INST1_SEG5 0
+
+#define GC_BASE__INST2_SEG0 0
+#define GC_BASE__INST2_SEG1 0
+#define GC_BASE__INST2_SEG2 0
+#define GC_BASE__INST2_SEG3 0
+#define GC_BASE__INST2_SEG4 0
+#define GC_BASE__INST2_SEG5 0
+
+#define GC_BASE__INST3_SEG0 0
+#define GC_BASE__INST3_SEG1 0
+#define GC_BASE__INST3_SEG2 0
+#define GC_BASE__INST3_SEG3 0
+#define GC_BASE__INST3_SEG4 0
+#define GC_BASE__INST3_SEG5 0
+
+#define GC_BASE__INST4_SEG0 0
+#define GC_BASE__INST4_SEG1 0
+#define GC_BASE__INST4_SEG2 0
+#define GC_BASE__INST4_SEG3 0
+#define GC_BASE__INST4_SEG4 0
+#define GC_BASE__INST4_SEG5 0
+
+#define GC_BASE__INST5_SEG0 0
+#define GC_BASE__INST5_SEG1 0
+#define GC_BASE__INST5_SEG2 0
+#define GC_BASE__INST5_SEG3 0
+#define GC_BASE__INST5_SEG4 0
+#define GC_BASE__INST5_SEG5 0
+
+#define GC_BASE__INST6_SEG0 0
+#define GC_BASE__INST6_SEG1 0
+#define GC_BASE__INST6_SEG2 0
+#define GC_BASE__INST6_SEG3 0
+#define GC_BASE__INST6_SEG4 0
+#define GC_BASE__INST6_SEG5 0
+
+#define GC_BASE__INST7_SEG0 0
+#define GC_BASE__INST7_SEG1 0
+#define GC_BASE__INST7_SEG2 0
+#define GC_BASE__INST7_SEG3 0
+#define GC_BASE__INST7_SEG4 0
+#define GC_BASE__INST7_SEG5 0
+
+#define HDP_BASE__INST0_SEG0 0x00000F20
+#define HDP_BASE__INST0_SEG1 0x0240A400
+#define HDP_BASE__INST0_SEG2 0
+#define HDP_BASE__INST0_SEG3 0
+#define HDP_BASE__INST0_SEG4 0
+#define HDP_BASE__INST0_SEG5 0
+
+#define HDP_BASE__INST1_SEG0 0
+#define HDP_BASE__INST1_SEG1 0
+#define HDP_BASE__INST1_SEG2 0
+#define HDP_BASE__INST1_SEG3 0
+#define HDP_BASE__INST1_SEG4 0
+#define HDP_BASE__INST1_SEG5 0
+
+#define HDP_BASE__INST2_SEG0 0
+#define HDP_BASE__INST2_SEG1 0
+#define HDP_BASE__INST2_SEG2 0
+#define HDP_BASE__INST2_SEG3 0
+#define HDP_BASE__INST2_SEG4 0
+#define HDP_BASE__INST2_SEG5 0
+
+#define HDP_BASE__INST3_SEG0 0
+#define HDP_BASE__INST3_SEG1 0
+#define HDP_BASE__INST3_SEG2 0
+#define HDP_BASE__INST3_SEG3 0
+#define HDP_BASE__INST3_SEG4 0
+#define HDP_BASE__INST3_SEG5 0
+
+#define HDP_BASE__INST4_SEG0 0
+#define HDP_BASE__INST4_SEG1 0
+#define HDP_BASE__INST4_SEG2 0
+#define HDP_BASE__INST4_SEG3 0
+#define HDP_BASE__INST4_SEG4 0
+#define HDP_BASE__INST4_SEG5 0
+
+#define HDP_BASE__INST5_SEG0 0
+#define HDP_BASE__INST5_SEG1 0
+#define HDP_BASE__INST5_SEG2 0
+#define HDP_BASE__INST5_SEG3 0
+#define HDP_BASE__INST5_SEG4 0
+#define HDP_BASE__INST5_SEG5 0
+
+#define HDP_BASE__INST6_SEG0 0
+#define HDP_BASE__INST6_SEG1 0
+#define HDP_BASE__INST6_SEG2 0
+#define HDP_BASE__INST6_SEG3 0
+#define HDP_BASE__INST6_SEG4 0
+#define HDP_BASE__INST6_SEG5 0
+
+#define HDP_BASE__INST7_SEG0 0
+#define HDP_BASE__INST7_SEG1 0
+#define HDP_BASE__INST7_SEG2 0
+#define HDP_BASE__INST7_SEG3 0
+#define HDP_BASE__INST7_SEG4 0
+#define HDP_BASE__INST7_SEG5 0
+
+#define ISP_BASE__INST0_SEG0 0x00018000
+#define ISP_BASE__INST0_SEG1 0x0240B000
+#define ISP_BASE__INST0_SEG2 0
+#define ISP_BASE__INST0_SEG3 0
+#define ISP_BASE__INST0_SEG4 0
+#define ISP_BASE__INST0_SEG5 0
+
+#define ISP_BASE__INST1_SEG0 0
+#define ISP_BASE__INST1_SEG1 0
+#define ISP_BASE__INST1_SEG2 0
+#define ISP_BASE__INST1_SEG3 0
+#define ISP_BASE__INST1_SEG4 0
+#define ISP_BASE__INST1_SEG5 0
+
+#define ISP_BASE__INST2_SEG0 0
+#define ISP_BASE__INST2_SEG1 0
+#define ISP_BASE__INST2_SEG2 0
+#define ISP_BASE__INST2_SEG3 0
+#define ISP_BASE__INST2_SEG4 0
+#define ISP_BASE__INST2_SEG5 0
+
+#define ISP_BASE__INST3_SEG0 0
+#define ISP_BASE__INST3_SEG1 0
+#define ISP_BASE__INST3_SEG2 0
+#define ISP_BASE__INST3_SEG3 0
+#define ISP_BASE__INST3_SEG4 0
+#define ISP_BASE__INST3_SEG5 0
+
+#define ISP_BASE__INST4_SEG0 0
+#define ISP_BASE__INST4_SEG1 0
+#define ISP_BASE__INST4_SEG2 0
+#define ISP_BASE__INST4_SEG3 0
+#define ISP_BASE__INST4_SEG4 0
+#define ISP_BASE__INST4_SEG5 0
+
+#define ISP_BASE__INST5_SEG0 0
+#define ISP_BASE__INST5_SEG1 0
+#define ISP_BASE__INST5_SEG2 0
+#define ISP_BASE__INST5_SEG3 0
+#define ISP_BASE__INST5_SEG4 0
+#define ISP_BASE__INST5_SEG5 0
+
+#define ISP_BASE__INST6_SEG0 0
+#define ISP_BASE__INST6_SEG1 0
+#define ISP_BASE__INST6_SEG2 0
+#define ISP_BASE__INST6_SEG3 0
+#define ISP_BASE__INST6_SEG4 0
+#define ISP_BASE__INST6_SEG5 0
+
+#define ISP_BASE__INST7_SEG0 0
+#define ISP_BASE__INST7_SEG1 0
+#define ISP_BASE__INST7_SEG2 0
+#define ISP_BASE__INST7_SEG3 0
+#define ISP_BASE__INST7_SEG4 0
+#define ISP_BASE__INST7_SEG5 0
+
+#define MMHUB_BASE__INST0_SEG0 0x00013200
+#define MMHUB_BASE__INST0_SEG1 0x0001A000
+#define MMHUB_BASE__INST0_SEG2 0x02408800
+#define MMHUB_BASE__INST0_SEG3 0
+#define MMHUB_BASE__INST0_SEG4 0
+#define MMHUB_BASE__INST0_SEG5 0
+
+#define MMHUB_BASE__INST1_SEG0 0
+#define MMHUB_BASE__INST1_SEG1 0
+#define MMHUB_BASE__INST1_SEG2 0
+#define MMHUB_BASE__INST1_SEG3 0
+#define MMHUB_BASE__INST1_SEG4 0
+#define MMHUB_BASE__INST1_SEG5 0
+
+#define MMHUB_BASE__INST2_SEG0 0
+#define MMHUB_BASE__INST2_SEG1 0
+#define MMHUB_BASE__INST2_SEG2 0
+#define MMHUB_BASE__INST2_SEG3 0
+#define MMHUB_BASE__INST2_SEG4 0
+#define MMHUB_BASE__INST2_SEG5 0
+
+#define MMHUB_BASE__INST3_SEG0 0
+#define MMHUB_BASE__INST3_SEG1 0
+#define MMHUB_BASE__INST3_SEG2 0
+#define MMHUB_BASE__INST3_SEG3 0
+#define MMHUB_BASE__INST3_SEG4 0
+#define MMHUB_BASE__INST3_SEG5 0
+
+#define MMHUB_BASE__INST4_SEG0 0
+#define MMHUB_BASE__INST4_SEG1 0
+#define MMHUB_BASE__INST4_SEG2 0
+#define MMHUB_BASE__INST4_SEG3 0
+#define MMHUB_BASE__INST4_SEG4 0
+#define MMHUB_BASE__INST4_SEG5 0
+
+#define MMHUB_BASE__INST5_SEG0 0
+#define MMHUB_BASE__INST5_SEG1 0
+#define MMHUB_BASE__INST5_SEG2 0
+#define MMHUB_BASE__INST5_SEG3 0
+#define MMHUB_BASE__INST5_SEG4 0
+#define MMHUB_BASE__INST5_SEG5 0
+
+#define MMHUB_BASE__INST6_SEG0 0
+#define MMHUB_BASE__INST6_SEG1 0
+#define MMHUB_BASE__INST6_SEG2 0
+#define MMHUB_BASE__INST6_SEG3 0
+#define MMHUB_BASE__INST6_SEG4 0
+#define MMHUB_BASE__INST6_SEG5 0
+
+#define MMHUB_BASE__INST7_SEG0 0
+#define MMHUB_BASE__INST7_SEG1 0
+#define MMHUB_BASE__INST7_SEG2 0
+#define MMHUB_BASE__INST7_SEG3 0
+#define MMHUB_BASE__INST7_SEG4 0
+#define MMHUB_BASE__INST7_SEG5 0
+
+#define MP0_BASE__INST0_SEG0 0x00016000
+#define MP0_BASE__INST0_SEG1 0x0243FC00
+#define MP0_BASE__INST0_SEG2 0x00DC0000
+#define MP0_BASE__INST0_SEG3 0x00E00000
+#define MP0_BASE__INST0_SEG4 0x00E40000
+#define MP0_BASE__INST0_SEG5 0
+
+#define MP0_BASE__INST1_SEG0 0
+#define MP0_BASE__INST1_SEG1 0
+#define MP0_BASE__INST1_SEG2 0
+#define MP0_BASE__INST1_SEG3 0
+#define MP0_BASE__INST1_SEG4 0
+#define MP0_BASE__INST1_SEG5 0
+
+#define MP0_BASE__INST2_SEG0 0
+#define MP0_BASE__INST2_SEG1 0
+#define MP0_BASE__INST2_SEG2 0
+#define MP0_BASE__INST2_SEG3 0
+#define MP0_BASE__INST2_SEG4 0
+#define MP0_BASE__INST2_SEG5 0
+
+#define MP0_BASE__INST3_SEG0 0
+#define MP0_BASE__INST3_SEG1 0
+#define MP0_BASE__INST3_SEG2 0
+#define MP0_BASE__INST3_SEG3 0
+#define MP0_BASE__INST3_SEG4 0
+#define MP0_BASE__INST3_SEG5 0
+
+#define MP0_BASE__INST4_SEG0 0
+#define MP0_BASE__INST4_SEG1 0
+#define MP0_BASE__INST4_SEG2 0
+#define MP0_BASE__INST4_SEG3 0
+#define MP0_BASE__INST4_SEG4 0
+#define MP0_BASE__INST4_SEG5 0
+
+#define MP0_BASE__INST5_SEG0 0
+#define MP0_BASE__INST5_SEG1 0
+#define MP0_BASE__INST5_SEG2 0
+#define MP0_BASE__INST5_SEG3 0
+#define MP0_BASE__INST5_SEG4 0
+#define MP0_BASE__INST5_SEG5 0
+
+#define MP0_BASE__INST6_SEG0 0
+#define MP0_BASE__INST6_SEG1 0
+#define MP0_BASE__INST6_SEG2 0
+#define MP0_BASE__INST6_SEG3 0
+#define MP0_BASE__INST6_SEG4 0
+#define MP0_BASE__INST6_SEG5 0
+
+#define MP0_BASE__INST7_SEG0 0
+#define MP0_BASE__INST7_SEG1 0
+#define MP0_BASE__INST7_SEG2 0
+#define MP0_BASE__INST7_SEG3 0
+#define MP0_BASE__INST7_SEG4 0
+#define MP0_BASE__INST7_SEG5 0
+
+#define MP1_BASE__INST0_SEG0 0x00016000
+#define MP1_BASE__INST0_SEG1 0x0243FC00
+#define MP1_BASE__INST0_SEG2 0x00DC0000
+#define MP1_BASE__INST0_SEG3 0x00E00000
+#define MP1_BASE__INST0_SEG4 0x00E40000
+#define MP1_BASE__INST0_SEG5 0
+
+#define MP1_BASE__INST1_SEG0 0
+#define MP1_BASE__INST1_SEG1 0
+#define MP1_BASE__INST1_SEG2 0
+#define MP1_BASE__INST1_SEG3 0
+#define MP1_BASE__INST1_SEG4 0
+#define MP1_BASE__INST1_SEG5 0
+
+#define MP1_BASE__INST2_SEG0 0
+#define MP1_BASE__INST2_SEG1 0
+#define MP1_BASE__INST2_SEG2 0
+#define MP1_BASE__INST2_SEG3 0
+#define MP1_BASE__INST2_SEG4 0
+#define MP1_BASE__INST2_SEG5 0
+
+#define MP1_BASE__INST3_SEG0 0
+#define MP1_BASE__INST3_SEG1 0
+#define MP1_BASE__INST3_SEG2 0
+#define MP1_BASE__INST3_SEG3 0
+#define MP1_BASE__INST3_SEG4 0
+#define MP1_BASE__INST3_SEG5 0
+
+#define MP1_BASE__INST4_SEG0 0
+#define MP1_BASE__INST4_SEG1 0
+#define MP1_BASE__INST4_SEG2 0
+#define MP1_BASE__INST4_SEG3 0
+#define MP1_BASE__INST4_SEG4 0
+#define MP1_BASE__INST4_SEG5 0
+
+#define MP1_BASE__INST5_SEG0 0
+#define MP1_BASE__INST5_SEG1 0
+#define MP1_BASE__INST5_SEG2 0
+#define MP1_BASE__INST5_SEG3 0
+#define MP1_BASE__INST5_SEG4 0
+#define MP1_BASE__INST5_SEG5 0
+
+#define MP1_BASE__INST6_SEG0 0
+#define MP1_BASE__INST6_SEG1 0
+#define MP1_BASE__INST6_SEG2 0
+#define MP1_BASE__INST6_SEG3 0
+#define MP1_BASE__INST6_SEG4 0
+#define MP1_BASE__INST6_SEG5 0
+
+#define MP1_BASE__INST7_SEG0 0
+#define MP1_BASE__INST7_SEG1 0
+#define MP1_BASE__INST7_SEG2 0
+#define MP1_BASE__INST7_SEG3 0
+#define MP1_BASE__INST7_SEG4 0
+#define MP1_BASE__INST7_SEG5 0
+
+#define MP2_BASE__INST0_SEG0 0x00016400
+#define MP2_BASE__INST0_SEG1 0x02400800
+#define MP2_BASE__INST0_SEG2 0x00F40000
+#define MP2_BASE__INST0_SEG3 0x00F80000
+#define MP2_BASE__INST0_SEG4 0x00FC0000
+#define MP2_BASE__INST0_SEG5 0
+
+#define MP2_BASE__INST1_SEG0 0
+#define MP2_BASE__INST1_SEG1 0
+#define MP2_BASE__INST1_SEG2 0
+#define MP2_BASE__INST1_SEG3 0
+#define MP2_BASE__INST1_SEG4 0
+#define MP2_BASE__INST1_SEG5 0
+
+#define MP2_BASE__INST2_SEG0 0
+#define MP2_BASE__INST2_SEG1 0
+#define MP2_BASE__INST2_SEG2 0
+#define MP2_BASE__INST2_SEG3 0
+#define MP2_BASE__INST2_SEG4 0
+#define MP2_BASE__INST2_SEG5 0
+
+#define MP2_BASE__INST3_SEG0 0
+#define MP2_BASE__INST3_SEG1 0
+#define MP2_BASE__INST3_SEG2 0
+#define MP2_BASE__INST3_SEG3 0
+#define MP2_BASE__INST3_SEG4 0
+#define MP2_BASE__INST3_SEG5 0
+
+#define MP2_BASE__INST4_SEG0 0
+#define MP2_BASE__INST4_SEG1 0
+#define MP2_BASE__INST4_SEG2 0
+#define MP2_BASE__INST4_SEG3 0
+#define MP2_BASE__INST4_SEG4 0
+#define MP2_BASE__INST4_SEG5 0
+
+#define MP2_BASE__INST5_SEG0 0
+#define MP2_BASE__INST5_SEG1 0
+#define MP2_BASE__INST5_SEG2 0
+#define MP2_BASE__INST5_SEG3 0
+#define MP2_BASE__INST5_SEG4 0
+#define MP2_BASE__INST5_SEG5 0
+
+#define MP2_BASE__INST6_SEG0 0
+#define MP2_BASE__INST6_SEG1 0
+#define MP2_BASE__INST6_SEG2 0
+#define MP2_BASE__INST6_SEG3 0
+#define MP2_BASE__INST6_SEG4 0
+#define MP2_BASE__INST6_SEG5 0
+
+#define MP2_BASE__INST7_SEG0 0
+#define MP2_BASE__INST7_SEG1 0
+#define MP2_BASE__INST7_SEG2 0
+#define MP2_BASE__INST7_SEG3 0
+#define MP2_BASE__INST7_SEG4 0
+#define MP2_BASE__INST7_SEG5 0
+
+#define NBIO_BASE__INST0_SEG0 0x00000000
+#define NBIO_BASE__INST0_SEG1 0x00000014
+#define NBIO_BASE__INST0_SEG2 0x00000D20
+#define NBIO_BASE__INST0_SEG3 0x00010400
+#define NBIO_BASE__INST0_SEG4 0x0241B000
+#define NBIO_BASE__INST0_SEG5 0x04040000
+
+#define NBIO_BASE__INST1_SEG0 0
+#define NBIO_BASE__INST1_SEG1 0
+#define NBIO_BASE__INST1_SEG2 0
+#define NBIO_BASE__INST1_SEG3 0
+#define NBIO_BASE__INST1_SEG4 0
+#define NBIO_BASE__INST1_SEG5 0
+
+#define NBIO_BASE__INST2_SEG0 0
+#define NBIO_BASE__INST2_SEG1 0
+#define NBIO_BASE__INST2_SEG2 0
+#define NBIO_BASE__INST2_SEG3 0
+#define NBIO_BASE__INST2_SEG4 0
+#define NBIO_BASE__INST2_SEG5 0
+
+#define NBIO_BASE__INST3_SEG0 0
+#define NBIO_BASE__INST3_SEG1 0
+#define NBIO_BASE__INST3_SEG2 0
+#define NBIO_BASE__INST3_SEG3 0
+#define NBIO_BASE__INST3_SEG4 0
+#define NBIO_BASE__INST3_SEG5 0
+
+#define NBIO_BASE__INST4_SEG0 0
+#define NBIO_BASE__INST4_SEG1 0
+#define NBIO_BASE__INST4_SEG2 0
+#define NBIO_BASE__INST4_SEG3 0
+#define NBIO_BASE__INST4_SEG4 0
+#define NBIO_BASE__INST4_SEG5 0
+
+#define NBIO_BASE__INST5_SEG0 0
+#define NBIO_BASE__INST5_SEG1 0
+#define NBIO_BASE__INST5_SEG2 0
+#define NBIO_BASE__INST5_SEG3 0
+#define NBIO_BASE__INST5_SEG4 0
+#define NBIO_BASE__INST5_SEG5 0
+
+#define NBIO_BASE__INST6_SEG0 0
+#define NBIO_BASE__INST6_SEG1 0
+#define NBIO_BASE__INST6_SEG2 0
+#define NBIO_BASE__INST6_SEG3 0
+#define NBIO_BASE__INST6_SEG4 0
+#define NBIO_BASE__INST6_SEG5 0
+
+#define NBIO_BASE__INST7_SEG0 0
+#define NBIO_BASE__INST7_SEG1 0
+#define NBIO_BASE__INST7_SEG2 0
+#define NBIO_BASE__INST7_SEG3 0
+#define NBIO_BASE__INST7_SEG4 0
+#define NBIO_BASE__INST7_SEG5 0
+
+#define OSSSYS_BASE__INST0_SEG0 0x000010A0
+#define OSSSYS_BASE__INST0_SEG1 0x0240A000
+#define OSSSYS_BASE__INST0_SEG2 0
+#define OSSSYS_BASE__INST0_SEG3 0
+#define OSSSYS_BASE__INST0_SEG4 0
+#define OSSSYS_BASE__INST0_SEG5 0
+
+#define OSSSYS_BASE__INST1_SEG0 0
+#define OSSSYS_BASE__INST1_SEG1 0
+#define OSSSYS_BASE__INST1_SEG2 0
+#define OSSSYS_BASE__INST1_SEG3 0
+#define OSSSYS_BASE__INST1_SEG4 0
+#define OSSSYS_BASE__INST1_SEG5 0
+
+#define OSSSYS_BASE__INST2_SEG0 0
+#define OSSSYS_BASE__INST2_SEG1 0
+#define OSSSYS_BASE__INST2_SEG2 0
+#define OSSSYS_BASE__INST2_SEG3 0
+#define OSSSYS_BASE__INST2_SEG4 0
+#define OSSSYS_BASE__INST2_SEG5 0
+
+#define OSSSYS_BASE__INST3_SEG0 0
+#define OSSSYS_BASE__INST3_SEG1 0
+#define OSSSYS_BASE__INST3_SEG2 0
+#define OSSSYS_BASE__INST3_SEG3 0
+#define OSSSYS_BASE__INST3_SEG4 0
+#define OSSSYS_BASE__INST3_SEG5 0
+
+#define OSSSYS_BASE__INST4_SEG0 0
+#define OSSSYS_BASE__INST4_SEG1 0
+#define OSSSYS_BASE__INST4_SEG2 0
+#define OSSSYS_BASE__INST4_SEG3 0
+#define OSSSYS_BASE__INST4_SEG4 0
+#define OSSSYS_BASE__INST4_SEG5 0
+
+#define OSSSYS_BASE__INST5_SEG0 0
+#define OSSSYS_BASE__INST5_SEG1 0
+#define OSSSYS_BASE__INST5_SEG2 0
+#define OSSSYS_BASE__INST5_SEG3 0
+#define OSSSYS_BASE__INST5_SEG4 0
+#define OSSSYS_BASE__INST5_SEG5 0
+
+#define OSSSYS_BASE__INST6_SEG0 0
+#define OSSSYS_BASE__INST6_SEG1 0
+#define OSSSYS_BASE__INST6_SEG2 0
+#define OSSSYS_BASE__INST6_SEG3 0
+#define OSSSYS_BASE__INST6_SEG4 0
+#define OSSSYS_BASE__INST6_SEG5 0
+
+#define OSSSYS_BASE__INST7_SEG0 0
+#define OSSSYS_BASE__INST7_SEG1 0
+#define OSSSYS_BASE__INST7_SEG2 0
+#define OSSSYS_BASE__INST7_SEG3 0
+#define OSSSYS_BASE__INST7_SEG4 0
+#define OSSSYS_BASE__INST7_SEG5 0
+
+#define PCIE0_BASE__INST0_SEG0 0x00000000
+#define PCIE0_BASE__INST0_SEG1 0x00000014
+#define PCIE0_BASE__INST0_SEG2 0x00000D20
+#define PCIE0_BASE__INST0_SEG3 0x00010400
+#define PCIE0_BASE__INST0_SEG4 0x0241B000
+#define PCIE0_BASE__INST0_SEG5 0x04040000
+
+#define PCIE0_BASE__INST1_SEG0 0
+#define PCIE0_BASE__INST1_SEG1 0
+#define PCIE0_BASE__INST1_SEG2 0
+#define PCIE0_BASE__INST1_SEG3 0
+#define PCIE0_BASE__INST1_SEG4 0
+#define PCIE0_BASE__INST1_SEG5 0
+
+#define PCIE0_BASE__INST2_SEG0 0
+#define PCIE0_BASE__INST2_SEG1 0
+#define PCIE0_BASE__INST2_SEG2 0
+#define PCIE0_BASE__INST2_SEG3 0
+#define PCIE0_BASE__INST2_SEG4 0
+#define PCIE0_BASE__INST2_SEG5 0
+
+#define PCIE0_BASE__INST3_SEG0 0
+#define PCIE0_BASE__INST3_SEG1 0
+#define PCIE0_BASE__INST3_SEG2 0
+#define PCIE0_BASE__INST3_SEG3 0
+#define PCIE0_BASE__INST3_SEG4 0
+#define PCIE0_BASE__INST3_SEG5 0
+
+#define PCIE0_BASE__INST4_SEG0 0
+#define PCIE0_BASE__INST4_SEG1 0
+#define PCIE0_BASE__INST4_SEG2 0
+#define PCIE0_BASE__INST4_SEG3 0
+#define PCIE0_BASE__INST4_SEG4 0
+#define PCIE0_BASE__INST4_SEG5 0
+
+#define PCIE0_BASE__INST5_SEG0 0
+#define PCIE0_BASE__INST5_SEG1 0
+#define PCIE0_BASE__INST5_SEG2 0
+#define PCIE0_BASE__INST5_SEG3 0
+#define PCIE0_BASE__INST5_SEG4 0
+#define PCIE0_BASE__INST5_SEG5 0
+
+#define PCIE0_BASE__INST6_SEG0 0
+#define PCIE0_BASE__INST6_SEG1 0
+#define PCIE0_BASE__INST6_SEG2 0
+#define PCIE0_BASE__INST6_SEG3 0
+#define PCIE0_BASE__INST6_SEG4 0
+#define PCIE0_BASE__INST6_SEG5 0
+
+#define PCIE0_BASE__INST7_SEG0 0
+#define PCIE0_BASE__INST7_SEG1 0
+#define PCIE0_BASE__INST7_SEG2 0
+#define PCIE0_BASE__INST7_SEG3 0
+#define PCIE0_BASE__INST7_SEG4 0
+#define PCIE0_BASE__INST7_SEG5 0
+
+#define SMUIO_BASE__INST0_SEG0 0x00016800
+#define SMUIO_BASE__INST0_SEG1 0x00016A00
+#define SMUIO_BASE__INST0_SEG2 0x02401000
+#define SMUIO_BASE__INST0_SEG3 0x00440000
+#define SMUIO_BASE__INST0_SEG4 0
+#define SMUIO_BASE__INST0_SEG5 0
+
+#define SMUIO_BASE__INST1_SEG0 0x0001BC00
+#define SMUIO_BASE__INST1_SEG1 0x0242D400
+#define SMUIO_BASE__INST1_SEG2 0
+#define SMUIO_BASE__INST1_SEG3 0
+#define SMUIO_BASE__INST1_SEG4 0
+#define SMUIO_BASE__INST1_SEG5 0
+
+#define SMUIO_BASE__INST2_SEG0 0
+#define SMUIO_BASE__INST2_SEG1 0
+#define SMUIO_BASE__INST2_SEG2 0
+#define SMUIO_BASE__INST2_SEG3 0
+#define SMUIO_BASE__INST2_SEG4 0
+#define SMUIO_BASE__INST2_SEG5 0
+
+#define SMUIO_BASE__INST3_SEG0 0
+#define SMUIO_BASE__INST3_SEG1 0
+#define SMUIO_BASE__INST3_SEG2 0
+#define SMUIO_BASE__INST3_SEG3 0
+#define SMUIO_BASE__INST3_SEG4 0
+#define SMUIO_BASE__INST3_SEG5 0
+
+#define SMUIO_BASE__INST4_SEG0 0
+#define SMUIO_BASE__INST4_SEG1 0
+#define SMUIO_BASE__INST4_SEG2 0
+#define SMUIO_BASE__INST4_SEG3 0
+#define SMUIO_BASE__INST4_SEG4 0
+#define SMUIO_BASE__INST4_SEG5 0
+
+#define SMUIO_BASE__INST5_SEG0 0
+#define SMUIO_BASE__INST5_SEG1 0
+#define SMUIO_BASE__INST5_SEG2 0
+#define SMUIO_BASE__INST5_SEG3 0
+#define SMUIO_BASE__INST5_SEG4 0
+#define SMUIO_BASE__INST5_SEG5 0
+
+#define SMUIO_BASE__INST6_SEG0 0
+#define SMUIO_BASE__INST6_SEG1 0
+#define SMUIO_BASE__INST6_SEG2 0
+#define SMUIO_BASE__INST6_SEG3 0
+#define SMUIO_BASE__INST6_SEG4 0
+#define SMUIO_BASE__INST6_SEG5 0
+
+#define SMUIO_BASE__INST7_SEG0 0
+#define SMUIO_BASE__INST7_SEG1 0
+#define SMUIO_BASE__INST7_SEG2 0
+#define SMUIO_BASE__INST7_SEG3 0
+#define SMUIO_BASE__INST7_SEG4 0
+#define SMUIO_BASE__INST7_SEG5 0
+
+#define THM_BASE__INST0_SEG0 0x00016600
+#define THM_BASE__INST0_SEG1 0x02400C00
+#define THM_BASE__INST0_SEG2 0
+#define THM_BASE__INST0_SEG3 0
+#define THM_BASE__INST0_SEG4 0
+#define THM_BASE__INST0_SEG5 0
+
+#define THM_BASE__INST1_SEG0 0
+#define THM_BASE__INST1_SEG1 0
+#define THM_BASE__INST1_SEG2 0
+#define THM_BASE__INST1_SEG3 0
+#define THM_BASE__INST1_SEG4 0
+#define THM_BASE__INST1_SEG5 0
+
+#define THM_BASE__INST2_SEG0 0
+#define THM_BASE__INST2_SEG1 0
+#define THM_BASE__INST2_SEG2 0
+#define THM_BASE__INST2_SEG3 0
+#define THM_BASE__INST2_SEG4 0
+#define THM_BASE__INST2_SEG5 0
+
+#define THM_BASE__INST3_SEG0 0
+#define THM_BASE__INST3_SEG1 0
+#define THM_BASE__INST3_SEG2 0
+#define THM_BASE__INST3_SEG3 0
+#define THM_BASE__INST3_SEG4 0
+#define THM_BASE__INST3_SEG5 0
+
+#define THM_BASE__INST4_SEG0 0
+#define THM_BASE__INST4_SEG1 0
+#define THM_BASE__INST4_SEG2 0
+#define THM_BASE__INST4_SEG3 0
+#define THM_BASE__INST4_SEG4 0
+#define THM_BASE__INST4_SEG5 0
+
+#define THM_BASE__INST5_SEG0 0
+#define THM_BASE__INST5_SEG1 0
+#define THM_BASE__INST5_SEG2 0
+#define THM_BASE__INST5_SEG3 0
+#define THM_BASE__INST5_SEG4 0
+#define THM_BASE__INST5_SEG5 0
+
+#define THM_BASE__INST6_SEG0 0
+#define THM_BASE__INST6_SEG1 0
+#define THM_BASE__INST6_SEG2 0
+#define THM_BASE__INST6_SEG3 0
+#define THM_BASE__INST6_SEG4 0
+#define THM_BASE__INST6_SEG5 0
+
+#define THM_BASE__INST7_SEG0 0
+#define THM_BASE__INST7_SEG1 0
+#define THM_BASE__INST7_SEG2 0
+#define THM_BASE__INST7_SEG3 0
+#define THM_BASE__INST7_SEG4 0
+#define THM_BASE__INST7_SEG5 0
+
+#define UMC_BASE__INST0_SEG0 0x00014000
+#define UMC_BASE__INST0_SEG1 0x02425800
+#define UMC_BASE__INST0_SEG2 0
+#define UMC_BASE__INST0_SEG3 0
+#define UMC_BASE__INST0_SEG4 0
+#define UMC_BASE__INST0_SEG5 0
+
+#define UMC_BASE__INST1_SEG0 0x00054000
+#define UMC_BASE__INST1_SEG1 0x02425C00
+#define UMC_BASE__INST1_SEG2 0
+#define UMC_BASE__INST1_SEG3 0
+#define UMC_BASE__INST1_SEG4 0
+#define UMC_BASE__INST1_SEG5 0
+
+#define UMC_BASE__INST2_SEG0 0x00094000
+#define UMC_BASE__INST2_SEG1 0x02426000
+#define UMC_BASE__INST2_SEG2 0
+#define UMC_BASE__INST2_SEG3 0
+#define UMC_BASE__INST2_SEG4 0
+#define UMC_BASE__INST2_SEG5 0
+
+#define UMC_BASE__INST3_SEG0 0x000D4000
+#define UMC_BASE__INST3_SEG1 0x02426400
+#define UMC_BASE__INST3_SEG2 0
+#define UMC_BASE__INST3_SEG3 0
+#define UMC_BASE__INST3_SEG4 0
+#define UMC_BASE__INST3_SEG5 0
+
+#define UMC_BASE__INST4_SEG0 0
+#define UMC_BASE__INST4_SEG1 0
+#define UMC_BASE__INST4_SEG2 0
+#define UMC_BASE__INST4_SEG3 0
+#define UMC_BASE__INST4_SEG4 0
+#define UMC_BASE__INST4_SEG5 0
+
+#define UMC_BASE__INST5_SEG0 0
+#define UMC_BASE__INST5_SEG1 0
+#define UMC_BASE__INST5_SEG2 0
+#define UMC_BASE__INST5_SEG3 0
+#define UMC_BASE__INST5_SEG4 0
+#define UMC_BASE__INST5_SEG5 0
+
+#define UMC_BASE__INST6_SEG0 0
+#define UMC_BASE__INST6_SEG1 0
+#define UMC_BASE__INST6_SEG2 0
+#define UMC_BASE__INST6_SEG3 0
+#define UMC_BASE__INST6_SEG4 0
+#define UMC_BASE__INST6_SEG5 0
+
+#define UMC_BASE__INST7_SEG0 0
+#define UMC_BASE__INST7_SEG1 0
+#define UMC_BASE__INST7_SEG2 0
+#define UMC_BASE__INST7_SEG3 0
+#define UMC_BASE__INST7_SEG4 0
+#define UMC_BASE__INST7_SEG5 0
+
+#define USB_BASE__INST0_SEG0 0x0242A800
+#define USB_BASE__INST0_SEG1 0x05B00000
+#define USB_BASE__INST0_SEG2 0
+#define USB_BASE__INST0_SEG3 0
+#define USB_BASE__INST0_SEG4 0
+#define USB_BASE__INST0_SEG5 0
+
+#define USB_BASE__INST1_SEG0 0x0242AC00
+#define USB_BASE__INST1_SEG1 0x05B80000
+#define USB_BASE__INST1_SEG2 0
+#define USB_BASE__INST1_SEG3 0
+#define USB_BASE__INST1_SEG4 0
+#define USB_BASE__INST1_SEG5 0
+
+#define USB_BASE__INST2_SEG0 0x0242B000
+#define USB_BASE__INST2_SEG1 0x05C00000
+#define USB_BASE__INST2_SEG2 0
+#define USB_BASE__INST2_SEG3 0
+#define USB_BASE__INST2_SEG4 0
+#define USB_BASE__INST2_SEG5 0
+
+#define USB_BASE__INST3_SEG0 0
+#define USB_BASE__INST3_SEG1 0
+#define USB_BASE__INST3_SEG2 0
+#define USB_BASE__INST3_SEG3 0
+#define USB_BASE__INST3_SEG4 0
+#define USB_BASE__INST3_SEG5 0
+
+#define USB_BASE__INST4_SEG0 0
+#define USB_BASE__INST4_SEG1 0
+#define USB_BASE__INST4_SEG2 0
+#define USB_BASE__INST4_SEG3 0
+#define USB_BASE__INST4_SEG4 0
+#define USB_BASE__INST4_SEG5 0
+
+#define USB_BASE__INST5_SEG0 0
+#define USB_BASE__INST5_SEG1 0
+#define USB_BASE__INST5_SEG2 0
+#define USB_BASE__INST5_SEG3 0
+#define USB_BASE__INST5_SEG4 0
+#define USB_BASE__INST5_SEG5 0
+
+#define USB_BASE__INST6_SEG0 0
+#define USB_BASE__INST6_SEG1 0
+#define USB_BASE__INST6_SEG2 0
+#define USB_BASE__INST6_SEG3 0
+#define USB_BASE__INST6_SEG4 0
+#define USB_BASE__INST6_SEG5 0
+
+#define USB_BASE__INST7_SEG0 0
+#define USB_BASE__INST7_SEG1 0
+#define USB_BASE__INST7_SEG2 0
+#define USB_BASE__INST7_SEG3 0
+#define USB_BASE__INST7_SEG4 0
+#define USB_BASE__INST7_SEG5 0
+
+#define VCN_BASE__INST0_SEG0 0x00007800
+#define VCN_BASE__INST0_SEG1 0x00007E00
+#define VCN_BASE__INST0_SEG2 0x02403000
+#define VCN_BASE__INST0_SEG3 0
+#define VCN_BASE__INST0_SEG4 0
+#define VCN_BASE__INST0_SEG5 0
+
+#define VCN_BASE__INST1_SEG0 0
+#define VCN_BASE__INST1_SEG1 0
+#define VCN_BASE__INST1_SEG2 0
+#define VCN_BASE__INST1_SEG3 0
+#define VCN_BASE__INST1_SEG4 0
+#define VCN_BASE__INST1_SEG5 0
+
+#define VCN_BASE__INST2_SEG0 0
+#define VCN_BASE__INST2_SEG1 0
+#define VCN_BASE__INST2_SEG2 0
+#define VCN_BASE__INST2_SEG3 0
+#define VCN_BASE__INST2_SEG4 0
+#define VCN_BASE__INST2_SEG5 0
+
+#define VCN_BASE__INST3_SEG0 0
+#define VCN_BASE__INST3_SEG1 0
+#define VCN_BASE__INST3_SEG2 0
+#define VCN_BASE__INST3_SEG3 0
+#define VCN_BASE__INST3_SEG4 0
+#define VCN_BASE__INST3_SEG5 0
+
+#define VCN_BASE__INST4_SEG0 0
+#define VCN_BASE__INST4_SEG1 0
+#define VCN_BASE__INST4_SEG2 0
+#define VCN_BASE__INST4_SEG3 0
+#define VCN_BASE__INST4_SEG4 0
+#define VCN_BASE__INST4_SEG5 0
+
+#define VCN_BASE__INST5_SEG0 0
+#define VCN_BASE__INST5_SEG1 0
+#define VCN_BASE__INST5_SEG2 0
+#define VCN_BASE__INST5_SEG3 0
+#define VCN_BASE__INST5_SEG4 0
+#define VCN_BASE__INST5_SEG5 0
+
+#define VCN_BASE__INST6_SEG0 0
+#define VCN_BASE__INST6_SEG1 0
+#define VCN_BASE__INST6_SEG2 0
+#define VCN_BASE__INST6_SEG3 0
+#define VCN_BASE__INST6_SEG4 0
+#define VCN_BASE__INST6_SEG5 0
+
+#define VCN_BASE__INST7_SEG0 0
+#define VCN_BASE__INST7_SEG1 0
+#define VCN_BASE__INST7_SEG2 0
+#define VCN_BASE__INST7_SEG3 0
+#define VCN_BASE__INST7_SEG4 0
+#define VCN_BASE__INST7_SEG5 0
+
+#endif
--
2.25.4
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^ permalink raw reply related [flat|nested] 9+ messages in thread
end of thread, other threads:[~2020-09-29 20:15 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-09-29 15:27 [PATCH 05/45] drm/amdgpu: add vangogh_reg_base_init function for van gogh Alex Deucher
2020-09-29 15:27 ` [PATCH 06/45] drm/amdgpu: add nv common ip block support " Alex Deucher
2020-09-29 15:27 ` [PATCH 09/45] drm/amdgpu: use gpu virtual address for interrupt packet write space for vangogh Alex Deucher
2020-09-29 15:27 ` [PATCH 36/45] drm/amdgpu: add TOC firmware support for apu (v3) Alex Deucher
-- strict thread matches above, loose matches on Subject: below --
2020-09-25 20:09 [PATCH 00/45] Add support for vangoh Alex Deucher
2020-09-25 20:09 ` [PATCH 05/45] drm/amdgpu: add vangogh_reg_base_init function for van gogh Alex Deucher
2020-09-28 20:48 ` Luben Tuikov
2020-09-29 14:57 ` Alex Deucher
2020-09-29 18:59 ` Luben Tuikov
2020-09-29 20:15 ` Alex Deucher
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