* [PATCH 2/4] drm/amd/amdgpu: Prepare implementation to support reporting of CU usage
@ 2020-09-29 17:59 Ramesh Errabolu
2020-09-29 19:57 ` Alex Deucher
2020-09-29 21:47 ` Kasiviswanathan, Harish
0 siblings, 2 replies; 5+ messages in thread
From: Ramesh Errabolu @ 2020-09-29 17:59 UTC (permalink / raw)
To: amd-gfx; +Cc: Ramesh Errabolu
[Why]
Allow user to know number of compute units (CU) that are in use at any
given moment.
[How]
Read registers of SQ that give number of waves that are in flight
of various queues. Use this information to determine number of CU's
in use.
Signed-off-by: Ramesh Errabolu <Ramesh.Errabolu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 +++--
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h | 3 +++
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 346d8288f6ab..6959aebae6d4 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -49,6 +49,7 @@
#include "amdgpu_ras.h"
#include "gfx_v9_4.h"
+#include "gfx_v9_0.h"
#include "asic_reg/pwr/pwr_10_0_offset.h"
#include "asic_reg/pwr/pwr_10_0_sh_mask.h"
@@ -788,7 +789,6 @@ static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev);
static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
struct amdgpu_cu_info *cu_info);
static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
-static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring);
static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring);
static int gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev,
@@ -2397,7 +2397,8 @@ static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev)
/* TODO */
}
-static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance)
+void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num,
+ u32 instance)
{
u32 data;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h
index 407472031daa..dfe8d4841f58 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h
@@ -26,4 +26,7 @@
extern const struct amdgpu_ip_block_version gfx_v9_0_ip_block;
+void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num,
+ u32 instance);
+
#endif
--
2.27.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH 2/4] drm/amd/amdgpu: Prepare implementation to support reporting of CU usage
2020-09-29 17:59 [PATCH 2/4] drm/amd/amdgpu: Prepare implementation to support reporting of CU usage Ramesh Errabolu
@ 2020-09-29 19:57 ` Alex Deucher
2020-09-29 21:47 ` Kasiviswanathan, Harish
1 sibling, 0 replies; 5+ messages in thread
From: Alex Deucher @ 2020-09-29 19:57 UTC (permalink / raw)
To: Ramesh Errabolu; +Cc: amd-gfx list
On Tue, Sep 29, 2020 at 2:00 PM Ramesh Errabolu <Ramesh.Errabolu@amd.com> wrote:
>
> [Why]
> Allow user to know number of compute units (CU) that are in use at any
> given moment.
>
> [How]
> Read registers of SQ that give number of waves that are in flight
> of various queues. Use this information to determine number of CU's
> in use.
>
> Signed-off-by: Ramesh Errabolu <Ramesh.Errabolu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 +++--
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h | 3 +++
> 2 files changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 346d8288f6ab..6959aebae6d4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -49,6 +49,7 @@
> #include "amdgpu_ras.h"
>
> #include "gfx_v9_4.h"
> +#include "gfx_v9_0.h"
>
> #include "asic_reg/pwr/pwr_10_0_offset.h"
> #include "asic_reg/pwr/pwr_10_0_sh_mask.h"
> @@ -788,7 +789,6 @@ static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev);
> static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
> struct amdgpu_cu_info *cu_info);
> static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
> -static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
> static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring);
> static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring);
> static int gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev,
> @@ -2397,7 +2397,8 @@ static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev)
> /* TODO */
> }
>
> -static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance)
> +void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num,
> + u32 instance)
> {
> u32 data;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h
> index 407472031daa..dfe8d4841f58 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h
> @@ -26,4 +26,7 @@
>
> extern const struct amdgpu_ip_block_version gfx_v9_0_ip_block;
>
> +void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num,
> + u32 instance);
> +
> #endif
> --
> 2.27.0
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread* RE: [PATCH 2/4] drm/amd/amdgpu: Prepare implementation to support reporting of CU usage
2020-09-29 17:59 [PATCH 2/4] drm/amd/amdgpu: Prepare implementation to support reporting of CU usage Ramesh Errabolu
2020-09-29 19:57 ` Alex Deucher
@ 2020-09-29 21:47 ` Kasiviswanathan, Harish
1 sibling, 0 replies; 5+ messages in thread
From: Kasiviswanathan, Harish @ 2020-09-29 21:47 UTC (permalink / raw)
To: Errabolu, Ramesh, amd-gfx; +Cc: Errabolu, Ramesh
[AMD Official Use Only - Internal Distribution Only]
Minor correction in the commit message. I think you are planning to report CU occupancy and not CU usage.
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Ramesh Errabolu
Sent: Tuesday, September 29, 2020 2:00 PM
To: amd-gfx@lists.freedesktop.org
Cc: Errabolu, Ramesh <Ramesh.Errabolu@amd.com>
Subject: [PATCH 2/4] drm/amd/amdgpu: Prepare implementation to support reporting of CU usage
[Why]
Allow user to know number of compute units (CU) that are in use at any given moment.
[How]
Read registers of SQ that give number of waves that are in flight of various queues. Use this information to determine number of CU's in use.
Signed-off-by: Ramesh Errabolu <Ramesh.Errabolu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 +++-- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h | 3 +++
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 346d8288f6ab..6959aebae6d4 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -49,6 +49,7 @@
#include "amdgpu_ras.h"
#include "gfx_v9_4.h"
+#include "gfx_v9_0.h"
#include "asic_reg/pwr/pwr_10_0_offset.h"
#include "asic_reg/pwr/pwr_10_0_sh_mask.h"
@@ -788,7 +789,6 @@ static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev); static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
struct amdgpu_cu_info *cu_info); static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev); -static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance); static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring); static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring); static int gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev, @@ -2397,7 +2397,8 @@ static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev)
/* TODO */
}
-static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance)
+void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num,
+ u32 instance)
{
u32 data;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h
index 407472031daa..dfe8d4841f58 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h
@@ -26,4 +26,7 @@
extern const struct amdgpu_ip_block_version gfx_v9_0_ip_block;
+void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num,
+ u32 instance);
+
#endif
--
2.27.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Charish.kasiviswanathan%40amd.com%7Cd26021125f48446b565508d864a185d5%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637369992488452463&sdata=Of8rMVEjoNIo1Nds2TfAh1BcuxeKCLGZDxe53bbat0U%3D&reserved=0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/4] drm/amd/amdgpu: Prepare implementation to support reporting of CU usage
@ 2020-09-29 17:25 Ramesh Errabolu
2020-09-29 17:45 ` Alex Deucher
0 siblings, 1 reply; 5+ messages in thread
From: Ramesh Errabolu @ 2020-09-29 17:25 UTC (permalink / raw)
To: amd-gfx; +Cc: Ramesh Errabolu
[Why]
Allow user to know number of compute units (CU) that are in use at any
given moment.
[How]
Read registers of SQ that give number of waves that are in flight
of various queues. Use this information to determine number of CU's
in use.
Signed-off-by: Ramesh Errabolu <Ramesh.Errabolu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 9 +++++----
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h | 3 +++
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 346d8288f6ab..b1ab9fd02db7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -49,6 +49,7 @@
#include "amdgpu_ras.h"
#include "gfx_v9_4.h"
+#include "gfx_v9_0.h"
#include "asic_reg/pwr/pwr_10_0_offset.h"
#include "asic_reg/pwr/pwr_10_0_sh_mask.h"
@@ -786,9 +787,8 @@ static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev);
static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev);
static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
- struct amdgpu_cu_info *cu_info);
+ struct amdgpu_cu_info *cu_info);
static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
-static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring);
static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring);
static int gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev,
@@ -2397,7 +2397,8 @@ static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev)
/* TODO */
}
-static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance)
+void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num,
+ u32 instance)
{
u32 data;
@@ -6924,7 +6925,7 @@ static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev)
}
static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
- struct amdgpu_cu_info *cu_info)
+ struct amdgpu_cu_info *cu_info)
{
int i, j, k, counter, active_cu_number = 0;
u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h
index 407472031daa..dfe8d4841f58 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h
@@ -26,4 +26,7 @@
extern const struct amdgpu_ip_block_version gfx_v9_0_ip_block;
+void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num,
+ u32 instance);
+
#endif
--
2.27.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH 2/4] drm/amd/amdgpu: Prepare implementation to support reporting of CU usage
2020-09-29 17:25 Ramesh Errabolu
@ 2020-09-29 17:45 ` Alex Deucher
0 siblings, 0 replies; 5+ messages in thread
From: Alex Deucher @ 2020-09-29 17:45 UTC (permalink / raw)
To: Ramesh Errabolu; +Cc: amd-gfx list
On Tue, Sep 29, 2020 at 1:26 PM Ramesh Errabolu <Ramesh.Errabolu@amd.com> wrote:
>
> [Why]
> Allow user to know number of compute units (CU) that are in use at any
> given moment.
>
> [How]
> Read registers of SQ that give number of waves that are in flight
> of various queues. Use this information to determine number of CU's
> in use.
>
> Signed-off-by: Ramesh Errabolu <Ramesh.Errabolu@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 9 +++++----
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h | 3 +++
> 2 files changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 346d8288f6ab..b1ab9fd02db7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -49,6 +49,7 @@
> #include "amdgpu_ras.h"
>
> #include "gfx_v9_4.h"
> +#include "gfx_v9_0.h"
>
> #include "asic_reg/pwr/pwr_10_0_offset.h"
> #include "asic_reg/pwr/pwr_10_0_sh_mask.h"
> @@ -786,9 +787,8 @@ static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
> static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev);
> static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev);
> static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
> - struct amdgpu_cu_info *cu_info);
> + struct amdgpu_cu_info *cu_info);
unrelated whitespace change. Please drop.
> static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
> -static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
> static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring);
> static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring);
> static int gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev,
> @@ -2397,7 +2397,8 @@ static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev)
> /* TODO */
> }
>
> -static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance)
> +void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num,
> + u32 instance)
> {
> u32 data;
>
> @@ -6924,7 +6925,7 @@ static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev)
> }
>
> static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
> - struct amdgpu_cu_info *cu_info)
> + struct amdgpu_cu_info *cu_info)
Unrelated whitespace change. Please drop.
Alex
> {
> int i, j, k, counter, active_cu_number = 0;
> u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h
> index 407472031daa..dfe8d4841f58 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h
> @@ -26,4 +26,7 @@
>
> extern const struct amdgpu_ip_block_version gfx_v9_0_ip_block;
>
> +void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num,
> + u32 instance);
> +
> #endif
> --
> 2.27.0
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2020-09-29 21:47 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-09-29 17:59 [PATCH 2/4] drm/amd/amdgpu: Prepare implementation to support reporting of CU usage Ramesh Errabolu
2020-09-29 19:57 ` Alex Deucher
2020-09-29 21:47 ` Kasiviswanathan, Harish
-- strict thread matches above, loose matches on Subject: below --
2020-09-29 17:25 Ramesh Errabolu
2020-09-29 17:45 ` Alex Deucher
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.