From: frank.chang@sifive.com
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>,
Frank Chang <frank.chang@sifive.com>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Richard Henderson <richard.henderson@linaro.org>,
Alistair Francis <Alistair.Francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [RFC v5 63/68] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert
Date: Wed, 30 Sep 2020 03:04:38 +0800 [thread overview]
Message-ID: <20200929190448.31116-64-frank.chang@sifive.com> (raw)
In-Reply-To: <20200929190448.31116-1-frank.chang@sifive.com>
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 22 +++++-----
target/riscv/insn32.decode | 15 ++++---
target/riscv/insn_trans/trans_rvv.c.inc | 58 +++++++++++++++++++++----
target/riscv/vector_helper.c | 45 ++++++++++---------
4 files changed, 96 insertions(+), 44 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 32edc77858..e5510be6f8 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -988,16 +988,18 @@ DEF_HELPER_5(vfwcvt_f_x_v_w, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfwcvt_f_f_v_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfwcvt_f_f_v_w, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_xu_f_v_h, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_xu_f_v_w, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_x_f_v_h, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_x_f_v_w, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_f_xu_v_h, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_f_xu_v_w, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_f_x_v_h, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_f_x_v_w, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_f_f_v_h, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_f_f_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_xu_f_w_b, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_xu_f_w_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_xu_f_w_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_x_f_w_b, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_x_f_w_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_x_f_w_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_f_xu_w_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_f_xu_w_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_f_x_w_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_f_x_w_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_f_f_w_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_f_f_w_w, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vredsum_vs_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 6253628b9c..51b4268fa7 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -575,11 +575,16 @@ vfwcvt_f_x_v 010010 . ..... 01011 001 ..... 1010111 @r2_vm
vfwcvt_f_f_v 010010 . ..... 01100 001 ..... 1010111 @r2_vm
vfwcvt_rtz_xu_f_v 010010 . ..... 01110 001 ..... 1010111 @r2_vm
vfwcvt_rtz_x_f_v 010010 . ..... 01111 001 ..... 1010111 @r2_vm
-vfncvt_xu_f_v 100010 . ..... 10000 001 ..... 1010111 @r2_vm
-vfncvt_x_f_v 100010 . ..... 10001 001 ..... 1010111 @r2_vm
-vfncvt_f_xu_v 100010 . ..... 10010 001 ..... 1010111 @r2_vm
-vfncvt_f_x_v 100010 . ..... 10011 001 ..... 1010111 @r2_vm
-vfncvt_f_f_v 100010 . ..... 10100 001 ..... 1010111 @r2_vm
+
+vfncvt_xu_f_w 010010 . ..... 10000 001 ..... 1010111 @r2_vm
+vfncvt_x_f_w 010010 . ..... 10001 001 ..... 1010111 @r2_vm
+vfncvt_f_xu_w 010010 . ..... 10010 001 ..... 1010111 @r2_vm
+vfncvt_f_x_w 010010 . ..... 10011 001 ..... 1010111 @r2_vm
+vfncvt_f_f_w 010010 . ..... 10100 001 ..... 1010111 @r2_vm
+vfncvt_rod_f_f_w 010010 . ..... 10101 001 ..... 1010111 @r2_vm
+vfncvt_rtz_xu_f_w 010010 . ..... 10110 001 ..... 1010111 @r2_vm
+vfncvt_rtz_x_f_w 010010 . ..... 10111 001 ..... 1010111 @r2_vm
+
vredsum_vs 000000 . ..... ..... 010 ..... 1010111 @r_vm
vredand_vs 000001 . ..... ..... 010 ..... 1010111 @r_vm
vredor_vs 000010 . ..... ..... 010 ..... 1010111 @r_vm
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 32e94c496c..db6c3d9bdf 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2873,17 +2873,17 @@ static bool opfv_narrow_check(DisasContext *s, arg_rmr *a)
vext_check_sd(s, a->rd, a->rs2, a->vm);
}
-#define GEN_OPFV_NARROW_TRANS(NAME) \
+#define GEN_OPFV_NARROW_TRANS(NAME, HELPER, FRM) \
static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
{ \
if (opfv_narrow_check(s, a)) { \
uint32_t data = 0; \
static gen_helper_gvec_3_ptr * const fns[2] = { \
- gen_helper_##NAME##_h, \
- gen_helper_##NAME##_w, \
+ gen_helper_##HELPER##_h, \
+ gen_helper_##HELPER##_w, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, RISCV_FRM_DYN); \
+ gen_set_rm(s, FRM); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -2898,11 +2898,51 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
return false; \
}
-GEN_OPFV_NARROW_TRANS(vfncvt_xu_f_v)
-GEN_OPFV_NARROW_TRANS(vfncvt_x_f_v)
-GEN_OPFV_NARROW_TRANS(vfncvt_f_xu_v)
-GEN_OPFV_NARROW_TRANS(vfncvt_f_x_v)
-GEN_OPFV_NARROW_TRANS(vfncvt_f_f_v)
+GEN_OPFV_NARROW_TRANS(vfncvt_f_xu_w, vfncvt_f_xu_w, RISCV_FRM_DYN)
+GEN_OPFV_NARROW_TRANS(vfncvt_f_x_w, vfncvt_f_x_w, RISCV_FRM_DYN)
+GEN_OPFV_NARROW_TRANS(vfncvt_f_f_w, vfncvt_f_f_w, RISCV_FRM_DYN)
+/* Reuse the helper function from vfncvt.f.f.w */
+GEN_OPFV_NARROW_TRANS(vfncvt_rod_f_f_w, vfncvt_f_f_w, RISCV_FRM_ROD)
+
+static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a)
+{
+ return require_rvv(s) &&
+ require_scale_rvf(s) &&
+ vext_check_isa_ill(s) &&
+ /* OPFV narrowing instructions ignore vs1 check */
+ vext_check_sd(s, a->rd, a->rs2, a->vm);
+}
+
+#define GEN_OPXFV_NARROW_TRANS(NAME, HELPER, FRM) \
+static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
+{ \
+ if (opxfv_narrow_check(s, a)) { \
+ uint32_t data = 0; \
+ static gen_helper_gvec_3_ptr * const fns[3] = { \
+ gen_helper_##HELPER##_b, \
+ gen_helper_##HELPER##_h, \
+ gen_helper_##HELPER##_w, \
+ }; \
+ TCGLabel *over = gen_new_label(); \
+ gen_set_rm(s, FRM); \
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
+ \
+ data = FIELD_DP32(data, VDATA, VM, a->vm); \
+ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
+ vreg_ofs(s, a->rs2), cpu_env, 0, \
+ s->vlen / 8, data, fns[s->sew]); \
+ mark_vs_dirty(s); \
+ gen_set_label(over); \
+ return true; \
+ } \
+ return false; \
+}
+
+GEN_OPXFV_NARROW_TRANS(vfncvt_xu_f_w, vfncvt_xu_f_w, RISCV_FRM_DYN)
+GEN_OPXFV_NARROW_TRANS(vfncvt_x_f_w, vfncvt_x_f_w, RISCV_FRM_DYN)
+/* Reuse the helper functions from vfncvt.xu.f.w and vfncvt.x.f.w */
+GEN_OPXFV_NARROW_TRANS(vfncvt_rtz_xu_f_w, vfncvt_xu_f_w, RISCV_FRM_RTZ)
+GEN_OPXFV_NARROW_TRANS(vfncvt_rtz_x_f_w, vfncvt_x_f_w, RISCV_FRM_RTZ)
/*
*** Vector Reduction Operations
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index e8de460b29..8d389af4b7 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4029,31 +4029,36 @@ GEN_VEXT_V_ENV(vfwcvt_f_f_v_w, 4, 8)
/* Narrowing Floating-Point/Integer Type-Convert Instructions */
/* (TD, T2, TX2) */
+#define NOP_UU_B uint8_t, uint16_t, uint32_t
#define NOP_UU_H uint16_t, uint32_t, uint32_t
#define NOP_UU_W uint32_t, uint64_t, uint64_t
/* vfncvt.xu.f.v vd, vs2, vm # Convert float to unsigned integer. */
-RVVCALL(OPFVV1, vfncvt_xu_f_v_h, NOP_UU_H, H2, H4, float32_to_uint16)
-RVVCALL(OPFVV1, vfncvt_xu_f_v_w, NOP_UU_W, H4, H8, float64_to_uint32)
-GEN_VEXT_V_ENV(vfncvt_xu_f_v_h, 2, 2)
-GEN_VEXT_V_ENV(vfncvt_xu_f_v_w, 4, 4)
+RVVCALL(OPFVV1, vfncvt_xu_f_w_b, NOP_UU_B, H1, H2, float16_to_uint8)
+RVVCALL(OPFVV1, vfncvt_xu_f_w_h, NOP_UU_H, H2, H4, float32_to_uint16)
+RVVCALL(OPFVV1, vfncvt_xu_f_w_w, NOP_UU_W, H4, H8, float64_to_uint32)
+GEN_VEXT_V_ENV(vfncvt_xu_f_w_b, 1, 1)
+GEN_VEXT_V_ENV(vfncvt_xu_f_w_h, 2, 2)
+GEN_VEXT_V_ENV(vfncvt_xu_f_w_w, 4, 4)
/* vfncvt.x.f.v vd, vs2, vm # Convert double-width float to signed integer. */
-RVVCALL(OPFVV1, vfncvt_x_f_v_h, NOP_UU_H, H2, H4, float32_to_int16)
-RVVCALL(OPFVV1, vfncvt_x_f_v_w, NOP_UU_W, H4, H8, float64_to_int32)
-GEN_VEXT_V_ENV(vfncvt_x_f_v_h, 2, 2)
-GEN_VEXT_V_ENV(vfncvt_x_f_v_w, 4, 4)
+RVVCALL(OPFVV1, vfncvt_x_f_w_b, NOP_UU_B, H1, H2, float16_to_int8)
+RVVCALL(OPFVV1, vfncvt_x_f_w_h, NOP_UU_H, H2, H4, float32_to_int16)
+RVVCALL(OPFVV1, vfncvt_x_f_w_w, NOP_UU_W, H4, H8, float64_to_int32)
+GEN_VEXT_V_ENV(vfncvt_x_f_w_b, 1, 1)
+GEN_VEXT_V_ENV(vfncvt_x_f_w_h, 2, 2)
+GEN_VEXT_V_ENV(vfncvt_x_f_w_w, 4, 4)
/* vfncvt.f.xu.v vd, vs2, vm # Convert double-width unsigned integer to float */
-RVVCALL(OPFVV1, vfncvt_f_xu_v_h, NOP_UU_H, H2, H4, uint32_to_float16)
-RVVCALL(OPFVV1, vfncvt_f_xu_v_w, NOP_UU_W, H4, H8, uint64_to_float32)
-GEN_VEXT_V_ENV(vfncvt_f_xu_v_h, 2, 2)
-GEN_VEXT_V_ENV(vfncvt_f_xu_v_w, 4, 4)
+RVVCALL(OPFVV1, vfncvt_f_xu_w_h, NOP_UU_H, H2, H4, uint32_to_float16)
+RVVCALL(OPFVV1, vfncvt_f_xu_w_w, NOP_UU_W, H4, H8, uint64_to_float32)
+GEN_VEXT_V_ENV(vfncvt_f_xu_w_h, 2, 2)
+GEN_VEXT_V_ENV(vfncvt_f_xu_w_w, 4, 4)
/* vfncvt.f.x.v vd, vs2, vm # Convert double-width integer to float. */
-RVVCALL(OPFVV1, vfncvt_f_x_v_h, NOP_UU_H, H2, H4, int32_to_float16)
-RVVCALL(OPFVV1, vfncvt_f_x_v_w, NOP_UU_W, H4, H8, int64_to_float32)
-GEN_VEXT_V_ENV(vfncvt_f_x_v_h, 2, 2)
-GEN_VEXT_V_ENV(vfncvt_f_x_v_w, 4, 4)
+RVVCALL(OPFVV1, vfncvt_f_x_w_h, NOP_UU_H, H2, H4, int32_to_float16)
+RVVCALL(OPFVV1, vfncvt_f_x_w_w, NOP_UU_W, H4, H8, int64_to_float32)
+GEN_VEXT_V_ENV(vfncvt_f_x_w_h, 2, 2)
+GEN_VEXT_V_ENV(vfncvt_f_x_w_w, 4, 4)
/* vfncvt.f.f.v vd, vs2, vm # Convert double float to single-width float. */
static uint16_t vfncvtffv16(uint32_t a, float_status *s)
@@ -4061,10 +4066,10 @@ static uint16_t vfncvtffv16(uint32_t a, float_status *s)
return float32_to_float16(a, true, s);
}
-RVVCALL(OPFVV1, vfncvt_f_f_v_h, NOP_UU_H, H2, H4, vfncvtffv16)
-RVVCALL(OPFVV1, vfncvt_f_f_v_w, NOP_UU_W, H4, H8, float64_to_float32)
-GEN_VEXT_V_ENV(vfncvt_f_f_v_h, 2, 2)
-GEN_VEXT_V_ENV(vfncvt_f_f_v_w, 4, 4)
+RVVCALL(OPFVV1, vfncvt_f_f_w_h, NOP_UU_H, H2, H4, vfncvtffv16)
+RVVCALL(OPFVV1, vfncvt_f_f_w_w, NOP_UU_W, H4, H8, float64_to_float32)
+GEN_VEXT_V_ENV(vfncvt_f_f_w_h, 2, 2)
+GEN_VEXT_V_ENV(vfncvt_f_f_w_w, 4, 4)
/*
*** Vector Reduction Operations
--
2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: frank.chang@sifive.com
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Frank Chang <frank.chang@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Richard Henderson <richard.henderson@linaro.org>,
LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [RFC v5 63/68] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert
Date: Wed, 30 Sep 2020 03:04:38 +0800 [thread overview]
Message-ID: <20200929190448.31116-64-frank.chang@sifive.com> (raw)
In-Reply-To: <20200929190448.31116-1-frank.chang@sifive.com>
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 22 +++++-----
target/riscv/insn32.decode | 15 ++++---
target/riscv/insn_trans/trans_rvv.c.inc | 58 +++++++++++++++++++++----
target/riscv/vector_helper.c | 45 ++++++++++---------
4 files changed, 96 insertions(+), 44 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 32edc77858..e5510be6f8 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -988,16 +988,18 @@ DEF_HELPER_5(vfwcvt_f_x_v_w, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfwcvt_f_f_v_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfwcvt_f_f_v_w, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_xu_f_v_h, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_xu_f_v_w, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_x_f_v_h, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_x_f_v_w, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_f_xu_v_h, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_f_xu_v_w, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_f_x_v_h, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_f_x_v_w, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_f_f_v_h, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_f_f_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_xu_f_w_b, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_xu_f_w_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_xu_f_w_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_x_f_w_b, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_x_f_w_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_x_f_w_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_f_xu_w_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_f_xu_w_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_f_x_w_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_f_x_w_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_f_f_w_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_f_f_w_w, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vredsum_vs_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 6253628b9c..51b4268fa7 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -575,11 +575,16 @@ vfwcvt_f_x_v 010010 . ..... 01011 001 ..... 1010111 @r2_vm
vfwcvt_f_f_v 010010 . ..... 01100 001 ..... 1010111 @r2_vm
vfwcvt_rtz_xu_f_v 010010 . ..... 01110 001 ..... 1010111 @r2_vm
vfwcvt_rtz_x_f_v 010010 . ..... 01111 001 ..... 1010111 @r2_vm
-vfncvt_xu_f_v 100010 . ..... 10000 001 ..... 1010111 @r2_vm
-vfncvt_x_f_v 100010 . ..... 10001 001 ..... 1010111 @r2_vm
-vfncvt_f_xu_v 100010 . ..... 10010 001 ..... 1010111 @r2_vm
-vfncvt_f_x_v 100010 . ..... 10011 001 ..... 1010111 @r2_vm
-vfncvt_f_f_v 100010 . ..... 10100 001 ..... 1010111 @r2_vm
+
+vfncvt_xu_f_w 010010 . ..... 10000 001 ..... 1010111 @r2_vm
+vfncvt_x_f_w 010010 . ..... 10001 001 ..... 1010111 @r2_vm
+vfncvt_f_xu_w 010010 . ..... 10010 001 ..... 1010111 @r2_vm
+vfncvt_f_x_w 010010 . ..... 10011 001 ..... 1010111 @r2_vm
+vfncvt_f_f_w 010010 . ..... 10100 001 ..... 1010111 @r2_vm
+vfncvt_rod_f_f_w 010010 . ..... 10101 001 ..... 1010111 @r2_vm
+vfncvt_rtz_xu_f_w 010010 . ..... 10110 001 ..... 1010111 @r2_vm
+vfncvt_rtz_x_f_w 010010 . ..... 10111 001 ..... 1010111 @r2_vm
+
vredsum_vs 000000 . ..... ..... 010 ..... 1010111 @r_vm
vredand_vs 000001 . ..... ..... 010 ..... 1010111 @r_vm
vredor_vs 000010 . ..... ..... 010 ..... 1010111 @r_vm
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 32e94c496c..db6c3d9bdf 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2873,17 +2873,17 @@ static bool opfv_narrow_check(DisasContext *s, arg_rmr *a)
vext_check_sd(s, a->rd, a->rs2, a->vm);
}
-#define GEN_OPFV_NARROW_TRANS(NAME) \
+#define GEN_OPFV_NARROW_TRANS(NAME, HELPER, FRM) \
static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
{ \
if (opfv_narrow_check(s, a)) { \
uint32_t data = 0; \
static gen_helper_gvec_3_ptr * const fns[2] = { \
- gen_helper_##NAME##_h, \
- gen_helper_##NAME##_w, \
+ gen_helper_##HELPER##_h, \
+ gen_helper_##HELPER##_w, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, RISCV_FRM_DYN); \
+ gen_set_rm(s, FRM); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -2898,11 +2898,51 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
return false; \
}
-GEN_OPFV_NARROW_TRANS(vfncvt_xu_f_v)
-GEN_OPFV_NARROW_TRANS(vfncvt_x_f_v)
-GEN_OPFV_NARROW_TRANS(vfncvt_f_xu_v)
-GEN_OPFV_NARROW_TRANS(vfncvt_f_x_v)
-GEN_OPFV_NARROW_TRANS(vfncvt_f_f_v)
+GEN_OPFV_NARROW_TRANS(vfncvt_f_xu_w, vfncvt_f_xu_w, RISCV_FRM_DYN)
+GEN_OPFV_NARROW_TRANS(vfncvt_f_x_w, vfncvt_f_x_w, RISCV_FRM_DYN)
+GEN_OPFV_NARROW_TRANS(vfncvt_f_f_w, vfncvt_f_f_w, RISCV_FRM_DYN)
+/* Reuse the helper function from vfncvt.f.f.w */
+GEN_OPFV_NARROW_TRANS(vfncvt_rod_f_f_w, vfncvt_f_f_w, RISCV_FRM_ROD)
+
+static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a)
+{
+ return require_rvv(s) &&
+ require_scale_rvf(s) &&
+ vext_check_isa_ill(s) &&
+ /* OPFV narrowing instructions ignore vs1 check */
+ vext_check_sd(s, a->rd, a->rs2, a->vm);
+}
+
+#define GEN_OPXFV_NARROW_TRANS(NAME, HELPER, FRM) \
+static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
+{ \
+ if (opxfv_narrow_check(s, a)) { \
+ uint32_t data = 0; \
+ static gen_helper_gvec_3_ptr * const fns[3] = { \
+ gen_helper_##HELPER##_b, \
+ gen_helper_##HELPER##_h, \
+ gen_helper_##HELPER##_w, \
+ }; \
+ TCGLabel *over = gen_new_label(); \
+ gen_set_rm(s, FRM); \
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
+ \
+ data = FIELD_DP32(data, VDATA, VM, a->vm); \
+ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
+ vreg_ofs(s, a->rs2), cpu_env, 0, \
+ s->vlen / 8, data, fns[s->sew]); \
+ mark_vs_dirty(s); \
+ gen_set_label(over); \
+ return true; \
+ } \
+ return false; \
+}
+
+GEN_OPXFV_NARROW_TRANS(vfncvt_xu_f_w, vfncvt_xu_f_w, RISCV_FRM_DYN)
+GEN_OPXFV_NARROW_TRANS(vfncvt_x_f_w, vfncvt_x_f_w, RISCV_FRM_DYN)
+/* Reuse the helper functions from vfncvt.xu.f.w and vfncvt.x.f.w */
+GEN_OPXFV_NARROW_TRANS(vfncvt_rtz_xu_f_w, vfncvt_xu_f_w, RISCV_FRM_RTZ)
+GEN_OPXFV_NARROW_TRANS(vfncvt_rtz_x_f_w, vfncvt_x_f_w, RISCV_FRM_RTZ)
/*
*** Vector Reduction Operations
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index e8de460b29..8d389af4b7 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4029,31 +4029,36 @@ GEN_VEXT_V_ENV(vfwcvt_f_f_v_w, 4, 8)
/* Narrowing Floating-Point/Integer Type-Convert Instructions */
/* (TD, T2, TX2) */
+#define NOP_UU_B uint8_t, uint16_t, uint32_t
#define NOP_UU_H uint16_t, uint32_t, uint32_t
#define NOP_UU_W uint32_t, uint64_t, uint64_t
/* vfncvt.xu.f.v vd, vs2, vm # Convert float to unsigned integer. */
-RVVCALL(OPFVV1, vfncvt_xu_f_v_h, NOP_UU_H, H2, H4, float32_to_uint16)
-RVVCALL(OPFVV1, vfncvt_xu_f_v_w, NOP_UU_W, H4, H8, float64_to_uint32)
-GEN_VEXT_V_ENV(vfncvt_xu_f_v_h, 2, 2)
-GEN_VEXT_V_ENV(vfncvt_xu_f_v_w, 4, 4)
+RVVCALL(OPFVV1, vfncvt_xu_f_w_b, NOP_UU_B, H1, H2, float16_to_uint8)
+RVVCALL(OPFVV1, vfncvt_xu_f_w_h, NOP_UU_H, H2, H4, float32_to_uint16)
+RVVCALL(OPFVV1, vfncvt_xu_f_w_w, NOP_UU_W, H4, H8, float64_to_uint32)
+GEN_VEXT_V_ENV(vfncvt_xu_f_w_b, 1, 1)
+GEN_VEXT_V_ENV(vfncvt_xu_f_w_h, 2, 2)
+GEN_VEXT_V_ENV(vfncvt_xu_f_w_w, 4, 4)
/* vfncvt.x.f.v vd, vs2, vm # Convert double-width float to signed integer. */
-RVVCALL(OPFVV1, vfncvt_x_f_v_h, NOP_UU_H, H2, H4, float32_to_int16)
-RVVCALL(OPFVV1, vfncvt_x_f_v_w, NOP_UU_W, H4, H8, float64_to_int32)
-GEN_VEXT_V_ENV(vfncvt_x_f_v_h, 2, 2)
-GEN_VEXT_V_ENV(vfncvt_x_f_v_w, 4, 4)
+RVVCALL(OPFVV1, vfncvt_x_f_w_b, NOP_UU_B, H1, H2, float16_to_int8)
+RVVCALL(OPFVV1, vfncvt_x_f_w_h, NOP_UU_H, H2, H4, float32_to_int16)
+RVVCALL(OPFVV1, vfncvt_x_f_w_w, NOP_UU_W, H4, H8, float64_to_int32)
+GEN_VEXT_V_ENV(vfncvt_x_f_w_b, 1, 1)
+GEN_VEXT_V_ENV(vfncvt_x_f_w_h, 2, 2)
+GEN_VEXT_V_ENV(vfncvt_x_f_w_w, 4, 4)
/* vfncvt.f.xu.v vd, vs2, vm # Convert double-width unsigned integer to float */
-RVVCALL(OPFVV1, vfncvt_f_xu_v_h, NOP_UU_H, H2, H4, uint32_to_float16)
-RVVCALL(OPFVV1, vfncvt_f_xu_v_w, NOP_UU_W, H4, H8, uint64_to_float32)
-GEN_VEXT_V_ENV(vfncvt_f_xu_v_h, 2, 2)
-GEN_VEXT_V_ENV(vfncvt_f_xu_v_w, 4, 4)
+RVVCALL(OPFVV1, vfncvt_f_xu_w_h, NOP_UU_H, H2, H4, uint32_to_float16)
+RVVCALL(OPFVV1, vfncvt_f_xu_w_w, NOP_UU_W, H4, H8, uint64_to_float32)
+GEN_VEXT_V_ENV(vfncvt_f_xu_w_h, 2, 2)
+GEN_VEXT_V_ENV(vfncvt_f_xu_w_w, 4, 4)
/* vfncvt.f.x.v vd, vs2, vm # Convert double-width integer to float. */
-RVVCALL(OPFVV1, vfncvt_f_x_v_h, NOP_UU_H, H2, H4, int32_to_float16)
-RVVCALL(OPFVV1, vfncvt_f_x_v_w, NOP_UU_W, H4, H8, int64_to_float32)
-GEN_VEXT_V_ENV(vfncvt_f_x_v_h, 2, 2)
-GEN_VEXT_V_ENV(vfncvt_f_x_v_w, 4, 4)
+RVVCALL(OPFVV1, vfncvt_f_x_w_h, NOP_UU_H, H2, H4, int32_to_float16)
+RVVCALL(OPFVV1, vfncvt_f_x_w_w, NOP_UU_W, H4, H8, int64_to_float32)
+GEN_VEXT_V_ENV(vfncvt_f_x_w_h, 2, 2)
+GEN_VEXT_V_ENV(vfncvt_f_x_w_w, 4, 4)
/* vfncvt.f.f.v vd, vs2, vm # Convert double float to single-width float. */
static uint16_t vfncvtffv16(uint32_t a, float_status *s)
@@ -4061,10 +4066,10 @@ static uint16_t vfncvtffv16(uint32_t a, float_status *s)
return float32_to_float16(a, true, s);
}
-RVVCALL(OPFVV1, vfncvt_f_f_v_h, NOP_UU_H, H2, H4, vfncvtffv16)
-RVVCALL(OPFVV1, vfncvt_f_f_v_w, NOP_UU_W, H4, H8, float64_to_float32)
-GEN_VEXT_V_ENV(vfncvt_f_f_v_h, 2, 2)
-GEN_VEXT_V_ENV(vfncvt_f_f_v_w, 4, 4)
+RVVCALL(OPFVV1, vfncvt_f_f_w_h, NOP_UU_H, H2, H4, vfncvtffv16)
+RVVCALL(OPFVV1, vfncvt_f_f_w_w, NOP_UU_W, H4, H8, float64_to_float32)
+GEN_VEXT_V_ENV(vfncvt_f_f_w_h, 2, 2)
+GEN_VEXT_V_ENV(vfncvt_f_f_w_w, 4, 4)
/*
*** Vector Reduction Operations
--
2.17.1
next prev parent reply other threads:[~2020-09-29 19:55 UTC|newest]
Thread overview: 149+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-29 19:03 [RFC v5 00/68] support vector extension v1.0 frank.chang
2020-09-29 19:03 ` [RFC v5 01/68] target/riscv: drop vector 0.7.1 and add 1.0 support frank.chang
2020-09-29 19:03 ` frank.chang
2020-09-29 19:03 ` [RFC v5 02/68] target/riscv: Use FIELD_EX32() to extract wd field frank.chang
2020-09-29 19:03 ` frank.chang
2020-09-29 19:03 ` [RFC v5 03/68] target/riscv: rvv-1.0: add mstatus VS field frank.chang
2020-09-29 19:03 ` frank.chang
2020-09-29 19:03 ` [RFC v5 04/68] target/riscv: rvv-1.0: add sstatus " frank.chang
2020-09-29 19:03 ` frank.chang
2020-09-29 19:03 ` [RFC v5 05/68] target/riscv: rvv-1.0: introduce writable misa.v field frank.chang
2020-09-29 19:03 ` frank.chang
2020-09-29 19:03 ` [RFC v5 06/68] target/riscv: rvv-1.0: add translation-time vector context status frank.chang
2020-09-29 19:03 ` frank.chang
2020-10-02 16:18 ` Richard Henderson
2020-10-02 16:18 ` Richard Henderson
2020-10-05 7:12 ` Frank Chang
2020-10-05 7:12 ` Frank Chang
2020-10-05 14:00 ` Richard Henderson
2020-10-05 14:00 ` Richard Henderson
2020-10-05 14:10 ` Frank Chang
2020-10-05 14:10 ` Frank Chang
2020-09-29 19:03 ` [RFC v5 07/68] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers frank.chang
2020-09-29 19:03 ` frank.chang
2020-09-29 19:03 ` [RFC v5 08/68] target/riscv: rvv-1.0: add vcsr register frank.chang
2020-09-29 19:03 ` frank.chang
2020-09-29 19:03 ` [RFC v5 09/68] target/riscv: rvv-1.0: add vlenb register frank.chang
2020-09-29 19:03 ` frank.chang
2020-09-29 19:03 ` [RFC v5 10/68] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers frank.chang
2020-09-29 19:03 ` frank.chang
2020-09-29 19:03 ` [RFC v5 11/68] target/riscv: rvv-1.0: remove MLEN calculations frank.chang
2020-09-29 19:03 ` frank.chang
2020-09-29 19:03 ` [RFC v5 12/68] target/riscv: rvv-1.0: add fractional LMUL frank.chang
2020-09-29 19:03 ` frank.chang
2020-09-29 19:03 ` [RFC v5 13/68] target/riscv: rvv-1.0: add VMA and VTA frank.chang
2020-09-29 19:03 ` frank.chang
2020-09-29 19:03 ` [RFC v5 14/68] target/riscv: rvv-1.0: update check functions frank.chang
2020-09-29 19:03 ` frank.chang
2020-09-29 19:03 ` [RFC v5 15/68] target/riscv: introduce more imm value modes in translator functions frank.chang
2020-09-29 19:03 ` frank.chang
2020-09-29 19:03 ` [RFC v5 16/68] target/riscv: rvv:1.0: add translation-time nan-box helper function frank.chang
2020-09-29 19:03 ` frank.chang
2020-09-29 19:03 ` [RFC v5 17/68] target/riscv: rvv-1.0: configure instructions frank.chang
2020-09-29 19:03 ` frank.chang
2020-09-29 19:03 ` [RFC v5 18/68] target/riscv: rvv-1.0: stride load and store instructions frank.chang
2020-09-29 19:03 ` frank.chang
2020-09-29 19:03 ` [RFC v5 19/68] target/riscv: rvv-1.0: index " frank.chang
2020-09-29 19:03 ` frank.chang
2020-09-29 19:03 ` [RFC v5 20/68] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns frank.chang
2020-09-29 19:03 ` frank.chang
2020-09-29 19:03 ` [RFC v5 21/68] target/riscv: rvv-1.0: fault-only-first unit stride load frank.chang
2020-09-29 19:03 ` frank.chang
2020-09-29 19:03 ` [RFC v5 22/68] target/riscv: rvv-1.0: amo operations frank.chang
2020-09-29 19:03 ` frank.chang
2020-09-29 19:03 ` [RFC v5 23/68] target/riscv: rvv-1.0: load/store whole register instructions frank.chang
2020-09-29 19:03 ` frank.chang
2020-09-29 19:03 ` [RFC v5 24/68] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns frank.chang
2020-09-29 19:03 ` frank.chang
2020-09-29 19:04 ` [RFC v5 25/68] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation frank.chang
2020-09-29 19:04 ` frank.chang
2020-09-29 19:04 ` [RFC v5 26/68] target/riscv: rvv-1.0: floating-point square-root instruction frank.chang
2020-09-29 19:04 ` frank.chang
2020-09-29 19:04 ` [RFC v5 27/68] target/riscv: rvv-1.0: floating-point classify instructions frank.chang
2020-09-29 19:04 ` frank.chang
2020-09-29 19:04 ` [RFC v5 28/68] target/riscv: rvv-1.0: mask population count instruction frank.chang
2020-09-29 19:04 ` frank.chang
2020-09-29 19:04 ` [RFC v5 29/68] target/riscv: rvv-1.0: find-first-set mask bit instruction frank.chang
2020-09-29 19:04 ` frank.chang
2020-09-29 19:04 ` [RFC v5 30/68] target/riscv: rvv-1.0: set-X-first mask bit instructions frank.chang
2020-09-29 19:04 ` frank.chang
2020-09-29 19:04 ` [RFC v5 31/68] target/riscv: rvv-1.0: iota instruction frank.chang
2020-09-29 19:04 ` frank.chang
2020-09-29 19:04 ` [RFC v5 32/68] target/riscv: rvv-1.0: element index instruction frank.chang
2020-09-29 19:04 ` frank.chang
2020-09-29 19:04 ` [RFC v5 33/68] target/riscv: rvv-1.0: allow load element with sign-extended frank.chang
2020-09-29 19:04 ` frank.chang
2020-09-29 19:04 ` [RFC v5 34/68] target/riscv: rvv-1.0: register gather instructions frank.chang
2020-09-29 19:04 ` frank.chang
2020-09-29 19:04 ` [RFC v5 35/68] target/riscv: rvv-1.0: integer scalar move instructions frank.chang
2020-09-29 19:04 ` frank.chang
2020-09-29 19:04 ` [RFC v5 36/68] target/riscv: rvv-1.0: floating-point move instruction frank.chang
2020-09-29 19:04 ` frank.chang
2020-09-29 19:04 ` [RFC v5 37/68] target/riscv: rvv-1.0: floating-point scalar move instructions frank.chang
2020-09-29 19:04 ` frank.chang
2020-09-29 19:04 ` [RFC v5 38/68] target/riscv: rvv-1.0: whole register " frank.chang
2020-09-29 19:04 ` frank.chang
2020-09-29 19:04 ` [RFC v5 39/68] target/riscv: rvv-1.0: integer extension instructions frank.chang
2020-09-29 19:04 ` frank.chang
2020-09-29 19:04 ` [RFC v5 40/68] target/riscv: rvv-1.0: single-width averaging add and subtract instructions frank.chang
2020-09-29 19:04 ` frank.chang
2020-09-29 19:04 ` [RFC v5 41/68] target/riscv: rvv-1.0: single-width bit shift instructions frank.chang
2020-09-29 19:04 ` frank.chang
2020-09-29 19:04 ` [RFC v5 42/68] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow frank.chang
2020-09-29 19:04 ` frank.chang
2020-09-29 19:04 ` [RFC v5 43/68] target/riscv: rvv-1.0: narrowing integer right shift instructions frank.chang
2020-09-29 19:04 ` frank.chang
2020-09-29 19:04 ` [RFC v5 44/68] target/riscv: rvv-1.0: widening integer multiply-add instructions frank.chang
2020-09-29 19:04 ` frank.chang
2020-09-29 19:04 ` [RFC v5 45/68] target/riscv: rvv-1.0: single-width saturating add and subtract instructions frank.chang
2020-09-29 19:04 ` frank.chang
2020-09-29 19:04 ` [RFC v5 46/68] target/riscv: rvv-1.0: integer comparison instructions frank.chang
2020-09-29 19:04 ` frank.chang
2020-09-29 19:04 ` [RFC v5 47/68] target/riscv: rvv-1.0: floating-point compare instructions frank.chang
2020-09-29 19:04 ` frank.chang
2020-09-29 19:04 ` [RFC v5 48/68] target/riscv: rvv-1.0: mask-register logical instructions frank.chang
2020-09-29 19:04 ` frank.chang
2020-09-29 19:04 ` [RFC v5 49/68] target/riscv: rvv-1.0: slide instructions frank.chang
2020-09-29 19:04 ` frank.chang
2020-09-29 19:04 ` [RFC v5 50/68] target/riscv: rvv-1.0: floating-point " frank.chang
2020-09-29 19:04 ` frank.chang
2020-09-29 19:04 ` [RFC v5 51/68] target/riscv: rvv-1.0: narrowing fixed-point clip instructions frank.chang
2020-09-29 19:04 ` frank.chang
2020-09-29 19:04 ` [RFC v5 52/68] target/riscv: rvv-1.0: single-width floating-point reduction frank.chang
2020-09-29 19:04 ` frank.chang
2020-09-29 19:04 ` [RFC v5 53/68] target/riscv: rvv-1.0: widening floating-point reduction instructions frank.chang
2020-09-29 19:04 ` frank.chang
2020-09-29 19:04 ` [RFC v5 54/68] target/riscv: rvv-1.0: single-width scaling shift instructions frank.chang
2020-09-29 19:04 ` frank.chang
2020-09-29 19:04 ` [RFC v5 55/68] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add frank.chang
2020-09-29 19:04 ` frank.chang
2020-09-29 19:04 ` [RFC v5 56/68] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf frank.chang
2020-09-29 19:04 ` frank.chang
2020-09-29 19:04 ` [RFC v5 57/68] target/riscv: rvv-1.0: remove integer extract instruction frank.chang
2020-09-29 19:04 ` frank.chang
2020-09-29 19:04 ` [RFC v5 58/68] target/riscv: rvv-1.0: floating-point min/max instructions frank.chang
2020-09-29 19:04 ` frank.chang
2020-09-29 19:04 ` [RFC v5 59/68] target/riscv: introduce floating-point rounding mode enum frank.chang
2020-09-29 19:04 ` frank.chang
2020-09-29 19:04 ` [RFC v5 60/68] target/riscv: rvv-1.0: floating-point/integer type-convert instructions frank.chang
2020-09-29 19:04 ` frank.chang
2020-09-29 19:04 ` [RFC v5 61/68] target/riscv: rvv-1.0: widening floating-point/integer type-convert frank.chang
2020-09-29 19:04 ` frank.chang
2020-09-29 19:04 ` [RFC v5 62/68] target/riscv: add "set round to odd" rounding mode helper function frank.chang
2020-09-29 19:04 ` frank.chang
2020-09-29 19:04 ` frank.chang [this message]
2020-09-29 19:04 ` [RFC v5 63/68] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert frank.chang
2020-09-29 19:04 ` [RFC v5 64/68] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits frank.chang
2020-09-29 19:04 ` frank.chang
2020-09-29 19:04 ` [RFC v5 65/68] target/riscv: gdb: modify gdb csr xml file to align with csr register map frank.chang
2020-09-29 19:04 ` frank.chang
2020-09-29 19:04 ` [RFC v5 66/68] target/riscv: gdb: support vector registers for rv64 & rv32 frank.chang
2020-09-29 19:04 ` frank.chang
2020-09-29 19:04 ` [RFC v5 67/68] target/riscv: implement vstart CSR frank.chang
2020-09-29 19:04 ` frank.chang
2020-09-29 19:04 ` [RFC v5 68/68] target/riscv: trigger illegal instruction exception if frm is not valid frank.chang
2020-09-29 19:04 ` frank.chang
2020-10-20 7:42 ` [RFC v5 00/68] support vector extension v1.0 Frank Chang
2020-11-10 2:09 ` Frank Chang
2020-11-10 4:01 ` Alistair Francis
2020-11-10 4:01 ` Alistair Francis
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