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* [Intel-gfx] [PATCH v2 00/11] drm/i915: Plumb crtc state to link training code
@ 2020-09-29 23:34 Ville Syrjala
  2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 01/11] drm/i915: s/pre_empemph/preemph/ Ville Syrjala
                   ` (20 more replies)
  0 siblings, 21 replies; 37+ messages in thread
From: Ville Syrjala @ 2020-09-29 23:34 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Another attempt at plumbing the crtc state to the depths of
the link training code. This time I tried to preserve the
PHY test stuff in a somewhat working condition.

The DDI buf trans stuff also started to bug me again so had 
to toss in a few cleanups in that area. Still pretty messy,
but with a bit more regular structure we could perhaps toss
in a few vfuncs to get rid of some if ladders at least.
Not entirely sure yet...

Ville Syrjälä (11):
  drm/i915: s/pre_empemph/preemph/
  drm/i915: s/old_crtc_state/crtc_state/
  drm/i915: Make intel_dp_process_phy_request() static
  drm/i915: Shove the PHY test into the hotplug work
  drm/i915: Split ICL combo PHY buf trans per output type
  drm/i915: Split ICL MG PHY buf trans per output type
  drm/i915: Split EHL combo PHY buf trans per output type
  drm/i915: Split TGL combo PHY buf trans per output type
  drm/i915: Split TGL DKL PHY buf trans per output type
  drm/i915: Plumb crtc_state to link training
  drm/i915: Eliminate intel_dp.regs.dp_tp_{ctl,status}

 drivers/gpu/drm/i915/display/intel_ddi.c      | 677 ++++++++++--------
 drivers/gpu/drm/i915/display/intel_ddi.h      |  11 +-
 .../drm/i915/display/intel_display_types.h    |  25 +-
 drivers/gpu/drm/i915/display/intel_dp.c       | 289 ++++++--
 drivers/gpu/drm/i915/display/intel_dp.h       |  11 +-
 .../drm/i915/display/intel_dp_link_training.c | 102 +--
 .../drm/i915/display/intel_dp_link_training.h |   8 +-
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |  24 +-
 drivers/gpu/drm/i915/display/intel_dpio_phy.c |  23 +-
 drivers/gpu/drm/i915/display/intel_dpio_phy.h |   2 +
 drivers/gpu/drm/i915/display/intel_hdmi.c     |   7 +-
 11 files changed, 718 insertions(+), 461 deletions(-)

-- 
2.26.2

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

* [Intel-gfx] [PATCH v2 01/11] drm/i915: s/pre_empemph/preemph/
  2020-09-29 23:34 [Intel-gfx] [PATCH v2 00/11] drm/i915: Plumb crtc state to link training code Ville Syrjala
@ 2020-09-29 23:34 ` Ville Syrjala
  2020-09-30 13:56   ` Imre Deak
  2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 02/11] drm/i915: s/old_crtc_state/crtc_state/ Ville Syrjala
                   ` (19 subsequent siblings)
  20 siblings, 1 reply; 37+ messages in thread
From: Ville Syrjala @ 2020-09-29 23:34 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

I managed to fumble some functions names. Fix them.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 54a4b81ea3ff..ff96540c8612 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4167,12 +4167,12 @@ static u8 intel_dp_voltage_max_3(struct intel_dp *intel_dp)
 	return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
 }
 
-static u8 intel_dp_pre_empemph_max_2(struct intel_dp *intel_dp)
+static u8 intel_dp_preemph_max_2(struct intel_dp *intel_dp)
 {
 	return DP_TRAIN_PRE_EMPH_LEVEL_2;
 }
 
-static u8 intel_dp_pre_empemph_max_3(struct intel_dp *intel_dp)
+static u8 intel_dp_preemph_max_3(struct intel_dp *intel_dp)
 {
 	return DP_TRAIN_PRE_EMPH_LEVEL_3;
 }
@@ -7953,10 +7953,10 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
 
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
 	    (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) {
-		dig_port->dp.preemph_max = intel_dp_pre_empemph_max_3;
+		dig_port->dp.preemph_max = intel_dp_preemph_max_3;
 		dig_port->dp.voltage_max = intel_dp_voltage_max_3;
 	} else {
-		dig_port->dp.preemph_max = intel_dp_pre_empemph_max_2;
+		dig_port->dp.preemph_max = intel_dp_preemph_max_2;
 		dig_port->dp.voltage_max = intel_dp_voltage_max_2;
 	}
 
-- 
2.26.2

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

* [Intel-gfx] [PATCH v2 02/11] drm/i915: s/old_crtc_state/crtc_state/
  2020-09-29 23:34 [Intel-gfx] [PATCH v2 00/11] drm/i915: Plumb crtc state to link training code Ville Syrjala
  2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 01/11] drm/i915: s/pre_empemph/preemph/ Ville Syrjala
@ 2020-09-29 23:34 ` Ville Syrjala
  2020-09-30 13:57   ` Imre Deak
  2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 03/11] drm/i915: Make intel_dp_process_phy_request() static Ville Syrjala
                   ` (18 subsequent siblings)
  20 siblings, 1 reply; 37+ messages in thread
From: Ville Syrjala @ 2020-09-29 23:34 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

intel_dp_enable_port() is called during the enable sequence,
so there is nothing old about the passed in crtc state.
Rename it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index ff96540c8612..3586d79f5599 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3850,7 +3850,7 @@ g4x_set_link_train(struct intel_dp *intel_dp,
 }
 
 static void intel_dp_enable_port(struct intel_dp *intel_dp,
-				 const struct intel_crtc_state *old_crtc_state)
+				 const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 
@@ -3865,7 +3865,7 @@ static void intel_dp_enable_port(struct intel_dp *intel_dp,
 	 * fail when the power sequencer is freshly used for this port.
 	 */
 	intel_dp->DP |= DP_PORT_EN;
-	if (old_crtc_state->has_audio)
+	if (crtc_state->has_audio)
 		intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 
 	intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
-- 
2.26.2

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

* [Intel-gfx] [PATCH v2 03/11] drm/i915: Make intel_dp_process_phy_request() static
  2020-09-29 23:34 [Intel-gfx] [PATCH v2 00/11] drm/i915: Plumb crtc state to link training code Ville Syrjala
  2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 01/11] drm/i915: s/pre_empemph/preemph/ Ville Syrjala
  2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 02/11] drm/i915: s/old_crtc_state/crtc_state/ Ville Syrjala
@ 2020-09-29 23:34 ` Ville Syrjala
  2020-09-30 13:58   ` Imre Deak
  2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 04/11] drm/i915: Shove the PHY test into the hotplug work Ville Syrjala
                   ` (17 subsequent siblings)
  20 siblings, 1 reply; 37+ messages in thread
From: Ville Syrjala @ 2020-09-29 23:34 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

intel_dp_process_phy_request() has no business being externally
visible. Make it static.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
 drivers/gpu/drm/i915/display/intel_dp.h | 1 -
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 3586d79f5599..5c673080ecb1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5562,7 +5562,7 @@ intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, uint8_t lane_cnt)
 		       trans_ddi_func_ctl_value);
 }
 
-void intel_dp_process_phy_request(struct intel_dp *intel_dp)
+static void intel_dp_process_phy_request(struct intel_dp *intel_dp)
 {
 	struct drm_dp_phy_test_params *data =
 		&intel_dp->compliance.test_data.phytest;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index a9580d1df35b..60f44f41fd08 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -123,7 +123,6 @@ void intel_read_dp_sdp(struct intel_encoder *encoder,
 		       struct intel_crtc_state *crtc_state,
 		       unsigned int type);
 bool intel_digital_port_connected(struct intel_encoder *encoder);
-void intel_dp_process_phy_request(struct intel_dp *intel_dp);
 
 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
 {
-- 
2.26.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

* [Intel-gfx] [PATCH v2 04/11] drm/i915: Shove the PHY test into the hotplug work
  2020-09-29 23:34 [Intel-gfx] [PATCH v2 00/11] drm/i915: Plumb crtc state to link training code Ville Syrjala
                   ` (2 preceding siblings ...)
  2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 03/11] drm/i915: Make intel_dp_process_phy_request() static Ville Syrjala
@ 2020-09-29 23:34 ` Ville Syrjala
  2020-09-30  8:10   ` kernel test robot
  2020-09-30 10:04   ` [Intel-gfx] [PATCH v3 " Ville Syrjala
  2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 05/11] drm/i915: Split ICL combo PHY buf trans per output type Ville Syrjala
                   ` (16 subsequent siblings)
  20 siblings, 2 replies; 37+ messages in thread
From: Ville Syrjala @ 2020-09-29 23:34 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Doing nay kind modeset stuff from the short hpd handler is
verboten. The ad-hoc PHY test modeset code violates this. And
by calling various link training related functions it's now
blocking further work to plumb the crtc state down into the
link training code.

Let's hack around that by pushing the PHY test stuff into the
hotplug work where it's less of a problem. Still not great but
at least acceptable. We take a few pages from the link retraining
handbook to handle the locking and whatnot.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 154 ++++++++++++++++++++----
 1 file changed, 128 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 5c673080ecb1..6718e01909cd 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5424,25 +5424,6 @@ static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
 	return test_result;
 }
 
-static u8 intel_dp_prepare_phytest(struct intel_dp *intel_dp)
-{
-	struct drm_dp_phy_test_params *data =
-		&intel_dp->compliance.test_data.phytest;
-
-	if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
-		DRM_DEBUG_KMS("DP Phy Test pattern AUX read failure\n");
-		return DP_TEST_NAK;
-	}
-
-	/*
-	 * link_mst is set to false to avoid executing mst related code
-	 * during compliance testing.
-	 */
-	intel_dp->link_mst = false;
-
-	return DP_TEST_ACK;
-}
-
 static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *dev_priv =
@@ -5590,15 +5571,18 @@ static void intel_dp_process_phy_request(struct intel_dp *intel_dp)
 
 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
 {
-	u8 test_result;
+	struct drm_dp_phy_test_params *data =
+		&intel_dp->compliance.test_data.phytest;
 
-	test_result = intel_dp_prepare_phytest(intel_dp);
-	if (test_result != DP_TEST_ACK)
-		DRM_ERROR("Phy test preparation failed\n");
+	if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
+		DRM_DEBUG_KMS("DP Phy Test pattern AUX read failure\n");
+		return DP_TEST_NAK;
+	}
 
-	intel_dp_process_phy_request(intel_dp);
+	/* Set test active flag here so userspace doesn't interrupt things */
+	intel_dp->compliance.test_active = true;
 
-	return test_result;
+	return DP_TEST_ACK;
 }
 
 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
@@ -5887,6 +5871,104 @@ int intel_dp_retrain_link(struct intel_encoder *encoder,
 	return 0;
 }
 
+static int intel_dp_prep_phy_test(struct intel_dp *intel_dp,
+				  struct drm_modeset_acquire_ctx *ctx,
+				  u32 *crtc_mask)
+{
+	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+	struct drm_connector_list_iter conn_iter;
+	struct intel_connector *connector;
+	int ret = 0;
+
+	*crtc_mask = 0;
+
+	drm_connector_list_iter_begin(&i915->drm, &conn_iter);
+	for_each_intel_connector_iter(connector, &conn_iter) {
+		struct drm_connector_state *conn_state =
+			connector->base.state;
+		struct intel_crtc_state *crtc_state;
+		struct intel_crtc *crtc;
+
+		if (!intel_dp_has_connector(intel_dp, conn_state))
+			continue;
+
+		crtc = to_intel_crtc(conn_state->crtc);
+		if (!crtc)
+			continue;
+
+		ret = drm_modeset_lock(&crtc->base.mutex, ctx);
+		if (ret)
+			break;
+
+		crtc_state = to_intel_crtc_state(crtc->base.state);
+
+		drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
+
+		if (!crtc_state->hw.active)
+			continue;
+
+		if (conn_state->commit &&
+		    !try_wait_for_completion(&conn_state->commit->hw_done))
+			continue;
+
+		*crtc_mask |= drm_crtc_mask(&crtc->base);
+	}
+	drm_connector_list_iter_end(&conn_iter);
+
+	return ret;
+}
+
+static int intel_dp_do_phy_test(struct intel_encoder *encoder,
+				struct drm_modeset_acquire_ctx *ctx)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+	u32 crtc_mask;
+	int ret;
+
+	ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
+			       ctx);
+	if (ret)
+		return ret;
+
+	ret = intel_dp_prep_phy_test(intel_dp, ctx, &crtc_mask);
+	if (ret)
+		return ret;
+
+	if (crtc_mask == 0)
+		return 0;
+
+	drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n",
+		    encoder->base.base.id, encoder->base.name);
+	intel_dp_process_phy_request(intel_dp);
+
+	return 0;
+}
+
+static void intel_dp_phy_test(struct intel_encoder *encoder)
+{
+	struct drm_modeset_acquire_ctx ctx;
+	int ret;
+
+	drm_modeset_acquire_init(&ctx, 0);
+
+	for (;;) {
+		ret = intel_dp_do_phy_test(encoder, &ctx);
+
+		if (ret == -EDEADLK) {
+			drm_modeset_backoff(&ctx);
+			continue;
+		}
+
+		break;
+	}
+
+	drm_modeset_drop_locks(&ctx);
+	drm_modeset_acquire_fini(&ctx);
+	drm_WARN(encoder->base.dev, ret,
+		 "Acquiring modeset locks failed with %i\n", ret);
+}
+
 /*
  * If display is now connected check links status,
  * there has been known issues of link loss triggering
@@ -5903,10 +5985,18 @@ static enum intel_hotplug_state
 intel_dp_hotplug(struct intel_encoder *encoder,
 		 struct intel_connector *connector)
 {
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 	struct drm_modeset_acquire_ctx ctx;
 	enum intel_hotplug_state state;
 	int ret;
 
+	if (intel_dp->compliance.test_active &&
+	    intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) {
+		intel_dp_phy_test(encoder);
+		/* just do the PHY test and nothing else */
+		return connector->base.status;
+	}
+
 	state = intel_encoder_hotplug(encoder, connector);
 
 	drm_modeset_acquire_init(&ctx, 0);
@@ -6011,11 +6101,23 @@ intel_dp_short_pulse(struct intel_dp *intel_dp)
 
 	intel_psr_short_pulse(intel_dp);
 
-	if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
+	switch (intel_dp->compliance.test_type) {
+	case DP_TEST_LINK_TRAINING:
 		drm_dbg_kms(&dev_priv->drm,
 			    "Link Training Compliance Test requested\n");
 		/* Send a Hotplug Uevent to userspace to start modeset */
 		drm_kms_helper_hotplug_event(&dev_priv->drm);
+		break;
+	case DP_TEST_LINK_PHY_TEST_PATTERN:
+		drm_dbg_kms(&dev_priv->drm,
+			    "PHY test pattern Compliance Test requested\n");
+		/*
+		 * Schedule long hpd to do the test
+		 *
+		 * FIXME get rid of the ad-hoc phy test modeset code
+		 * and properly incorporate it into the normal modeset.
+		 */
+		return false;
 	}
 
 	return true;
-- 
2.26.2

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

* [Intel-gfx] [PATCH v2 05/11] drm/i915: Split ICL combo PHY buf trans per output type
  2020-09-29 23:34 [Intel-gfx] [PATCH v2 00/11] drm/i915: Plumb crtc state to link training code Ville Syrjala
                   ` (3 preceding siblings ...)
  2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 04/11] drm/i915: Shove the PHY test into the hotplug work Ville Syrjala
@ 2020-09-29 23:34 ` Ville Syrjala
  2020-09-30 15:19   ` Imre Deak
  2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 06/11] drm/i915: Split ICL MG " Ville Syrjala
                   ` (15 subsequent siblings)
  20 siblings, 1 reply; 37+ messages in thread
From: Ville Syrjala @ 2020-09-29 23:34 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Make the mess inside the buf trans funcs a bit more manageable by
splitting along the lines of output type.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 42 +++++++++++++++++++-----
 1 file changed, 33 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 4d06178cd76c..4c3416d89f30 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1034,24 +1034,48 @@ cnl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
 }
 
 static const struct cnl_ddi_buf_trans *
-icl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
-			int *n_entries)
+icl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, int type, int rate,
+			     int *n_entries)
+{
+	*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
+	return icl_combo_phy_ddi_translations_hdmi;
+}
+
+static const struct cnl_ddi_buf_trans *
+icl_get_combo_buf_trans_dp(struct intel_encoder *encoder, int type, int rate,
+			   int *n_entries)
+{
+	*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
+	return icl_combo_phy_ddi_translations_dp_hbr2;
+}
+
+static const struct cnl_ddi_buf_trans *
+icl_get_combo_buf_trans_edp(struct intel_encoder *encoder, int type, int rate,
+			    int *n_entries)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
-	if (type == INTEL_OUTPUT_HDMI) {
-		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
-		return icl_combo_phy_ddi_translations_hdmi;
-	} else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
+	if (rate > 540000) {
 		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
 		return icl_combo_phy_ddi_translations_edp_hbr3;
-	} else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
+	} else if (dev_priv->vbt.edp.low_vswing) {
 		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
 		return icl_combo_phy_ddi_translations_edp_hbr2;
 	}
 
-	*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
-	return icl_combo_phy_ddi_translations_dp_hbr2;
+	return icl_get_combo_buf_trans_dp(encoder, type, rate, n_entries);
+}
+
+static const struct cnl_ddi_buf_trans *
+icl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
+			int *n_entries)
+{
+	if (type == INTEL_OUTPUT_HDMI)
+		return icl_get_combo_buf_trans_hdmi(encoder, type, rate, n_entries);
+	else if (type == INTEL_OUTPUT_EDP)
+		return icl_get_combo_buf_trans_edp(encoder, type, rate, n_entries);
+	else
+		return icl_get_combo_buf_trans_dp(encoder, type, rate, n_entries);
 }
 
 static const struct icl_mg_phy_ddi_buf_trans *
-- 
2.26.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

* [Intel-gfx] [PATCH v2 06/11] drm/i915: Split ICL MG PHY buf trans per output type
  2020-09-29 23:34 [Intel-gfx] [PATCH v2 00/11] drm/i915: Plumb crtc state to link training code Ville Syrjala
                   ` (4 preceding siblings ...)
  2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 05/11] drm/i915: Split ICL combo PHY buf trans per output type Ville Syrjala
@ 2020-09-29 23:34 ` Ville Syrjala
  2020-09-30 15:21   ` Imre Deak
  2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 07/11] drm/i915: Split EHL combo " Ville Syrjala
                   ` (14 subsequent siblings)
  20 siblings, 1 reply; 37+ messages in thread
From: Ville Syrjala @ 2020-09-29 23:34 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Make the mess inside the buf trans funcs a bit more manageable by
splitting along the lines of output type.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 31 ++++++++++++++++++------
 1 file changed, 23 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 4c3416d89f30..e3c6d4942b68 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1079,19 +1079,34 @@ icl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
 }
 
 static const struct icl_mg_phy_ddi_buf_trans *
-icl_get_mg_buf_trans(struct intel_encoder *encoder, int type, int rate,
-		     int *n_entries)
+icl_get_mg_buf_trans_hdmi(struct intel_encoder *encoder, int type, int rate,
+			  int *n_entries)
 {
-	if (type == INTEL_OUTPUT_HDMI) {
-		*n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hdmi);
-		return icl_mg_phy_ddi_translations_hdmi;
-	} else if (rate > 270000) {
+	*n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hdmi);
+	return icl_mg_phy_ddi_translations_hdmi;
+}
+
+static const struct icl_mg_phy_ddi_buf_trans *
+icl_get_mg_buf_trans_dp(struct intel_encoder *encoder, int type, int rate,
+			int *n_entries)
+{
+	if (rate > 270000) {
 		*n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hbr2_hbr3);
 		return icl_mg_phy_ddi_translations_hbr2_hbr3;
+	} else {
+		*n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_rbr_hbr);
+		return icl_mg_phy_ddi_translations_rbr_hbr;
 	}
+}
 
-	*n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_rbr_hbr);
-	return icl_mg_phy_ddi_translations_rbr_hbr;
+static const struct icl_mg_phy_ddi_buf_trans *
+icl_get_mg_buf_trans(struct intel_encoder *encoder, int type, int rate,
+		     int *n_entries)
+{
+	if (type == INTEL_OUTPUT_HDMI)
+		return icl_get_mg_buf_trans_hdmi(encoder, type, rate, n_entries);
+	else
+		return icl_get_mg_buf_trans_dp(encoder, type, rate, n_entries);
 }
 
 static const struct cnl_ddi_buf_trans *
-- 
2.26.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

* [Intel-gfx] [PATCH v2 07/11] drm/i915: Split EHL combo PHY buf trans per output type
  2020-09-29 23:34 [Intel-gfx] [PATCH v2 00/11] drm/i915: Plumb crtc state to link training code Ville Syrjala
                   ` (5 preceding siblings ...)
  2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 06/11] drm/i915: Split ICL MG " Ville Syrjala
@ 2020-09-29 23:34 ` Ville Syrjala
  2020-09-30 15:24   ` Imre Deak
  2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 08/11] drm/i915: Split TGL " Ville Syrjala
                   ` (13 subsequent siblings)
  20 siblings, 1 reply; 37+ messages in thread
From: Ville Syrjala @ 2020-09-29 23:34 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Make the mess inside the buf trans funcs a bit more manageable by
splitting along the lines of output type.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 63 +++++++++++++++---------
 1 file changed, 41 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index e3c6d4942b68..da7090803ea1 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1109,32 +1109,51 @@ icl_get_mg_buf_trans(struct intel_encoder *encoder, int type, int rate,
 		return icl_get_mg_buf_trans_dp(encoder, type, rate, n_entries);
 }
 
+static const struct cnl_ddi_buf_trans *
+ehl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, int type, int rate,
+			     int *n_entries)
+{
+	*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
+	return icl_combo_phy_ddi_translations_hdmi;
+}
+
+static const struct cnl_ddi_buf_trans *
+ehl_get_combo_buf_trans_dp(struct intel_encoder *encoder, int type, int rate,
+			   int *n_entries)
+{
+	*n_entries = ARRAY_SIZE(ehl_combo_phy_ddi_translations_dp);
+	return ehl_combo_phy_ddi_translations_dp;
+}
+
+static const struct cnl_ddi_buf_trans *
+ehl_get_combo_buf_trans_edp(struct intel_encoder *encoder, int type, int rate,
+			    int *n_entries)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
+	if (dev_priv->vbt.edp.low_vswing) {
+		if (rate > 540000) {
+			*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
+			return icl_combo_phy_ddi_translations_edp_hbr3;
+		} else {
+			*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
+			return icl_combo_phy_ddi_translations_edp_hbr2;
+		}
+	}
+
+	return ehl_get_combo_buf_trans_dp(encoder, type, rate, n_entries);
+}
+
 static const struct cnl_ddi_buf_trans *
 ehl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
 			int *n_entries)
 {
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-
-	switch (type) {
-	case INTEL_OUTPUT_HDMI:
-		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
-		return icl_combo_phy_ddi_translations_hdmi;
-	case INTEL_OUTPUT_EDP:
-		if (dev_priv->vbt.edp.low_vswing) {
-			if (rate > 540000) {
-				*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
-				return icl_combo_phy_ddi_translations_edp_hbr3;
-			} else {
-				*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
-				return icl_combo_phy_ddi_translations_edp_hbr2;
-			}
-		}
-		/* fall through */
-	default:
-		/* All combo DP and eDP ports that do not support low_vswing */
-		*n_entries = ARRAY_SIZE(ehl_combo_phy_ddi_translations_dp);
-		return ehl_combo_phy_ddi_translations_dp;
-	}
+	if (type == INTEL_OUTPUT_HDMI)
+		return ehl_get_combo_buf_trans_hdmi(encoder, type, rate, n_entries);
+	else if (type == INTEL_OUTPUT_EDP)
+		return ehl_get_combo_buf_trans_edp(encoder, type, rate, n_entries);
+	else
+		return ehl_get_combo_buf_trans_dp(encoder, type, rate, n_entries);
 }
 
 static const struct cnl_ddi_buf_trans *
-- 
2.26.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

* [Intel-gfx] [PATCH v2 08/11] drm/i915: Split TGL combo PHY buf trans per output type
  2020-09-29 23:34 [Intel-gfx] [PATCH v2 00/11] drm/i915: Plumb crtc state to link training code Ville Syrjala
                   ` (6 preceding siblings ...)
  2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 07/11] drm/i915: Split EHL combo " Ville Syrjala
@ 2020-09-29 23:34 ` Ville Syrjala
  2020-09-30 15:29   ` Imre Deak
  2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 09/11] drm/i915: Split TGL DKL " Ville Syrjala
                   ` (12 subsequent siblings)
  20 siblings, 1 reply; 37+ messages in thread
From: Ville Syrjala @ 2020-09-29 23:34 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Make the mess inside the buf trans funcs a bit more manageable by
splitting along the lines of output type.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 83 ++++++++++++++----------
 1 file changed, 49 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index da7090803ea1..fea06c1b09d9 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1157,51 +1157,66 @@ ehl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
 }
 
 static const struct cnl_ddi_buf_trans *
-tgl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
-			int *n_entries)
+tgl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, int type, int rate,
+			     int *n_entries)
+{
+	*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
+	return icl_combo_phy_ddi_translations_hdmi;
+}
+
+static const struct cnl_ddi_buf_trans *
+tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder, int type, int rate,
+			   int *n_entries)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
-	switch (type) {
-	case INTEL_OUTPUT_HDMI:
-		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
-		return icl_combo_phy_ddi_translations_hdmi;
-	case INTEL_OUTPUT_EDP:
-		if (dev_priv->vbt.edp.hobl) {
-			struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-
-			if (!intel_dp->hobl_failed && rate <= 540000) {
-				/* Same table applies to TGL, RKL and DG1 */
-				*n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_edp_hbr2_hobl);
-				return tgl_combo_phy_ddi_translations_edp_hbr2_hobl;
-			}
-		}
-
-		if (rate > 540000) {
-			*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
-			return icl_combo_phy_ddi_translations_edp_hbr3;
-		} else if (dev_priv->vbt.edp.low_vswing) {
-			*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
-			return icl_combo_phy_ddi_translations_edp_hbr2;
-		}
-		/* fall through */
-	default:
-		/* All combo DP and eDP ports that do not support low_vswing */
-		if (rate > 270000) {
-			if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
-				*n_entries = ARRAY_SIZE(tgl_uy_combo_phy_ddi_translations_dp_hbr2);
-				return tgl_uy_combo_phy_ddi_translations_dp_hbr2;
-			}
-
+	if (rate > 270000) {
+		if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
+			*n_entries = ARRAY_SIZE(tgl_uy_combo_phy_ddi_translations_dp_hbr2);
+			return tgl_uy_combo_phy_ddi_translations_dp_hbr2;
+		} else {
 			*n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2);
 			return tgl_combo_phy_ddi_translations_dp_hbr2;
 		}
-
+	} else {
 		*n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr);
 		return tgl_combo_phy_ddi_translations_dp_hbr;
 	}
 }
 
+static const struct cnl_ddi_buf_trans *
+tgl_get_combo_buf_trans_edp(struct intel_encoder *encoder, int type, int rate,
+			    int *n_entries)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+	if (rate > 540000) {
+		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
+		return icl_combo_phy_ddi_translations_edp_hbr3;
+	} else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) {
+		*n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_edp_hbr2_hobl);
+		return tgl_combo_phy_ddi_translations_edp_hbr2_hobl;
+	} else if (dev_priv->vbt.edp.low_vswing) {
+		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
+		return icl_combo_phy_ddi_translations_edp_hbr2;
+	}
+
+	return tgl_get_combo_buf_trans_dp(encoder, type, rate, n_entries);
+}
+
+static const struct cnl_ddi_buf_trans *
+tgl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
+			int *n_entries)
+{
+	if (type == INTEL_OUTPUT_HDMI)
+		return tgl_get_combo_buf_trans_hdmi(encoder, type, rate, n_entries);
+	else if (type == INTEL_OUTPUT_EDP)
+		return tgl_get_combo_buf_trans_edp(encoder, type, rate, n_entries);
+	else
+		return tgl_get_combo_buf_trans_dp(encoder, type, rate, n_entries);
+}
+
 static const struct tgl_dkl_phy_ddi_buf_trans *
 tgl_get_dkl_buf_trans(struct intel_encoder *encoder, int type, int rate,
 		      int *n_entries)
-- 
2.26.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

* [Intel-gfx] [PATCH v2 09/11] drm/i915: Split TGL DKL PHY buf trans per output type
  2020-09-29 23:34 [Intel-gfx] [PATCH v2 00/11] drm/i915: Plumb crtc state to link training code Ville Syrjala
                   ` (7 preceding siblings ...)
  2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 08/11] drm/i915: Split TGL " Ville Syrjala
@ 2020-09-29 23:34 ` Ville Syrjala
  2020-09-30 15:31   ` Imre Deak
  2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 10/11] drm/i915: Plumb crtc_state to link training Ville Syrjala
                   ` (11 subsequent siblings)
  20 siblings, 1 reply; 37+ messages in thread
From: Ville Syrjala @ 2020-09-29 23:34 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Make the mess inside the buf trans funcs a bit more manageable by
splitting along the lines of output type.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 31 ++++++++++++++++++------
 1 file changed, 23 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index fea06c1b09d9..7032c367075a 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1218,19 +1218,34 @@ tgl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
 }
 
 static const struct tgl_dkl_phy_ddi_buf_trans *
-tgl_get_dkl_buf_trans(struct intel_encoder *encoder, int type, int rate,
-		      int *n_entries)
+tgl_get_dkl_buf_trans_hdmi(struct intel_encoder *encoder, int type, int rate,
+			   int *n_entries)
 {
-	if (type == INTEL_OUTPUT_HDMI) {
-		*n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans);
-		return tgl_dkl_phy_hdmi_ddi_trans;
-	} else if (rate > 270000) {
+	*n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans);
+	return tgl_dkl_phy_hdmi_ddi_trans;
+}
+
+static const struct tgl_dkl_phy_ddi_buf_trans *
+tgl_get_dkl_buf_trans_dp(struct intel_encoder *encoder, int type, int rate,
+			 int *n_entries)
+{
+	if (rate > 270000) {
 		*n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans_hbr2);
 		return tgl_dkl_phy_dp_ddi_trans_hbr2;
+	} else {
+		*n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans);
+		return tgl_dkl_phy_dp_ddi_trans;
 	}
+}
 
-	*n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans);
-	return tgl_dkl_phy_dp_ddi_trans;
+static const struct tgl_dkl_phy_ddi_buf_trans *
+tgl_get_dkl_buf_trans(struct intel_encoder *encoder, int type, int rate,
+		      int *n_entries)
+{
+	if (type == INTEL_OUTPUT_HDMI)
+		return tgl_get_dkl_buf_trans_hdmi(encoder, type, rate, n_entries);
+	else
+		return tgl_get_dkl_buf_trans_dp(encoder, type, rate, n_entries);
 }
 
 static int intel_ddi_hdmi_level(struct intel_encoder *encoder)
-- 
2.26.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

* [Intel-gfx] [PATCH v2 10/11] drm/i915: Plumb crtc_state to link training
  2020-09-29 23:34 [Intel-gfx] [PATCH v2 00/11] drm/i915: Plumb crtc state to link training code Ville Syrjala
                   ` (8 preceding siblings ...)
  2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 09/11] drm/i915: Split TGL DKL " Ville Syrjala
@ 2020-09-29 23:34 ` Ville Syrjala
  2020-09-30 16:36   ` Imre Deak
  2020-10-01 11:10   ` [Intel-gfx] [PATCH v4 " Ville Syrjala
  2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 11/11] drm/i915: Eliminate intel_dp.regs.dp_tp_{ctl, status} Ville Syrjala
                   ` (10 subsequent siblings)
  20 siblings, 2 replies; 37+ messages in thread
From: Ville Syrjala @ 2020-09-29 23:34 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Get rid of mode crtc->config usage, and some ad-hoc intel_dp state
usage by plumbing the crtc state all the way down to the link training
code.

Unfortunately we do have to keep some cached state in intel_dp so
that we can do the "does the link need retraining?" checks from
the short hpd handler.

v2: Add intel_crtc_state forward declaration
v3: Don't kill the PHY test code totally since it's
    now in the hotplug work where we can get at the states

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c      | 416 +++++++++---------
 drivers/gpu/drm/i915/display/intel_ddi.h      |   6 +-
 .../drm/i915/display/intel_display_types.h    |  17 +-
 drivers/gpu/drm/i915/display/intel_dp.c       | 123 ++++--
 drivers/gpu/drm/i915/display/intel_dp.h       |  10 +-
 .../drm/i915/display/intel_dp_link_training.c | 102 +++--
 .../drm/i915/display/intel_dp_link_training.h |   8 +-
 drivers/gpu/drm/i915/display/intel_dpio_phy.c |  23 +-
 drivers/gpu/drm/i915/display/intel_dpio_phy.h |   2 +
 drivers/gpu/drm/i915/display/intel_hdmi.c     |   7 +-
 10 files changed, 388 insertions(+), 326 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 7032c367075a..cdf3e5540482 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1034,7 +1034,8 @@ cnl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
 }
 
 static const struct cnl_ddi_buf_trans *
-icl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, int type, int rate,
+icl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder,
+			     const struct intel_crtc_state *crtc_state,
 			     int *n_entries)
 {
 	*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
@@ -1042,7 +1043,8 @@ icl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, int type, int rate,
 }
 
 static const struct cnl_ddi_buf_trans *
-icl_get_combo_buf_trans_dp(struct intel_encoder *encoder, int type, int rate,
+icl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
+			   const struct intel_crtc_state *crtc_state,
 			   int *n_entries)
 {
 	*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
@@ -1050,12 +1052,13 @@ icl_get_combo_buf_trans_dp(struct intel_encoder *encoder, int type, int rate,
 }
 
 static const struct cnl_ddi_buf_trans *
-icl_get_combo_buf_trans_edp(struct intel_encoder *encoder, int type, int rate,
+icl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
+			    const struct intel_crtc_state *crtc_state,
 			    int *n_entries)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
-	if (rate > 540000) {
+	if (crtc_state->port_clock > 540000) {
 		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
 		return icl_combo_phy_ddi_translations_edp_hbr3;
 	} else if (dev_priv->vbt.edp.low_vswing) {
@@ -1063,23 +1066,25 @@ icl_get_combo_buf_trans_edp(struct intel_encoder *encoder, int type, int rate,
 		return icl_combo_phy_ddi_translations_edp_hbr2;
 	}
 
-	return icl_get_combo_buf_trans_dp(encoder, type, rate, n_entries);
+	return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
 }
 
 static const struct cnl_ddi_buf_trans *
-icl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
+icl_get_combo_buf_trans(struct intel_encoder *encoder,
+			const struct intel_crtc_state *crtc_state,
 			int *n_entries)
 {
-	if (type == INTEL_OUTPUT_HDMI)
-		return icl_get_combo_buf_trans_hdmi(encoder, type, rate, n_entries);
-	else if (type == INTEL_OUTPUT_EDP)
-		return icl_get_combo_buf_trans_edp(encoder, type, rate, n_entries);
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+		return icl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries);
+	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
+		return icl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
 	else
-		return icl_get_combo_buf_trans_dp(encoder, type, rate, n_entries);
+		return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
 }
 
 static const struct icl_mg_phy_ddi_buf_trans *
-icl_get_mg_buf_trans_hdmi(struct intel_encoder *encoder, int type, int rate,
+icl_get_mg_buf_trans_hdmi(struct intel_encoder *encoder,
+			  const struct intel_crtc_state *crtc_state,
 			  int *n_entries)
 {
 	*n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hdmi);
@@ -1087,10 +1092,11 @@ icl_get_mg_buf_trans_hdmi(struct intel_encoder *encoder, int type, int rate,
 }
 
 static const struct icl_mg_phy_ddi_buf_trans *
-icl_get_mg_buf_trans_dp(struct intel_encoder *encoder, int type, int rate,
+icl_get_mg_buf_trans_dp(struct intel_encoder *encoder,
+			const struct intel_crtc_state *crtc_state,
 			int *n_entries)
 {
-	if (rate > 270000) {
+	if (crtc_state->port_clock > 270000) {
 		*n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hbr2_hbr3);
 		return icl_mg_phy_ddi_translations_hbr2_hbr3;
 	} else {
@@ -1100,17 +1106,19 @@ icl_get_mg_buf_trans_dp(struct intel_encoder *encoder, int type, int rate,
 }
 
 static const struct icl_mg_phy_ddi_buf_trans *
-icl_get_mg_buf_trans(struct intel_encoder *encoder, int type, int rate,
+icl_get_mg_buf_trans(struct intel_encoder *encoder,
+		     const struct intel_crtc_state *crtc_state,
 		     int *n_entries)
 {
-	if (type == INTEL_OUTPUT_HDMI)
-		return icl_get_mg_buf_trans_hdmi(encoder, type, rate, n_entries);
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+		return icl_get_mg_buf_trans_hdmi(encoder, crtc_state, n_entries);
 	else
-		return icl_get_mg_buf_trans_dp(encoder, type, rate, n_entries);
+		return icl_get_mg_buf_trans_dp(encoder, crtc_state, n_entries);
 }
 
 static const struct cnl_ddi_buf_trans *
-ehl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, int type, int rate,
+ehl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder,
+			     const struct intel_crtc_state *crtc_state,
 			     int *n_entries)
 {
 	*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
@@ -1118,7 +1126,8 @@ ehl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, int type, int rate,
 }
 
 static const struct cnl_ddi_buf_trans *
-ehl_get_combo_buf_trans_dp(struct intel_encoder *encoder, int type, int rate,
+ehl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
+			   const struct intel_crtc_state *crtc_state,
 			   int *n_entries)
 {
 	*n_entries = ARRAY_SIZE(ehl_combo_phy_ddi_translations_dp);
@@ -1126,13 +1135,14 @@ ehl_get_combo_buf_trans_dp(struct intel_encoder *encoder, int type, int rate,
 }
 
 static const struct cnl_ddi_buf_trans *
-ehl_get_combo_buf_trans_edp(struct intel_encoder *encoder, int type, int rate,
+ehl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
+			    const struct intel_crtc_state *crtc_state,
 			    int *n_entries)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
 	if (dev_priv->vbt.edp.low_vswing) {
-		if (rate > 540000) {
+		if (crtc_state->port_clock > 540000) {
 			*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
 			return icl_combo_phy_ddi_translations_edp_hbr3;
 		} else {
@@ -1141,23 +1151,25 @@ ehl_get_combo_buf_trans_edp(struct intel_encoder *encoder, int type, int rate,
 		}
 	}
 
-	return ehl_get_combo_buf_trans_dp(encoder, type, rate, n_entries);
+	return ehl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
 }
 
 static const struct cnl_ddi_buf_trans *
-ehl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
+ehl_get_combo_buf_trans(struct intel_encoder *encoder,
+			const struct intel_crtc_state *crtc_state,
 			int *n_entries)
 {
-	if (type == INTEL_OUTPUT_HDMI)
-		return ehl_get_combo_buf_trans_hdmi(encoder, type, rate, n_entries);
-	else if (type == INTEL_OUTPUT_EDP)
-		return ehl_get_combo_buf_trans_edp(encoder, type, rate, n_entries);
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+		return ehl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries);
+	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
+		return ehl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
 	else
-		return ehl_get_combo_buf_trans_dp(encoder, type, rate, n_entries);
+		return ehl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
 }
 
 static const struct cnl_ddi_buf_trans *
-tgl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, int type, int rate,
+tgl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder,
+			     const struct intel_crtc_state *crtc_state,
 			     int *n_entries)
 {
 	*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
@@ -1165,12 +1177,13 @@ tgl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, int type, int rate,
 }
 
 static const struct cnl_ddi_buf_trans *
-tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder, int type, int rate,
+tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
+			   const struct intel_crtc_state *crtc_state,
 			   int *n_entries)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
-	if (rate > 270000) {
+	if (crtc_state->port_clock > 270000) {
 		if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
 			*n_entries = ARRAY_SIZE(tgl_uy_combo_phy_ddi_translations_dp_hbr2);
 			return tgl_uy_combo_phy_ddi_translations_dp_hbr2;
@@ -1185,13 +1198,14 @@ tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder, int type, int rate,
 }
 
 static const struct cnl_ddi_buf_trans *
-tgl_get_combo_buf_trans_edp(struct intel_encoder *encoder, int type, int rate,
+tgl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
+			    const struct intel_crtc_state *crtc_state,
 			    int *n_entries)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 
-	if (rate > 540000) {
+	if (crtc_state->port_clock > 540000) {
 		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
 		return icl_combo_phy_ddi_translations_edp_hbr3;
 	} else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) {
@@ -1202,23 +1216,25 @@ tgl_get_combo_buf_trans_edp(struct intel_encoder *encoder, int type, int rate,
 		return icl_combo_phy_ddi_translations_edp_hbr2;
 	}
 
-	return tgl_get_combo_buf_trans_dp(encoder, type, rate, n_entries);
+	return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
 }
 
 static const struct cnl_ddi_buf_trans *
-tgl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
+tgl_get_combo_buf_trans(struct intel_encoder *encoder,
+			const struct intel_crtc_state *crtc_state,
 			int *n_entries)
 {
-	if (type == INTEL_OUTPUT_HDMI)
-		return tgl_get_combo_buf_trans_hdmi(encoder, type, rate, n_entries);
-	else if (type == INTEL_OUTPUT_EDP)
-		return tgl_get_combo_buf_trans_edp(encoder, type, rate, n_entries);
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+		return tgl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries);
+	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
+		return tgl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
 	else
-		return tgl_get_combo_buf_trans_dp(encoder, type, rate, n_entries);
+		return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
 }
 
 static const struct tgl_dkl_phy_ddi_buf_trans *
-tgl_get_dkl_buf_trans_hdmi(struct intel_encoder *encoder, int type, int rate,
+tgl_get_dkl_buf_trans_hdmi(struct intel_encoder *encoder,
+			   const struct intel_crtc_state *crtc_state,
 			   int *n_entries)
 {
 	*n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans);
@@ -1226,10 +1242,11 @@ tgl_get_dkl_buf_trans_hdmi(struct intel_encoder *encoder, int type, int rate,
 }
 
 static const struct tgl_dkl_phy_ddi_buf_trans *
-tgl_get_dkl_buf_trans_dp(struct intel_encoder *encoder, int type, int rate,
+tgl_get_dkl_buf_trans_dp(struct intel_encoder *encoder,
+			 const struct intel_crtc_state *crtc_state,
 			 int *n_entries)
 {
-	if (rate > 270000) {
+	if (crtc_state->port_clock > 270000) {
 		*n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans_hbr2);
 		return tgl_dkl_phy_dp_ddi_trans_hbr2;
 	} else {
@@ -1239,16 +1256,18 @@ tgl_get_dkl_buf_trans_dp(struct intel_encoder *encoder, int type, int rate,
 }
 
 static const struct tgl_dkl_phy_ddi_buf_trans *
-tgl_get_dkl_buf_trans(struct intel_encoder *encoder, int type, int rate,
+tgl_get_dkl_buf_trans(struct intel_encoder *encoder,
+		      const struct intel_crtc_state *crtc_state,
 		      int *n_entries)
 {
-	if (type == INTEL_OUTPUT_HDMI)
-		return tgl_get_dkl_buf_trans_hdmi(encoder, type, rate, n_entries);
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+		return tgl_get_dkl_buf_trans_hdmi(encoder, crtc_state, n_entries);
 	else
-		return tgl_get_dkl_buf_trans_dp(encoder, type, rate, n_entries);
+		return tgl_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries);
 }
 
-static int intel_ddi_hdmi_level(struct intel_encoder *encoder)
+static int intel_ddi_hdmi_level(struct intel_encoder *encoder,
+				const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	int n_entries, level, default_entry;
@@ -1256,19 +1275,15 @@ static int intel_ddi_hdmi_level(struct intel_encoder *encoder)
 
 	if (INTEL_GEN(dev_priv) >= 12) {
 		if (intel_phy_is_combo(dev_priv, phy))
-			tgl_get_combo_buf_trans(encoder, INTEL_OUTPUT_HDMI,
-						0, &n_entries);
+			tgl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries);
 		else
-			tgl_get_dkl_buf_trans(encoder, INTEL_OUTPUT_HDMI, 0,
-					      &n_entries);
+			tgl_get_dkl_buf_trans_hdmi(encoder, crtc_state, &n_entries);
 		default_entry = n_entries - 1;
 	} else if (INTEL_GEN(dev_priv) == 11) {
 		if (intel_phy_is_combo(dev_priv, phy))
-			icl_get_combo_buf_trans(encoder, INTEL_OUTPUT_HDMI,
-						0, &n_entries);
+			icl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries);
 		else
-			icl_get_mg_buf_trans(encoder, INTEL_OUTPUT_HDMI, 0,
-					     &n_entries);
+			icl_get_mg_buf_trans_hdmi(encoder, crtc_state, &n_entries);
 		default_entry = n_entries - 1;
 	} else if (IS_CANNONLAKE(dev_priv)) {
 		cnl_get_buf_trans_hdmi(encoder, &n_entries);
@@ -1595,14 +1610,15 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
 		       DP_TP_CTL_ENABLE);
 }
 
-static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
+static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
+				      const struct intel_crtc_state *crtc_state)
 {
 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 
 	intel_dp->DP = dig_port->saved_port_bits |
 		DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
-	intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
+	intel_dp->DP |= DDI_PORT_WIDTH(crtc_state->lane_count);
 }
 
 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
@@ -2266,13 +2282,14 @@ static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
 }
 
 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
-			       int level, enum intel_output_type type)
+			       const struct intel_crtc_state *crtc_state,
+			       int level)
 {
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	u8 iboost;
 
-	if (type == INTEL_OUTPUT_HDMI)
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
 		iboost = intel_bios_hdmi_boost_level(encoder);
 	else
 		iboost = intel_bios_dp_boost_level(encoder);
@@ -2281,14 +2298,12 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder,
 		const struct ddi_buf_trans *ddi_translations;
 		int n_entries;
 
-		if (type == INTEL_OUTPUT_HDMI)
+		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
 			ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
-		else if (type == INTEL_OUTPUT_EDP)
-			ddi_translations = intel_ddi_get_buf_trans_edp(encoder,
-								       &n_entries);
+		else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
+			ddi_translations = intel_ddi_get_buf_trans_edp(encoder, &n_entries);
 		else
-			ddi_translations = intel_ddi_get_buf_trans_dp(encoder,
-								      &n_entries);
+			ddi_translations = intel_ddi_get_buf_trans_dp(encoder, &n_entries);
 
 		if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
 			return;
@@ -2311,16 +2326,17 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder,
 }
 
 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
-				    int level, enum intel_output_type type)
+				    const struct intel_crtc_state *crtc_state,
+				    int level)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	const struct bxt_ddi_buf_trans *ddi_translations;
 	enum port port = encoder->port;
 	int n_entries;
 
-	if (type == INTEL_OUTPUT_HDMI)
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
 		ddi_translations = bxt_get_buf_trans_hdmi(encoder, &n_entries);
-	else if (type == INTEL_OUTPUT_EDP)
+	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 		ddi_translations = bxt_get_buf_trans_edp(encoder, &n_entries);
 	else
 		ddi_translations = bxt_get_buf_trans_dp(encoder, &n_entries);
@@ -2337,7 +2353,8 @@ static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
 				     ddi_translations[level].deemphasis);
 }
 
-static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp)
+static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp,
+				   const struct intel_crtc_state *crtc_state)
 {
 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -2347,33 +2364,28 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp)
 
 	if (INTEL_GEN(dev_priv) >= 12) {
 		if (intel_phy_is_combo(dev_priv, phy))
-			tgl_get_combo_buf_trans(encoder, encoder->type,
-						intel_dp->link_rate, &n_entries);
+			tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
 		else
-			tgl_get_dkl_buf_trans(encoder, encoder->type,
-					      intel_dp->link_rate, &n_entries);
+			tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
 	} else if (INTEL_GEN(dev_priv) == 11) {
 		if (IS_ELKHARTLAKE(dev_priv))
-			ehl_get_combo_buf_trans(encoder, encoder->type,
-						intel_dp->link_rate, &n_entries);
+			ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
 		else if (intel_phy_is_combo(dev_priv, phy))
-			icl_get_combo_buf_trans(encoder, encoder->type,
-						intel_dp->link_rate, &n_entries);
+			icl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
 		else
-			icl_get_mg_buf_trans(encoder, encoder->type,
-					     intel_dp->link_rate, &n_entries);
+			icl_get_mg_buf_trans(encoder, crtc_state, &n_entries);
 	} else if (IS_CANNONLAKE(dev_priv)) {
-		if (encoder->type == INTEL_OUTPUT_EDP)
+		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 			cnl_get_buf_trans_edp(encoder, &n_entries);
 		else
 			cnl_get_buf_trans_dp(encoder, &n_entries);
 	} else if (IS_GEN9_LP(dev_priv)) {
-		if (encoder->type == INTEL_OUTPUT_EDP)
+		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 			bxt_get_buf_trans_edp(encoder, &n_entries);
 		else
 			bxt_get_buf_trans_dp(encoder, &n_entries);
 	} else {
-		if (encoder->type == INTEL_OUTPUT_EDP)
+		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 			intel_ddi_get_buf_trans_edp(encoder, &n_entries);
 		else
 			intel_ddi_get_buf_trans_dp(encoder, &n_entries);
@@ -2400,7 +2412,8 @@ static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp)
 }
 
 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
-				   int level, enum intel_output_type type)
+				   const struct intel_crtc_state *crtc_state,
+				   int level)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	const struct cnl_ddi_buf_trans *ddi_translations;
@@ -2408,9 +2421,9 @@ static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
 	int n_entries, ln;
 	u32 val;
 
-	if (type == INTEL_OUTPUT_HDMI)
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
 		ddi_translations = cnl_get_buf_trans_hdmi(encoder, &n_entries);
-	else if (type == INTEL_OUTPUT_EDP)
+	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 		ddi_translations = cnl_get_buf_trans_edp(encoder, &n_entries);
 	else
 		ddi_translations = cnl_get_buf_trans_dp(encoder, &n_entries);
@@ -2464,22 +2477,16 @@ static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
 }
 
 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
-				    int level, enum intel_output_type type)
+				    const struct intel_crtc_state *crtc_state,
+				    int level)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum port port = encoder->port;
 	int width, rate, ln;
 	u32 val;
 
-	if (type == INTEL_OUTPUT_HDMI) {
-		width = 4;
-		rate = 0; /* Rate is always < than 6GHz for HDMI */
-	} else {
-		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-
-		width = intel_dp->lane_count;
-		rate = intel_dp->link_rate;
-	}
+	width = crtc_state->lane_count;
+	rate = crtc_state->port_clock;
 
 	/*
 	 * 1. If port type is eDP or DP,
@@ -2487,10 +2494,10 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
 	 * else clear to 0b.
 	 */
 	val = intel_de_read(dev_priv, CNL_PORT_PCS_DW1_LN0(port));
-	if (type != INTEL_OUTPUT_HDMI)
-		val |= COMMON_KEEPER_EN;
-	else
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
 		val &= ~COMMON_KEEPER_EN;
+	else
+		val |= COMMON_KEEPER_EN;
 	intel_de_write(dev_priv, CNL_PORT_PCS_DW1_GRP(port), val);
 
 	/* 2. Program loadgen select */
@@ -2522,7 +2529,7 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
 	intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
 
 	/* 5. Program swing and de-emphasis */
-	cnl_ddi_vswing_program(encoder, level, type);
+	cnl_ddi_vswing_program(encoder, crtc_state, level);
 
 	/* 6. Set training enable to trigger update */
 	val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
@@ -2531,23 +2538,21 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
 }
 
 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
-					 u32 level, int type, int rate)
+					 const struct intel_crtc_state *crtc_state,
+					 int level)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	const struct cnl_ddi_buf_trans *ddi_translations;
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
-	const struct cnl_ddi_buf_trans *ddi_translations = NULL;
-	u32 n_entries, val;
-	int ln;
+	int n_entries, ln;
+	u32 val;
 
 	if (INTEL_GEN(dev_priv) >= 12)
-		ddi_translations = tgl_get_combo_buf_trans(encoder, type, rate,
-							   &n_entries);
+		ddi_translations = tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
 	else if (IS_ELKHARTLAKE(dev_priv))
-		ddi_translations = ehl_get_combo_buf_trans(encoder, type, rate,
-							   &n_entries);
+		ddi_translations = ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
 	else
-		ddi_translations = icl_get_combo_buf_trans(encoder, type, rate,
-							   &n_entries);
+		ddi_translations = icl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
 	if (!ddi_translations)
 		return;
 
@@ -2558,7 +2563,7 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
 		level = n_entries - 1;
 	}
 
-	if (type == INTEL_OUTPUT_EDP) {
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
 		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 
 		val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED;
@@ -2606,25 +2611,16 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
 }
 
 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
-					      u32 level,
-					      enum intel_output_type type)
+					      const struct intel_crtc_state *crtc_state,
+					      int level)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
-	int width = 0;
-	int rate = 0;
+	int width, rate, ln;
 	u32 val;
-	int ln = 0;
 
-	if (type == INTEL_OUTPUT_HDMI) {
-		width = 4;
-		/* Rate is always < than 6GHz for HDMI */
-	} else {
-		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-
-		width = intel_dp->lane_count;
-		rate = intel_dp->link_rate;
-	}
+	width = crtc_state->lane_count;
+	rate = crtc_state->port_clock;
 
 	/*
 	 * 1. If port type is eDP or DP,
@@ -2632,7 +2628,7 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
 	 * else clear to 0b.
 	 */
 	val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy));
-	if (type == INTEL_OUTPUT_HDMI)
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
 		val &= ~COMMON_KEEPER_EN;
 	else
 		val |= COMMON_KEEPER_EN;
@@ -2667,7 +2663,7 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
 	intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
 
 	/* 5. Program swing and de-emphasis */
-	icl_ddi_combo_vswing_program(encoder, level, type, rate);
+	icl_ddi_combo_vswing_program(encoder, crtc_state, level);
 
 	/* 6. Set training enable to trigger update */
 	val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
@@ -2676,23 +2672,16 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
 }
 
 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
-					   int link_clock, u32 level,
-					   enum intel_output_type type)
+					   const struct intel_crtc_state *crtc_state,
+					   int level)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
 	const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
-	u32 n_entries, val;
-	int ln, rate = 0;
+	int n_entries, ln;
+	u32 val;
 
-	if (type != INTEL_OUTPUT_HDMI) {
-		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-
-		rate = intel_dp->link_rate;
-	}
-
-	ddi_translations = icl_get_mg_buf_trans(encoder, type, rate,
-						&n_entries);
+	ddi_translations = icl_get_mg_buf_trans(encoder, crtc_state, &n_entries);
 	/* The table does not have values for level 3 and level 9. */
 	if (level >= n_entries || level == 3 || level == 9) {
 		drm_dbg_kms(&dev_priv->drm,
@@ -2759,7 +2748,7 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
 	 */
 	for (ln = 0; ln < 2; ln++) {
 		val = intel_de_read(dev_priv, MG_CLKHUB(ln, tc_port));
-		if (link_clock < 300000)
+		if (crtc_state->port_clock < 300000)
 			val |= CFG_LOW_RATE_LKREN_EN;
 		else
 			val &= ~CFG_LOW_RATE_LKREN_EN;
@@ -2770,7 +2759,7 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
 	for (ln = 0; ln < 2; ln++) {
 		val = intel_de_read(dev_priv, MG_TX1_DCC(ln, tc_port));
 		val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
-		if (link_clock <= 500000) {
+		if (crtc_state->port_clock <= 500000) {
 			val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
 		} else {
 			val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
@@ -2780,7 +2769,7 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
 
 		val = intel_de_read(dev_priv, MG_TX2_DCC(ln, tc_port));
 		val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
-		if (link_clock <= 500000) {
+		if (crtc_state->port_clock <= 500000) {
 			val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
 		} else {
 			val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
@@ -2806,38 +2795,30 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
 }
 
 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
-				    int link_clock,
-				    u32 level,
-				    enum intel_output_type type)
+				    const struct intel_crtc_state *crtc_state,
+				    int level)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 
 	if (intel_phy_is_combo(dev_priv, phy))
-		icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
+		icl_combo_phy_ddi_vswing_sequence(encoder, crtc_state, level);
 	else
-		icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level,
-					       type);
+		icl_mg_phy_ddi_vswing_sequence(encoder, crtc_state, level);
 }
 
 static void
-tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock,
-				u32 level, enum intel_output_type type)
+tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
+				const struct intel_crtc_state *crtc_state,
+				int level)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
 	const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations;
-	u32 n_entries, val, ln, dpcnt_mask, dpcnt_val;
-	int rate = 0;
+	u32 val, dpcnt_mask, dpcnt_val;
+	int n_entries, ln;
 
-	if (type == INTEL_OUTPUT_HDMI) {
-		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-
-		rate = intel_dp->link_rate;
-	}
-
-	ddi_translations = tgl_get_dkl_buf_trans(encoder, encoder->type, rate,
-						 &n_entries);
+	ddi_translations = tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
 
 	if (level >= n_entries)
 		level = n_entries - 1;
@@ -2873,20 +2854,20 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock,
 }
 
 static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder,
-				    int link_clock,
-				    u32 level,
-				    enum intel_output_type type)
+				    const struct intel_crtc_state *crtc_state,
+				    int level)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 
 	if (intel_phy_is_combo(dev_priv, phy))
-		icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
+		icl_combo_phy_ddi_vswing_sequence(encoder, crtc_state, level);
 	else
-		tgl_dkl_phy_ddi_vswing_sequence(encoder, link_clock, level, type);
+		tgl_dkl_phy_ddi_vswing_sequence(encoder, crtc_state, level);
 }
 
-static u32 translate_signal_level(struct intel_dp *intel_dp, int signal_levels)
+static int translate_signal_level(struct intel_dp *intel_dp,
+				  u8 signal_levels)
 {
 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 	int i;
@@ -2903,55 +2884,58 @@ static u32 translate_signal_level(struct intel_dp *intel_dp, int signal_levels)
 	return 0;
 }
 
-static u32 intel_ddi_dp_level(struct intel_dp *intel_dp)
+static int intel_ddi_dp_level(struct intel_dp *intel_dp)
 {
 	u8 train_set = intel_dp->train_set[0];
-	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
-					 DP_TRAIN_PRE_EMPHASIS_MASK);
+	u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
+					DP_TRAIN_PRE_EMPHASIS_MASK);
 
 	return translate_signal_level(intel_dp, signal_levels);
 }
 
 static void
-tgl_set_signal_levels(struct intel_dp *intel_dp)
+tgl_set_signal_levels(struct intel_dp *intel_dp,
+		      const struct intel_crtc_state *crtc_state)
 {
 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 	int level = intel_ddi_dp_level(intel_dp);
 
-	tgl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
-				level, encoder->type);
+	tgl_ddi_vswing_sequence(encoder, crtc_state, level);
 }
 
 static void
-icl_set_signal_levels(struct intel_dp *intel_dp)
+icl_set_signal_levels(struct intel_dp *intel_dp,
+		      const struct intel_crtc_state *crtc_state)
 {
 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 	int level = intel_ddi_dp_level(intel_dp);
 
-	icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
-				level, encoder->type);
+	icl_ddi_vswing_sequence(encoder, crtc_state, level);
 }
 
 static void
-cnl_set_signal_levels(struct intel_dp *intel_dp)
+cnl_set_signal_levels(struct intel_dp *intel_dp,
+		      const struct intel_crtc_state *crtc_state)
 {
 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 	int level = intel_ddi_dp_level(intel_dp);
 
-	cnl_ddi_vswing_sequence(encoder, level, encoder->type);
+	cnl_ddi_vswing_sequence(encoder, crtc_state, level);
 }
 
 static void
-bxt_set_signal_levels(struct intel_dp *intel_dp)
+bxt_set_signal_levels(struct intel_dp *intel_dp,
+		      const struct intel_crtc_state *crtc_state)
 {
 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 	int level = intel_ddi_dp_level(intel_dp);
 
-	bxt_ddi_vswing_sequence(encoder, level, encoder->type);
+	bxt_ddi_vswing_sequence(encoder, crtc_state, level);
 }
 
 static void
-hsw_set_signal_levels(struct intel_dp *intel_dp)
+hsw_set_signal_levels(struct intel_dp *intel_dp,
+		      const struct intel_crtc_state *crtc_state)
 {
 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -2968,7 +2952,7 @@ hsw_set_signal_levels(struct intel_dp *intel_dp)
 	intel_dp->DP |= signal_levels;
 
 	if (IS_GEN9_BC(dev_priv))
-		skl_ddi_set_iboost(encoder, level, encoder->type);
+		skl_ddi_set_iboost(encoder, crtc_state, level);
 
 	intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
 	intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
@@ -3375,8 +3359,9 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
 	int level = intel_ddi_dp_level(intel_dp);
 	enum transcoder transcoder = crtc_state->cpu_transcoder;
 
-	intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
-				 crtc_state->lane_count, is_mst);
+	intel_dp_set_link_params(intel_dp,
+				 crtc_state->port_clock,
+				 crtc_state->lane_count);
 
 	intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder);
 	intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder);
@@ -3448,8 +3433,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
 	 */
 
 	/* 7.e Configure voltage swing and related IO settings */
-	tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level,
-				encoder->type);
+	tgl_ddi_vswing_sequence(encoder, crtc_state, level);
 
 	/*
 	 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up
@@ -3472,7 +3456,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
 	 * We only configure what the register value will be here.  Actual
 	 * enabling happens during link training farther down.
 	 */
-	intel_ddi_init_dp_buf_reg(encoder);
+	intel_ddi_init_dp_buf_reg(encoder, crtc_state);
 
 	if (!is_mst)
 		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
@@ -3492,11 +3476,11 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
 	 *     Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
 	 *     (timeout after 800 us)
 	 */
-	intel_dp_start_link_train(intel_dp);
+	intel_dp_start_link_train(intel_dp, crtc_state);
 
 	/* 7.k Set DP_TP_CTL link training to Normal */
 	if (!is_trans_port_sync_mode(crtc_state))
-		intel_dp_stop_link_train(intel_dp);
+		intel_dp_stop_link_train(intel_dp, crtc_state);
 
 	/* 7.l Configure and enable FEC if needed */
 	intel_ddi_enable_fec(encoder, crtc_state);
@@ -3522,8 +3506,9 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
 	else
 		drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A);
 
-	intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
-				 crtc_state->lane_count, is_mst);
+	intel_dp_set_link_params(intel_dp,
+				 crtc_state->port_clock,
+				 crtc_state->lane_count);
 
 	intel_edp_panel_on(intel_dp);
 
@@ -3537,12 +3522,11 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
 	icl_program_mg_dp_mode(dig_port, crtc_state);
 
 	if (INTEL_GEN(dev_priv) >= 11)
-		icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
-					level, encoder->type);
+		icl_ddi_vswing_sequence(encoder, crtc_state, level);
 	else if (IS_CANNONLAKE(dev_priv))
-		cnl_ddi_vswing_sequence(encoder, level, encoder->type);
+		cnl_ddi_vswing_sequence(encoder, crtc_state, level);
 	else if (IS_GEN9_LP(dev_priv))
-		bxt_ddi_vswing_sequence(encoder, level, encoder->type);
+		bxt_ddi_vswing_sequence(encoder, crtc_state, level);
 	else
 		intel_prepare_dp_ddi_buffers(encoder, crtc_state);
 
@@ -3555,17 +3539,17 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
 					       lane_reversal);
 	}
 
-	intel_ddi_init_dp_buf_reg(encoder);
+	intel_ddi_init_dp_buf_reg(encoder, crtc_state);
 	if (!is_mst)
 		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
 	intel_dp_configure_protocol_converter(intel_dp);
 	intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
 					      true);
 	intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
-	intel_dp_start_link_train(intel_dp);
+	intel_dp_start_link_train(intel_dp, crtc_state);
 	if ((port != PORT_A || INTEL_GEN(dev_priv) >= 9) &&
 	    !is_trans_port_sync_mode(crtc_state))
-		intel_dp_stop_link_train(intel_dp);
+		intel_dp_stop_link_train(intel_dp, crtc_state);
 
 	intel_ddi_enable_fec(encoder, crtc_state);
 
@@ -3605,7 +3589,7 @@ static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state,
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 	struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	int level = intel_ddi_hdmi_level(encoder);
+	int level = intel_ddi_hdmi_level(encoder, crtc_state);
 
 	intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
 	intel_ddi_clk_select(encoder, crtc_state);
@@ -3615,20 +3599,18 @@ static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state,
 	icl_program_mg_dp_mode(dig_port, crtc_state);
 
 	if (INTEL_GEN(dev_priv) >= 12)
-		tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
-					level, INTEL_OUTPUT_HDMI);
+		tgl_ddi_vswing_sequence(encoder, crtc_state, level);
 	else if (INTEL_GEN(dev_priv) == 11)
-		icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
-					level, INTEL_OUTPUT_HDMI);
+		icl_ddi_vswing_sequence(encoder, crtc_state, level);
 	else if (IS_CANNONLAKE(dev_priv))
-		cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
+		cnl_ddi_vswing_sequence(encoder, crtc_state, level);
 	else if (IS_GEN9_LP(dev_priv))
-		bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
+		bxt_ddi_vswing_sequence(encoder, crtc_state, level);
 	else
 		intel_prepare_hdmi_ddi_buffers(encoder, level);
 
 	if (IS_GEN9_BC(dev_priv))
-		skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
+		skl_ddi_set_iboost(encoder, crtc_state, level);
 
 	intel_ddi_enable_pipe_clock(encoder, crtc_state);
 
@@ -3918,12 +3900,14 @@ static void trans_port_sync_stop_link_train(struct intel_atomic_state *state,
 		    crtc_state->cpu_transcoder)
 			continue;
 
-		intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder));
+		intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder),
+					 slave_crtc_state);
 	}
 
 	usleep_range(200, 400);
 
-	intel_dp_stop_link_train(enc_to_intel_dp(encoder));
+	intel_dp_stop_link_train(enc_to_intel_dp(encoder),
+				 crtc_state);
 }
 
 static void intel_enable_ddi_dp(struct intel_atomic_state *state,
@@ -3936,7 +3920,7 @@ static void intel_enable_ddi_dp(struct intel_atomic_state *state,
 	enum port port = encoder->port;
 
 	if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
-		intel_dp_stop_link_train(intel_dp);
+		intel_dp_stop_link_train(intel_dp, crtc_state);
 
 	intel_edp_backlight_on(crtc_state, conn_state);
 	intel_psr_enable(intel_dp, crtc_state, conn_state);
@@ -4197,7 +4181,8 @@ intel_ddi_pre_pll_enable(struct intel_atomic_state *state,
 						crtc_state->lane_lat_optim_mask);
 }
 
-static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
+static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
+					   const struct intel_crtc_state *crtc_state)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
@@ -4224,10 +4209,11 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
 			intel_wait_ddi_buf_idle(dev_priv, port);
 	}
 
-	dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1;
-	if (intel_dp->link_mst)
+	dp_tp_ctl = DP_TP_CTL_ENABLE |
+		    DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
 		dp_tp_ctl |= DP_TP_CTL_MODE_MST;
-	else {
+	} else {
 		dp_tp_ctl |= DP_TP_CTL_MODE_SST;
 		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
 			dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
@@ -4243,6 +4229,7 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
 }
 
 static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
+				     const struct intel_crtc_state *crtc_state,
 				     u8 dp_train_pat)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -4273,7 +4260,8 @@ static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
 	intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, temp);
 }
 
-static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp)
+static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp,
+					  const struct intel_crtc_state *crtc_state)
 {
 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h
index f5fb62fc9400..9a2ac73164f8 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi.h
@@ -41,8 +41,10 @@ void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
 				    bool state);
 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
 					 struct intel_crtc_state *crtc_state);
-u32 bxt_signal_levels(struct intel_dp *intel_dp);
-u32 ddi_signal_levels(struct intel_dp *intel_dp);
+u32 bxt_signal_levels(struct intel_dp *intel_dp,
+		      const struct intel_crtc_state *crtc_state);
+u32 ddi_signal_levels(struct intel_dp *intel_dp,
+		      const struct intel_crtc_state *crtc_state);
 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
 				     enum transcoder cpu_transcoder,
 				     bool enable);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index e3339e41ddf7..66d197153c93 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1273,7 +1273,6 @@ struct intel_dp {
 	int link_rate;
 	u8 lane_count;
 	u8 sink_count;
-	bool link_mst;
 	bool link_trained;
 	bool has_hdmi_sink;
 	bool has_audio;
@@ -1366,13 +1365,19 @@ struct intel_dp {
 	i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
 
 	/* This is called before a link training is starterd */
-	void (*prepare_link_retrain)(struct intel_dp *intel_dp);
-	void (*set_link_train)(struct intel_dp *intel_dp, u8 dp_train_pat);
-	void (*set_idle_link_train)(struct intel_dp *intel_dp);
-	void (*set_signal_levels)(struct intel_dp *intel_dp);
+	void (*prepare_link_retrain)(struct intel_dp *intel_dp,
+				     const struct intel_crtc_state *crtc_state);
+	void (*set_link_train)(struct intel_dp *intel_dp,
+			       const struct intel_crtc_state *crtc_state,
+			       u8 dp_train_pat);
+	void (*set_idle_link_train)(struct intel_dp *intel_dp,
+				    const struct intel_crtc_state *crtc_state);
+	void (*set_signal_levels)(struct intel_dp *intel_dp,
+				  const struct intel_crtc_state *crtc_state);
 
 	u8 (*preemph_max)(struct intel_dp *intel_dp);
-	u8 (*voltage_max)(struct intel_dp *intel_dp);
+	u8 (*voltage_max)(struct intel_dp *intel_dp,
+			  const struct intel_crtc_state *crtc_state);
 
 	/* Displayport compliance testing */
 	struct intel_dp_compliance compliance;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 6718e01909cd..5ac8a06575d4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2799,13 +2799,11 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 }
 
 void intel_dp_set_link_params(struct intel_dp *intel_dp,
-			      int link_rate, u8 lane_count,
-			      bool link_mst)
+			      int link_rate, int lane_count)
 {
 	intel_dp->link_trained = false;
 	intel_dp->link_rate = link_rate;
 	intel_dp->lane_count = lane_count;
-	intel_dp->link_mst = link_mst;
 }
 
 static void intel_dp_prepare(struct intel_encoder *encoder,
@@ -2817,10 +2815,9 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
 
-	intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
-				 pipe_config->lane_count,
-				 intel_crtc_has_type(pipe_config,
-						     INTEL_OUTPUT_DP_MST));
+	intel_dp_set_link_params(intel_dp,
+				 pipe_config->port_clock,
+				 pipe_config->lane_count);
 
 	/*
 	 * There are four kinds of DP registers:
@@ -3791,6 +3788,7 @@ static void chv_post_disable_dp(struct intel_atomic_state *state,
 
 static void
 cpt_set_link_train(struct intel_dp *intel_dp,
+		   const struct intel_crtc_state *crtc_state,
 		   u8 dp_train_pat)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -3821,6 +3819,7 @@ cpt_set_link_train(struct intel_dp *intel_dp,
 
 static void
 g4x_set_link_train(struct intel_dp *intel_dp,
+		   const struct intel_crtc_state *crtc_state,
 		   u8 dp_train_pat)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -3856,7 +3855,8 @@ static void intel_dp_enable_port(struct intel_dp *intel_dp,
 
 	/* enable with pattern 1 (as per spec) */
 
-	intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
+	intel_dp_program_link_training_pattern(intel_dp, crtc_state,
+					       DP_TRAINING_PATTERN_1);
 
 	/*
 	 * Magic for VLV/CHV. We _must_ first set up the register
@@ -3947,8 +3947,8 @@ static void intel_enable_dp(struct intel_atomic_state *state,
 
 	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
 	intel_dp_configure_protocol_converter(intel_dp);
-	intel_dp_start_link_train(intel_dp);
-	intel_dp_stop_link_train(intel_dp);
+	intel_dp_start_link_train(intel_dp, pipe_config);
+	intel_dp_stop_link_train(intel_dp, pipe_config);
 
 	if (pipe_config->has_audio) {
 		drm_dbg(&dev_priv->drm, "Enabling DP audio on pipe %c\n",
@@ -4157,12 +4157,14 @@ intel_dp_get_link_status(struct intel_dp *intel_dp, u8 link_status[DP_LINK_STATU
 				DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
 }
 
-static u8 intel_dp_voltage_max_2(struct intel_dp *intel_dp)
+static u8 intel_dp_voltage_max_2(struct intel_dp *intel_dp,
+				 const struct intel_crtc_state *crtc_state)
 {
 	return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
 }
 
-static u8 intel_dp_voltage_max_3(struct intel_dp *intel_dp)
+static u8 intel_dp_voltage_max_3(struct intel_dp *intel_dp,
+				 const struct intel_crtc_state *crtc_state)
 {
 	return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
 }
@@ -4177,7 +4179,8 @@ static u8 intel_dp_preemph_max_3(struct intel_dp *intel_dp)
 	return DP_TRAIN_PRE_EMPH_LEVEL_3;
 }
 
-static void vlv_set_signal_levels(struct intel_dp *intel_dp)
+static void vlv_set_signal_levels(struct intel_dp *intel_dp,
+				  const struct intel_crtc_state *crtc_state)
 {
 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 	unsigned long demph_reg_value, preemph_reg_value,
@@ -4257,11 +4260,13 @@ static void vlv_set_signal_levels(struct intel_dp *intel_dp)
 		return;
 	}
 
-	vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
+	vlv_set_phy_signal_level(encoder, crtc_state,
+				 demph_reg_value, preemph_reg_value,
 				 uniqtranscale_reg_value, 0);
 }
 
-static void chv_set_signal_levels(struct intel_dp *intel_dp)
+static void chv_set_signal_levels(struct intel_dp *intel_dp,
+				  const struct intel_crtc_state *crtc_state)
 {
 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 	u32 deemph_reg_value, margin_reg_value;
@@ -4338,8 +4343,9 @@ static void chv_set_signal_levels(struct intel_dp *intel_dp)
 		return;
 	}
 
-	chv_set_phy_signal_level(encoder, deemph_reg_value,
-				 margin_reg_value, uniq_trans_scale);
+	chv_set_phy_signal_level(encoder, crtc_state,
+				 deemph_reg_value, margin_reg_value,
+				 uniq_trans_scale);
 }
 
 static u32 g4x_signal_levels(u8 train_set)
@@ -4380,7 +4386,8 @@ static u32 g4x_signal_levels(u8 train_set)
 }
 
 static void
-g4x_set_signal_levels(struct intel_dp *intel_dp)
+g4x_set_signal_levels(struct intel_dp *intel_dp,
+		      const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	u8 train_set = intel_dp->train_set[0];
@@ -4427,7 +4434,8 @@ static u32 snb_cpu_edp_signal_levels(u8 train_set)
 }
 
 static void
-snb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp)
+snb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp,
+			      const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	u8 train_set = intel_dp->train_set[0];
@@ -4478,7 +4486,8 @@ static u32 ivb_cpu_edp_signal_levels(u8 train_set)
 }
 
 static void
-ivb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp)
+ivb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp,
+			      const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	u8 train_set = intel_dp->train_set[0];
@@ -4496,7 +4505,8 @@ ivb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp)
 	intel_de_posting_read(dev_priv, intel_dp->output_reg);
 }
 
-void intel_dp_set_signal_levels(struct intel_dp *intel_dp)
+void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
+				const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	u8 train_set = intel_dp->train_set[0];
@@ -4510,11 +4520,12 @@ void intel_dp_set_signal_levels(struct intel_dp *intel_dp)
 		    train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ?
 		    " (max)" : "");
 
-	intel_dp->set_signal_levels(intel_dp);
+	intel_dp->set_signal_levels(intel_dp, crtc_state);
 }
 
 void
 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
+				       const struct intel_crtc_state *crtc_state,
 				       u8 dp_train_pat)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -4525,13 +4536,14 @@ intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
 			    "Using DP training pattern TPS%d\n",
 			    dp_train_pat & train_pat_mask);
 
-	intel_dp->set_link_train(intel_dp, dp_train_pat);
+	intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat);
 }
 
-void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
+void intel_dp_set_idle_link_train(struct intel_dp *intel_dp,
+				  const struct intel_crtc_state *crtc_state)
 {
 	if (intel_dp->set_idle_link_train)
-		intel_dp->set_idle_link_train(intel_dp);
+		intel_dp->set_idle_link_train(intel_dp, crtc_state);
 }
 
 static void
@@ -5424,14 +5436,14 @@ static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
 	return test_result;
 }
 
-static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
+static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,
+					const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv =
 			to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
-	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_dp_phy_test_params *data =
 			&intel_dp->compliance.test_data.phytest;
-	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum pipe pipe = crtc->pipe;
 	u32 pattern_val;
 
@@ -5491,7 +5503,8 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
 }
 
 static void
-intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp)
+intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp,
+				  const struct intel_crtc_state *crtc_state)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_device *dev = dig_port->base.base.dev;
@@ -5517,7 +5530,8 @@ intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp)
 }
 
 static void
-intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, uint8_t lane_cnt)
+intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp,
+				 const struct intel_crtc_state *crtc_state)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_device *dev = dig_port->base.base.dev;
@@ -5543,7 +5557,8 @@ intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, uint8_t lane_cnt)
 		       trans_ddi_func_ctl_value);
 }
 
-static void intel_dp_process_phy_request(struct intel_dp *intel_dp)
+static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
+					 const struct intel_crtc_state *crtc_state)
 {
 	struct drm_dp_phy_test_params *data =
 		&intel_dp->compliance.test_data.phytest;
@@ -5555,15 +5570,15 @@ static void intel_dp_process_phy_request(struct intel_dp *intel_dp)
 	}
 
 	/* retrieve vswing & pre-emphasis setting */
-	intel_dp_get_adjust_train(intel_dp, link_status);
+	intel_dp_get_adjust_train(intel_dp, crtc_state, link_status);
 
-	intel_dp_autotest_phy_ddi_disable(intel_dp);
+	intel_dp_autotest_phy_ddi_disable(intel_dp, crtc_state);
 
-	intel_dp_set_signal_levels(intel_dp);
+	intel_dp_set_signal_levels(intel_dp, crtc_state);
 
-	intel_dp_phy_pattern_update(intel_dp);
+	intel_dp_phy_pattern_update(intel_dp, crtc_state);
 
-	intel_dp_autotest_phy_ddi_enable(intel_dp, data->num_lanes);
+	intel_dp_autotest_phy_ddi_enable(intel_dp, crtc_state);
 
 	drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
 				    link_status[DP_DPCD_REV]);
@@ -5719,6 +5734,10 @@ intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
 	/*
 	 * Validate the cached values of intel_dp->link_rate and
 	 * intel_dp->lane_count before attempting to retrain.
+	 *
+	 * FIXME would be nice to user the crtc state here, but since
+	 * we need to call this from the short HPD handler that seems
+	 * a bit hard.
 	 */
 	if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
 					intel_dp->lane_count))
@@ -5852,8 +5871,20 @@ int intel_dp_retrain_link(struct intel_encoder *encoder,
 							      intel_crtc_pch_transcoder(crtc), false);
 	}
 
-	intel_dp_start_link_train(intel_dp);
-	intel_dp_stop_link_train(intel_dp);
+	for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
+		const struct intel_crtc_state *crtc_state =
+			to_intel_crtc_state(crtc->base.state);
+
+		/* retrain on the MST master transcoder */
+		if (INTEL_GEN(dev_priv) >= 12 &&
+		    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
+		    crtc_state->cpu_transcoder != crtc_state->mst_master_transcoder)
+			continue;
+
+		intel_dp_start_link_train(intel_dp, crtc_state);
+		intel_dp_stop_link_train(intel_dp, crtc_state);
+		break;
+	}
 
 	for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
 		const struct intel_crtc_state *crtc_state =
@@ -5923,6 +5954,7 @@ static int intel_dp_do_phy_test(struct intel_encoder *encoder,
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+	struct intel_crtc *crtc;
 	u32 crtc_mask;
 	int ret;
 
@@ -5940,7 +5972,20 @@ static int intel_dp_do_phy_test(struct intel_encoder *encoder,
 
 	drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n",
 		    encoder->base.base.id, encoder->base.name);
-	intel_dp_process_phy_request(intel_dp);
+
+	for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
+		const struct intel_crtc_state *crtc_state =
+			to_intel_crtc_state(crtc->base.state);
+
+		/* test on the MST master transcoder */
+		if (INTEL_GEN(dev_priv) >= 12 &&
+		    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
+		    crtc_state->cpu_transcoder != crtc_state->mst_master_transcoder)
+			continue;
+
+		intel_dp_process_phy_request(intel_dp, crtc_state);
+		break;
+	}
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 60f44f41fd08..66854aab9887 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -45,8 +45,7 @@ bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
 bool intel_dp_init_connector(struct intel_digital_port *dig_port,
 			     struct intel_connector *intel_connector);
 void intel_dp_set_link_params(struct intel_dp *intel_dp,
-			      int link_rate, u8 lane_count,
-			      bool link_mst);
+			      int link_rate, int lane_count);
 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 					    int link_rate, u8 lane_count);
 int intel_dp_retrain_link(struct intel_encoder *encoder,
@@ -93,10 +92,13 @@ void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
 
 void
 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
+				       const struct intel_crtc_state *crtc_state,
 				       u8 dp_train_pat);
 void
-intel_dp_set_signal_levels(struct intel_dp *intel_dp);
-void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
+intel_dp_set_signal_levels(struct intel_dp *intel_dp,
+			   const struct intel_crtc_state *crtc_state);
+void intel_dp_set_idle_link_train(struct intel_dp *intel_dp,
+				  const struct intel_crtc_state *crtc_state);
 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
 			   u8 *link_bw, u8 *rate_select);
 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index f2c8b56be9ea..51e8d46d9b7f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -49,8 +49,10 @@ static u8 dp_voltage_max(u8 preemph)
 	}
 }
 
-void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
-			       const u8 link_status[DP_LINK_STATUS_SIZE])
+void
+intel_dp_get_adjust_train(struct intel_dp *intel_dp,
+			  const struct intel_crtc_state *crtc_state,
+			  const u8 link_status[DP_LINK_STATUS_SIZE])
 {
 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 	u8 v = 0;
@@ -59,7 +61,7 @@ void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
 	u8 voltage_max;
 	u8 preemph_max;
 
-	for (lane = 0; lane < intel_dp->lane_count; lane++) {
+	for (lane = 0; lane < crtc_state->lane_count; lane++) {
 		v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane));
 		p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane));
 	}
@@ -74,7 +76,7 @@ void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
 
 	v = min(v, dp_voltage_max(p));
 
-	voltage_max = intel_dp->voltage_max(intel_dp);
+	voltage_max = intel_dp->voltage_max(intel_dp, crtc_state);
 	drm_WARN_ON_ONCE(&i915->drm,
 			 voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_2 &&
 			 voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_3);
@@ -88,12 +90,14 @@ void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
 
 static bool
 intel_dp_set_link_train(struct intel_dp *intel_dp,
+			const struct intel_crtc_state *crtc_state,
 			u8 dp_train_pat)
 {
 	u8 buf[sizeof(intel_dp->train_set) + 1];
 	int ret, len;
 
-	intel_dp_program_link_training_pattern(intel_dp, dp_train_pat);
+	intel_dp_program_link_training_pattern(intel_dp, crtc_state,
+					       dp_train_pat);
 
 	buf[0] = dp_train_pat;
 	if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
@@ -102,8 +106,8 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
 		len = 1;
 	} else {
 		/* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
-		memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
-		len = intel_dp->lane_count + 1;
+		memcpy(buf + 1, intel_dp->train_set, crtc_state->lane_count);
+		len = crtc_state->lane_count + 1;
 	}
 
 	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
@@ -114,31 +118,34 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
 
 static bool
 intel_dp_reset_link_train(struct intel_dp *intel_dp,
-			u8 dp_train_pat)
+			  const struct intel_crtc_state *crtc_state,
+			  u8 dp_train_pat)
 {
 	memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
-	intel_dp_set_signal_levels(intel_dp);
-	return intel_dp_set_link_train(intel_dp, dp_train_pat);
+	intel_dp_set_signal_levels(intel_dp, crtc_state);
+	return intel_dp_set_link_train(intel_dp, crtc_state, dp_train_pat);
 }
 
 static bool
-intel_dp_update_link_train(struct intel_dp *intel_dp)
+intel_dp_update_link_train(struct intel_dp *intel_dp,
+			   const struct intel_crtc_state *crtc_state)
 {
 	int ret;
 
-	intel_dp_set_signal_levels(intel_dp);
+	intel_dp_set_signal_levels(intel_dp, crtc_state);
 
 	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
-				intel_dp->train_set, intel_dp->lane_count);
+				intel_dp->train_set, crtc_state->lane_count);
 
-	return ret == intel_dp->lane_count;
+	return ret == crtc_state->lane_count;
 }
 
-static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp)
+static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,
+					     const struct intel_crtc_state *crtc_state)
 {
 	int lane;
 
-	for (lane = 0; lane < intel_dp->lane_count; lane++)
+	for (lane = 0; lane < crtc_state->lane_count; lane++)
 		if ((intel_dp->train_set[lane] &
 		     DP_TRAIN_MAX_SWING_REACHED) == 0)
 			return false;
@@ -148,7 +155,8 @@ static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp)
 
 /* Enable corresponding port and start training pattern 1 */
 static bool
-intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
+intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
+				      const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 	u8 voltage;
@@ -158,9 +166,9 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
 	u8 link_bw, rate_select;
 
 	if (intel_dp->prepare_link_retrain)
-		intel_dp->prepare_link_retrain(intel_dp);
+		intel_dp->prepare_link_retrain(intel_dp, crtc_state);
 
-	intel_dp_compute_rate(intel_dp, intel_dp->link_rate,
+	intel_dp_compute_rate(intel_dp, crtc_state->port_clock,
 			      &link_bw, &rate_select);
 
 	if (link_bw)
@@ -172,7 +180,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
 
 	/* Write the link configuration data */
 	link_config[0] = link_bw;
-	link_config[1] = intel_dp->lane_count;
+	link_config[1] = crtc_state->lane_count;
 	if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
 		link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 	drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
@@ -189,7 +197,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
 	intel_dp->DP |= DP_PORT_EN;
 
 	/* clock recovery */
-	if (!intel_dp_reset_link_train(intel_dp,
+	if (!intel_dp_reset_link_train(intel_dp, crtc_state,
 				       DP_TRAINING_PATTERN_1 |
 				       DP_LINK_SCRAMBLING_DISABLE)) {
 		drm_err(&i915->drm, "failed to enable link training\n");
@@ -220,7 +228,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
 			return false;
 		}
 
-		if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
+		if (drm_dp_clock_recovery_ok(link_status, crtc_state->lane_count)) {
 			drm_dbg_kms(&i915->drm, "clock recovery OK\n");
 			return true;
 		}
@@ -239,8 +247,8 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
 		voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
 
 		/* Update training set as requested by target */
-		intel_dp_get_adjust_train(intel_dp, link_status);
-		if (!intel_dp_update_link_train(intel_dp)) {
+		intel_dp_get_adjust_train(intel_dp, crtc_state, link_status);
+		if (!intel_dp_update_link_train(intel_dp, crtc_state)) {
 			drm_err(&i915->drm,
 				"failed to update link training\n");
 			return false;
@@ -252,7 +260,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
 		else
 			voltage_tries = 1;
 
-		if (intel_dp_link_max_vswing_reached(intel_dp))
+		if (intel_dp_link_max_vswing_reached(intel_dp, crtc_state))
 			max_vswing_reached = true;
 
 	}
@@ -266,7 +274,8 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
  * or for 1.4 devices that support it, training Pattern 3 for HBR2
  * or 1.2 devices that support it, Training Pattern 2 otherwise.
  */
-static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
+static u32 intel_dp_training_pattern(struct intel_dp *intel_dp,
+				     const struct intel_crtc_state *crtc_state)
 {
 	bool source_tps3, sink_tps3, source_tps4, sink_tps4;
 
@@ -280,7 +289,7 @@ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
 	sink_tps4 = drm_dp_tps4_supported(intel_dp->dpcd);
 	if (source_tps4 && sink_tps4) {
 		return DP_TRAINING_PATTERN_4;
-	} else if (intel_dp->link_rate == 810000) {
+	} else if (crtc_state->port_clock == 810000) {
 		if (!source_tps4)
 			drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
 				    "8.1 Gbps link rate without source HBR3/TPS4 support\n");
@@ -297,7 +306,7 @@ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
 	sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd);
 	if (source_tps3 && sink_tps3) {
 		return  DP_TRAINING_PATTERN_3;
-	} else if (intel_dp->link_rate >= 540000) {
+	} else if (crtc_state->port_clock >= 540000) {
 		if (!source_tps3)
 			drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
 				    ">=5.4/6.48 Gbps link rate without source HBR2/TPS3 support\n");
@@ -310,7 +319,8 @@ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
 }
 
 static bool
-intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
+intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
+					    const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 	int tries;
@@ -318,13 +328,13 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
 	u8 link_status[DP_LINK_STATUS_SIZE];
 	bool channel_eq = false;
 
-	training_pattern = intel_dp_training_pattern(intel_dp);
+	training_pattern = intel_dp_training_pattern(intel_dp, crtc_state);
 	/* Scrambling is disabled for TPS2/3 and enabled for TPS4 */
 	if (training_pattern != DP_TRAINING_PATTERN_4)
 		training_pattern |= DP_LINK_SCRAMBLING_DISABLE;
 
 	/* channel equalization */
-	if (!intel_dp_set_link_train(intel_dp,
+	if (!intel_dp_set_link_train(intel_dp, crtc_state,
 				     training_pattern)) {
 		drm_err(&i915->drm, "failed to start channel equalization\n");
 		return false;
@@ -341,7 +351,7 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
 
 		/* Make sure clock is still ok */
 		if (!drm_dp_clock_recovery_ok(link_status,
-					      intel_dp->lane_count)) {
+					      crtc_state->lane_count)) {
 			intel_dp_dump_link_status(link_status);
 			drm_dbg_kms(&i915->drm,
 				    "Clock recovery check failed, cannot "
@@ -350,7 +360,7 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
 		}
 
 		if (drm_dp_channel_eq_ok(link_status,
-					 intel_dp->lane_count)) {
+					 crtc_state->lane_count)) {
 			channel_eq = true;
 			drm_dbg_kms(&i915->drm, "Channel EQ done. DP Training "
 				    "successful\n");
@@ -358,8 +368,8 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
 		}
 
 		/* Update training set as requested by target */
-		intel_dp_get_adjust_train(intel_dp, link_status);
-		if (!intel_dp_update_link_train(intel_dp)) {
+		intel_dp_get_adjust_train(intel_dp, crtc_state, link_status);
+		if (!intel_dp_update_link_train(intel_dp, crtc_state)) {
 			drm_err(&i915->drm,
 				"failed to update link training\n");
 			break;
@@ -373,35 +383,37 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
 			    "Channel equalization failed 5 times\n");
 	}
 
-	intel_dp_set_idle_link_train(intel_dp);
+	intel_dp_set_idle_link_train(intel_dp, crtc_state);
 
 	return channel_eq;
 
 }
 
-void intel_dp_stop_link_train(struct intel_dp *intel_dp)
+void intel_dp_stop_link_train(struct intel_dp *intel_dp,
+			      const struct intel_crtc_state *crtc_state)
 {
 	intel_dp->link_trained = true;
 
-	intel_dp_set_link_train(intel_dp,
+	intel_dp_set_link_train(intel_dp, crtc_state,
 				DP_TRAINING_PATTERN_DISABLE);
 }
 
 void
-intel_dp_start_link_train(struct intel_dp *intel_dp)
+intel_dp_start_link_train(struct intel_dp *intel_dp,
+			  const struct intel_crtc_state *crtc_state)
 {
 	struct intel_connector *intel_connector = intel_dp->attached_connector;
 
-	if (!intel_dp_link_training_clock_recovery(intel_dp))
+	if (!intel_dp_link_training_clock_recovery(intel_dp, crtc_state))
 		goto failure_handling;
-	if (!intel_dp_link_training_channel_equalization(intel_dp))
+	if (!intel_dp_link_training_channel_equalization(intel_dp, crtc_state))
 		goto failure_handling;
 
 	drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
 		    "[CONNECTOR:%d:%s] Link Training Passed at Link Rate = %d, Lane count = %d",
 		    intel_connector->base.base.id,
 		    intel_connector->base.name,
-		    intel_dp->link_rate, intel_dp->lane_count);
+		    crtc_state->port_clock, crtc_state->lane_count);
 	return;
 
  failure_handling:
@@ -409,15 +421,15 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
 		    "[CONNECTOR:%d:%s] Link Training failed at link rate = %d, lane count = %d",
 		    intel_connector->base.base.id,
 		    intel_connector->base.name,
-		    intel_dp->link_rate, intel_dp->lane_count);
+		    crtc_state->port_clock, crtc_state->lane_count);
 
 	if (intel_dp->hobl_active) {
 		drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
 			    "Link Training failed with HOBL active, not enabling it from now on");
 		intel_dp->hobl_failed = true;
 	} else if (intel_dp_get_link_train_fallback_values(intel_dp,
-							   intel_dp->link_rate,
-							   intel_dp->lane_count)) {
+							   crtc_state->port_clock,
+							   crtc_state->lane_count)) {
 		return;
 	}
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
index 01f1dabbb060..648a6d1f9fa2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
@@ -8,11 +8,15 @@
 
 #include <drm/drm_dp_helper.h>
 
+struct intel_crtc_state;
 struct intel_dp;
 
 void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
+			       const struct intel_crtc_state *crtc_state,
 			       const u8 link_status[DP_LINK_STATUS_SIZE]);
-void intel_dp_start_link_train(struct intel_dp *intel_dp);
-void intel_dp_stop_link_train(struct intel_dp *intel_dp);
+void intel_dp_start_link_train(struct intel_dp *intel_dp,
+			       const struct intel_crtc_state *crtc_state);
+void intel_dp_stop_link_train(struct intel_dp *intel_dp,
+			      const struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_DP_LINK_TRAINING_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index 7910522273b2..514c4a7adffc 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -644,16 +644,16 @@ bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
 	return mask;
 }
 
-
 void chv_set_phy_signal_level(struct intel_encoder *encoder,
+			      const struct intel_crtc_state *crtc_state,
 			      u32 deemph_reg_value, u32 margin_reg_value,
 			      bool uniq_trans_scale)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
-	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
-	enum pipe pipe = intel_crtc->pipe;
+	enum pipe pipe = crtc->pipe;
 	u32 val;
 	int i;
 
@@ -666,7 +666,7 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder,
 	val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
 
-	if (intel_crtc->config->lane_count > 2) {
+	if (crtc_state->lane_count > 2) {
 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
 		val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
 		val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
@@ -679,7 +679,7 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder,
 	val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
 
-	if (intel_crtc->config->lane_count > 2) {
+	if (crtc_state->lane_count > 2) {
 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
 		val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
 		val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
@@ -687,7 +687,7 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder,
 	}
 
 	/* Program swing deemph */
-	for (i = 0; i < intel_crtc->config->lane_count; i++) {
+	for (i = 0; i < crtc_state->lane_count; i++) {
 		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
 		val &= ~DPIO_SWING_DEEMPH9P5_MASK;
 		val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
@@ -695,7 +695,7 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder,
 	}
 
 	/* Program swing margin */
-	for (i = 0; i < intel_crtc->config->lane_count; i++) {
+	for (i = 0; i < crtc_state->lane_count; i++) {
 		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
 
 		val &= ~DPIO_SWING_MARGIN000_MASK;
@@ -718,7 +718,7 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder,
 	 * For now, for this unique transition scale selection, set bit
 	 * 27 for ch0 and ch1.
 	 */
-	for (i = 0; i < intel_crtc->config->lane_count; i++) {
+	for (i = 0; i < crtc_state->lane_count; i++) {
 		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
 		if (uniq_trans_scale)
 			val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
@@ -732,7 +732,7 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder,
 	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
 
-	if (intel_crtc->config->lane_count > 2) {
+	if (crtc_state->lane_count > 2) {
 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
 		val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
@@ -992,14 +992,15 @@ void chv_phy_post_pll_disable(struct intel_encoder *encoder,
 }
 
 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
+			      const struct intel_crtc_state *crtc_state,
 			      u32 demph_reg_value, u32 preemph_reg_value,
 			      u32 uniqtranscale_reg_value, u32 tx3_demph)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
-	enum pipe pipe = intel_crtc->pipe;
+	enum pipe pipe = crtc->pipe;
 
 	vlv_dpio_get(dev_priv);
 
diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.h b/drivers/gpu/drm/i915/display/intel_dpio_phy.h
index f418aab90b7e..6473440e7457 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.h
@@ -32,6 +32,7 @@ void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
 u8 bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
 
 void chv_set_phy_signal_level(struct intel_encoder *encoder,
+			      const struct intel_crtc_state *crtc_state,
 			      u32 deemph_reg_value, u32 margin_reg_value,
 			      bool uniq_trans_scale);
 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
@@ -46,6 +47,7 @@ void chv_phy_post_pll_disable(struct intel_encoder *encoder,
 			      const struct intel_crtc_state *old_crtc_state);
 
 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
+			      const struct intel_crtc_state *crtc_state,
 			      u32 demph_reg_value, u32 preemph_reg_value,
 			      u32 uniqtranscale_reg_value, u32 tx3_demph);
 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 3f2008d845c2..414a46a6b5f3 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2775,8 +2775,9 @@ static void vlv_hdmi_pre_enable(struct intel_atomic_state *state,
 	vlv_phy_pre_encoder_enable(encoder, pipe_config);
 
 	/* HDMI 1.0V-2dB */
-	vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
-				 0x2b247878);
+	vlv_set_phy_signal_level(encoder, pipe_config,
+				 0x2b245f5f, 0x00002000,
+				 0x5578b83a, 0x2b247878);
 
 	dig_port->set_infoframes(encoder,
 			      pipe_config->has_infoframe,
@@ -2853,7 +2854,7 @@ static void chv_hdmi_pre_enable(struct intel_atomic_state *state,
 
 	/* FIXME: Program the support xxx V-dB */
 	/* Use 800mV-0dB */
-	chv_set_phy_signal_level(encoder, 128, 102, false);
+	chv_set_phy_signal_level(encoder, pipe_config, 128, 102, false);
 
 	dig_port->set_infoframes(encoder,
 			      pipe_config->has_infoframe,
-- 
2.26.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

* [Intel-gfx] [PATCH v2 11/11] drm/i915: Eliminate intel_dp.regs.dp_tp_{ctl, status}
  2020-09-29 23:34 [Intel-gfx] [PATCH v2 00/11] drm/i915: Plumb crtc state to link training code Ville Syrjala
                   ` (9 preceding siblings ...)
  2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 10/11] drm/i915: Plumb crtc_state to link training Ville Syrjala
@ 2020-09-29 23:34 ` Ville Syrjala
  2020-09-30 17:04   ` Imre Deak
  2020-09-29 23:50 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plumb crtc state to link training code (rev3) Patchwork
                   ` (9 subsequent siblings)
  20 siblings, 1 reply; 37+ messages in thread
From: Ville Syrjala @ 2020-09-29 23:34 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Now that we've plumbed the crtc state all the way down we can
eliminate the DP_TP_{CTL,STATUS} register offsets from intel_dp,
and instead we derive them directly from the crtc state.

And thus we can get rid of the nasty hack in intel_ddi_get_config()
which mutates intel_dp during the readout.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c      | 107 ++++++++++--------
 drivers/gpu/drm/i915/display/intel_ddi.h      |   5 +
 .../drm/i915/display/intel_display_types.h    |   8 --
 drivers/gpu/drm/i915/display/intel_dp.c       |   2 -
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |  24 ++--
 5 files changed, 76 insertions(+), 70 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index cdf3e5540482..11297a8af3b7 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3295,6 +3295,37 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
 	}
 }
 
+static enum transcoder
+tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state)
+{
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
+		return crtc_state->mst_master_transcoder;
+	else
+		return crtc_state->cpu_transcoder;
+}
+
+i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder,
+			 const struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
+	if (INTEL_GEN(dev_priv) >= 12)
+		return TGL_DP_TP_CTL(tgl_dp_tp_transcoder(crtc_state));
+	else
+		return DP_TP_CTL(encoder->port);
+}
+
+i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder,
+			    const struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
+	if (INTEL_GEN(dev_priv) >= 12)
+		return TGL_DP_TP_STATUS(tgl_dp_tp_transcoder(crtc_state));
+	else
+		return DP_TP_STATUS(encoder->port);
+}
+
 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
 					const struct intel_crtc_state *crtc_state)
 {
@@ -3319,11 +3350,12 @@ static void intel_ddi_enable_fec(struct intel_encoder *encoder,
 		return;
 
 	intel_dp = enc_to_intel_dp(encoder);
-	val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
+	val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
 	val |= DP_TP_CTL_FEC_ENABLE;
-	intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val);
+	intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
 
-	if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
+	if (intel_de_wait_for_set(dev_priv,
+				  dp_tp_status_reg(encoder, crtc_state),
 				  DP_TP_STATUS_FEC_ENABLE_LIVE, 1))
 		drm_err(&dev_priv->drm,
 			"Timed out waiting for FEC Enable Status\n");
@@ -3340,10 +3372,10 @@ static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
 		return;
 
 	intel_dp = enc_to_intel_dp(encoder);
-	val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
+	val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
 	val &= ~DP_TP_CTL_FEC_ENABLE;
-	intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val);
-	intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl);
+	intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
+	intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
 }
 
 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
@@ -3357,15 +3389,11 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 	bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
 	int level = intel_ddi_dp_level(intel_dp);
-	enum transcoder transcoder = crtc_state->cpu_transcoder;
 
 	intel_dp_set_link_params(intel_dp,
 				 crtc_state->port_clock,
 				 crtc_state->lane_count);
 
-	intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder);
-	intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder);
-
 	/*
 	 * 1. Enable Power Wells
 	 *
@@ -3682,12 +3710,10 @@ static void intel_disable_ddi_buf(struct intel_encoder *encoder,
 	}
 
 	if (intel_crtc_has_dp_encoder(crtc_state)) {
-		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-
-		val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
+		val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
 		val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
 		val |= DP_TP_CTL_LINK_TRAIN_PAT1;
-		intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val);
+		intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
 	}
 
 	/* Disable FEC in DP Sink */
@@ -4184,13 +4210,13 @@ intel_ddi_pre_pll_enable(struct intel_atomic_state *state,
 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
 					   const struct intel_crtc_state *crtc_state)
 {
-	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
-	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
-	enum port port = dig_port->base.port;
+	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	enum port port = encoder->port;
 	u32 dp_tp_ctl, ddi_buf_ctl;
 	bool wait = false;
 
-	dp_tp_ctl = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
+	dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
 
 	if (dp_tp_ctl & DP_TP_CTL_ENABLE) {
 		ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port));
@@ -4202,8 +4228,8 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
 
 		dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
 		dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1;
-		intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, dp_tp_ctl);
-		intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl);
+		intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
+		intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
 
 		if (wait)
 			intel_wait_ddi_buf_idle(dev_priv, port);
@@ -4218,8 +4244,8 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
 		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
 			dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
 	}
-	intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, dp_tp_ctl);
-	intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl);
+	intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
+	intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
 
 	intel_dp->DP |= DDI_BUF_CTL_ENABLE;
 	intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
@@ -4232,11 +4258,12 @@ static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
 				     const struct intel_crtc_state *crtc_state,
 				     u8 dp_train_pat)
 {
-	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
 	u32 temp;
 
-	temp = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
+	temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
 
 	temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
 	switch (dp_train_pat & train_pat_mask) {
@@ -4257,7 +4284,7 @@ static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
 		break;
 	}
 
-	intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, temp);
+	intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp);
 }
 
 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp,
@@ -4268,10 +4295,10 @@ static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp,
 	enum port port = encoder->port;
 	u32 val;
 
-	val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
+	val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
 	val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
 	val |= DP_TP_CTL_LINK_TRAIN_IDLE;
-	intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val);
+	intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
 
 	/*
 	 * Until TGL on PORT_A we can have only eDP in SST mode. There the only
@@ -4283,7 +4310,8 @@ static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp,
 	if (port == PORT_A && INTEL_GEN(dev_priv) < 12)
 		return;
 
-	if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
+	if (intel_de_wait_for_set(dev_priv,
+				  dp_tp_status_reg(encoder, crtc_state),
 				  DP_TP_STATUS_IDLE_DONE, 1))
 		drm_err(&dev_priv->drm,
 			"Timed out waiting for DP idle patterns\n");
@@ -4381,7 +4409,6 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
 	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
-	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 	u32 temp, flags = 0;
 
 	/* XXX: DSI transcoder paranoia */
@@ -4451,12 +4478,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
 		intel_dp_get_m_n(intel_crtc, pipe_config);
 
 		if (INTEL_GEN(dev_priv) >= 11) {
-			i915_reg_t dp_tp_ctl;
-
-			if (IS_GEN(dev_priv, 11))
-				dp_tp_ctl = DP_TP_CTL(encoder->port);
-			else
-				dp_tp_ctl = TGL_DP_TP_CTL(pipe_config->cpu_transcoder);
+			i915_reg_t dp_tp_ctl = dp_tp_ctl_reg(encoder, pipe_config);
 
 			pipe_config->fec_enable =
 				intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE;
@@ -4489,16 +4511,6 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
 		break;
 	}
 
-	if (INTEL_GEN(dev_priv) >= 12) {
-		enum transcoder transcoder =
-			intel_dp_mst_is_slave_trans(pipe_config) ?
-			pipe_config->mst_master_transcoder :
-			pipe_config->cpu_transcoder;
-
-		intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder);
-		intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder);
-	}
-
 	pipe_config->has_audio =
 		intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
 
@@ -4763,11 +4775,6 @@ intel_ddi_init_dp_connector(struct intel_digital_port *dig_port)
 	dig_port->dp.voltage_max = intel_ddi_dp_voltage_max;
 	dig_port->dp.preemph_max = intel_ddi_dp_preemph_max;
 
-	if (INTEL_GEN(dev_priv) < 12) {
-		dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port);
-		dig_port->dp.regs.dp_tp_status = DP_TP_STATUS(port);
-	}
-
 	if (!intel_dp_init_connector(dig_port, connector)) {
 		kfree(connector);
 		return NULL;
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h
index 9a2ac73164f8..dcc711cfe4fe 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi.h
@@ -7,6 +7,7 @@
 #define __INTEL_DDI_H__
 
 #include "intel_display.h"
+#include "i915_reg.h"
 
 struct drm_connector_state;
 struct drm_i915_private;
@@ -18,6 +19,10 @@ struct intel_dpll_hw_state;
 struct intel_encoder;
 enum transcoder;
 
+i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder,
+			 const struct intel_crtc_state *crtc_state);
+i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder,
+			    const struct intel_crtc_state *crtc_state);
 void intel_ddi_fdi_post_disable(struct intel_atomic_state *state,
 				struct intel_encoder *intel_encoder,
 				const struct intel_crtc_state *old_crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 66d197153c93..d5dc18cb8c39 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1338,14 +1338,6 @@ struct intel_dp {
 	bool is_mst;
 	int active_mst_links;
 
-	/*
-	 * DP_TP_* registers may be either on port or transcoder register space.
-	 */
-	struct {
-		i915_reg_t dp_tp_ctl;
-		i915_reg_t dp_tp_status;
-	} regs;
-
 	/* connector directly attached - won't be use for modeset in mst world */
 	struct intel_connector *attached_connector;
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 5ac8a06575d4..208851296cce 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -8109,8 +8109,6 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
 
 	dig_port->dp.output_reg = output_reg;
 	dig_port->max_lanes = 4;
-	dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port);
-	dig_port->dp.regs.dp_tp_status = DP_TP_STATUS(port);
 
 	intel_encoder->type = INTEL_OUTPUT_DP;
 	intel_encoder->power_domain = intel_port_to_power_domain(port);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 6a874b779b1f..82f38c386dbd 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -318,19 +318,23 @@ intel_dp_mst_atomic_check(struct drm_connector *connector,
 	return ret;
 }
 
-static void clear_act_sent(struct intel_dp *intel_dp)
+static void clear_act_sent(struct intel_encoder *encoder,
+			   const struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 
-	intel_de_write(i915, intel_dp->regs.dp_tp_status,
+	intel_de_write(i915, dp_tp_status_reg(encoder, crtc_state),
 		       DP_TP_STATUS_ACT_SENT);
 }
 
-static void wait_for_act_sent(struct intel_dp *intel_dp)
+static void wait_for_act_sent(struct intel_encoder *encoder,
+			      const struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
+	struct intel_dp *intel_dp = &intel_mst->primary->dp;
 
-	if (intel_de_wait_for_set(i915, intel_dp->regs.dp_tp_status,
+	if (intel_de_wait_for_set(i915, dp_tp_status_reg(encoder, crtc_state),
 				  DP_TP_STATUS_ACT_SENT, 1))
 		drm_err(&i915->drm, "Timed out waiting for ACT sent\n");
 
@@ -392,7 +396,7 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
 
 	drm_dp_update_payload_part2(&intel_dp->mst_mgr);
 
-	clear_act_sent(intel_dp);
+	clear_act_sent(encoder, old_crtc_state);
 
 	val = intel_de_read(dev_priv,
 			    TRANS_DDI_FUNC_CTL(old_crtc_state->cpu_transcoder));
@@ -401,7 +405,7 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
 		       TRANS_DDI_FUNC_CTL(old_crtc_state->cpu_transcoder),
 		       val);
 
-	wait_for_act_sent(intel_dp);
+	wait_for_act_sent(encoder, old_crtc_state);
 
 	drm_dp_mst_deallocate_vcpi(&intel_dp->mst_mgr, connector->port);
 
@@ -535,7 +539,7 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
 
 	drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder);
 
-	clear_act_sent(intel_dp);
+	clear_act_sent(encoder, pipe_config);
 
 	intel_ddi_enable_transcoder_func(encoder, pipe_config);
 
@@ -549,7 +553,7 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
 	drm_dbg_kms(&dev_priv->drm, "active links %d\n",
 		    intel_dp->active_mst_links);
 
-	wait_for_act_sent(intel_dp);
+	wait_for_act_sent(encoder, pipe_config);
 
 	drm_dp_update_payload_part2(&intel_dp->mst_mgr);
 
-- 
2.26.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plumb crtc state to link training code (rev3)
  2020-09-29 23:34 [Intel-gfx] [PATCH v2 00/11] drm/i915: Plumb crtc state to link training code Ville Syrjala
                   ` (10 preceding siblings ...)
  2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 11/11] drm/i915: Eliminate intel_dp.regs.dp_tp_{ctl, status} Ville Syrjala
@ 2020-09-29 23:50 ` Patchwork
  2020-09-29 23:51 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
                   ` (8 subsequent siblings)
  20 siblings, 0 replies; 37+ messages in thread
From: Patchwork @ 2020-09-29 23:50 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

== Series Details ==

Series: drm/i915: Plumb crtc state to link training code (rev3)
URL   : https://patchwork.freedesktop.org/series/76993/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
e1b9ea43cc51 drm/i915: s/pre_empemph/preemph/
099b31ec3c93 drm/i915: s/old_crtc_state/crtc_state/
a5235039ab34 drm/i915: Make intel_dp_process_phy_request() static
3f3c4a5bf30d drm/i915: Shove the PHY test into the hotplug work
a5f3aceec002 drm/i915: Split ICL combo PHY buf trans per output type
fccaa6c84e89 drm/i915: Split ICL MG PHY buf trans per output type
cdd8092d9acb drm/i915: Split EHL combo PHY buf trans per output type
-:62: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or return
#62: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1138:
+			return icl_combo_phy_ddi_translations_edp_hbr3;
+		} else {

total: 0 errors, 1 warnings, 0 checks, 70 lines checked
7676ef2864b7 drm/i915: Split TGL combo PHY buf trans per output type
-:72: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or return
#72: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1177:
+			return tgl_uy_combo_phy_ddi_translations_dp_hbr2;
+		} else {

total: 0 errors, 1 warnings, 0 checks, 100 lines checked
b0e21d0d4119 drm/i915: Split TGL DKL PHY buf trans per output type
c0ea3b11329e drm/i915: Plumb crtc_state to link training
4c9eb175070d drm/i915: Eliminate intel_dp.regs.dp_tp_{ctl, status}


_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Plumb crtc state to link training code (rev3)
  2020-09-29 23:34 [Intel-gfx] [PATCH v2 00/11] drm/i915: Plumb crtc state to link training code Ville Syrjala
                   ` (11 preceding siblings ...)
  2020-09-29 23:50 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plumb crtc state to link training code (rev3) Patchwork
@ 2020-09-29 23:51 ` Patchwork
  2020-09-30  0:07 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
                   ` (7 subsequent siblings)
  20 siblings, 0 replies; 37+ messages in thread
From: Patchwork @ 2020-09-29 23:51 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

== Series Details ==

Series: drm/i915: Plumb crtc state to link training code (rev3)
URL   : https://patchwork.freedesktop.org/series/76993/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+drivers/gpu/drm/i915/display/intel_dp.c:6042:39:    unsigned int enum drm_connector_status
+drivers/gpu/drm/i915/display/intel_dp.c:6042:39:    unsigned int enum intel_hotplug_state
+drivers/gpu/drm/i915/display/intel_dp.c:6042:39: warning: mixing different enum types:


_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Plumb crtc state to link training code (rev3)
  2020-09-29 23:34 [Intel-gfx] [PATCH v2 00/11] drm/i915: Plumb crtc state to link training code Ville Syrjala
                   ` (12 preceding siblings ...)
  2020-09-29 23:51 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2020-09-30  0:07 ` Patchwork
  2020-09-30 10:28 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plumb crtc state to link training code (rev4) Patchwork
                   ` (6 subsequent siblings)
  20 siblings, 0 replies; 37+ messages in thread
From: Patchwork @ 2020-09-30  0:07 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx


[-- Attachment #1.1: Type: text/plain, Size: 8066 bytes --]

== Series Details ==

Series: drm/i915: Plumb crtc state to link training code (rev3)
URL   : https://patchwork.freedesktop.org/series/76993/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9075 -> Patchwork_18594
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/index.html

Known issues
------------

  Here are the changes found in Patchwork_18594 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - fi-byt-j1900:       [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/fi-byt-j1900/igt@i915_pm_rpm@basic-pci-d3-state.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/fi-byt-j1900/igt@i915_pm_rpm@basic-pci-d3-state.html

  * igt@i915_pm_rpm@module-reload:
    - fi-bsw-kefka:       [PASS][3] -> [INCOMPLETE][4] ([i915#151] / [i915#1844] / [i915#1909])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/fi-bsw-kefka/igt@i915_pm_rpm@module-reload.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/fi-bsw-kefka/igt@i915_pm_rpm@module-reload.html

  * igt@kms_chamelium@dp-crc-fast:
    - fi-kbl-7500u:       [PASS][5] -> [FAIL][6] ([i915#1161] / [i915#262])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
    - fi-icl-u2:          [PASS][7] -> [FAIL][8] ([i915#1161] / [i915#262])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/fi-icl-u2/igt@kms_chamelium@dp-crc-fast.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/fi-icl-u2/igt@kms_chamelium@dp-crc-fast.html
    - fi-cml-u2:          [PASS][9] -> [FAIL][10] ([i915#1161] / [i915#262])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/fi-cml-u2/igt@kms_chamelium@dp-crc-fast.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/fi-cml-u2/igt@kms_chamelium@dp-crc-fast.html

  * igt@kms_chamelium@hdmi-crc-fast:
    - fi-kbl-7500u:       [PASS][11] -> [FAIL][12] ([i915#1161] / [i915#2260])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/fi-kbl-7500u/igt@kms_chamelium@hdmi-crc-fast.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/fi-kbl-7500u/igt@kms_chamelium@hdmi-crc-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - fi-icl-u2:          [PASS][13] -> [DMESG-WARN][14] ([i915#1982])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_flip@basic-flip-vs-modeset@c-dp2:
    - fi-skl-6700k2:      [PASS][15] -> [DMESG-WARN][16] ([i915#2203]) +3 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/fi-skl-6700k2/igt@kms_flip@basic-flip-vs-modeset@c-dp2.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/fi-skl-6700k2/igt@kms_flip@basic-flip-vs-modeset@c-dp2.html

  * igt@kms_flip@basic-flip-vs-wf_vblank@c-dp2:
    - fi-skl-guc:         [PASS][17] -> [DMESG-WARN][18] ([i915#2203]) +1 similar issue
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/fi-skl-guc/igt@kms_flip@basic-flip-vs-wf_vblank@c-dp2.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/fi-skl-guc/igt@kms_flip@basic-flip-vs-wf_vblank@c-dp2.html

  * igt@kms_psr@cursor_plane_move:
    - fi-kbl-r:           [PASS][19] -> [SKIP][20] ([fdo#109271] / [i915#668]) +3 similar issues
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/fi-kbl-r/igt@kms_psr@cursor_plane_move.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/fi-kbl-r/igt@kms_psr@cursor_plane_move.html

  
#### Possible fixes ####

  * igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1:
    - fi-icl-u2:          [DMESG-WARN][21] ([i915#1982]) -> [PASS][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html

  
#### Warnings ####

  * igt@kms_flip@basic-flip-vs-wf_vblank@a-dp1:
    - fi-kbl-x1275:       [DMESG-WARN][23] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][24] ([i915#62] / [i915#92]) +1 similar issue
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-wf_vblank@a-dp1.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-wf_vblank@a-dp1.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - fi-kbl-x1275:       [DMESG-WARN][25] ([i915#1982] / [i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][26] ([i915#62] / [i915#92])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/fi-kbl-x1275/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/fi-kbl-x1275/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  * igt@prime_vgem@basic-fence-flip:
    - fi-kbl-x1275:       [DMESG-WARN][27] ([i915#62] / [i915#92]) -> [DMESG-WARN][28] ([i915#62] / [i915#92] / [i915#95]) +5 similar issues
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/fi-kbl-x1275/igt@prime_vgem@basic-fence-flip.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/fi-kbl-x1275/igt@prime_vgem@basic-fence-flip.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#1161]: https://gitlab.freedesktop.org/drm/intel/issues/1161
  [i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151
  [i915#1844]: https://gitlab.freedesktop.org/drm/intel/issues/1844
  [i915#1909]: https://gitlab.freedesktop.org/drm/intel/issues/1909
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
  [i915#2260]: https://gitlab.freedesktop.org/drm/intel/issues/2260
  [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
  [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
  [i915#668]: https://gitlab.freedesktop.org/drm/intel/issues/668
  [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95


Participating hosts (46 -> 38)
------------------------------

  Missing    (8): fi-ilk-m540 fi-tgl-dsi fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_9075 -> Patchwork_18594

  CI-20190529: 20190529
  CI_DRM_9075: fd24361b2b76956b5c056bc430a4c77edecb7744 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5792: cbaf441899f3b4f36cca5996aa6a69e7399b2dbd @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_18594: 4c9eb175070d931ba14945be9780a2667fa8fc5f @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

4c9eb175070d drm/i915: Eliminate intel_dp.regs.dp_tp_{ctl, status}
c0ea3b11329e drm/i915: Plumb crtc_state to link training
b0e21d0d4119 drm/i915: Split TGL DKL PHY buf trans per output type
7676ef2864b7 drm/i915: Split TGL combo PHY buf trans per output type
cdd8092d9acb drm/i915: Split EHL combo PHY buf trans per output type
fccaa6c84e89 drm/i915: Split ICL MG PHY buf trans per output type
a5f3aceec002 drm/i915: Split ICL combo PHY buf trans per output type
3f3c4a5bf30d drm/i915: Shove the PHY test into the hotplug work
a5235039ab34 drm/i915: Make intel_dp_process_phy_request() static
099b31ec3c93 drm/i915: s/old_crtc_state/crtc_state/
e1b9ea43cc51 drm/i915: s/pre_empemph/preemph/

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/index.html

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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

* Re: [Intel-gfx] [PATCH v2 04/11] drm/i915: Shove the PHY test into the hotplug work
  2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 04/11] drm/i915: Shove the PHY test into the hotplug work Ville Syrjala
@ 2020-09-30  8:10   ` kernel test robot
  2020-09-30 10:04   ` [Intel-gfx] [PATCH v3 " Ville Syrjala
  1 sibling, 0 replies; 37+ messages in thread
From: kernel test robot @ 2020-09-30  8:10 UTC (permalink / raw)
  To: Ville Syrjala, intel-gfx; +Cc: kbuild-all

[-- Attachment #1: Type: text/plain, Size: 3845 bytes --]

Hi Ville,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip v5.9-rc7 next-20200929]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Ville-Syrjala/drm-i915-Plumb-crtc-state-to-link-training-code/20200930-073629
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-s021-20200930 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
reproduce:
        # apt-get install sparse
        # sparse version: v0.6.2-201-g24bdaac6-dirty
        # https://github.com/0day-ci/linux/commit/a504af17c918ba91652d9c0c5ed45d9e0ca98dfd
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Ville-Syrjala/drm-i915-Plumb-crtc-state-to-link-training-code/20200930-073629
        git checkout a504af17c918ba91652d9c0c5ed45d9e0ca98dfd
        # save the attached .config to linux build tree
        make W=1 C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' ARCH=x86_64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

	echo
	echo "sparse warnings: (new ones prefixed by >>)"
	echo
>> drivers/gpu/drm/i915/display/intel_dp.c:5977:39: sparse: sparse: mixing different enum types:
>> drivers/gpu/drm/i915/display/intel_dp.c:5977:39: sparse:    unsigned int enum drm_connector_status
>> drivers/gpu/drm/i915/display/intel_dp.c:5977:39: sparse:    unsigned int enum intel_hotplug_state

vim +5977 drivers/gpu/drm/i915/display/intel_dp.c

  5951	
  5952	/*
  5953	 * If display is now connected check links status,
  5954	 * there has been known issues of link loss triggering
  5955	 * long pulse.
  5956	 *
  5957	 * Some sinks (eg. ASUS PB287Q) seem to perform some
  5958	 * weird HPD ping pong during modesets. So we can apparently
  5959	 * end up with HPD going low during a modeset, and then
  5960	 * going back up soon after. And once that happens we must
  5961	 * retrain the link to get a picture. That's in case no
  5962	 * userspace component reacted to intermittent HPD dip.
  5963	 */
  5964	static enum intel_hotplug_state
  5965	intel_dp_hotplug(struct intel_encoder *encoder,
  5966			 struct intel_connector *connector)
  5967	{
  5968		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
  5969		struct drm_modeset_acquire_ctx ctx;
  5970		enum intel_hotplug_state state;
  5971		int ret;
  5972	
  5973		if (intel_dp->compliance.test_active &&
  5974		    intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) {
  5975			intel_dp_phy_test(encoder);
  5976			/* just do the PHY test and nothing else */
> 5977			return connector->base.status;
  5978		}
  5979	
  5980		state = intel_encoder_hotplug(encoder, connector);
  5981	
  5982		drm_modeset_acquire_init(&ctx, 0);
  5983	
  5984		for (;;) {
  5985			ret = intel_dp_retrain_link(encoder, &ctx);
  5986	
  5987			if (ret == -EDEADLK) {
  5988				drm_modeset_backoff(&ctx);
  5989				continue;
  5990			}
  5991	
  5992			break;
  5993		}
  5994	
  5995		drm_modeset_drop_locks(&ctx);
  5996		drm_modeset_acquire_fini(&ctx);
  5997		drm_WARN(encoder->base.dev, ret,
  5998			 "Acquiring modeset locks failed with %i\n", ret);
  5999	
  6000		/*
  6001		 * Keeping it consistent with intel_ddi_hotplug() and
  6002		 * intel_hdmi_hotplug().
  6003		 */
  6004		if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries)
  6005			state = INTEL_HOTPLUG_RETRY;
  6006	
  6007		return state;
  6008	}
  6009	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

* [Intel-gfx] [PATCH v3 04/11] drm/i915: Shove the PHY test into the hotplug work
  2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 04/11] drm/i915: Shove the PHY test into the hotplug work Ville Syrjala
  2020-09-30  8:10   ` kernel test robot
@ 2020-09-30 10:04   ` Ville Syrjala
  2020-09-30 15:12     ` Imre Deak
  1 sibling, 1 reply; 37+ messages in thread
From: Ville Syrjala @ 2020-09-30 10:04 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Doing nay kind modeset stuff from the short hpd handler is
verboten. The ad-hoc PHY test modeset code violates this. And
by calling various link training related functions it's now
blocking further work to plumb the crtc state down into the
link training code.

Let's hack around that by pushing the PHY test stuff into the
hotplug work where it's less of a problem. Still not great but
at least acceptable. We take a few pages from the link retraining
handbook to handle the locking and whatnot.

v2: Fix the intel_dp_hotplug() return value

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 154 ++++++++++++++++++++----
 1 file changed, 128 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 5c673080ecb1..132b06a649d8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5424,25 +5424,6 @@ static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
 	return test_result;
 }
 
-static u8 intel_dp_prepare_phytest(struct intel_dp *intel_dp)
-{
-	struct drm_dp_phy_test_params *data =
-		&intel_dp->compliance.test_data.phytest;
-
-	if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
-		DRM_DEBUG_KMS("DP Phy Test pattern AUX read failure\n");
-		return DP_TEST_NAK;
-	}
-
-	/*
-	 * link_mst is set to false to avoid executing mst related code
-	 * during compliance testing.
-	 */
-	intel_dp->link_mst = false;
-
-	return DP_TEST_ACK;
-}
-
 static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *dev_priv =
@@ -5590,15 +5571,18 @@ static void intel_dp_process_phy_request(struct intel_dp *intel_dp)
 
 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
 {
-	u8 test_result;
+	struct drm_dp_phy_test_params *data =
+		&intel_dp->compliance.test_data.phytest;
 
-	test_result = intel_dp_prepare_phytest(intel_dp);
-	if (test_result != DP_TEST_ACK)
-		DRM_ERROR("Phy test preparation failed\n");
+	if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
+		DRM_DEBUG_KMS("DP Phy Test pattern AUX read failure\n");
+		return DP_TEST_NAK;
+	}
 
-	intel_dp_process_phy_request(intel_dp);
+	/* Set test active flag here so userspace doesn't interrupt things */
+	intel_dp->compliance.test_active = true;
 
-	return test_result;
+	return DP_TEST_ACK;
 }
 
 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
@@ -5887,6 +5871,104 @@ int intel_dp_retrain_link(struct intel_encoder *encoder,
 	return 0;
 }
 
+static int intel_dp_prep_phy_test(struct intel_dp *intel_dp,
+				  struct drm_modeset_acquire_ctx *ctx,
+				  u32 *crtc_mask)
+{
+	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+	struct drm_connector_list_iter conn_iter;
+	struct intel_connector *connector;
+	int ret = 0;
+
+	*crtc_mask = 0;
+
+	drm_connector_list_iter_begin(&i915->drm, &conn_iter);
+	for_each_intel_connector_iter(connector, &conn_iter) {
+		struct drm_connector_state *conn_state =
+			connector->base.state;
+		struct intel_crtc_state *crtc_state;
+		struct intel_crtc *crtc;
+
+		if (!intel_dp_has_connector(intel_dp, conn_state))
+			continue;
+
+		crtc = to_intel_crtc(conn_state->crtc);
+		if (!crtc)
+			continue;
+
+		ret = drm_modeset_lock(&crtc->base.mutex, ctx);
+		if (ret)
+			break;
+
+		crtc_state = to_intel_crtc_state(crtc->base.state);
+
+		drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
+
+		if (!crtc_state->hw.active)
+			continue;
+
+		if (conn_state->commit &&
+		    !try_wait_for_completion(&conn_state->commit->hw_done))
+			continue;
+
+		*crtc_mask |= drm_crtc_mask(&crtc->base);
+	}
+	drm_connector_list_iter_end(&conn_iter);
+
+	return ret;
+}
+
+static int intel_dp_do_phy_test(struct intel_encoder *encoder,
+				struct drm_modeset_acquire_ctx *ctx)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+	u32 crtc_mask;
+	int ret;
+
+	ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
+			       ctx);
+	if (ret)
+		return ret;
+
+	ret = intel_dp_prep_phy_test(intel_dp, ctx, &crtc_mask);
+	if (ret)
+		return ret;
+
+	if (crtc_mask == 0)
+		return 0;
+
+	drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n",
+		    encoder->base.base.id, encoder->base.name);
+	intel_dp_process_phy_request(intel_dp);
+
+	return 0;
+}
+
+static void intel_dp_phy_test(struct intel_encoder *encoder)
+{
+	struct drm_modeset_acquire_ctx ctx;
+	int ret;
+
+	drm_modeset_acquire_init(&ctx, 0);
+
+	for (;;) {
+		ret = intel_dp_do_phy_test(encoder, &ctx);
+
+		if (ret == -EDEADLK) {
+			drm_modeset_backoff(&ctx);
+			continue;
+		}
+
+		break;
+	}
+
+	drm_modeset_drop_locks(&ctx);
+	drm_modeset_acquire_fini(&ctx);
+	drm_WARN(encoder->base.dev, ret,
+		 "Acquiring modeset locks failed with %i\n", ret);
+}
+
 /*
  * If display is now connected check links status,
  * there has been known issues of link loss triggering
@@ -5903,10 +5985,18 @@ static enum intel_hotplug_state
 intel_dp_hotplug(struct intel_encoder *encoder,
 		 struct intel_connector *connector)
 {
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 	struct drm_modeset_acquire_ctx ctx;
 	enum intel_hotplug_state state;
 	int ret;
 
+	if (intel_dp->compliance.test_active &&
+	    intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) {
+		intel_dp_phy_test(encoder);
+		/* just do the PHY test and nothing else */
+		return INTEL_HOTPLUG_UNCHANGED;
+	}
+
 	state = intel_encoder_hotplug(encoder, connector);
 
 	drm_modeset_acquire_init(&ctx, 0);
@@ -6011,11 +6101,23 @@ intel_dp_short_pulse(struct intel_dp *intel_dp)
 
 	intel_psr_short_pulse(intel_dp);
 
-	if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
+	switch (intel_dp->compliance.test_type) {
+	case DP_TEST_LINK_TRAINING:
 		drm_dbg_kms(&dev_priv->drm,
 			    "Link Training Compliance Test requested\n");
 		/* Send a Hotplug Uevent to userspace to start modeset */
 		drm_kms_helper_hotplug_event(&dev_priv->drm);
+		break;
+	case DP_TEST_LINK_PHY_TEST_PATTERN:
+		drm_dbg_kms(&dev_priv->drm,
+			    "PHY test pattern Compliance Test requested\n");
+		/*
+		 * Schedule long hpd to do the test
+		 *
+		 * FIXME get rid of the ad-hoc phy test modeset code
+		 * and properly incorporate it into the normal modeset.
+		 */
+		return false;
 	}
 
 	return true;
-- 
2.26.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plumb crtc state to link training code (rev4)
  2020-09-29 23:34 [Intel-gfx] [PATCH v2 00/11] drm/i915: Plumb crtc state to link training code Ville Syrjala
                   ` (13 preceding siblings ...)
  2020-09-30  0:07 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-09-30 10:28 ` Patchwork
  2020-09-30 13:12 ` [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Plumb crtc state to link training code (rev3) Patchwork
                   ` (5 subsequent siblings)
  20 siblings, 0 replies; 37+ messages in thread
From: Patchwork @ 2020-09-30 10:28 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

== Series Details ==

Series: drm/i915: Plumb crtc state to link training code (rev4)
URL   : https://patchwork.freedesktop.org/series/76993/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
accbc4f3f980 drm/i915: s/pre_empemph/preemph/
27807980feec drm/i915: s/old_crtc_state/crtc_state/
ef095a1ea266 drm/i915: Make intel_dp_process_phy_request() static
df5118aa27a3 drm/i915: Shove the PHY test into the hotplug work
da9bb32c16d1 drm/i915: Split ICL combo PHY buf trans per output type
65c7a6b7faaf drm/i915: Split ICL MG PHY buf trans per output type
d8721a405542 drm/i915: Split EHL combo PHY buf trans per output type
-:62: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or return
#62: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1138:
+			return icl_combo_phy_ddi_translations_edp_hbr3;
+		} else {

total: 0 errors, 1 warnings, 0 checks, 70 lines checked
5cc36c02d3b3 drm/i915: Split TGL combo PHY buf trans per output type
-:72: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or return
#72: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1177:
+			return tgl_uy_combo_phy_ddi_translations_dp_hbr2;
+		} else {

total: 0 errors, 1 warnings, 0 checks, 100 lines checked
f653b950e1e9 drm/i915: Split TGL DKL PHY buf trans per output type
4ebece3b04fd drm/i915: Plumb crtc_state to link training
651a007abfa9 drm/i915: Eliminate intel_dp.regs.dp_tp_{ctl, status}


_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Plumb crtc state to link training code (rev3)
  2020-09-29 23:34 [Intel-gfx] [PATCH v2 00/11] drm/i915: Plumb crtc state to link training code Ville Syrjala
                   ` (14 preceding siblings ...)
  2020-09-30 10:28 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plumb crtc state to link training code (rev4) Patchwork
@ 2020-09-30 13:12 ` Patchwork
  2020-09-30 15:35 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Plumb crtc state to link training code (rev4) Patchwork
                   ` (4 subsequent siblings)
  20 siblings, 0 replies; 37+ messages in thread
From: Patchwork @ 2020-09-30 13:12 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx


[-- Attachment #1.1: Type: text/plain, Size: 16893 bytes --]

== Series Details ==

Series: drm/i915: Plumb crtc state to link training code (rev3)
URL   : https://patchwork.freedesktop.org/series/76993/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9075_full -> Patchwork_18594_full
====================================================

Summary
-------

  **WARNING**

  Minor unknown changes coming with Patchwork_18594_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_18594_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_18594_full:

### IGT changes ###

#### Warnings ####

  * igt@kms_content_protection@atomic:
    - shard-kbl:          [TIMEOUT][1] ([i915#1319] / [i915#1958]) -> [DMESG-FAIL][2] +4 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/shard-kbl6/igt@kms_content_protection@atomic.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/shard-kbl1/igt@kms_content_protection@atomic.html

  * igt@kms_content_protection@uevent:
    - shard-kbl:          [FAIL][3] ([i915#2105]) -> [DMESG-FAIL][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/shard-kbl3/igt@kms_content_protection@uevent.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/shard-kbl7/igt@kms_content_protection@uevent.html

  
Known issues
------------

  Here are the changes found in Patchwork_18594_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_suspend@forcewake:
    - shard-kbl:          [PASS][5] -> [DMESG-WARN][6] ([i915#180]) +1 similar issue
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/shard-kbl1/igt@i915_suspend@forcewake.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/shard-kbl7/igt@i915_suspend@forcewake.html

  * igt@kms_big_fb@linear-64bpp-rotate-180:
    - shard-apl:          [PASS][7] -> [DMESG-WARN][8] ([i915#1635] / [i915#1982])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/shard-apl4/igt@kms_big_fb@linear-64bpp-rotate-180.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/shard-apl4/igt@kms_big_fb@linear-64bpp-rotate-180.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1:
    - shard-skl:          [PASS][9] -> [FAIL][10] ([i915#2122])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/shard-skl6/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/shard-skl3/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html

  * igt@kms_flip@plain-flip-ts-check-interruptible@c-hdmi-a1:
    - shard-glk:          [PASS][11] -> [FAIL][12] ([i915#2122])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/shard-glk1/igt@kms_flip@plain-flip-ts-check-interruptible@c-hdmi-a1.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/shard-glk1/igt@kms_flip@plain-flip-ts-check-interruptible@c-hdmi-a1.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
    - shard-tglb:         [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) +1 similar issue
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-modesetfrombusy:
    - shard-tglb:         [PASS][15] -> [SKIP][16] ([i915#668]) +1 similar issue
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-modesetfrombusy.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-modesetfrombusy.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-render:
    - shard-skl:          [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) +9 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/shard-skl5/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-render.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/shard-skl6/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-render.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-skl:          [PASS][19] -> [FAIL][20] ([i915#1188])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/shard-skl1/igt@kms_hdr@bpc-switch-suspend.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/shard-skl2/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
    - shard-skl:          [PASS][21] -> [FAIL][22] ([fdo#108145] / [i915#265])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html

  * igt@kms_psr2_su@page_flip:
    - shard-iclb:         [PASS][23] -> [SKIP][24] ([fdo#109642] / [fdo#111068])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/shard-iclb2/igt@kms_psr2_su@page_flip.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/shard-iclb6/igt@kms_psr2_su@page_flip.html

  * igt@kms_psr@psr2_primary_render:
    - shard-iclb:         [PASS][25] -> [SKIP][26] ([fdo#109441])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/shard-iclb2/igt@kms_psr@psr2_primary_render.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/shard-iclb6/igt@kms_psr@psr2_primary_render.html

  * igt@kms_psr@sprite_mmap_cpu:
    - shard-iclb:         [PASS][27] -> [SKIP][28] ([i915#668]) +25 similar issues
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/shard-iclb8/igt@kms_psr@sprite_mmap_cpu.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/shard-iclb3/igt@kms_psr@sprite_mmap_cpu.html

  * igt@kms_setmode@basic:
    - shard-apl:          [PASS][29] -> [FAIL][30] ([i915#1635] / [i915#31])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/shard-apl8/igt@kms_setmode@basic.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/shard-apl2/igt@kms_setmode@basic.html

  * igt@perf@polling-parameterized:
    - shard-apl:          [PASS][31] -> [FAIL][32] ([i915#1542] / [i915#1635])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/shard-apl4/igt@perf@polling-parameterized.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/shard-apl8/igt@perf@polling-parameterized.html

  
#### Possible fixes ####

  * {igt@gem_ctx_persistence@heartbeat-many}:
    - shard-tglb:         [FAIL][33] ([i915#2520]) -> [PASS][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/shard-tglb3/igt@gem_ctx_persistence@heartbeat-many.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/shard-tglb3/igt@gem_ctx_persistence@heartbeat-many.html

  * {igt@gem_ctx_persistence@heartbeat-stop}:
    - shard-kbl:          [FAIL][35] ([i915#2520]) -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/shard-kbl7/igt@gem_ctx_persistence@heartbeat-stop.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/shard-kbl3/igt@gem_ctx_persistence@heartbeat-stop.html

  * igt@i915_selftest@live@gt_heartbeat:
    - shard-skl:          [DMESG-FAIL][37] ([i915#541]) -> [PASS][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/shard-skl8/igt@i915_selftest@live@gt_heartbeat.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/shard-skl2/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@mock@contexts:
    - shard-skl:          [INCOMPLETE][39] ([i915#198] / [i915#2278]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/shard-skl1/igt@i915_selftest@mock@contexts.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/shard-skl5/igt@i915_selftest@mock@contexts.html

  * igt@i915_suspend@debugfs-reader:
    - shard-skl:          [INCOMPLETE][41] ([i915#198]) -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/shard-skl6/igt@i915_suspend@debugfs-reader.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/shard-skl3/igt@i915_suspend@debugfs-reader.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-skl:          [FAIL][43] ([i915#2346]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/shard-skl5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_cursor_legacy@short-flip-before-cursor-atomic-transitions-varying-size:
    - shard-apl:          [DMESG-WARN][45] ([i915#1635] / [i915#1982]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/shard-apl7/igt@kms_cursor_legacy@short-flip-before-cursor-atomic-transitions-varying-size.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/shard-apl6/igt@kms_cursor_legacy@short-flip-before-cursor-atomic-transitions-varying-size.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1:
    - shard-apl:          [FAIL][47] ([i915#1635] / [i915#79]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/shard-apl6/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/shard-apl8/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
    - shard-kbl:          [DMESG-WARN][49] ([i915#180]) -> [PASS][50] +7 similar issues
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/shard-kbl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt:
    - shard-tglb:         [DMESG-WARN][51] ([i915#1982]) -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/shard-tglb3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/shard-tglb3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_hdr@bpc-switch:
    - shard-skl:          [FAIL][53] ([i915#1188]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/shard-skl5/igt@kms_hdr@bpc-switch.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/shard-skl3/igt@kms_hdr@bpc-switch.html

  * igt@kms_plane@plane-panning-bottom-right-pipe-b-planes:
    - shard-skl:          [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] +12 similar issues
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/shard-skl8/igt@kms_plane@plane-panning-bottom-right-pipe-b-planes.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/shard-skl2/igt@kms_plane@plane-panning-bottom-right-pipe-b-planes.html

  * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
    - shard-skl:          [FAIL][57] ([fdo#108145] / [i915#265]) -> [PASS][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/shard-skl5/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html

  * igt@kms_psr@psr2_cursor_mmap_cpu:
    - shard-iclb:         [SKIP][59] ([fdo#109441]) -> [PASS][60] +2 similar issues
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/shard-iclb5/igt@kms_psr@psr2_cursor_mmap_cpu.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html

  
#### Warnings ####

  * igt@kms_content_protection@lic:
    - shard-apl:          [TIMEOUT][61] ([i915#1319] / [i915#1635] / [i915#1958]) -> [DMESG-FAIL][62] ([i915#1635]) +4 similar issues
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/shard-apl3/igt@kms_content_protection@lic.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/shard-apl1/igt@kms_content_protection@lic.html

  * igt@kms_content_protection@uevent:
    - shard-apl:          [FAIL][63] ([i915#1635] / [i915#2105]) -> [DMESG-FAIL][64] ([i915#1635])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/shard-apl7/igt@kms_content_protection@uevent.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/shard-apl6/igt@kms_content_protection@uevent.html

  * igt@kms_setmode@basic:
    - shard-skl:          [DMESG-FAIL][65] ([i915#1982] / [i915#31]) -> [FAIL][66] ([i915#31])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/shard-skl7/igt@kms_setmode@basic.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/shard-skl8/igt@kms_setmode@basic.html

  * igt@perf@polling-small-buf:
    - shard-skl:          [DMESG-WARN][67] ([i915#1982]) -> [DMESG-FAIL][68] ([i915#1982])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/shard-skl5/igt@perf@polling-small-buf.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/shard-skl4/igt@perf@polling-small-buf.html

  * igt@runner@aborted:
    - shard-skl:          [FAIL][69] ([i915#1436] / [i915#2439]) -> [FAIL][70] ([i915#1611] / [i915#2029])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9075/shard-skl1/igt@runner@aborted.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/shard-skl4/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
  [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
  [i915#1611]: https://gitlab.freedesktop.org/drm/intel/issues/1611
  [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958
  [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
  [i915#2105]: https://gitlab.freedesktop.org/drm/intel/issues/2105
  [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
  [i915#2278]: https://gitlab.freedesktop.org/drm/intel/issues/2278
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2439]: https://gitlab.freedesktop.org/drm/intel/issues/2439
  [i915#2469]: https://gitlab.freedesktop.org/drm/intel/issues/2469
  [i915#2476]: https://gitlab.freedesktop.org/drm/intel/issues/2476
  [i915#2519]: https://gitlab.freedesktop.org/drm/intel/issues/2519
  [i915#2520]: https://gitlab.freedesktop.org/drm/intel/issues/2520
  [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
  [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
  [i915#668]: https://gitlab.freedesktop.org/drm/intel/issues/668
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79


Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * Linux: CI_DRM_9075 -> Patchwork_18594

  CI-20190529: 20190529
  CI_DRM_9075: fd24361b2b76956b5c056bc430a4c77edecb7744 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5792: cbaf441899f3b4f36cca5996aa6a69e7399b2dbd @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_18594: 4c9eb175070d931ba14945be9780a2667fa8fc5f @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18594/index.html

[-- Attachment #1.2: Type: text/html, Size: 20085 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

* Re: [Intel-gfx] [PATCH v2 01/11] drm/i915: s/pre_empemph/preemph/
  2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 01/11] drm/i915: s/pre_empemph/preemph/ Ville Syrjala
@ 2020-09-30 13:56   ` Imre Deak
  0 siblings, 0 replies; 37+ messages in thread
From: Imre Deak @ 2020-09-30 13:56 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

On Wed, Sep 30, 2020 at 02:34:39AM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> I managed to fumble some functions names. Fix them.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 54a4b81ea3ff..ff96540c8612 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4167,12 +4167,12 @@ static u8 intel_dp_voltage_max_3(struct intel_dp *intel_dp)
>  	return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
>  }
>  
> -static u8 intel_dp_pre_empemph_max_2(struct intel_dp *intel_dp)
> +static u8 intel_dp_preemph_max_2(struct intel_dp *intel_dp)
>  {
>  	return DP_TRAIN_PRE_EMPH_LEVEL_2;
>  }
>  
> -static u8 intel_dp_pre_empemph_max_3(struct intel_dp *intel_dp)
> +static u8 intel_dp_preemph_max_3(struct intel_dp *intel_dp)
>  {
>  	return DP_TRAIN_PRE_EMPH_LEVEL_3;
>  }
> @@ -7953,10 +7953,10 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
>  
>  	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
>  	    (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) {
> -		dig_port->dp.preemph_max = intel_dp_pre_empemph_max_3;
> +		dig_port->dp.preemph_max = intel_dp_preemph_max_3;
>  		dig_port->dp.voltage_max = intel_dp_voltage_max_3;
>  	} else {
> -		dig_port->dp.preemph_max = intel_dp_pre_empemph_max_2;
> +		dig_port->dp.preemph_max = intel_dp_preemph_max_2;
>  		dig_port->dp.voltage_max = intel_dp_voltage_max_2;
>  	}
>  
> -- 
> 2.26.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

* Re: [Intel-gfx] [PATCH v2 02/11] drm/i915: s/old_crtc_state/crtc_state/
  2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 02/11] drm/i915: s/old_crtc_state/crtc_state/ Ville Syrjala
@ 2020-09-30 13:57   ` Imre Deak
  0 siblings, 0 replies; 37+ messages in thread
From: Imre Deak @ 2020-09-30 13:57 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

On Wed, Sep 30, 2020 at 02:34:40AM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> intel_dp_enable_port() is called during the enable sequence,
> so there is nothing old about the passed in crtc state.
> Rename it.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index ff96540c8612..3586d79f5599 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3850,7 +3850,7 @@ g4x_set_link_train(struct intel_dp *intel_dp,
>  }
>  
>  static void intel_dp_enable_port(struct intel_dp *intel_dp,
> -				 const struct intel_crtc_state *old_crtc_state)
> +				 const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  
> @@ -3865,7 +3865,7 @@ static void intel_dp_enable_port(struct intel_dp *intel_dp,
>  	 * fail when the power sequencer is freshly used for this port.
>  	 */
>  	intel_dp->DP |= DP_PORT_EN;
> -	if (old_crtc_state->has_audio)
> +	if (crtc_state->has_audio)
>  		intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
>  
>  	intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
> -- 
> 2.26.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

* Re: [Intel-gfx] [PATCH v2 03/11] drm/i915: Make intel_dp_process_phy_request() static
  2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 03/11] drm/i915: Make intel_dp_process_phy_request() static Ville Syrjala
@ 2020-09-30 13:58   ` Imre Deak
  0 siblings, 0 replies; 37+ messages in thread
From: Imre Deak @ 2020-09-30 13:58 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

On Wed, Sep 30, 2020 at 02:34:41AM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> intel_dp_process_phy_request() has no business being externally
> visible. Make it static.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
>  drivers/gpu/drm/i915/display/intel_dp.h | 1 -
>  2 files changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 3586d79f5599..5c673080ecb1 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -5562,7 +5562,7 @@ intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, uint8_t lane_cnt)
>  		       trans_ddi_func_ctl_value);
>  }
>  
> -void intel_dp_process_phy_request(struct intel_dp *intel_dp)
> +static void intel_dp_process_phy_request(struct intel_dp *intel_dp)
>  {
>  	struct drm_dp_phy_test_params *data =
>  		&intel_dp->compliance.test_data.phytest;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index a9580d1df35b..60f44f41fd08 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -123,7 +123,6 @@ void intel_read_dp_sdp(struct intel_encoder *encoder,
>  		       struct intel_crtc_state *crtc_state,
>  		       unsigned int type);
>  bool intel_digital_port_connected(struct intel_encoder *encoder);
> -void intel_dp_process_phy_request(struct intel_dp *intel_dp);
>  
>  static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
>  {
> -- 
> 2.26.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

* Re: [Intel-gfx] [PATCH v3 04/11] drm/i915: Shove the PHY test into the hotplug work
  2020-09-30 10:04   ` [Intel-gfx] [PATCH v3 " Ville Syrjala
@ 2020-09-30 15:12     ` Imre Deak
  0 siblings, 0 replies; 37+ messages in thread
From: Imre Deak @ 2020-09-30 15:12 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

On Wed, Sep 30, 2020 at 01:04:12PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Doing nay kind modeset stuff from the short hpd handler is
> verboten. The ad-hoc PHY test modeset code violates this. And
> by calling various link training related functions it's now
> blocking further work to plumb the crtc state down into the
> link training code.
> 
> Let's hack around that by pushing the PHY test stuff into the
> hotplug work where it's less of a problem. Still not great but
> at least acceptable. We take a few pages from the link retraining
> handbook to handle the locking and whatnot.
> 
> v2: Fix the intel_dp_hotplug() return value
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Looks ok to me:
Reviewed-by: Imre Deak <imre.deak@intel.com>

CC'ing also Animesh and Manasi.

> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 154 ++++++++++++++++++++----
>  1 file changed, 128 insertions(+), 26 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 5c673080ecb1..132b06a649d8 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -5424,25 +5424,6 @@ static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
>  	return test_result;
>  }
>  
> -static u8 intel_dp_prepare_phytest(struct intel_dp *intel_dp)
> -{
> -	struct drm_dp_phy_test_params *data =
> -		&intel_dp->compliance.test_data.phytest;
> -
> -	if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
> -		DRM_DEBUG_KMS("DP Phy Test pattern AUX read failure\n");
> -		return DP_TEST_NAK;
> -	}
> -
> -	/*
> -	 * link_mst is set to false to avoid executing mst related code
> -	 * during compliance testing.
> -	 */
> -	intel_dp->link_mst = false;
> -
> -	return DP_TEST_ACK;
> -}
> -
>  static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
>  {
>  	struct drm_i915_private *dev_priv =
> @@ -5590,15 +5571,18 @@ static void intel_dp_process_phy_request(struct intel_dp *intel_dp)
>  
>  static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
>  {
> -	u8 test_result;
> +	struct drm_dp_phy_test_params *data =
> +		&intel_dp->compliance.test_data.phytest;
>  
> -	test_result = intel_dp_prepare_phytest(intel_dp);
> -	if (test_result != DP_TEST_ACK)
> -		DRM_ERROR("Phy test preparation failed\n");
> +	if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
> +		DRM_DEBUG_KMS("DP Phy Test pattern AUX read failure\n");
> +		return DP_TEST_NAK;
> +	}
>  
> -	intel_dp_process_phy_request(intel_dp);
> +	/* Set test active flag here so userspace doesn't interrupt things */
> +	intel_dp->compliance.test_active = true;
>  
> -	return test_result;
> +	return DP_TEST_ACK;
>  }
>  
>  static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
> @@ -5887,6 +5871,104 @@ int intel_dp_retrain_link(struct intel_encoder *encoder,
>  	return 0;
>  }
>  
> +static int intel_dp_prep_phy_test(struct intel_dp *intel_dp,
> +				  struct drm_modeset_acquire_ctx *ctx,
> +				  u32 *crtc_mask)
> +{
> +	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> +	struct drm_connector_list_iter conn_iter;
> +	struct intel_connector *connector;
> +	int ret = 0;
> +
> +	*crtc_mask = 0;
> +
> +	drm_connector_list_iter_begin(&i915->drm, &conn_iter);
> +	for_each_intel_connector_iter(connector, &conn_iter) {
> +		struct drm_connector_state *conn_state =
> +			connector->base.state;
> +		struct intel_crtc_state *crtc_state;
> +		struct intel_crtc *crtc;
> +
> +		if (!intel_dp_has_connector(intel_dp, conn_state))
> +			continue;
> +
> +		crtc = to_intel_crtc(conn_state->crtc);
> +		if (!crtc)
> +			continue;
> +
> +		ret = drm_modeset_lock(&crtc->base.mutex, ctx);
> +		if (ret)
> +			break;
> +
> +		crtc_state = to_intel_crtc_state(crtc->base.state);
> +
> +		drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
> +
> +		if (!crtc_state->hw.active)
> +			continue;
> +
> +		if (conn_state->commit &&
> +		    !try_wait_for_completion(&conn_state->commit->hw_done))
> +			continue;
> +
> +		*crtc_mask |= drm_crtc_mask(&crtc->base);
> +	}
> +	drm_connector_list_iter_end(&conn_iter);
> +
> +	return ret;
> +}
> +
> +static int intel_dp_do_phy_test(struct intel_encoder *encoder,
> +				struct drm_modeset_acquire_ctx *ctx)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +	u32 crtc_mask;
> +	int ret;
> +
> +	ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
> +			       ctx);
> +	if (ret)
> +		return ret;
> +
> +	ret = intel_dp_prep_phy_test(intel_dp, ctx, &crtc_mask);
> +	if (ret)
> +		return ret;
> +
> +	if (crtc_mask == 0)
> +		return 0;
> +
> +	drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n",
> +		    encoder->base.base.id, encoder->base.name);
> +	intel_dp_process_phy_request(intel_dp);
> +
> +	return 0;
> +}
> +
> +static void intel_dp_phy_test(struct intel_encoder *encoder)
> +{
> +	struct drm_modeset_acquire_ctx ctx;
> +	int ret;
> +
> +	drm_modeset_acquire_init(&ctx, 0);
> +
> +	for (;;) {
> +		ret = intel_dp_do_phy_test(encoder, &ctx);
> +
> +		if (ret == -EDEADLK) {
> +			drm_modeset_backoff(&ctx);
> +			continue;
> +		}
> +
> +		break;
> +	}
> +
> +	drm_modeset_drop_locks(&ctx);
> +	drm_modeset_acquire_fini(&ctx);
> +	drm_WARN(encoder->base.dev, ret,
> +		 "Acquiring modeset locks failed with %i\n", ret);
> +}
> +
>  /*
>   * If display is now connected check links status,
>   * there has been known issues of link loss triggering
> @@ -5903,10 +5985,18 @@ static enum intel_hotplug_state
>  intel_dp_hotplug(struct intel_encoder *encoder,
>  		 struct intel_connector *connector)
>  {
> +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>  	struct drm_modeset_acquire_ctx ctx;
>  	enum intel_hotplug_state state;
>  	int ret;
>  
> +	if (intel_dp->compliance.test_active &&
> +	    intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) {
> +		intel_dp_phy_test(encoder);
> +		/* just do the PHY test and nothing else */
> +		return INTEL_HOTPLUG_UNCHANGED;
> +	}
> +
>  	state = intel_encoder_hotplug(encoder, connector);
>  
>  	drm_modeset_acquire_init(&ctx, 0);
> @@ -6011,11 +6101,23 @@ intel_dp_short_pulse(struct intel_dp *intel_dp)
>  
>  	intel_psr_short_pulse(intel_dp);
>  
> -	if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
> +	switch (intel_dp->compliance.test_type) {
> +	case DP_TEST_LINK_TRAINING:
>  		drm_dbg_kms(&dev_priv->drm,
>  			    "Link Training Compliance Test requested\n");
>  		/* Send a Hotplug Uevent to userspace to start modeset */
>  		drm_kms_helper_hotplug_event(&dev_priv->drm);
> +		break;
> +	case DP_TEST_LINK_PHY_TEST_PATTERN:
> +		drm_dbg_kms(&dev_priv->drm,
> +			    "PHY test pattern Compliance Test requested\n");
> +		/*
> +		 * Schedule long hpd to do the test
> +		 *
> +		 * FIXME get rid of the ad-hoc phy test modeset code
> +		 * and properly incorporate it into the normal modeset.
> +		 */
> +		return false;
>  	}
>  
>  	return true;
> -- 
> 2.26.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

* Re: [Intel-gfx] [PATCH v2 05/11] drm/i915: Split ICL combo PHY buf trans per output type
  2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 05/11] drm/i915: Split ICL combo PHY buf trans per output type Ville Syrjala
@ 2020-09-30 15:19   ` Imre Deak
  0 siblings, 0 replies; 37+ messages in thread
From: Imre Deak @ 2020-09-30 15:19 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

On Wed, Sep 30, 2020 at 02:34:43AM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Make the mess inside the buf trans funcs a bit more manageable by
> splitting along the lines of output type.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 42 +++++++++++++++++++-----
>  1 file changed, 33 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 4d06178cd76c..4c3416d89f30 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1034,24 +1034,48 @@ cnl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
>  }
>  
>  static const struct cnl_ddi_buf_trans *
> -icl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
> -			int *n_entries)
> +icl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, int type, int rate,
> +			     int *n_entries)
> +{
> +	*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
> +	return icl_combo_phy_ddi_translations_hdmi;
> +}
> +
> +static const struct cnl_ddi_buf_trans *
> +icl_get_combo_buf_trans_dp(struct intel_encoder *encoder, int type, int rate,
> +			   int *n_entries)
> +{
> +	*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
> +	return icl_combo_phy_ddi_translations_dp_hbr2;
> +}
> +
> +static const struct cnl_ddi_buf_trans *
> +icl_get_combo_buf_trans_edp(struct intel_encoder *encoder, int type, int rate,
> +			    int *n_entries)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  
> -	if (type == INTEL_OUTPUT_HDMI) {
> -		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
> -		return icl_combo_phy_ddi_translations_hdmi;
> -	} else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
> +	if (rate > 540000) {
>  		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
>  		return icl_combo_phy_ddi_translations_edp_hbr3;
> -	} else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
> +	} else if (dev_priv->vbt.edp.low_vswing) {
>  		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
>  		return icl_combo_phy_ddi_translations_edp_hbr2;
>  	}
>  
> -	*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
> -	return icl_combo_phy_ddi_translations_dp_hbr2;
> +	return icl_get_combo_buf_trans_dp(encoder, type, rate, n_entries);
> +}
> +
> +static const struct cnl_ddi_buf_trans *
> +icl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
> +			int *n_entries)
> +{
> +	if (type == INTEL_OUTPUT_HDMI)
> +		return icl_get_combo_buf_trans_hdmi(encoder, type, rate, n_entries);
> +	else if (type == INTEL_OUTPUT_EDP)
> +		return icl_get_combo_buf_trans_edp(encoder, type, rate, n_entries);
> +	else
> +		return icl_get_combo_buf_trans_dp(encoder, type, rate, n_entries);
>  }
>  
>  static const struct icl_mg_phy_ddi_buf_trans *
> -- 
> 2.26.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

* Re: [Intel-gfx] [PATCH v2 06/11] drm/i915: Split ICL MG PHY buf trans per output type
  2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 06/11] drm/i915: Split ICL MG " Ville Syrjala
@ 2020-09-30 15:21   ` Imre Deak
  0 siblings, 0 replies; 37+ messages in thread
From: Imre Deak @ 2020-09-30 15:21 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

On Wed, Sep 30, 2020 at 02:34:44AM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Make the mess inside the buf trans funcs a bit more manageable by
> splitting along the lines of output type.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 31 ++++++++++++++++++------
>  1 file changed, 23 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 4c3416d89f30..e3c6d4942b68 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1079,19 +1079,34 @@ icl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
>  }
>  
>  static const struct icl_mg_phy_ddi_buf_trans *
> -icl_get_mg_buf_trans(struct intel_encoder *encoder, int type, int rate,
> -		     int *n_entries)
> +icl_get_mg_buf_trans_hdmi(struct intel_encoder *encoder, int type, int rate,
> +			  int *n_entries)
>  {
> -	if (type == INTEL_OUTPUT_HDMI) {
> -		*n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hdmi);
> -		return icl_mg_phy_ddi_translations_hdmi;
> -	} else if (rate > 270000) {
> +	*n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hdmi);
> +	return icl_mg_phy_ddi_translations_hdmi;
> +}
> +
> +static const struct icl_mg_phy_ddi_buf_trans *
> +icl_get_mg_buf_trans_dp(struct intel_encoder *encoder, int type, int rate,
> +			int *n_entries)
> +{
> +	if (rate > 270000) {
>  		*n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hbr2_hbr3);
>  		return icl_mg_phy_ddi_translations_hbr2_hbr3;
> +	} else {
> +		*n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_rbr_hbr);
> +		return icl_mg_phy_ddi_translations_rbr_hbr;
>  	}
> +}
>  
> -	*n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_rbr_hbr);
> -	return icl_mg_phy_ddi_translations_rbr_hbr;
> +static const struct icl_mg_phy_ddi_buf_trans *
> +icl_get_mg_buf_trans(struct intel_encoder *encoder, int type, int rate,
> +		     int *n_entries)
> +{
> +	if (type == INTEL_OUTPUT_HDMI)
> +		return icl_get_mg_buf_trans_hdmi(encoder, type, rate, n_entries);
> +	else
> +		return icl_get_mg_buf_trans_dp(encoder, type, rate, n_entries);
>  }
>  
>  static const struct cnl_ddi_buf_trans *
> -- 
> 2.26.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

* Re: [Intel-gfx] [PATCH v2 07/11] drm/i915: Split EHL combo PHY buf trans per output type
  2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 07/11] drm/i915: Split EHL combo " Ville Syrjala
@ 2020-09-30 15:24   ` Imre Deak
  0 siblings, 0 replies; 37+ messages in thread
From: Imre Deak @ 2020-09-30 15:24 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

On Wed, Sep 30, 2020 at 02:34:45AM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Make the mess inside the buf trans funcs a bit more manageable by
> splitting along the lines of output type.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 63 +++++++++++++++---------
>  1 file changed, 41 insertions(+), 22 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index e3c6d4942b68..da7090803ea1 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1109,32 +1109,51 @@ icl_get_mg_buf_trans(struct intel_encoder *encoder, int type, int rate,
>  		return icl_get_mg_buf_trans_dp(encoder, type, rate, n_entries);
>  }
>  
> +static const struct cnl_ddi_buf_trans *
> +ehl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, int type, int rate,
> +			     int *n_entries)
> +{
> +	*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
> +	return icl_combo_phy_ddi_translations_hdmi;
> +}
> +
> +static const struct cnl_ddi_buf_trans *
> +ehl_get_combo_buf_trans_dp(struct intel_encoder *encoder, int type, int rate,
> +			   int *n_entries)
> +{
> +	*n_entries = ARRAY_SIZE(ehl_combo_phy_ddi_translations_dp);
> +	return ehl_combo_phy_ddi_translations_dp;
> +}
> +
> +static const struct cnl_ddi_buf_trans *
> +ehl_get_combo_buf_trans_edp(struct intel_encoder *encoder, int type, int rate,
> +			    int *n_entries)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +
> +	if (dev_priv->vbt.edp.low_vswing) {
> +		if (rate > 540000) {
> +			*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
> +			return icl_combo_phy_ddi_translations_edp_hbr3;
> +		} else {
> +			*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
> +			return icl_combo_phy_ddi_translations_edp_hbr2;
> +		}
> +	}
> +
> +	return ehl_get_combo_buf_trans_dp(encoder, type, rate, n_entries);
> +}
> +
>  static const struct cnl_ddi_buf_trans *
>  ehl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
>  			int *n_entries)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -
> -	switch (type) {
> -	case INTEL_OUTPUT_HDMI:
> -		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
> -		return icl_combo_phy_ddi_translations_hdmi;
> -	case INTEL_OUTPUT_EDP:
> -		if (dev_priv->vbt.edp.low_vswing) {
> -			if (rate > 540000) {
> -				*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
> -				return icl_combo_phy_ddi_translations_edp_hbr3;
> -			} else {
> -				*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
> -				return icl_combo_phy_ddi_translations_edp_hbr2;
> -			}
> -		}
> -		/* fall through */
> -	default:
> -		/* All combo DP and eDP ports that do not support low_vswing */
> -		*n_entries = ARRAY_SIZE(ehl_combo_phy_ddi_translations_dp);
> -		return ehl_combo_phy_ddi_translations_dp;
> -	}
> +	if (type == INTEL_OUTPUT_HDMI)
> +		return ehl_get_combo_buf_trans_hdmi(encoder, type, rate, n_entries);
> +	else if (type == INTEL_OUTPUT_EDP)
> +		return ehl_get_combo_buf_trans_edp(encoder, type, rate, n_entries);
> +	else
> +		return ehl_get_combo_buf_trans_dp(encoder, type, rate, n_entries);
>  }
>  
>  static const struct cnl_ddi_buf_trans *
> -- 
> 2.26.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

* Re: [Intel-gfx] [PATCH v2 08/11] drm/i915: Split TGL combo PHY buf trans per output type
  2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 08/11] drm/i915: Split TGL " Ville Syrjala
@ 2020-09-30 15:29   ` Imre Deak
  0 siblings, 0 replies; 37+ messages in thread
From: Imre Deak @ 2020-09-30 15:29 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

On Wed, Sep 30, 2020 at 02:34:46AM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Make the mess inside the buf trans funcs a bit more manageable by
> splitting along the lines of output type.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 83 ++++++++++++++----------
>  1 file changed, 49 insertions(+), 34 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index da7090803ea1..fea06c1b09d9 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1157,51 +1157,66 @@ ehl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
>  }
>  
>  static const struct cnl_ddi_buf_trans *
> -tgl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
> -			int *n_entries)
> +tgl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, int type, int rate,
> +			     int *n_entries)
> +{
> +	*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
> +	return icl_combo_phy_ddi_translations_hdmi;
> +}
> +
> +static const struct cnl_ddi_buf_trans *
> +tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder, int type, int rate,
> +			   int *n_entries)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  
> -	switch (type) {
> -	case INTEL_OUTPUT_HDMI:
> -		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
> -		return icl_combo_phy_ddi_translations_hdmi;
> -	case INTEL_OUTPUT_EDP:
> -		if (dev_priv->vbt.edp.hobl) {
> -			struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> -
> -			if (!intel_dp->hobl_failed && rate <= 540000) {
> -				/* Same table applies to TGL, RKL and DG1 */
> -				*n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_edp_hbr2_hobl);
> -				return tgl_combo_phy_ddi_translations_edp_hbr2_hobl;
> -			}
> -		}
> -
> -		if (rate > 540000) {
> -			*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
> -			return icl_combo_phy_ddi_translations_edp_hbr3;
> -		} else if (dev_priv->vbt.edp.low_vswing) {
> -			*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
> -			return icl_combo_phy_ddi_translations_edp_hbr2;
> -		}
> -		/* fall through */
> -	default:
> -		/* All combo DP and eDP ports that do not support low_vswing */
> -		if (rate > 270000) {
> -			if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
> -				*n_entries = ARRAY_SIZE(tgl_uy_combo_phy_ddi_translations_dp_hbr2);
> -				return tgl_uy_combo_phy_ddi_translations_dp_hbr2;
> -			}
> -
> +	if (rate > 270000) {
> +		if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
> +			*n_entries = ARRAY_SIZE(tgl_uy_combo_phy_ddi_translations_dp_hbr2);
> +			return tgl_uy_combo_phy_ddi_translations_dp_hbr2;
> +		} else {
>  			*n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2);
>  			return tgl_combo_phy_ddi_translations_dp_hbr2;
>  		}
> -
> +	} else {
>  		*n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr);
>  		return tgl_combo_phy_ddi_translations_dp_hbr;
>  	}
>  }
>  
> +static const struct cnl_ddi_buf_trans *
> +tgl_get_combo_buf_trans_edp(struct intel_encoder *encoder, int type, int rate,
> +			    int *n_entries)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +
> +	if (rate > 540000) {
> +		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
> +		return icl_combo_phy_ddi_translations_edp_hbr3;
> +	} else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) {
> +		*n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_edp_hbr2_hobl);
> +		return tgl_combo_phy_ddi_translations_edp_hbr2_hobl;
> +	} else if (dev_priv->vbt.edp.low_vswing) {
> +		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
> +		return icl_combo_phy_ddi_translations_edp_hbr2;
> +	}
> +
> +	return tgl_get_combo_buf_trans_dp(encoder, type, rate, n_entries);
> +}
> +
> +static const struct cnl_ddi_buf_trans *
> +tgl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
> +			int *n_entries)
> +{
> +	if (type == INTEL_OUTPUT_HDMI)
> +		return tgl_get_combo_buf_trans_hdmi(encoder, type, rate, n_entries);
> +	else if (type == INTEL_OUTPUT_EDP)
> +		return tgl_get_combo_buf_trans_edp(encoder, type, rate, n_entries);
> +	else
> +		return tgl_get_combo_buf_trans_dp(encoder, type, rate, n_entries);
> +}
> +
>  static const struct tgl_dkl_phy_ddi_buf_trans *
>  tgl_get_dkl_buf_trans(struct intel_encoder *encoder, int type, int rate,
>  		      int *n_entries)
> -- 
> 2.26.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

* Re: [Intel-gfx] [PATCH v2 09/11] drm/i915: Split TGL DKL PHY buf trans per output type
  2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 09/11] drm/i915: Split TGL DKL " Ville Syrjala
@ 2020-09-30 15:31   ` Imre Deak
  0 siblings, 0 replies; 37+ messages in thread
From: Imre Deak @ 2020-09-30 15:31 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

On Wed, Sep 30, 2020 at 02:34:47AM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Make the mess inside the buf trans funcs a bit more manageable by
> splitting along the lines of output type.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 31 ++++++++++++++++++------
>  1 file changed, 23 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index fea06c1b09d9..7032c367075a 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1218,19 +1218,34 @@ tgl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
>  }
>  
>  static const struct tgl_dkl_phy_ddi_buf_trans *
> -tgl_get_dkl_buf_trans(struct intel_encoder *encoder, int type, int rate,
> -		      int *n_entries)
> +tgl_get_dkl_buf_trans_hdmi(struct intel_encoder *encoder, int type, int rate,
> +			   int *n_entries)
>  {
> -	if (type == INTEL_OUTPUT_HDMI) {
> -		*n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans);
> -		return tgl_dkl_phy_hdmi_ddi_trans;
> -	} else if (rate > 270000) {
> +	*n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans);
> +	return tgl_dkl_phy_hdmi_ddi_trans;
> +}
> +
> +static const struct tgl_dkl_phy_ddi_buf_trans *
> +tgl_get_dkl_buf_trans_dp(struct intel_encoder *encoder, int type, int rate,
> +			 int *n_entries)
> +{
> +	if (rate > 270000) {
>  		*n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans_hbr2);
>  		return tgl_dkl_phy_dp_ddi_trans_hbr2;
> +	} else {
> +		*n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans);
> +		return tgl_dkl_phy_dp_ddi_trans;
>  	}
> +}
>  
> -	*n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans);
> -	return tgl_dkl_phy_dp_ddi_trans;
> +static const struct tgl_dkl_phy_ddi_buf_trans *
> +tgl_get_dkl_buf_trans(struct intel_encoder *encoder, int type, int rate,
> +		      int *n_entries)
> +{
> +	if (type == INTEL_OUTPUT_HDMI)
> +		return tgl_get_dkl_buf_trans_hdmi(encoder, type, rate, n_entries);
> +	else
> +		return tgl_get_dkl_buf_trans_dp(encoder, type, rate, n_entries);
>  }
>  
>  static int intel_ddi_hdmi_level(struct intel_encoder *encoder)
> -- 
> 2.26.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Plumb crtc state to link training code (rev4)
  2020-09-29 23:34 [Intel-gfx] [PATCH v2 00/11] drm/i915: Plumb crtc state to link training code Ville Syrjala
                   ` (15 preceding siblings ...)
  2020-09-30 13:12 ` [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Plumb crtc state to link training code (rev3) Patchwork
@ 2020-09-30 15:35 ` Patchwork
  2020-10-01 11:27 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plumb crtc state to link training code (rev5) Patchwork
                   ` (3 subsequent siblings)
  20 siblings, 0 replies; 37+ messages in thread
From: Patchwork @ 2020-09-30 15:35 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx


[-- Attachment #1.1: Type: text/plain, Size: 18529 bytes --]

== Series Details ==

Series: drm/i915: Plumb crtc state to link training code (rev4)
URL   : https://patchwork.freedesktop.org/series/76993/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9077_full -> Patchwork_18596_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_18596_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_18596_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_18596_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_exec_endless@dispatch@bcs0:
    - shard-iclb:         [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9077/shard-iclb5/igt@gem_exec_endless@dispatch@bcs0.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18596/shard-iclb8/igt@gem_exec_endless@dispatch@bcs0.html

  
#### Warnings ####

  * igt@kms_content_protection@atomic:
    - shard-kbl:          [TIMEOUT][3] ([i915#1319] / [i915#1958]) -> [DMESG-FAIL][4] +3 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9077/shard-kbl1/igt@kms_content_protection@atomic.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18596/shard-kbl4/igt@kms_content_protection@atomic.html

  * igt@kms_content_protection@uevent:
    - shard-kbl:          [FAIL][5] ([i915#2105]) -> [DMESG-FAIL][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9077/shard-kbl1/igt@kms_content_protection@uevent.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18596/shard-kbl6/igt@kms_content_protection@uevent.html

  
Known issues
------------

  Here are the changes found in Patchwork_18596_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_reloc@basic-many-active@vecs0:
    - shard-glk:          [PASS][7] -> [FAIL][8] ([i915#2389]) +1 similar issue
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9077/shard-glk6/igt@gem_exec_reloc@basic-many-active@vecs0.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18596/shard-glk2/igt@gem_exec_reloc@basic-many-active@vecs0.html

  * igt@gem_userptr_blits@sync-unmap-cycles:
    - shard-skl:          [PASS][9] -> [TIMEOUT][10] ([i915#1958] / [i915#2424])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9077/shard-skl9/igt@gem_userptr_blits@sync-unmap-cycles.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18596/shard-skl2/igt@gem_userptr_blits@sync-unmap-cycles.html

  * igt@gem_userptr_blits@unsync-unmap-cycles:
    - shard-skl:          [PASS][11] -> [TIMEOUT][12] ([i915#1958])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9077/shard-skl2/igt@gem_userptr_blits@unsync-unmap-cycles.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18596/shard-skl8/igt@gem_userptr_blits@unsync-unmap-cycles.html

  * igt@i915_pm_rpm@system-suspend-execbuf:
    - shard-skl:          [PASS][13] -> [INCOMPLETE][14] ([i915#151])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9077/shard-skl1/igt@i915_pm_rpm@system-suspend-execbuf.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18596/shard-skl9/igt@i915_pm_rpm@system-suspend-execbuf.html

  * igt@kms_big_fb@linear-8bpp-rotate-180:
    - shard-apl:          [PASS][15] -> [DMESG-WARN][16] ([i915#1635] / [i915#1982])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9077/shard-apl2/igt@kms_big_fb@linear-8bpp-rotate-180.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18596/shard-apl2/igt@kms_big_fb@linear-8bpp-rotate-180.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a1:
    - shard-glk:          [PASS][17] -> [FAIL][18] ([i915#79])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9077/shard-glk2/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a1.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18596/shard-glk7/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a1.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
    - shard-kbl:          [PASS][19] -> [DMESG-WARN][20] ([i915#180]) +2 similar issues
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9077/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18596/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html

  * igt@kms_frontbuffer_tracking@fbcpsr-badstride:
    - shard-tglb:         [PASS][21] -> [SKIP][22] ([i915#668]) +7 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9077/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-badstride.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18596/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-badstride.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-pwrite:
    - shard-iclb:         [PASS][23] -> [SKIP][24] ([i915#668]) +19 similar issues
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9077/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-pwrite.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18596/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-wc:
    - shard-tglb:         [PASS][25] -> [DMESG-WARN][26] ([i915#1982]) +4 similar issues
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9077/shard-tglb3/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-wc.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18596/shard-tglb6/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-wc.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-skl:          [PASS][27] -> [FAIL][28] ([i915#1188])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9077/shard-skl8/igt@kms_hdr@bpc-switch-dpms.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18596/shard-skl2/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_plane_cursor@pipe-b-viewport-size-128:
    - shard-skl:          [PASS][29] -> [DMESG-WARN][30] ([i915#1982]) +14 similar issues
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9077/shard-skl5/igt@kms_plane_cursor@pipe-b-viewport-size-128.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18596/shard-skl4/igt@kms_plane_cursor@pipe-b-viewport-size-128.html

  * igt@kms_psr@psr2_cursor_mmap_cpu:
    - shard-iclb:         [PASS][31] -> [SKIP][32] ([fdo#109441]) +2 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9077/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18596/shard-iclb6/igt@kms_psr@psr2_cursor_mmap_cpu.html

  * igt@kms_vblank@pipe-c-ts-continuation-suspend:
    - shard-skl:          [PASS][33] -> [INCOMPLETE][34] ([i915#198])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9077/shard-skl4/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18596/shard-skl3/igt@kms_vblank@pipe-c-ts-continuation-suspend.html

  
#### Possible fixes ####

  * igt@i915_selftest@mock@contexts:
    - shard-apl:          [INCOMPLETE][35] ([i915#1635] / [i915#2278]) -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9077/shard-apl6/igt@i915_selftest@mock@contexts.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18596/shard-apl6/igt@i915_selftest@mock@contexts.html

  * {igt@kms_async_flips@async-flip-with-page-flip-events}:
    - shard-kbl:          [FAIL][37] ([i915#2521]) -> [PASS][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9077/shard-kbl7/igt@kms_async_flips@async-flip-with-page-flip-events.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18596/shard-kbl2/igt@kms_async_flips@async-flip-with-page-flip-events.html
    - shard-glk:          [FAIL][39] ([i915#2521]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9077/shard-glk7/igt@kms_async_flips@async-flip-with-page-flip-events.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18596/shard-glk9/igt@kms_async_flips@async-flip-with-page-flip-events.html
    - shard-apl:          [FAIL][41] ([i915#1635] / [i915#2521]) -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9077/shard-apl3/igt@kms_async_flips@async-flip-with-page-flip-events.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18596/shard-apl4/igt@kms_async_flips@async-flip-with-page-flip-events.html

  * igt@kms_cursor_crc@pipe-a-cursor-128x128-random:
    - shard-skl:          [FAIL][43] ([i915#54]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9077/shard-skl10/igt@kms_cursor_crc@pipe-a-cursor-128x128-random.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18596/shard-skl6/igt@kms_cursor_crc@pipe-a-cursor-128x128-random.html

  * igt@kms_draw_crc@draw-method-xrgb8888-blt-xtiled:
    - shard-skl:          [FAIL][45] ([i915#52] / [i915#54]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9077/shard-skl7/igt@kms_draw_crc@draw-method-xrgb8888-blt-xtiled.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18596/shard-skl9/igt@kms_draw_crc@draw-method-xrgb8888-blt-xtiled.html

  * igt@kms_flip@dpms-vs-vblank-race@a-hdmi-a1:
    - shard-glk:          [DMESG-WARN][47] ([i915#1982]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9077/shard-glk3/igt@kms_flip@dpms-vs-vblank-race@a-hdmi-a1.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18596/shard-glk3/igt@kms_flip@dpms-vs-vblank-race@a-hdmi-a1.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
    - shard-skl:          [FAIL][49] ([i915#79]) -> [PASS][50] +1 similar issue
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9077/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18596/shard-skl3/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@a-hdmi-a1:
    - shard-glk:          [FAIL][51] ([i915#2122]) -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9077/shard-glk6/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-hdmi-a1.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18596/shard-glk2/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-hdmi-a1.html

  * igt@kms_frontbuffer_tracking@basic:
    - shard-kbl:          [DMESG-WARN][53] ([i915#1982]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9077/shard-kbl1/igt@kms_frontbuffer_tracking@basic.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18596/shard-kbl4/igt@kms_frontbuffer_tracking@basic.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-kbl:          [INCOMPLETE][55] ([i915#155]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9077/shard-kbl3/igt@kms_frontbuffer_tracking@fbc-suspend.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18596/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render:
    - shard-tglb:         [DMESG-WARN][57] ([i915#1982]) -> [PASS][58] +1 similar issue
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9077/shard-tglb7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18596/shard-tglb6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_hdr@bpc-switch:
    - shard-skl:          [FAIL][59] ([i915#1188]) -> [PASS][60]
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9077/shard-skl8/igt@kms_hdr@bpc-switch.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18596/shard-skl1/igt@kms_hdr@bpc-switch.html

  * igt@kms_panel_fitting@atomic-fastset:
    - shard-iclb:         [FAIL][61] ([i915#83]) -> [PASS][62]
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9077/shard-iclb8/igt@kms_panel_fitting@atomic-fastset.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18596/shard-iclb3/igt@kms_panel_fitting@atomic-fastset.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
    - shard-skl:          [INCOMPLETE][63] ([i915#198]) -> [PASS][64] +1 similar issue
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9077/shard-skl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18596/shard-skl10/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html

  * igt@kms_plane@plane-panning-top-left-pipe-c-planes:
    - shard-skl:          [DMESG-WARN][65] ([i915#1982]) -> [PASS][66] +4 similar issues
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9077/shard-skl8/igt@kms_plane@plane-panning-top-left-pipe-c-planes.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18596/shard-skl7/igt@kms_plane@plane-panning-top-left-pipe-c-planes.html

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
    - shard-skl:          [FAIL][67] ([fdo#108145] / [i915#265]) -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9077/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18596/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html

  * igt@kms_psr@psr2_cursor_plane_onoff:
    - shard-iclb:         [SKIP][69] ([fdo#109441]) -> [PASS][70] +1 similar issue
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9077/shard-iclb5/igt@kms_psr@psr2_cursor_plane_onoff.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18596/shard-iclb2/igt@kms_psr@psr2_cursor_plane_onoff.html

  * igt@kms_vblank@pipe-a-ts-continuation-suspend:
    - shard-kbl:          [DMESG-WARN][71] ([i915#180]) -> [PASS][72] +4 similar issues
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9077/shard-kbl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18596/shard-kbl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html

  * igt@prime_vgem@sync@rcs0:
    - shard-iclb:         [INCOMPLETE][73] ([i915#409]) -> [PASS][74]
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9077/shard-iclb6/igt@prime_vgem@sync@rcs0.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18596/shard-iclb2/igt@prime_vgem@sync@rcs0.html

  
#### Warnings ####

  * igt@kms_content_protection@lic:
    - shard-apl:          [TIMEOUT][75] ([i915#1319] / [i915#1635] / [i915#1958]) -> [DMESG-FAIL][76] ([i915#1635]) +4 similar issues
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9077/shard-apl4/igt@kms_content_protection@lic.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18596/shard-apl6/igt@kms_content_protection@lic.html

  * igt@kms_content_protection@uevent:
    - shard-apl:          [FAIL][77] ([i915#1635] / [i915#2105]) -> [DMESG-FAIL][78] ([i915#1635])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9077/shard-apl1/igt@kms_content_protection@uevent.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18596/shard-apl7/igt@kms_content_protection@uevent.html

  * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
    - shard-skl:          [DMESG-FAIL][79] ([fdo#108145] / [i915#1982]) -> [DMESG-WARN][80] ([i915#1982])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9077/shard-skl10/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18596/shard-skl6/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
  [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
  [i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151
  [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
  [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958
  [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2105]: https://gitlab.freedesktop.org/drm/intel/issues/2105
  [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
  [i915#2278]: https://gitlab.freedesktop.org/drm/intel/issues/2278
  [i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389
  [i915#2424]: https://gitlab.freedesktop.org/drm/intel/issues/2424
  [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#409]: https://gitlab.freedesktop.org/drm/intel/issues/409
  [i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52
  [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
  [i915#668]: https://gitlab.freedesktop.org/drm/intel/issues/668
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#83]: https://gitlab.freedesktop.org/drm/intel/issues/83


Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * Linux: CI_DRM_9077 -> Patchwork_18596

  CI-20190529: 20190529
  CI_DRM_9077: ae1f3f7de609df105aeceed2655656ffc838d720 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5793: c34792447c9fc4d05dd75873cdb99d9ffe57ea23 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_18596: 651a007abfa9f60588e3d6baea24e68e92fcb191 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18596/index.html

[-- Attachment #1.2: Type: text/html, Size: 22059 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

* Re: [Intel-gfx] [PATCH v2 10/11] drm/i915: Plumb crtc_state to link training
  2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 10/11] drm/i915: Plumb crtc_state to link training Ville Syrjala
@ 2020-09-30 16:36   ` Imre Deak
  2020-09-30 18:50     ` Ville Syrjälä
  2020-10-01 11:10   ` [Intel-gfx] [PATCH v4 " Ville Syrjala
  1 sibling, 1 reply; 37+ messages in thread
From: Imre Deak @ 2020-09-30 16:36 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

On Wed, Sep 30, 2020 at 02:34:48AM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Get rid of mode crtc->config usage, and some ad-hoc intel_dp state
> usage by plumbing the crtc state all the way down to the link training
> code.
> 
> Unfortunately we do have to keep some cached state in intel_dp so
> that we can do the "does the link need retraining?" checks from
> the short hpd handler.
> 
> v2: Add intel_crtc_state forward declaration
> v3: Don't kill the PHY test code totally since it's
>     now in the hotplug work where we can get at the states
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

4 nitpicks below.

> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c      | 416 +++++++++---------
>  drivers/gpu/drm/i915/display/intel_ddi.h      |   6 +-
>  .../drm/i915/display/intel_display_types.h    |  17 +-
>  drivers/gpu/drm/i915/display/intel_dp.c       | 123 ++++--
>  drivers/gpu/drm/i915/display/intel_dp.h       |  10 +-
>  .../drm/i915/display/intel_dp_link_training.c | 102 +++--
>  .../drm/i915/display/intel_dp_link_training.h |   8 +-
>  drivers/gpu/drm/i915/display/intel_dpio_phy.c |  23 +-
>  drivers/gpu/drm/i915/display/intel_dpio_phy.h |   2 +
>  drivers/gpu/drm/i915/display/intel_hdmi.c     |   7 +-
>  10 files changed, 388 insertions(+), 326 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 7032c367075a..cdf3e5540482 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1034,7 +1034,8 @@ cnl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
>  }
>  
>  static const struct cnl_ddi_buf_trans *
> -icl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, int type, int rate,
> +icl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder,
> +			     const struct intel_crtc_state *crtc_state,
>  			     int *n_entries)
>  {
>  	*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
> @@ -1042,7 +1043,8 @@ icl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, int type, int rate,
>  }
>  
>  static const struct cnl_ddi_buf_trans *
> -icl_get_combo_buf_trans_dp(struct intel_encoder *encoder, int type, int rate,
> +icl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
> +			   const struct intel_crtc_state *crtc_state,
>  			   int *n_entries)
>  {
>  	*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
> @@ -1050,12 +1052,13 @@ icl_get_combo_buf_trans_dp(struct intel_encoder *encoder, int type, int rate,
>  }
>  
>  static const struct cnl_ddi_buf_trans *
> -icl_get_combo_buf_trans_edp(struct intel_encoder *encoder, int type, int rate,
> +icl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
> +			    const struct intel_crtc_state *crtc_state,
>  			    int *n_entries)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  
> -	if (rate > 540000) {
> +	if (crtc_state->port_clock > 540000) {
>  		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
>  		return icl_combo_phy_ddi_translations_edp_hbr3;
>  	} else if (dev_priv->vbt.edp.low_vswing) {
> @@ -1063,23 +1066,25 @@ icl_get_combo_buf_trans_edp(struct intel_encoder *encoder, int type, int rate,
>  		return icl_combo_phy_ddi_translations_edp_hbr2;
>  	}
>  
> -	return icl_get_combo_buf_trans_dp(encoder, type, rate, n_entries);
> +	return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
>  }
>  
>  static const struct cnl_ddi_buf_trans *
> -icl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
> +icl_get_combo_buf_trans(struct intel_encoder *encoder,
> +			const struct intel_crtc_state *crtc_state,
>  			int *n_entries)
>  {
> -	if (type == INTEL_OUTPUT_HDMI)
> -		return icl_get_combo_buf_trans_hdmi(encoder, type, rate, n_entries);
> -	else if (type == INTEL_OUTPUT_EDP)
> -		return icl_get_combo_buf_trans_edp(encoder, type, rate, n_entries);
> +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> +		return icl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries);
> +	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> +		return icl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
>  	else
> -		return icl_get_combo_buf_trans_dp(encoder, type, rate, n_entries);
> +		return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
>  }
>  
>  static const struct icl_mg_phy_ddi_buf_trans *
> -icl_get_mg_buf_trans_hdmi(struct intel_encoder *encoder, int type, int rate,
> +icl_get_mg_buf_trans_hdmi(struct intel_encoder *encoder,
> +			  const struct intel_crtc_state *crtc_state,
>  			  int *n_entries)
>  {
>  	*n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hdmi);
> @@ -1087,10 +1092,11 @@ icl_get_mg_buf_trans_hdmi(struct intel_encoder *encoder, int type, int rate,
>  }
>  
>  static const struct icl_mg_phy_ddi_buf_trans *
> -icl_get_mg_buf_trans_dp(struct intel_encoder *encoder, int type, int rate,
> +icl_get_mg_buf_trans_dp(struct intel_encoder *encoder,
> +			const struct intel_crtc_state *crtc_state,
>  			int *n_entries)
>  {
> -	if (rate > 270000) {
> +	if (crtc_state->port_clock > 270000) {
>  		*n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hbr2_hbr3);
>  		return icl_mg_phy_ddi_translations_hbr2_hbr3;
>  	} else {
> @@ -1100,17 +1106,19 @@ icl_get_mg_buf_trans_dp(struct intel_encoder *encoder, int type, int rate,
>  }
>  
>  static const struct icl_mg_phy_ddi_buf_trans *
> -icl_get_mg_buf_trans(struct intel_encoder *encoder, int type, int rate,
> +icl_get_mg_buf_trans(struct intel_encoder *encoder,
> +		     const struct intel_crtc_state *crtc_state,
>  		     int *n_entries)
>  {
> -	if (type == INTEL_OUTPUT_HDMI)
> -		return icl_get_mg_buf_trans_hdmi(encoder, type, rate, n_entries);
> +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> +		return icl_get_mg_buf_trans_hdmi(encoder, crtc_state, n_entries);
>  	else
> -		return icl_get_mg_buf_trans_dp(encoder, type, rate, n_entries);
> +		return icl_get_mg_buf_trans_dp(encoder, crtc_state, n_entries);
>  }
>  
>  static const struct cnl_ddi_buf_trans *
> -ehl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, int type, int rate,
> +ehl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder,
> +			     const struct intel_crtc_state *crtc_state,
>  			     int *n_entries)
>  {
>  	*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
> @@ -1118,7 +1126,8 @@ ehl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, int type, int rate,
>  }
>  
>  static const struct cnl_ddi_buf_trans *
> -ehl_get_combo_buf_trans_dp(struct intel_encoder *encoder, int type, int rate,
> +ehl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
> +			   const struct intel_crtc_state *crtc_state,
>  			   int *n_entries)
>  {
>  	*n_entries = ARRAY_SIZE(ehl_combo_phy_ddi_translations_dp);
> @@ -1126,13 +1135,14 @@ ehl_get_combo_buf_trans_dp(struct intel_encoder *encoder, int type, int rate,
>  }
>  
>  static const struct cnl_ddi_buf_trans *
> -ehl_get_combo_buf_trans_edp(struct intel_encoder *encoder, int type, int rate,
> +ehl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
> +			    const struct intel_crtc_state *crtc_state,
>  			    int *n_entries)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  
>  	if (dev_priv->vbt.edp.low_vswing) {
> -		if (rate > 540000) {
> +		if (crtc_state->port_clock > 540000) {
>  			*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
>  			return icl_combo_phy_ddi_translations_edp_hbr3;
>  		} else {
> @@ -1141,23 +1151,25 @@ ehl_get_combo_buf_trans_edp(struct intel_encoder *encoder, int type, int rate,
>  		}
>  	}
>  
> -	return ehl_get_combo_buf_trans_dp(encoder, type, rate, n_entries);
> +	return ehl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
>  }
>  
>  static const struct cnl_ddi_buf_trans *
> -ehl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
> +ehl_get_combo_buf_trans(struct intel_encoder *encoder,
> +			const struct intel_crtc_state *crtc_state,
>  			int *n_entries)
>  {
> -	if (type == INTEL_OUTPUT_HDMI)
> -		return ehl_get_combo_buf_trans_hdmi(encoder, type, rate, n_entries);
> -	else if (type == INTEL_OUTPUT_EDP)
> -		return ehl_get_combo_buf_trans_edp(encoder, type, rate, n_entries);
> +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> +		return ehl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries);
> +	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> +		return ehl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
>  	else
> -		return ehl_get_combo_buf_trans_dp(encoder, type, rate, n_entries);
> +		return ehl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
>  }
>  
>  static const struct cnl_ddi_buf_trans *
> -tgl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, int type, int rate,
> +tgl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder,
> +			     const struct intel_crtc_state *crtc_state,
>  			     int *n_entries)
>  {
>  	*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
> @@ -1165,12 +1177,13 @@ tgl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, int type, int rate,
>  }
>  
>  static const struct cnl_ddi_buf_trans *
> -tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder, int type, int rate,
> +tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
> +			   const struct intel_crtc_state *crtc_state,
>  			   int *n_entries)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  
> -	if (rate > 270000) {
> +	if (crtc_state->port_clock > 270000) {
>  		if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
>  			*n_entries = ARRAY_SIZE(tgl_uy_combo_phy_ddi_translations_dp_hbr2);
>  			return tgl_uy_combo_phy_ddi_translations_dp_hbr2;
> @@ -1185,13 +1198,14 @@ tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder, int type, int rate,
>  }
>  
>  static const struct cnl_ddi_buf_trans *
> -tgl_get_combo_buf_trans_edp(struct intel_encoder *encoder, int type, int rate,
> +tgl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
> +			    const struct intel_crtc_state *crtc_state,
>  			    int *n_entries)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>  
> -	if (rate > 540000) {
> +	if (crtc_state->port_clock > 540000) {
>  		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
>  		return icl_combo_phy_ddi_translations_edp_hbr3;
>  	} else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) {
> @@ -1202,23 +1216,25 @@ tgl_get_combo_buf_trans_edp(struct intel_encoder *encoder, int type, int rate,
>  		return icl_combo_phy_ddi_translations_edp_hbr2;
>  	}
>  
> -	return tgl_get_combo_buf_trans_dp(encoder, type, rate, n_entries);
> +	return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
>  }
>  
>  static const struct cnl_ddi_buf_trans *
> -tgl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
> +tgl_get_combo_buf_trans(struct intel_encoder *encoder,
> +			const struct intel_crtc_state *crtc_state,
>  			int *n_entries)
>  {
> -	if (type == INTEL_OUTPUT_HDMI)
> -		return tgl_get_combo_buf_trans_hdmi(encoder, type, rate, n_entries);
> -	else if (type == INTEL_OUTPUT_EDP)
> -		return tgl_get_combo_buf_trans_edp(encoder, type, rate, n_entries);
> +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> +		return tgl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries);
> +	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> +		return tgl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
>  	else
> -		return tgl_get_combo_buf_trans_dp(encoder, type, rate, n_entries);
> +		return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
>  }
>  
>  static const struct tgl_dkl_phy_ddi_buf_trans *
> -tgl_get_dkl_buf_trans_hdmi(struct intel_encoder *encoder, int type, int rate,
> +tgl_get_dkl_buf_trans_hdmi(struct intel_encoder *encoder,
> +			   const struct intel_crtc_state *crtc_state,
>  			   int *n_entries)
>  {
>  	*n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans);
> @@ -1226,10 +1242,11 @@ tgl_get_dkl_buf_trans_hdmi(struct intel_encoder *encoder, int type, int rate,
>  }
>  
>  static const struct tgl_dkl_phy_ddi_buf_trans *
> -tgl_get_dkl_buf_trans_dp(struct intel_encoder *encoder, int type, int rate,
> +tgl_get_dkl_buf_trans_dp(struct intel_encoder *encoder,
> +			 const struct intel_crtc_state *crtc_state,
>  			 int *n_entries)
>  {
> -	if (rate > 270000) {
> +	if (crtc_state->port_clock > 270000) {
>  		*n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans_hbr2);
>  		return tgl_dkl_phy_dp_ddi_trans_hbr2;
>  	} else {
> @@ -1239,16 +1256,18 @@ tgl_get_dkl_buf_trans_dp(struct intel_encoder *encoder, int type, int rate,
>  }
>  
>  static const struct tgl_dkl_phy_ddi_buf_trans *
> -tgl_get_dkl_buf_trans(struct intel_encoder *encoder, int type, int rate,
> +tgl_get_dkl_buf_trans(struct intel_encoder *encoder,
> +		      const struct intel_crtc_state *crtc_state,
>  		      int *n_entries)
>  {
> -	if (type == INTEL_OUTPUT_HDMI)
> -		return tgl_get_dkl_buf_trans_hdmi(encoder, type, rate, n_entries);
> +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> +		return tgl_get_dkl_buf_trans_hdmi(encoder, crtc_state, n_entries);
>  	else
> -		return tgl_get_dkl_buf_trans_dp(encoder, type, rate, n_entries);
> +		return tgl_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries);
>  }
>  
> -static int intel_ddi_hdmi_level(struct intel_encoder *encoder)
> +static int intel_ddi_hdmi_level(struct intel_encoder *encoder,
> +				const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	int n_entries, level, default_entry;
> @@ -1256,19 +1275,15 @@ static int intel_ddi_hdmi_level(struct intel_encoder *encoder)
>  
>  	if (INTEL_GEN(dev_priv) >= 12) {
>  		if (intel_phy_is_combo(dev_priv, phy))
> -			tgl_get_combo_buf_trans(encoder, INTEL_OUTPUT_HDMI,
> -						0, &n_entries);
> +			tgl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries);
>  		else
> -			tgl_get_dkl_buf_trans(encoder, INTEL_OUTPUT_HDMI, 0,
> -					      &n_entries);
> +			tgl_get_dkl_buf_trans_hdmi(encoder, crtc_state, &n_entries);
>  		default_entry = n_entries - 1;
>  	} else if (INTEL_GEN(dev_priv) == 11) {
>  		if (intel_phy_is_combo(dev_priv, phy))
> -			icl_get_combo_buf_trans(encoder, INTEL_OUTPUT_HDMI,
> -						0, &n_entries);
> +			icl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries);
>  		else
> -			icl_get_mg_buf_trans(encoder, INTEL_OUTPUT_HDMI, 0,
> -					     &n_entries);
> +			icl_get_mg_buf_trans_hdmi(encoder, crtc_state, &n_entries);
>  		default_entry = n_entries - 1;
>  	} else if (IS_CANNONLAKE(dev_priv)) {
>  		cnl_get_buf_trans_hdmi(encoder, &n_entries);
> @@ -1595,14 +1610,15 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
>  		       DP_TP_CTL_ENABLE);
>  }
>  
> -static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
> +static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
> +				      const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>  
>  	intel_dp->DP = dig_port->saved_port_bits |
>  		DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
> -	intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
> +	intel_dp->DP |= DDI_PORT_WIDTH(crtc_state->lane_count);
>  }
>  
>  static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
> @@ -2266,13 +2282,14 @@ static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
>  }
>  
>  static void skl_ddi_set_iboost(struct intel_encoder *encoder,
> -			       int level, enum intel_output_type type)
> +			       const struct intel_crtc_state *crtc_state,
> +			       int level)
>  {
>  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	u8 iboost;
>  
> -	if (type == INTEL_OUTPUT_HDMI)
> +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
>  		iboost = intel_bios_hdmi_boost_level(encoder);
>  	else
>  		iboost = intel_bios_dp_boost_level(encoder);
> @@ -2281,14 +2298,12 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder,
>  		const struct ddi_buf_trans *ddi_translations;
>  		int n_entries;
>  
> -		if (type == INTEL_OUTPUT_HDMI)
> +		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
>  			ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
> -		else if (type == INTEL_OUTPUT_EDP)
> -			ddi_translations = intel_ddi_get_buf_trans_edp(encoder,
> -								       &n_entries);
> +		else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> +			ddi_translations = intel_ddi_get_buf_trans_edp(encoder, &n_entries);
>  		else
> -			ddi_translations = intel_ddi_get_buf_trans_dp(encoder,
> -								      &n_entries);
> +			ddi_translations = intel_ddi_get_buf_trans_dp(encoder, &n_entries);
>  
>  		if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
>  			return;
> @@ -2311,16 +2326,17 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder,
>  }
>  
>  static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
> -				    int level, enum intel_output_type type)
> +				    const struct intel_crtc_state *crtc_state,
> +				    int level)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	const struct bxt_ddi_buf_trans *ddi_translations;
>  	enum port port = encoder->port;
>  	int n_entries;
>  
> -	if (type == INTEL_OUTPUT_HDMI)
> +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
>  		ddi_translations = bxt_get_buf_trans_hdmi(encoder, &n_entries);
> -	else if (type == INTEL_OUTPUT_EDP)
> +	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
>  		ddi_translations = bxt_get_buf_trans_edp(encoder, &n_entries);
>  	else
>  		ddi_translations = bxt_get_buf_trans_dp(encoder, &n_entries);
> @@ -2337,7 +2353,8 @@ static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
>  				     ddi_translations[level].deemphasis);
>  }
>  
> -static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp)
> +static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp,
> +				   const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> @@ -2347,33 +2364,28 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp)
>  
>  	if (INTEL_GEN(dev_priv) >= 12) {
>  		if (intel_phy_is_combo(dev_priv, phy))
> -			tgl_get_combo_buf_trans(encoder, encoder->type,
> -						intel_dp->link_rate, &n_entries);
> +			tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
>  		else
> -			tgl_get_dkl_buf_trans(encoder, encoder->type,
> -					      intel_dp->link_rate, &n_entries);
> +			tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
>  	} else if (INTEL_GEN(dev_priv) == 11) {
>  		if (IS_ELKHARTLAKE(dev_priv))
> -			ehl_get_combo_buf_trans(encoder, encoder->type,
> -						intel_dp->link_rate, &n_entries);
> +			ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
>  		else if (intel_phy_is_combo(dev_priv, phy))
> -			icl_get_combo_buf_trans(encoder, encoder->type,
> -						intel_dp->link_rate, &n_entries);
> +			icl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
>  		else
> -			icl_get_mg_buf_trans(encoder, encoder->type,
> -					     intel_dp->link_rate, &n_entries);
> +			icl_get_mg_buf_trans(encoder, crtc_state, &n_entries);
>  	} else if (IS_CANNONLAKE(dev_priv)) {
> -		if (encoder->type == INTEL_OUTPUT_EDP)
> +		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
>  			cnl_get_buf_trans_edp(encoder, &n_entries);
>  		else
>  			cnl_get_buf_trans_dp(encoder, &n_entries);
>  	} else if (IS_GEN9_LP(dev_priv)) {
> -		if (encoder->type == INTEL_OUTPUT_EDP)
> +		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
>  			bxt_get_buf_trans_edp(encoder, &n_entries);
>  		else
>  			bxt_get_buf_trans_dp(encoder, &n_entries);
>  	} else {
> -		if (encoder->type == INTEL_OUTPUT_EDP)
> +		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
>  			intel_ddi_get_buf_trans_edp(encoder, &n_entries);
>  		else
>  			intel_ddi_get_buf_trans_dp(encoder, &n_entries);
> @@ -2400,7 +2412,8 @@ static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp)
>  }
>  
>  static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
> -				   int level, enum intel_output_type type)
> +				   const struct intel_crtc_state *crtc_state,
> +				   int level)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	const struct cnl_ddi_buf_trans *ddi_translations;
> @@ -2408,9 +2421,9 @@ static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
>  	int n_entries, ln;
>  	u32 val;
>  
> -	if (type == INTEL_OUTPUT_HDMI)
> +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
>  		ddi_translations = cnl_get_buf_trans_hdmi(encoder, &n_entries);
> -	else if (type == INTEL_OUTPUT_EDP)
> +	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
>  		ddi_translations = cnl_get_buf_trans_edp(encoder, &n_entries);
>  	else
>  		ddi_translations = cnl_get_buf_trans_dp(encoder, &n_entries);
> @@ -2464,22 +2477,16 @@ static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
>  }
>  
>  static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
> -				    int level, enum intel_output_type type)
> +				    const struct intel_crtc_state *crtc_state,
> +				    int level)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	enum port port = encoder->port;
>  	int width, rate, ln;
>  	u32 val;
>  
> -	if (type == INTEL_OUTPUT_HDMI) {
> -		width = 4;
> -		rate = 0; /* Rate is always < than 6GHz for HDMI */
> -	} else {
> -		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> -
> -		width = intel_dp->lane_count;
> -		rate = intel_dp->link_rate;
> -	}
> +	width = crtc_state->lane_count;
> +	rate = crtc_state->port_clock;
>  
>  	/*
>  	 * 1. If port type is eDP or DP,
> @@ -2487,10 +2494,10 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
>  	 * else clear to 0b.
>  	 */
>  	val = intel_de_read(dev_priv, CNL_PORT_PCS_DW1_LN0(port));
> -	if (type != INTEL_OUTPUT_HDMI)
> -		val |= COMMON_KEEPER_EN;
> -	else
> +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
>  		val &= ~COMMON_KEEPER_EN;
> +	else
> +		val |= COMMON_KEEPER_EN;
>  	intel_de_write(dev_priv, CNL_PORT_PCS_DW1_GRP(port), val);
>  
>  	/* 2. Program loadgen select */
> @@ -2522,7 +2529,7 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
>  	intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
>  
>  	/* 5. Program swing and de-emphasis */
> -	cnl_ddi_vswing_program(encoder, level, type);
> +	cnl_ddi_vswing_program(encoder, crtc_state, level);
>  
>  	/* 6. Set training enable to trigger update */
>  	val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
> @@ -2531,23 +2538,21 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
>  }
>  
>  static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
> -					 u32 level, int type, int rate)
> +					 const struct intel_crtc_state *crtc_state,
> +					 int level)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	const struct cnl_ddi_buf_trans *ddi_translations;
>  	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> -	const struct cnl_ddi_buf_trans *ddi_translations = NULL;
> -	u32 n_entries, val;
> -	int ln;
> +	int n_entries, ln;
> +	u32 val;
>  
>  	if (INTEL_GEN(dev_priv) >= 12)
> -		ddi_translations = tgl_get_combo_buf_trans(encoder, type, rate,
> -							   &n_entries);
> +		ddi_translations = tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
>  	else if (IS_ELKHARTLAKE(dev_priv))
> -		ddi_translations = ehl_get_combo_buf_trans(encoder, type, rate,
> -							   &n_entries);
> +		ddi_translations = ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
>  	else
> -		ddi_translations = icl_get_combo_buf_trans(encoder, type, rate,
> -							   &n_entries);
> +		ddi_translations = icl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
>  	if (!ddi_translations)
>  		return;
>  
> @@ -2558,7 +2563,7 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
>  		level = n_entries - 1;
>  	}
>  
> -	if (type == INTEL_OUTPUT_EDP) {
> +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
>  		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>  
>  		val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED;
> @@ -2606,25 +2611,16 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
>  }
>  
>  static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
> -					      u32 level,
> -					      enum intel_output_type type)
> +					      const struct intel_crtc_state *crtc_state,
> +					      int level)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> -	int width = 0;
> -	int rate = 0;
> +	int width, rate, ln;
>  	u32 val;
> -	int ln = 0;
>  
> -	if (type == INTEL_OUTPUT_HDMI) {
> -		width = 4;
> -		/* Rate is always < than 6GHz for HDMI */
> -	} else {
> -		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> -
> -		width = intel_dp->lane_count;
> -		rate = intel_dp->link_rate;
> -	}
> +	width = crtc_state->lane_count;
> +	rate = crtc_state->port_clock;
>  
>  	/*
>  	 * 1. If port type is eDP or DP,
> @@ -2632,7 +2628,7 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
>  	 * else clear to 0b.
>  	 */
>  	val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy));
> -	if (type == INTEL_OUTPUT_HDMI)
> +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
>  		val &= ~COMMON_KEEPER_EN;
>  	else
>  		val |= COMMON_KEEPER_EN;
> @@ -2667,7 +2663,7 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
>  	intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
>  
>  	/* 5. Program swing and de-emphasis */
> -	icl_ddi_combo_vswing_program(encoder, level, type, rate);
> +	icl_ddi_combo_vswing_program(encoder, crtc_state, level);
>  
>  	/* 6. Set training enable to trigger update */
>  	val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
> @@ -2676,23 +2672,16 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
>  }
>  
>  static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
> -					   int link_clock, u32 level,
> -					   enum intel_output_type type)
> +					   const struct intel_crtc_state *crtc_state,
> +					   int level)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
>  	const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
> -	u32 n_entries, val;
> -	int ln, rate = 0;
> +	int n_entries, ln;
> +	u32 val;
>  
> -	if (type != INTEL_OUTPUT_HDMI) {
> -		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> -
> -		rate = intel_dp->link_rate;
> -	}
> -
> -	ddi_translations = icl_get_mg_buf_trans(encoder, type, rate,
> -						&n_entries);
> +	ddi_translations = icl_get_mg_buf_trans(encoder, crtc_state, &n_entries);
>  	/* The table does not have values for level 3 and level 9. */
>  	if (level >= n_entries || level == 3 || level == 9) {
>  		drm_dbg_kms(&dev_priv->drm,
> @@ -2759,7 +2748,7 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
>  	 */
>  	for (ln = 0; ln < 2; ln++) {
>  		val = intel_de_read(dev_priv, MG_CLKHUB(ln, tc_port));
> -		if (link_clock < 300000)
> +		if (crtc_state->port_clock < 300000)
>  			val |= CFG_LOW_RATE_LKREN_EN;
>  		else
>  			val &= ~CFG_LOW_RATE_LKREN_EN;
> @@ -2770,7 +2759,7 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
>  	for (ln = 0; ln < 2; ln++) {
>  		val = intel_de_read(dev_priv, MG_TX1_DCC(ln, tc_port));
>  		val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
> -		if (link_clock <= 500000) {
> +		if (crtc_state->port_clock <= 500000) {
>  			val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
>  		} else {
>  			val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
> @@ -2780,7 +2769,7 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
>  
>  		val = intel_de_read(dev_priv, MG_TX2_DCC(ln, tc_port));
>  		val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
> -		if (link_clock <= 500000) {
> +		if (crtc_state->port_clock <= 500000) {
>  			val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
>  		} else {
>  			val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
> @@ -2806,38 +2795,30 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
>  }
>  
>  static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
> -				    int link_clock,
> -				    u32 level,
> -				    enum intel_output_type type)
> +				    const struct intel_crtc_state *crtc_state,
> +				    int level)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
>  
>  	if (intel_phy_is_combo(dev_priv, phy))
> -		icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
> +		icl_combo_phy_ddi_vswing_sequence(encoder, crtc_state, level);
>  	else
> -		icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level,
> -					       type);
> +		icl_mg_phy_ddi_vswing_sequence(encoder, crtc_state, level);
>  }
>  
>  static void
> -tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock,
> -				u32 level, enum intel_output_type type)
> +tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
> +				const struct intel_crtc_state *crtc_state,
> +				int level)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
>  	const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations;
> -	u32 n_entries, val, ln, dpcnt_mask, dpcnt_val;
> -	int rate = 0;
> +	u32 val, dpcnt_mask, dpcnt_val;
> +	int n_entries, ln;
>  
> -	if (type == INTEL_OUTPUT_HDMI) {
> -		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> -
> -		rate = intel_dp->link_rate;

Looks like a bugfix and then would make sense to fix it in a separate
patch.

> -	}
> -
> -	ddi_translations = tgl_get_dkl_buf_trans(encoder, encoder->type, rate,
> -						 &n_entries);
> +	ddi_translations = tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
>  
>  	if (level >= n_entries)
>  		level = n_entries - 1;
> @@ -2873,20 +2854,20 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock,
>  }
>  
>  static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder,
> -				    int link_clock,
> -				    u32 level,
> -				    enum intel_output_type type)
> +				    const struct intel_crtc_state *crtc_state,
> +				    int level)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
>  
>  	if (intel_phy_is_combo(dev_priv, phy))
> -		icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
> +		icl_combo_phy_ddi_vswing_sequence(encoder, crtc_state, level);
>  	else
> -		tgl_dkl_phy_ddi_vswing_sequence(encoder, link_clock, level, type);
> +		tgl_dkl_phy_ddi_vswing_sequence(encoder, crtc_state, level);
>  }
>  
> -static u32 translate_signal_level(struct intel_dp *intel_dp, int signal_levels)
> +static int translate_signal_level(struct intel_dp *intel_dp,
> +				  u8 signal_levels)
>  {
>  	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>  	int i;
> @@ -2903,55 +2884,58 @@ static u32 translate_signal_level(struct intel_dp *intel_dp, int signal_levels)
>  	return 0;
>  }
>  
> -static u32 intel_ddi_dp_level(struct intel_dp *intel_dp)
> +static int intel_ddi_dp_level(struct intel_dp *intel_dp)
>  {
>  	u8 train_set = intel_dp->train_set[0];
> -	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
> -					 DP_TRAIN_PRE_EMPHASIS_MASK);
> +	u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
> +					DP_TRAIN_PRE_EMPHASIS_MASK);
>  
>  	return translate_signal_level(intel_dp, signal_levels);
>  }
>  
>  static void
> -tgl_set_signal_levels(struct intel_dp *intel_dp)
> +tgl_set_signal_levels(struct intel_dp *intel_dp,
> +		      const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
>  	int level = intel_ddi_dp_level(intel_dp);
>  
> -	tgl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
> -				level, encoder->type);
> +	tgl_ddi_vswing_sequence(encoder, crtc_state, level);
>  }
>  
>  static void
> -icl_set_signal_levels(struct intel_dp *intel_dp)
> +icl_set_signal_levels(struct intel_dp *intel_dp,
> +		      const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
>  	int level = intel_ddi_dp_level(intel_dp);
>  
> -	icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
> -				level, encoder->type);
> +	icl_ddi_vswing_sequence(encoder, crtc_state, level);
>  }
>  
>  static void
> -cnl_set_signal_levels(struct intel_dp *intel_dp)
> +cnl_set_signal_levels(struct intel_dp *intel_dp,
> +		      const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
>  	int level = intel_ddi_dp_level(intel_dp);
>  
> -	cnl_ddi_vswing_sequence(encoder, level, encoder->type);
> +	cnl_ddi_vswing_sequence(encoder, crtc_state, level);
>  }
>  
>  static void
> -bxt_set_signal_levels(struct intel_dp *intel_dp)
> +bxt_set_signal_levels(struct intel_dp *intel_dp,
> +		      const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
>  	int level = intel_ddi_dp_level(intel_dp);
>  
> -	bxt_ddi_vswing_sequence(encoder, level, encoder->type);
> +	bxt_ddi_vswing_sequence(encoder, crtc_state, level);
>  }
>  
>  static void
> -hsw_set_signal_levels(struct intel_dp *intel_dp)
> +hsw_set_signal_levels(struct intel_dp *intel_dp,
> +		      const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> @@ -2968,7 +2952,7 @@ hsw_set_signal_levels(struct intel_dp *intel_dp)
>  	intel_dp->DP |= signal_levels;
>  
>  	if (IS_GEN9_BC(dev_priv))
> -		skl_ddi_set_iboost(encoder, level, encoder->type);
> +		skl_ddi_set_iboost(encoder, crtc_state, level);
>  
>  	intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
>  	intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
> @@ -3375,8 +3359,9 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
>  	int level = intel_ddi_dp_level(intel_dp);
>  	enum transcoder transcoder = crtc_state->cpu_transcoder;
>  
> -	intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
> -				 crtc_state->lane_count, is_mst);
> +	intel_dp_set_link_params(intel_dp,
> +				 crtc_state->port_clock,
> +				 crtc_state->lane_count);
>  
>  	intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder);
>  	intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder);
> @@ -3448,8 +3433,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
>  	 */
>  
>  	/* 7.e Configure voltage swing and related IO settings */
> -	tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level,
> -				encoder->type);
> +	tgl_ddi_vswing_sequence(encoder, crtc_state, level);
>  
>  	/*
>  	 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up
> @@ -3472,7 +3456,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
>  	 * We only configure what the register value will be here.  Actual
>  	 * enabling happens during link training farther down.
>  	 */
> -	intel_ddi_init_dp_buf_reg(encoder);
> +	intel_ddi_init_dp_buf_reg(encoder, crtc_state);
>  
>  	if (!is_mst)
>  		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
> @@ -3492,11 +3476,11 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
>  	 *     Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
>  	 *     (timeout after 800 us)
>  	 */
> -	intel_dp_start_link_train(intel_dp);
> +	intel_dp_start_link_train(intel_dp, crtc_state);
>  
>  	/* 7.k Set DP_TP_CTL link training to Normal */
>  	if (!is_trans_port_sync_mode(crtc_state))
> -		intel_dp_stop_link_train(intel_dp);
> +		intel_dp_stop_link_train(intel_dp, crtc_state);
>  
>  	/* 7.l Configure and enable FEC if needed */
>  	intel_ddi_enable_fec(encoder, crtc_state);
> @@ -3522,8 +3506,9 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
>  	else
>  		drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A);
>  
> -	intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
> -				 crtc_state->lane_count, is_mst);
> +	intel_dp_set_link_params(intel_dp,
> +				 crtc_state->port_clock,
> +				 crtc_state->lane_count);
>  
>  	intel_edp_panel_on(intel_dp);
>  
> @@ -3537,12 +3522,11 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
>  	icl_program_mg_dp_mode(dig_port, crtc_state);
>  
>  	if (INTEL_GEN(dev_priv) >= 11)
> -		icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
> -					level, encoder->type);
> +		icl_ddi_vswing_sequence(encoder, crtc_state, level);
>  	else if (IS_CANNONLAKE(dev_priv))
> -		cnl_ddi_vswing_sequence(encoder, level, encoder->type);
> +		cnl_ddi_vswing_sequence(encoder, crtc_state, level);
>  	else if (IS_GEN9_LP(dev_priv))
> -		bxt_ddi_vswing_sequence(encoder, level, encoder->type);
> +		bxt_ddi_vswing_sequence(encoder, crtc_state, level);
>  	else
>  		intel_prepare_dp_ddi_buffers(encoder, crtc_state);
>  
> @@ -3555,17 +3539,17 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
>  					       lane_reversal);
>  	}
>  
> -	intel_ddi_init_dp_buf_reg(encoder);
> +	intel_ddi_init_dp_buf_reg(encoder, crtc_state);
>  	if (!is_mst)
>  		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
>  	intel_dp_configure_protocol_converter(intel_dp);
>  	intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
>  					      true);
>  	intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
> -	intel_dp_start_link_train(intel_dp);
> +	intel_dp_start_link_train(intel_dp, crtc_state);
>  	if ((port != PORT_A || INTEL_GEN(dev_priv) >= 9) &&
>  	    !is_trans_port_sync_mode(crtc_state))
> -		intel_dp_stop_link_train(intel_dp);
> +		intel_dp_stop_link_train(intel_dp, crtc_state);
>  
>  	intel_ddi_enable_fec(encoder, crtc_state);
>  
> @@ -3605,7 +3589,7 @@ static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state,
>  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>  	struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	int level = intel_ddi_hdmi_level(encoder);
> +	int level = intel_ddi_hdmi_level(encoder, crtc_state);
>  
>  	intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
>  	intel_ddi_clk_select(encoder, crtc_state);
> @@ -3615,20 +3599,18 @@ static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state,
>  	icl_program_mg_dp_mode(dig_port, crtc_state);
>  
>  	if (INTEL_GEN(dev_priv) >= 12)
> -		tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
> -					level, INTEL_OUTPUT_HDMI);
> +		tgl_ddi_vswing_sequence(encoder, crtc_state, level);
>  	else if (INTEL_GEN(dev_priv) == 11)
> -		icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
> -					level, INTEL_OUTPUT_HDMI);
> +		icl_ddi_vswing_sequence(encoder, crtc_state, level);
>  	else if (IS_CANNONLAKE(dev_priv))
> -		cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
> +		cnl_ddi_vswing_sequence(encoder, crtc_state, level);
>  	else if (IS_GEN9_LP(dev_priv))
> -		bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
> +		bxt_ddi_vswing_sequence(encoder, crtc_state, level);
>  	else
>  		intel_prepare_hdmi_ddi_buffers(encoder, level);
>  
>  	if (IS_GEN9_BC(dev_priv))
> -		skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
> +		skl_ddi_set_iboost(encoder, crtc_state, level);
>  
>  	intel_ddi_enable_pipe_clock(encoder, crtc_state);
>  
> @@ -3918,12 +3900,14 @@ static void trans_port_sync_stop_link_train(struct intel_atomic_state *state,
>  		    crtc_state->cpu_transcoder)
>  			continue;
>  
> -		intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder));
> +		intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder),
> +					 slave_crtc_state);
>  	}
>  
>  	usleep_range(200, 400);
>  
> -	intel_dp_stop_link_train(enc_to_intel_dp(encoder));
> +	intel_dp_stop_link_train(enc_to_intel_dp(encoder),
> +				 crtc_state);
>  }
>  
>  static void intel_enable_ddi_dp(struct intel_atomic_state *state,
> @@ -3936,7 +3920,7 @@ static void intel_enable_ddi_dp(struct intel_atomic_state *state,
>  	enum port port = encoder->port;
>  
>  	if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
> -		intel_dp_stop_link_train(intel_dp);
> +		intel_dp_stop_link_train(intel_dp, crtc_state);
>  
>  	intel_edp_backlight_on(crtc_state, conn_state);
>  	intel_psr_enable(intel_dp, crtc_state, conn_state);
> @@ -4197,7 +4181,8 @@ intel_ddi_pre_pll_enable(struct intel_atomic_state *state,
>  						crtc_state->lane_lat_optim_mask);
>  }
>  
> -static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
> +static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
> +					   const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>  	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> @@ -4224,10 +4209,11 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
>  			intel_wait_ddi_buf_idle(dev_priv, port);
>  	}
>  
> -	dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1;
> -	if (intel_dp->link_mst)
> +	dp_tp_ctl = DP_TP_CTL_ENABLE |
> +		    DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;

Disable scrambling looks like some HW debugging feature, the HW toggles it
automatically based on the spec. There was a recent related change
removing setting it in intel_ddi_set_link_train().

If needed, it should be a separate change imo.


> +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
>  		dp_tp_ctl |= DP_TP_CTL_MODE_MST;
> -	else {
> +	} else {
>  		dp_tp_ctl |= DP_TP_CTL_MODE_SST;
>  		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
>  			dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
> @@ -4243,6 +4229,7 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
>  }
>  
>  static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
> +				     const struct intel_crtc_state *crtc_state,
>  				     u8 dp_train_pat)
>  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> @@ -4273,7 +4260,8 @@ static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
>  	intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, temp);
>  }
>  
> -static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp)
> +static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp,
> +					  const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h
> index f5fb62fc9400..9a2ac73164f8 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.h
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.h
> @@ -41,8 +41,10 @@ void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
>  				    bool state);
>  void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
>  					 struct intel_crtc_state *crtc_state);
> -u32 bxt_signal_levels(struct intel_dp *intel_dp);
> -u32 ddi_signal_levels(struct intel_dp *intel_dp);
> +u32 bxt_signal_levels(struct intel_dp *intel_dp,
> +		      const struct intel_crtc_state *crtc_state);
> +u32 ddi_signal_levels(struct intel_dp *intel_dp,
> +		      const struct intel_crtc_state *crtc_state);
>  int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
>  				     enum transcoder cpu_transcoder,
>  				     bool enable);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index e3339e41ddf7..66d197153c93 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1273,7 +1273,6 @@ struct intel_dp {
>  	int link_rate;
>  	u8 lane_count;
>  	u8 sink_count;
> -	bool link_mst;
>  	bool link_trained;
>  	bool has_hdmi_sink;
>  	bool has_audio;
> @@ -1366,13 +1365,19 @@ struct intel_dp {
>  	i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
>  
>  	/* This is called before a link training is starterd */
> -	void (*prepare_link_retrain)(struct intel_dp *intel_dp);
> -	void (*set_link_train)(struct intel_dp *intel_dp, u8 dp_train_pat);
> -	void (*set_idle_link_train)(struct intel_dp *intel_dp);
> -	void (*set_signal_levels)(struct intel_dp *intel_dp);
> +	void (*prepare_link_retrain)(struct intel_dp *intel_dp,
> +				     const struct intel_crtc_state *crtc_state);
> +	void (*set_link_train)(struct intel_dp *intel_dp,
> +			       const struct intel_crtc_state *crtc_state,
> +			       u8 dp_train_pat);
> +	void (*set_idle_link_train)(struct intel_dp *intel_dp,
> +				    const struct intel_crtc_state *crtc_state);
> +	void (*set_signal_levels)(struct intel_dp *intel_dp,
> +				  const struct intel_crtc_state *crtc_state);
>  
>  	u8 (*preemph_max)(struct intel_dp *intel_dp);
> -	u8 (*voltage_max)(struct intel_dp *intel_dp);
> +	u8 (*voltage_max)(struct intel_dp *intel_dp,
> +			  const struct intel_crtc_state *crtc_state);
>  
>  	/* Displayport compliance testing */
>  	struct intel_dp_compliance compliance;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 6718e01909cd..5ac8a06575d4 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2799,13 +2799,11 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>  }
>  
>  void intel_dp_set_link_params(struct intel_dp *intel_dp,
> -			      int link_rate, u8 lane_count,
> -			      bool link_mst)
> +			      int link_rate, int lane_count)
>  {
>  	intel_dp->link_trained = false;
>  	intel_dp->link_rate = link_rate;
>  	intel_dp->lane_count = lane_count;
> -	intel_dp->link_mst = link_mst;
>  }
>  
>  static void intel_dp_prepare(struct intel_encoder *encoder,
> @@ -2817,10 +2815,9 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
>  	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
>  	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
>  
> -	intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
> -				 pipe_config->lane_count,
> -				 intel_crtc_has_type(pipe_config,
> -						     INTEL_OUTPUT_DP_MST));
> +	intel_dp_set_link_params(intel_dp,
> +				 pipe_config->port_clock,
> +				 pipe_config->lane_count);
>  
>  	/*
>  	 * There are four kinds of DP registers:
> @@ -3791,6 +3788,7 @@ static void chv_post_disable_dp(struct intel_atomic_state *state,
>  
>  static void
>  cpt_set_link_train(struct intel_dp *intel_dp,
> +		   const struct intel_crtc_state *crtc_state,
>  		   u8 dp_train_pat)
>  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> @@ -3821,6 +3819,7 @@ cpt_set_link_train(struct intel_dp *intel_dp,
>  
>  static void
>  g4x_set_link_train(struct intel_dp *intel_dp,
> +		   const struct intel_crtc_state *crtc_state,
>  		   u8 dp_train_pat)
>  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> @@ -3856,7 +3855,8 @@ static void intel_dp_enable_port(struct intel_dp *intel_dp,
>  
>  	/* enable with pattern 1 (as per spec) */
>  
> -	intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
> +	intel_dp_program_link_training_pattern(intel_dp, crtc_state,
> +					       DP_TRAINING_PATTERN_1);
>  
>  	/*
>  	 * Magic for VLV/CHV. We _must_ first set up the register
> @@ -3947,8 +3947,8 @@ static void intel_enable_dp(struct intel_atomic_state *state,
>  
>  	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
>  	intel_dp_configure_protocol_converter(intel_dp);
> -	intel_dp_start_link_train(intel_dp);
> -	intel_dp_stop_link_train(intel_dp);
> +	intel_dp_start_link_train(intel_dp, pipe_config);
> +	intel_dp_stop_link_train(intel_dp, pipe_config);
>  
>  	if (pipe_config->has_audio) {
>  		drm_dbg(&dev_priv->drm, "Enabling DP audio on pipe %c\n",
> @@ -4157,12 +4157,14 @@ intel_dp_get_link_status(struct intel_dp *intel_dp, u8 link_status[DP_LINK_STATU
>  				DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
>  }
>  
> -static u8 intel_dp_voltage_max_2(struct intel_dp *intel_dp)
> +static u8 intel_dp_voltage_max_2(struct intel_dp *intel_dp,
> +				 const struct intel_crtc_state *crtc_state)
>  {
>  	return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
>  }
>  
> -static u8 intel_dp_voltage_max_3(struct intel_dp *intel_dp)
> +static u8 intel_dp_voltage_max_3(struct intel_dp *intel_dp,
> +				 const struct intel_crtc_state *crtc_state)
>  {
>  	return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
>  }
> @@ -4177,7 +4179,8 @@ static u8 intel_dp_preemph_max_3(struct intel_dp *intel_dp)
>  	return DP_TRAIN_PRE_EMPH_LEVEL_3;
>  }
>  
> -static void vlv_set_signal_levels(struct intel_dp *intel_dp)
> +static void vlv_set_signal_levels(struct intel_dp *intel_dp,
> +				  const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
>  	unsigned long demph_reg_value, preemph_reg_value,
> @@ -4257,11 +4260,13 @@ static void vlv_set_signal_levels(struct intel_dp *intel_dp)
>  		return;
>  	}
>  
> -	vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
> +	vlv_set_phy_signal_level(encoder, crtc_state,
> +				 demph_reg_value, preemph_reg_value,
>  				 uniqtranscale_reg_value, 0);
>  }
>  
> -static void chv_set_signal_levels(struct intel_dp *intel_dp)
> +static void chv_set_signal_levels(struct intel_dp *intel_dp,
> +				  const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
>  	u32 deemph_reg_value, margin_reg_value;
> @@ -4338,8 +4343,9 @@ static void chv_set_signal_levels(struct intel_dp *intel_dp)
>  		return;
>  	}
>  
> -	chv_set_phy_signal_level(encoder, deemph_reg_value,
> -				 margin_reg_value, uniq_trans_scale);
> +	chv_set_phy_signal_level(encoder, crtc_state,
> +				 deemph_reg_value, margin_reg_value,
> +				 uniq_trans_scale);
>  }
>  
>  static u32 g4x_signal_levels(u8 train_set)
> @@ -4380,7 +4386,8 @@ static u32 g4x_signal_levels(u8 train_set)
>  }
>  
>  static void
> -g4x_set_signal_levels(struct intel_dp *intel_dp)
> +g4x_set_signal_levels(struct intel_dp *intel_dp,
> +		      const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  	u8 train_set = intel_dp->train_set[0];
> @@ -4427,7 +4434,8 @@ static u32 snb_cpu_edp_signal_levels(u8 train_set)
>  }
>  
>  static void
> -snb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp)
> +snb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp,
> +			      const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  	u8 train_set = intel_dp->train_set[0];
> @@ -4478,7 +4486,8 @@ static u32 ivb_cpu_edp_signal_levels(u8 train_set)
>  }
>  
>  static void
> -ivb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp)
> +ivb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp,
> +			      const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  	u8 train_set = intel_dp->train_set[0];
> @@ -4496,7 +4505,8 @@ ivb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp)
>  	intel_de_posting_read(dev_priv, intel_dp->output_reg);
>  }
>  
> -void intel_dp_set_signal_levels(struct intel_dp *intel_dp)
> +void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
> +				const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  	u8 train_set = intel_dp->train_set[0];
> @@ -4510,11 +4520,12 @@ void intel_dp_set_signal_levels(struct intel_dp *intel_dp)
>  		    train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ?
>  		    " (max)" : "");
>  
> -	intel_dp->set_signal_levels(intel_dp);
> +	intel_dp->set_signal_levels(intel_dp, crtc_state);
>  }
>  
>  void
>  intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
> +				       const struct intel_crtc_state *crtc_state,
>  				       u8 dp_train_pat)
>  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> @@ -4525,13 +4536,14 @@ intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
>  			    "Using DP training pattern TPS%d\n",
>  			    dp_train_pat & train_pat_mask);
>  
> -	intel_dp->set_link_train(intel_dp, dp_train_pat);
> +	intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat);
>  }
>  
> -void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
> +void intel_dp_set_idle_link_train(struct intel_dp *intel_dp,
> +				  const struct intel_crtc_state *crtc_state)
>  {
>  	if (intel_dp->set_idle_link_train)
> -		intel_dp->set_idle_link_train(intel_dp);
> +		intel_dp->set_idle_link_train(intel_dp, crtc_state);
>  }
>  
>  static void
> @@ -5424,14 +5436,14 @@ static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
>  	return test_result;
>  }
>  
> -static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
> +static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,
> +					const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv =
>  			to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
> -	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>  	struct drm_dp_phy_test_params *data =
>  			&intel_dp->compliance.test_data.phytest;
> -	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	enum pipe pipe = crtc->pipe;
>  	u32 pattern_val;
>  
> @@ -5491,7 +5503,8 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
>  }
>  
>  static void
> -intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp)
> +intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp,
> +				  const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>  	struct drm_device *dev = dig_port->base.base.dev;
> @@ -5517,7 +5530,8 @@ intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp)
>  }
>  
>  static void
> -intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, uint8_t lane_cnt)
> +intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp,
> +				 const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>  	struct drm_device *dev = dig_port->base.base.dev;
> @@ -5543,7 +5557,8 @@ intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, uint8_t lane_cnt)
>  		       trans_ddi_func_ctl_value);
>  }
>  
> -static void intel_dp_process_phy_request(struct intel_dp *intel_dp)
> +static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
> +					 const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_dp_phy_test_params *data =
>  		&intel_dp->compliance.test_data.phytest;
> @@ -5555,15 +5570,15 @@ static void intel_dp_process_phy_request(struct intel_dp *intel_dp)
>  	}
>  
>  	/* retrieve vswing & pre-emphasis setting */
> -	intel_dp_get_adjust_train(intel_dp, link_status);
> +	intel_dp_get_adjust_train(intel_dp, crtc_state, link_status);
>  
> -	intel_dp_autotest_phy_ddi_disable(intel_dp);
> +	intel_dp_autotest_phy_ddi_disable(intel_dp, crtc_state);
>  
> -	intel_dp_set_signal_levels(intel_dp);
> +	intel_dp_set_signal_levels(intel_dp, crtc_state);
>  
> -	intel_dp_phy_pattern_update(intel_dp);
> +	intel_dp_phy_pattern_update(intel_dp, crtc_state);
>  
> -	intel_dp_autotest_phy_ddi_enable(intel_dp, data->num_lanes);
> +	intel_dp_autotest_phy_ddi_enable(intel_dp, crtc_state);
>  
>  	drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
>  				    link_status[DP_DPCD_REV]);
> @@ -5719,6 +5734,10 @@ intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
>  	/*
>  	 * Validate the cached values of intel_dp->link_rate and
>  	 * intel_dp->lane_count before attempting to retrain.
> +	 *
> +	 * FIXME would be nice to user the crtc state here, but since
> +	 * we need to call this from the short HPD handler that seems
> +	 * a bit hard.
>  	 */
>  	if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
>  					intel_dp->lane_count))
> @@ -5852,8 +5871,20 @@ int intel_dp_retrain_link(struct intel_encoder *encoder,
>  							      intel_crtc_pch_transcoder(crtc), false);
>  	}
>  
> -	intel_dp_start_link_train(intel_dp);
> -	intel_dp_stop_link_train(intel_dp);
> +	for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
> +		const struct intel_crtc_state *crtc_state =
> +			to_intel_crtc_state(crtc->base.state);
> +
> +		/* retrain on the MST master transcoder */
> +		if (INTEL_GEN(dev_priv) >= 12 &&
> +		    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
> +		    crtc_state->cpu_transcoder != crtc_state->mst_master_transcoder)

Could use intel_dp_mst_is_master_trans().

> +			continue;
> +
> +		intel_dp_start_link_train(intel_dp, crtc_state);
> +		intel_dp_stop_link_train(intel_dp, crtc_state);
> +		break;
> +	}
>  
>  	for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
>  		const struct intel_crtc_state *crtc_state =
> @@ -5923,6 +5954,7 @@ static int intel_dp_do_phy_test(struct intel_encoder *encoder,
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +	struct intel_crtc *crtc;
>  	u32 crtc_mask;
>  	int ret;
>  
> @@ -5940,7 +5972,20 @@ static int intel_dp_do_phy_test(struct intel_encoder *encoder,
>  
>  	drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n",
>  		    encoder->base.base.id, encoder->base.name);
> -	intel_dp_process_phy_request(intel_dp);
> +
> +	for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
> +		const struct intel_crtc_state *crtc_state =
> +			to_intel_crtc_state(crtc->base.state);
> +
> +		/* test on the MST master transcoder */
> +		if (INTEL_GEN(dev_priv) >= 12 &&
> +		    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
> +		    crtc_state->cpu_transcoder != crtc_state->mst_master_transcoder)

Here too.

> +			continue;
> +
> +		intel_dp_process_phy_request(intel_dp, crtc_state);
> +		break;
> +	}
>  
>  	return 0;
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index 60f44f41fd08..66854aab9887 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -45,8 +45,7 @@ bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
>  bool intel_dp_init_connector(struct intel_digital_port *dig_port,
>  			     struct intel_connector *intel_connector);
>  void intel_dp_set_link_params(struct intel_dp *intel_dp,
> -			      int link_rate, u8 lane_count,
> -			      bool link_mst);
> +			      int link_rate, int lane_count);
>  int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
>  					    int link_rate, u8 lane_count);
>  int intel_dp_retrain_link(struct intel_encoder *encoder,
> @@ -93,10 +92,13 @@ void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
>  
>  void
>  intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
> +				       const struct intel_crtc_state *crtc_state,
>  				       u8 dp_train_pat);
>  void
> -intel_dp_set_signal_levels(struct intel_dp *intel_dp);
> -void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
> +intel_dp_set_signal_levels(struct intel_dp *intel_dp,
> +			   const struct intel_crtc_state *crtc_state);
> +void intel_dp_set_idle_link_train(struct intel_dp *intel_dp,
> +				  const struct intel_crtc_state *crtc_state);
>  void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
>  			   u8 *link_bw, u8 *rate_select);
>  bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index f2c8b56be9ea..51e8d46d9b7f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -49,8 +49,10 @@ static u8 dp_voltage_max(u8 preemph)
>  	}
>  }
>  
> -void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
> -			       const u8 link_status[DP_LINK_STATUS_SIZE])
> +void
> +intel_dp_get_adjust_train(struct intel_dp *intel_dp,
> +			  const struct intel_crtc_state *crtc_state,
> +			  const u8 link_status[DP_LINK_STATUS_SIZE])
>  {
>  	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>  	u8 v = 0;
> @@ -59,7 +61,7 @@ void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
>  	u8 voltage_max;
>  	u8 preemph_max;
>  
> -	for (lane = 0; lane < intel_dp->lane_count; lane++) {
> +	for (lane = 0; lane < crtc_state->lane_count; lane++) {
>  		v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane));
>  		p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane));
>  	}
> @@ -74,7 +76,7 @@ void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
>  
>  	v = min(v, dp_voltage_max(p));
>  
> -	voltage_max = intel_dp->voltage_max(intel_dp);
> +	voltage_max = intel_dp->voltage_max(intel_dp, crtc_state);
>  	drm_WARN_ON_ONCE(&i915->drm,
>  			 voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_2 &&
>  			 voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_3);
> @@ -88,12 +90,14 @@ void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
>  
>  static bool
>  intel_dp_set_link_train(struct intel_dp *intel_dp,
> +			const struct intel_crtc_state *crtc_state,
>  			u8 dp_train_pat)
>  {
>  	u8 buf[sizeof(intel_dp->train_set) + 1];
>  	int ret, len;
>  
> -	intel_dp_program_link_training_pattern(intel_dp, dp_train_pat);
> +	intel_dp_program_link_training_pattern(intel_dp, crtc_state,
> +					       dp_train_pat);
>  
>  	buf[0] = dp_train_pat;
>  	if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
> @@ -102,8 +106,8 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
>  		len = 1;
>  	} else {
>  		/* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
> -		memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
> -		len = intel_dp->lane_count + 1;
> +		memcpy(buf + 1, intel_dp->train_set, crtc_state->lane_count);
> +		len = crtc_state->lane_count + 1;
>  	}
>  
>  	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
> @@ -114,31 +118,34 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
>  
>  static bool
>  intel_dp_reset_link_train(struct intel_dp *intel_dp,
> -			u8 dp_train_pat)
> +			  const struct intel_crtc_state *crtc_state,
> +			  u8 dp_train_pat)
>  {
>  	memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
> -	intel_dp_set_signal_levels(intel_dp);
> -	return intel_dp_set_link_train(intel_dp, dp_train_pat);
> +	intel_dp_set_signal_levels(intel_dp, crtc_state);
> +	return intel_dp_set_link_train(intel_dp, crtc_state, dp_train_pat);
>  }
>  
>  static bool
> -intel_dp_update_link_train(struct intel_dp *intel_dp)
> +intel_dp_update_link_train(struct intel_dp *intel_dp,
> +			   const struct intel_crtc_state *crtc_state)
>  {
>  	int ret;
>  
> -	intel_dp_set_signal_levels(intel_dp);
> +	intel_dp_set_signal_levels(intel_dp, crtc_state);
>  
>  	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
> -				intel_dp->train_set, intel_dp->lane_count);
> +				intel_dp->train_set, crtc_state->lane_count);
>  
> -	return ret == intel_dp->lane_count;
> +	return ret == crtc_state->lane_count;
>  }
>  
> -static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp)
> +static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,
> +					     const struct intel_crtc_state *crtc_state)
>  {
>  	int lane;
>  
> -	for (lane = 0; lane < intel_dp->lane_count; lane++)
> +	for (lane = 0; lane < crtc_state->lane_count; lane++)
>  		if ((intel_dp->train_set[lane] &
>  		     DP_TRAIN_MAX_SWING_REACHED) == 0)
>  			return false;
> @@ -148,7 +155,8 @@ static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp)
>  
>  /* Enable corresponding port and start training pattern 1 */
>  static bool
> -intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
> +intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
> +				      const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>  	u8 voltage;
> @@ -158,9 +166,9 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
>  	u8 link_bw, rate_select;
>  
>  	if (intel_dp->prepare_link_retrain)
> -		intel_dp->prepare_link_retrain(intel_dp);
> +		intel_dp->prepare_link_retrain(intel_dp, crtc_state);
>  
> -	intel_dp_compute_rate(intel_dp, intel_dp->link_rate,
> +	intel_dp_compute_rate(intel_dp, crtc_state->port_clock,
>  			      &link_bw, &rate_select);
>  
>  	if (link_bw)
> @@ -172,7 +180,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
>  
>  	/* Write the link configuration data */
>  	link_config[0] = link_bw;
> -	link_config[1] = intel_dp->lane_count;
> +	link_config[1] = crtc_state->lane_count;
>  	if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
>  		link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
>  	drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
> @@ -189,7 +197,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
>  	intel_dp->DP |= DP_PORT_EN;
>  
>  	/* clock recovery */
> -	if (!intel_dp_reset_link_train(intel_dp,
> +	if (!intel_dp_reset_link_train(intel_dp, crtc_state,
>  				       DP_TRAINING_PATTERN_1 |
>  				       DP_LINK_SCRAMBLING_DISABLE)) {
>  		drm_err(&i915->drm, "failed to enable link training\n");
> @@ -220,7 +228,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
>  			return false;
>  		}
>  
> -		if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
> +		if (drm_dp_clock_recovery_ok(link_status, crtc_state->lane_count)) {
>  			drm_dbg_kms(&i915->drm, "clock recovery OK\n");
>  			return true;
>  		}
> @@ -239,8 +247,8 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
>  		voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
>  
>  		/* Update training set as requested by target */
> -		intel_dp_get_adjust_train(intel_dp, link_status);
> -		if (!intel_dp_update_link_train(intel_dp)) {
> +		intel_dp_get_adjust_train(intel_dp, crtc_state, link_status);
> +		if (!intel_dp_update_link_train(intel_dp, crtc_state)) {
>  			drm_err(&i915->drm,
>  				"failed to update link training\n");
>  			return false;
> @@ -252,7 +260,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
>  		else
>  			voltage_tries = 1;
>  
> -		if (intel_dp_link_max_vswing_reached(intel_dp))
> +		if (intel_dp_link_max_vswing_reached(intel_dp, crtc_state))
>  			max_vswing_reached = true;
>  
>  	}
> @@ -266,7 +274,8 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
>   * or for 1.4 devices that support it, training Pattern 3 for HBR2
>   * or 1.2 devices that support it, Training Pattern 2 otherwise.
>   */
> -static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
> +static u32 intel_dp_training_pattern(struct intel_dp *intel_dp,
> +				     const struct intel_crtc_state *crtc_state)
>  {
>  	bool source_tps3, sink_tps3, source_tps4, sink_tps4;
>  
> @@ -280,7 +289,7 @@ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
>  	sink_tps4 = drm_dp_tps4_supported(intel_dp->dpcd);
>  	if (source_tps4 && sink_tps4) {
>  		return DP_TRAINING_PATTERN_4;
> -	} else if (intel_dp->link_rate == 810000) {
> +	} else if (crtc_state->port_clock == 810000) {
>  		if (!source_tps4)
>  			drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
>  				    "8.1 Gbps link rate without source HBR3/TPS4 support\n");
> @@ -297,7 +306,7 @@ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
>  	sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd);
>  	if (source_tps3 && sink_tps3) {
>  		return  DP_TRAINING_PATTERN_3;
> -	} else if (intel_dp->link_rate >= 540000) {
> +	} else if (crtc_state->port_clock >= 540000) {
>  		if (!source_tps3)
>  			drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
>  				    ">=5.4/6.48 Gbps link rate without source HBR2/TPS3 support\n");
> @@ -310,7 +319,8 @@ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
>  }
>  
>  static bool
> -intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
> +intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
> +					    const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>  	int tries;
> @@ -318,13 +328,13 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
>  	u8 link_status[DP_LINK_STATUS_SIZE];
>  	bool channel_eq = false;
>  
> -	training_pattern = intel_dp_training_pattern(intel_dp);
> +	training_pattern = intel_dp_training_pattern(intel_dp, crtc_state);
>  	/* Scrambling is disabled for TPS2/3 and enabled for TPS4 */
>  	if (training_pattern != DP_TRAINING_PATTERN_4)
>  		training_pattern |= DP_LINK_SCRAMBLING_DISABLE;
>  
>  	/* channel equalization */
> -	if (!intel_dp_set_link_train(intel_dp,
> +	if (!intel_dp_set_link_train(intel_dp, crtc_state,
>  				     training_pattern)) {
>  		drm_err(&i915->drm, "failed to start channel equalization\n");
>  		return false;
> @@ -341,7 +351,7 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
>  
>  		/* Make sure clock is still ok */
>  		if (!drm_dp_clock_recovery_ok(link_status,
> -					      intel_dp->lane_count)) {
> +					      crtc_state->lane_count)) {
>  			intel_dp_dump_link_status(link_status);
>  			drm_dbg_kms(&i915->drm,
>  				    "Clock recovery check failed, cannot "
> @@ -350,7 +360,7 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
>  		}
>  
>  		if (drm_dp_channel_eq_ok(link_status,
> -					 intel_dp->lane_count)) {
> +					 crtc_state->lane_count)) {
>  			channel_eq = true;
>  			drm_dbg_kms(&i915->drm, "Channel EQ done. DP Training "
>  				    "successful\n");
> @@ -358,8 +368,8 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
>  		}
>  
>  		/* Update training set as requested by target */
> -		intel_dp_get_adjust_train(intel_dp, link_status);
> -		if (!intel_dp_update_link_train(intel_dp)) {
> +		intel_dp_get_adjust_train(intel_dp, crtc_state, link_status);
> +		if (!intel_dp_update_link_train(intel_dp, crtc_state)) {
>  			drm_err(&i915->drm,
>  				"failed to update link training\n");
>  			break;
> @@ -373,35 +383,37 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
>  			    "Channel equalization failed 5 times\n");
>  	}
>  
> -	intel_dp_set_idle_link_train(intel_dp);
> +	intel_dp_set_idle_link_train(intel_dp, crtc_state);
>  
>  	return channel_eq;
>  
>  }
>  
> -void intel_dp_stop_link_train(struct intel_dp *intel_dp)
> +void intel_dp_stop_link_train(struct intel_dp *intel_dp,
> +			      const struct intel_crtc_state *crtc_state)
>  {
>  	intel_dp->link_trained = true;
>  
> -	intel_dp_set_link_train(intel_dp,
> +	intel_dp_set_link_train(intel_dp, crtc_state,
>  				DP_TRAINING_PATTERN_DISABLE);
>  }
>  
>  void
> -intel_dp_start_link_train(struct intel_dp *intel_dp)
> +intel_dp_start_link_train(struct intel_dp *intel_dp,
> +			  const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_connector *intel_connector = intel_dp->attached_connector;
>  
> -	if (!intel_dp_link_training_clock_recovery(intel_dp))
> +	if (!intel_dp_link_training_clock_recovery(intel_dp, crtc_state))
>  		goto failure_handling;
> -	if (!intel_dp_link_training_channel_equalization(intel_dp))
> +	if (!intel_dp_link_training_channel_equalization(intel_dp, crtc_state))
>  		goto failure_handling;
>  
>  	drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
>  		    "[CONNECTOR:%d:%s] Link Training Passed at Link Rate = %d, Lane count = %d",
>  		    intel_connector->base.base.id,
>  		    intel_connector->base.name,
> -		    intel_dp->link_rate, intel_dp->lane_count);
> +		    crtc_state->port_clock, crtc_state->lane_count);
>  	return;
>  
>   failure_handling:
> @@ -409,15 +421,15 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
>  		    "[CONNECTOR:%d:%s] Link Training failed at link rate = %d, lane count = %d",
>  		    intel_connector->base.base.id,
>  		    intel_connector->base.name,
> -		    intel_dp->link_rate, intel_dp->lane_count);
> +		    crtc_state->port_clock, crtc_state->lane_count);
>  
>  	if (intel_dp->hobl_active) {
>  		drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
>  			    "Link Training failed with HOBL active, not enabling it from now on");
>  		intel_dp->hobl_failed = true;
>  	} else if (intel_dp_get_link_train_fallback_values(intel_dp,
> -							   intel_dp->link_rate,
> -							   intel_dp->lane_count)) {
> +							   crtc_state->port_clock,
> +							   crtc_state->lane_count)) {
>  		return;
>  	}
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> index 01f1dabbb060..648a6d1f9fa2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> @@ -8,11 +8,15 @@
>  
>  #include <drm/drm_dp_helper.h>
>  
> +struct intel_crtc_state;
>  struct intel_dp;
>  
>  void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
> +			       const struct intel_crtc_state *crtc_state,
>  			       const u8 link_status[DP_LINK_STATUS_SIZE]);
> -void intel_dp_start_link_train(struct intel_dp *intel_dp);
> -void intel_dp_stop_link_train(struct intel_dp *intel_dp);
> +void intel_dp_start_link_train(struct intel_dp *intel_dp,
> +			       const struct intel_crtc_state *crtc_state);
> +void intel_dp_stop_link_train(struct intel_dp *intel_dp,
> +			      const struct intel_crtc_state *crtc_state);
>  
>  #endif /* __INTEL_DP_LINK_TRAINING_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> index 7910522273b2..514c4a7adffc 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> @@ -644,16 +644,16 @@ bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
>  	return mask;
>  }
>  
> -
>  void chv_set_phy_signal_level(struct intel_encoder *encoder,
> +			      const struct intel_crtc_state *crtc_state,
>  			      u32 deemph_reg_value, u32 margin_reg_value,
>  			      bool uniq_trans_scale)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> -	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
> -	enum pipe pipe = intel_crtc->pipe;
> +	enum pipe pipe = crtc->pipe;
>  	u32 val;
>  	int i;
>  
> @@ -666,7 +666,7 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder,
>  	val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
>  	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
>  
> -	if (intel_crtc->config->lane_count > 2) {
> +	if (crtc_state->lane_count > 2) {
>  		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
>  		val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
>  		val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
> @@ -679,7 +679,7 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder,
>  	val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
>  	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
>  
> -	if (intel_crtc->config->lane_count > 2) {
> +	if (crtc_state->lane_count > 2) {
>  		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
>  		val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
>  		val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
> @@ -687,7 +687,7 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder,
>  	}
>  
>  	/* Program swing deemph */
> -	for (i = 0; i < intel_crtc->config->lane_count; i++) {
> +	for (i = 0; i < crtc_state->lane_count; i++) {
>  		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
>  		val &= ~DPIO_SWING_DEEMPH9P5_MASK;
>  		val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
> @@ -695,7 +695,7 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder,
>  	}
>  
>  	/* Program swing margin */
> -	for (i = 0; i < intel_crtc->config->lane_count; i++) {
> +	for (i = 0; i < crtc_state->lane_count; i++) {
>  		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
>  
>  		val &= ~DPIO_SWING_MARGIN000_MASK;
> @@ -718,7 +718,7 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder,
>  	 * For now, for this unique transition scale selection, set bit
>  	 * 27 for ch0 and ch1.
>  	 */
> -	for (i = 0; i < intel_crtc->config->lane_count; i++) {
> +	for (i = 0; i < crtc_state->lane_count; i++) {
>  		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
>  		if (uniq_trans_scale)
>  			val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
> @@ -732,7 +732,7 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder,
>  	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
>  	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
>  
> -	if (intel_crtc->config->lane_count > 2) {
> +	if (crtc_state->lane_count > 2) {
>  		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
>  		val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
>  		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
> @@ -992,14 +992,15 @@ void chv_phy_post_pll_disable(struct intel_encoder *encoder,
>  }
>  
>  void vlv_set_phy_signal_level(struct intel_encoder *encoder,
> +			      const struct intel_crtc_state *crtc_state,
>  			      u32 demph_reg_value, u32 preemph_reg_value,
>  			      u32 uniqtranscale_reg_value, u32 tx3_demph)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
>  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
> -	enum pipe pipe = intel_crtc->pipe;
> +	enum pipe pipe = crtc->pipe;
>  
>  	vlv_dpio_get(dev_priv);
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.h b/drivers/gpu/drm/i915/display/intel_dpio_phy.h
> index f418aab90b7e..6473440e7457 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.h
> @@ -32,6 +32,7 @@ void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
>  u8 bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
>  
>  void chv_set_phy_signal_level(struct intel_encoder *encoder,
> +			      const struct intel_crtc_state *crtc_state,
>  			      u32 deemph_reg_value, u32 margin_reg_value,
>  			      bool uniq_trans_scale);
>  void chv_data_lane_soft_reset(struct intel_encoder *encoder,
> @@ -46,6 +47,7 @@ void chv_phy_post_pll_disable(struct intel_encoder *encoder,
>  			      const struct intel_crtc_state *old_crtc_state);
>  
>  void vlv_set_phy_signal_level(struct intel_encoder *encoder,
> +			      const struct intel_crtc_state *crtc_state,
>  			      u32 demph_reg_value, u32 preemph_reg_value,
>  			      u32 uniqtranscale_reg_value, u32 tx3_demph);
>  void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 3f2008d845c2..414a46a6b5f3 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -2775,8 +2775,9 @@ static void vlv_hdmi_pre_enable(struct intel_atomic_state *state,
>  	vlv_phy_pre_encoder_enable(encoder, pipe_config);
>  
>  	/* HDMI 1.0V-2dB */
> -	vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
> -				 0x2b247878);
> +	vlv_set_phy_signal_level(encoder, pipe_config,
> +				 0x2b245f5f, 0x00002000,
> +				 0x5578b83a, 0x2b247878);
>  
>  	dig_port->set_infoframes(encoder,
>  			      pipe_config->has_infoframe,
> @@ -2853,7 +2854,7 @@ static void chv_hdmi_pre_enable(struct intel_atomic_state *state,
>  
>  	/* FIXME: Program the support xxx V-dB */
>  	/* Use 800mV-0dB */
> -	chv_set_phy_signal_level(encoder, 128, 102, false);
> +	chv_set_phy_signal_level(encoder, pipe_config, 128, 102, false);
>  
>  	dig_port->set_infoframes(encoder,
>  			      pipe_config->has_infoframe,
> -- 
> 2.26.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

* Re: [Intel-gfx] [PATCH v2 11/11] drm/i915: Eliminate intel_dp.regs.dp_tp_{ctl, status}
  2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 11/11] drm/i915: Eliminate intel_dp.regs.dp_tp_{ctl, status} Ville Syrjala
@ 2020-09-30 17:04   ` Imre Deak
  0 siblings, 0 replies; 37+ messages in thread
From: Imre Deak @ 2020-09-30 17:04 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

On Wed, Sep 30, 2020 at 02:34:49AM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Now that we've plumbed the crtc state all the way down we can
> eliminate the DP_TP_{CTL,STATUS} register offsets from intel_dp,
> and instead we derive them directly from the crtc state.
> 
> And thus we can get rid of the nasty hack in intel_ddi_get_config()
> which mutates intel_dp during the readout.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c      | 107 ++++++++++--------
>  drivers/gpu/drm/i915/display/intel_ddi.h      |   5 +
>  .../drm/i915/display/intel_display_types.h    |   8 --
>  drivers/gpu/drm/i915/display/intel_dp.c       |   2 -
>  drivers/gpu/drm/i915/display/intel_dp_mst.c   |  24 ++--
>  5 files changed, 76 insertions(+), 70 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index cdf3e5540482..11297a8af3b7 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3295,6 +3295,37 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
>  	}
>  }
>  
> +static enum transcoder
> +tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state)
> +{
> +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
> +		return crtc_state->mst_master_transcoder;
> +	else
> +		return crtc_state->cpu_transcoder;
> +}
> +
> +i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder,
> +			 const struct intel_crtc_state *crtc_state)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +
> +	if (INTEL_GEN(dev_priv) >= 12)
> +		return TGL_DP_TP_CTL(tgl_dp_tp_transcoder(crtc_state));
> +	else
> +		return DP_TP_CTL(encoder->port);
> +}
> +
> +i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder,
> +			    const struct intel_crtc_state *crtc_state)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +
> +	if (INTEL_GEN(dev_priv) >= 12)
> +		return TGL_DP_TP_STATUS(tgl_dp_tp_transcoder(crtc_state));
> +	else
> +		return DP_TP_STATUS(encoder->port);
> +}
> +
>  static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
>  					const struct intel_crtc_state *crtc_state)
>  {
> @@ -3319,11 +3350,12 @@ static void intel_ddi_enable_fec(struct intel_encoder *encoder,
>  		return;
>  
>  	intel_dp = enc_to_intel_dp(encoder);
> -	val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
> +	val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
>  	val |= DP_TP_CTL_FEC_ENABLE;
> -	intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val);
> +	intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
>  
> -	if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
> +	if (intel_de_wait_for_set(dev_priv,
> +				  dp_tp_status_reg(encoder, crtc_state),
>  				  DP_TP_STATUS_FEC_ENABLE_LIVE, 1))
>  		drm_err(&dev_priv->drm,
>  			"Timed out waiting for FEC Enable Status\n");
> @@ -3340,10 +3372,10 @@ static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
>  		return;
>  
>  	intel_dp = enc_to_intel_dp(encoder);
> -	val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
> +	val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
>  	val &= ~DP_TP_CTL_FEC_ENABLE;
> -	intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val);
> -	intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl);
> +	intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
> +	intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
>  }
>  
>  static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
> @@ -3357,15 +3389,11 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
>  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>  	bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
>  	int level = intel_ddi_dp_level(intel_dp);
> -	enum transcoder transcoder = crtc_state->cpu_transcoder;
>  
>  	intel_dp_set_link_params(intel_dp,
>  				 crtc_state->port_clock,
>  				 crtc_state->lane_count);
>  
> -	intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder);
> -	intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder);
> -
>  	/*
>  	 * 1. Enable Power Wells
>  	 *
> @@ -3682,12 +3710,10 @@ static void intel_disable_ddi_buf(struct intel_encoder *encoder,
>  	}
>  
>  	if (intel_crtc_has_dp_encoder(crtc_state)) {
> -		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> -
> -		val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
> +		val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
>  		val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
>  		val |= DP_TP_CTL_LINK_TRAIN_PAT1;
> -		intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val);
> +		intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
>  	}
>  
>  	/* Disable FEC in DP Sink */
> @@ -4184,13 +4210,13 @@ intel_ddi_pre_pll_enable(struct intel_atomic_state *state,
>  static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
>  					   const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> -	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> -	enum port port = dig_port->base.port;
> +	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	enum port port = encoder->port;
>  	u32 dp_tp_ctl, ddi_buf_ctl;
>  	bool wait = false;
>  
> -	dp_tp_ctl = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
> +	dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
>  
>  	if (dp_tp_ctl & DP_TP_CTL_ENABLE) {
>  		ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port));
> @@ -4202,8 +4228,8 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
>  
>  		dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
>  		dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1;
> -		intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, dp_tp_ctl);
> -		intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl);
> +		intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
> +		intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
>  
>  		if (wait)
>  			intel_wait_ddi_buf_idle(dev_priv, port);
> @@ -4218,8 +4244,8 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
>  		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
>  			dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
>  	}
> -	intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, dp_tp_ctl);
> -	intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl);
> +	intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
> +	intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
>  
>  	intel_dp->DP |= DDI_BUF_CTL_ENABLE;
>  	intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
> @@ -4232,11 +4258,12 @@ static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
>  				     const struct intel_crtc_state *crtc_state,
>  				     u8 dp_train_pat)
>  {
> -	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
>  	u32 temp;
>  
> -	temp = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
> +	temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
>  
>  	temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
>  	switch (dp_train_pat & train_pat_mask) {
> @@ -4257,7 +4284,7 @@ static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
>  		break;
>  	}
>  
> -	intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, temp);
> +	intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp);
>  }
>  
>  static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp,
> @@ -4268,10 +4295,10 @@ static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp,
>  	enum port port = encoder->port;
>  	u32 val;
>  
> -	val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
> +	val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
>  	val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
>  	val |= DP_TP_CTL_LINK_TRAIN_IDLE;
> -	intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val);
> +	intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
>  
>  	/*
>  	 * Until TGL on PORT_A we can have only eDP in SST mode. There the only
> @@ -4283,7 +4310,8 @@ static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp,
>  	if (port == PORT_A && INTEL_GEN(dev_priv) < 12)
>  		return;
>  
> -	if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
> +	if (intel_de_wait_for_set(dev_priv,
> +				  dp_tp_status_reg(encoder, crtc_state),
>  				  DP_TP_STATUS_IDLE_DONE, 1))
>  		drm_err(&dev_priv->drm,
>  			"Timed out waiting for DP idle patterns\n");
> @@ -4381,7 +4409,6 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
>  	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
> -	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>  	u32 temp, flags = 0;
>  
>  	/* XXX: DSI transcoder paranoia */
> @@ -4451,12 +4478,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
>  		intel_dp_get_m_n(intel_crtc, pipe_config);
>  
>  		if (INTEL_GEN(dev_priv) >= 11) {
> -			i915_reg_t dp_tp_ctl;
> -
> -			if (IS_GEN(dev_priv, 11))
> -				dp_tp_ctl = DP_TP_CTL(encoder->port);
> -			else
> -				dp_tp_ctl = TGL_DP_TP_CTL(pipe_config->cpu_transcoder);
> +			i915_reg_t dp_tp_ctl = dp_tp_ctl_reg(encoder, pipe_config);
>  
>  			pipe_config->fec_enable =
>  				intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE;
> @@ -4489,16 +4511,6 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
>  		break;
>  	}
>  
> -	if (INTEL_GEN(dev_priv) >= 12) {
> -		enum transcoder transcoder =
> -			intel_dp_mst_is_slave_trans(pipe_config) ?
> -			pipe_config->mst_master_transcoder :
> -			pipe_config->cpu_transcoder;
> -
> -		intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder);
> -		intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder);
> -	}
> -
>  	pipe_config->has_audio =
>  		intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
>  
> @@ -4763,11 +4775,6 @@ intel_ddi_init_dp_connector(struct intel_digital_port *dig_port)
>  	dig_port->dp.voltage_max = intel_ddi_dp_voltage_max;
>  	dig_port->dp.preemph_max = intel_ddi_dp_preemph_max;
>  
> -	if (INTEL_GEN(dev_priv) < 12) {
> -		dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port);
> -		dig_port->dp.regs.dp_tp_status = DP_TP_STATUS(port);
> -	}
> -
>  	if (!intel_dp_init_connector(dig_port, connector)) {
>  		kfree(connector);
>  		return NULL;
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h
> index 9a2ac73164f8..dcc711cfe4fe 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.h
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.h
> @@ -7,6 +7,7 @@
>  #define __INTEL_DDI_H__
>  
>  #include "intel_display.h"
> +#include "i915_reg.h"
>  
>  struct drm_connector_state;
>  struct drm_i915_private;
> @@ -18,6 +19,10 @@ struct intel_dpll_hw_state;
>  struct intel_encoder;
>  enum transcoder;
>  
> +i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder,
> +			 const struct intel_crtc_state *crtc_state);
> +i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder,
> +			    const struct intel_crtc_state *crtc_state);
>  void intel_ddi_fdi_post_disable(struct intel_atomic_state *state,
>  				struct intel_encoder *intel_encoder,
>  				const struct intel_crtc_state *old_crtc_state,
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 66d197153c93..d5dc18cb8c39 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1338,14 +1338,6 @@ struct intel_dp {
>  	bool is_mst;
>  	int active_mst_links;
>  
> -	/*
> -	 * DP_TP_* registers may be either on port or transcoder register space.
> -	 */
> -	struct {
> -		i915_reg_t dp_tp_ctl;
> -		i915_reg_t dp_tp_status;
> -	} regs;
> -
>  	/* connector directly attached - won't be use for modeset in mst world */
>  	struct intel_connector *attached_connector;
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 5ac8a06575d4..208851296cce 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -8109,8 +8109,6 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
>  
>  	dig_port->dp.output_reg = output_reg;
>  	dig_port->max_lanes = 4;
> -	dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port);
> -	dig_port->dp.regs.dp_tp_status = DP_TP_STATUS(port);
>  
>  	intel_encoder->type = INTEL_OUTPUT_DP;
>  	intel_encoder->power_domain = intel_port_to_power_domain(port);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 6a874b779b1f..82f38c386dbd 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -318,19 +318,23 @@ intel_dp_mst_atomic_check(struct drm_connector *connector,
>  	return ret;
>  }
>  
> -static void clear_act_sent(struct intel_dp *intel_dp)
> +static void clear_act_sent(struct intel_encoder *encoder,
> +			   const struct intel_crtc_state *crtc_state)
>  {
> -	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> +	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>  
> -	intel_de_write(i915, intel_dp->regs.dp_tp_status,
> +	intel_de_write(i915, dp_tp_status_reg(encoder, crtc_state),
>  		       DP_TP_STATUS_ACT_SENT);
>  }
>  
> -static void wait_for_act_sent(struct intel_dp *intel_dp)
> +static void wait_for_act_sent(struct intel_encoder *encoder,
> +			      const struct intel_crtc_state *crtc_state)
>  {
> -	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> +	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> +	struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
> +	struct intel_dp *intel_dp = &intel_mst->primary->dp;
>  
> -	if (intel_de_wait_for_set(i915, intel_dp->regs.dp_tp_status,
> +	if (intel_de_wait_for_set(i915, dp_tp_status_reg(encoder, crtc_state),
>  				  DP_TP_STATUS_ACT_SENT, 1))
>  		drm_err(&i915->drm, "Timed out waiting for ACT sent\n");
>  
> @@ -392,7 +396,7 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
>  
>  	drm_dp_update_payload_part2(&intel_dp->mst_mgr);
>  
> -	clear_act_sent(intel_dp);
> +	clear_act_sent(encoder, old_crtc_state);
>  
>  	val = intel_de_read(dev_priv,
>  			    TRANS_DDI_FUNC_CTL(old_crtc_state->cpu_transcoder));
> @@ -401,7 +405,7 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
>  		       TRANS_DDI_FUNC_CTL(old_crtc_state->cpu_transcoder),
>  		       val);
>  
> -	wait_for_act_sent(intel_dp);
> +	wait_for_act_sent(encoder, old_crtc_state);
>  
>  	drm_dp_mst_deallocate_vcpi(&intel_dp->mst_mgr, connector->port);
>  
> @@ -535,7 +539,7 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
>  
>  	drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder);
>  
> -	clear_act_sent(intel_dp);
> +	clear_act_sent(encoder, pipe_config);
>  
>  	intel_ddi_enable_transcoder_func(encoder, pipe_config);
>  
> @@ -549,7 +553,7 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
>  	drm_dbg_kms(&dev_priv->drm, "active links %d\n",
>  		    intel_dp->active_mst_links);
>  
> -	wait_for_act_sent(intel_dp);
> +	wait_for_act_sent(encoder, pipe_config);
>  
>  	drm_dp_update_payload_part2(&intel_dp->mst_mgr);
>  
> -- 
> 2.26.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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^ permalink raw reply	[flat|nested] 37+ messages in thread

* Re: [Intel-gfx] [PATCH v2 10/11] drm/i915: Plumb crtc_state to link training
  2020-09-30 16:36   ` Imre Deak
@ 2020-09-30 18:50     ` Ville Syrjälä
  0 siblings, 0 replies; 37+ messages in thread
From: Ville Syrjälä @ 2020-09-30 18:50 UTC (permalink / raw)
  To: Imre Deak; +Cc: intel-gfx

On Wed, Sep 30, 2020 at 07:36:24PM +0300, Imre Deak wrote:
> On Wed, Sep 30, 2020 at 02:34:48AM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Get rid of mode crtc->config usage, and some ad-hoc intel_dp state
> > usage by plumbing the crtc state all the way down to the link training
> > code.
> > 
> > Unfortunately we do have to keep some cached state in intel_dp so
> > that we can do the "does the link need retraining?" checks from
> > the short hpd handler.
> > 
> > v2: Add intel_crtc_state forward declaration
> > v3: Don't kill the PHY test code totally since it's
> >     now in the hotplug work where we can get at the states
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Reviewed-by: Imre Deak <imre.deak@intel.com>
> 
> 4 nitpicks below.
> 
<snip>
> >  static void
> > -tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock,
> > -				u32 level, enum intel_output_type type)
> > +tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
> > +				const struct intel_crtc_state *crtc_state,
> > +				int level)
> >  {
> >  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> >  	enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
> >  	const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations;
> > -	u32 n_entries, val, ln, dpcnt_mask, dpcnt_val;
> > -	int rate = 0;
> > +	u32 val, dpcnt_mask, dpcnt_val;
> > +	int n_entries, ln;
> >  
> > -	if (type == INTEL_OUTPUT_HDMI) {
> > -		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > -
> > -		rate = intel_dp->link_rate;
> 
> Looks like a bugfix and then would make sense to fix it in a separate
> patch.

Didn't even notie this one. I need to check whether it's a current bug
or if I just fumbled the earlier patches somehow.

<snip>
> > @@ -4224,10 +4209,11 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
> >  			intel_wait_ddi_buf_idle(dev_priv, port);
> >  	}
> >  
> > -	dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1;
> > -	if (intel_dp->link_mst)
> > +	dp_tp_ctl = DP_TP_CTL_ENABLE |
> > +		    DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
> 
> Disable scrambling looks like some HW debugging feature, the HW toggles it
> automatically based on the spec. There was a recent related change
> removing setting it in intel_ddi_set_link_train().
> 
> If needed, it should be a separate change imo.

This is just a rebase fail on my part I think.
Thanks for catching it.

<snip>
> > @@ -5852,8 +5871,20 @@ int intel_dp_retrain_link(struct intel_encoder *encoder,
> >  							      intel_crtc_pch_transcoder(crtc), false);
> >  	}
> >  
> > -	intel_dp_start_link_train(intel_dp);
> > -	intel_dp_stop_link_train(intel_dp);
> > +	for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
> > +		const struct intel_crtc_state *crtc_state =
> > +			to_intel_crtc_state(crtc->base.state);
> > +
> > +		/* retrain on the MST master transcoder */
> > +		if (INTEL_GEN(dev_priv) >= 12 &&
> > +		    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
> > +		    crtc_state->cpu_transcoder != crtc_state->mst_master_transcoder)
> 
> Could use intel_dp_mst_is_master_trans().

Ack. Didn't remember we had such a thing.

> 
> > +			continue;
> > +
> > +		intel_dp_start_link_train(intel_dp, crtc_state);
> > +		intel_dp_stop_link_train(intel_dp, crtc_state);
> > +		break;
> > +	}
> >  
> >  	for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
> >  		const struct intel_crtc_state *crtc_state =
> > @@ -5923,6 +5954,7 @@ static int intel_dp_do_phy_test(struct intel_encoder *encoder,
> >  {
> >  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> >  	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > +	struct intel_crtc *crtc;
> >  	u32 crtc_mask;
> >  	int ret;
> >  
> > @@ -5940,7 +5972,20 @@ static int intel_dp_do_phy_test(struct intel_encoder *encoder,
> >  
> >  	drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n",
> >  		    encoder->base.base.id, encoder->base.name);
> > -	intel_dp_process_phy_request(intel_dp);
> > +
> > +	for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
> > +		const struct intel_crtc_state *crtc_state =
> > +			to_intel_crtc_state(crtc->base.state);
> > +
> > +		/* test on the MST master transcoder */
> > +		if (INTEL_GEN(dev_priv) >= 12 &&
> > +		    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
> > +		    crtc_state->cpu_transcoder != crtc_state->mst_master_transcoder)
> 
> Here too.
> 
-- 
Ville Syrjälä
Intel
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^ permalink raw reply	[flat|nested] 37+ messages in thread

* [Intel-gfx] [PATCH v4 10/11] drm/i915: Plumb crtc_state to link training
  2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 10/11] drm/i915: Plumb crtc_state to link training Ville Syrjala
  2020-09-30 16:36   ` Imre Deak
@ 2020-10-01 11:10   ` Ville Syrjala
  1 sibling, 0 replies; 37+ messages in thread
From: Ville Syrjala @ 2020-10-01 11:10 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Get rid of mode crtc->config usage, and some ad-hoc intel_dp state
usage by plumbing the crtc state all the way down to the link training
code.

Unfortunately we do have to keep some cached state in intel_dp so
that we can do the "does the link need retraining?" checks from
the short hpd handler.

v2: Add intel_crtc_state forward declaration
v3: Don't kill the PHY test code totally since it's
    now in the hotplug work where we can get at the states
v4: Don't resurrect the debug scrambling disable bit (Imre)
    Use intel_dp_mst_is_master_trans() (Imre)

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c      | 413 +++++++++---------
 drivers/gpu/drm/i915/display/intel_ddi.h      |   6 +-
 .../drm/i915/display/intel_display_types.h    |  17 +-
 drivers/gpu/drm/i915/display/intel_dp.c       | 123 ++++--
 drivers/gpu/drm/i915/display/intel_dp.h       |  10 +-
 .../drm/i915/display/intel_dp_link_training.c | 102 +++--
 .../drm/i915/display/intel_dp_link_training.h |   8 +-
 drivers/gpu/drm/i915/display/intel_dpio_phy.c |  23 +-
 drivers/gpu/drm/i915/display/intel_dpio_phy.h |   2 +
 drivers/gpu/drm/i915/display/intel_hdmi.c     |   7 +-
 10 files changed, 386 insertions(+), 325 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 7032c367075a..dbf0ffc05c8f 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1034,7 +1034,8 @@ cnl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
 }
 
 static const struct cnl_ddi_buf_trans *
-icl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, int type, int rate,
+icl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder,
+			     const struct intel_crtc_state *crtc_state,
 			     int *n_entries)
 {
 	*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
@@ -1042,7 +1043,8 @@ icl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, int type, int rate,
 }
 
 static const struct cnl_ddi_buf_trans *
-icl_get_combo_buf_trans_dp(struct intel_encoder *encoder, int type, int rate,
+icl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
+			   const struct intel_crtc_state *crtc_state,
 			   int *n_entries)
 {
 	*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
@@ -1050,12 +1052,13 @@ icl_get_combo_buf_trans_dp(struct intel_encoder *encoder, int type, int rate,
 }
 
 static const struct cnl_ddi_buf_trans *
-icl_get_combo_buf_trans_edp(struct intel_encoder *encoder, int type, int rate,
+icl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
+			    const struct intel_crtc_state *crtc_state,
 			    int *n_entries)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
-	if (rate > 540000) {
+	if (crtc_state->port_clock > 540000) {
 		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
 		return icl_combo_phy_ddi_translations_edp_hbr3;
 	} else if (dev_priv->vbt.edp.low_vswing) {
@@ -1063,23 +1066,25 @@ icl_get_combo_buf_trans_edp(struct intel_encoder *encoder, int type, int rate,
 		return icl_combo_phy_ddi_translations_edp_hbr2;
 	}
 
-	return icl_get_combo_buf_trans_dp(encoder, type, rate, n_entries);
+	return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
 }
 
 static const struct cnl_ddi_buf_trans *
-icl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
+icl_get_combo_buf_trans(struct intel_encoder *encoder,
+			const struct intel_crtc_state *crtc_state,
 			int *n_entries)
 {
-	if (type == INTEL_OUTPUT_HDMI)
-		return icl_get_combo_buf_trans_hdmi(encoder, type, rate, n_entries);
-	else if (type == INTEL_OUTPUT_EDP)
-		return icl_get_combo_buf_trans_edp(encoder, type, rate, n_entries);
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+		return icl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries);
+	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
+		return icl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
 	else
-		return icl_get_combo_buf_trans_dp(encoder, type, rate, n_entries);
+		return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
 }
 
 static const struct icl_mg_phy_ddi_buf_trans *
-icl_get_mg_buf_trans_hdmi(struct intel_encoder *encoder, int type, int rate,
+icl_get_mg_buf_trans_hdmi(struct intel_encoder *encoder,
+			  const struct intel_crtc_state *crtc_state,
 			  int *n_entries)
 {
 	*n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hdmi);
@@ -1087,10 +1092,11 @@ icl_get_mg_buf_trans_hdmi(struct intel_encoder *encoder, int type, int rate,
 }
 
 static const struct icl_mg_phy_ddi_buf_trans *
-icl_get_mg_buf_trans_dp(struct intel_encoder *encoder, int type, int rate,
+icl_get_mg_buf_trans_dp(struct intel_encoder *encoder,
+			const struct intel_crtc_state *crtc_state,
 			int *n_entries)
 {
-	if (rate > 270000) {
+	if (crtc_state->port_clock > 270000) {
 		*n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hbr2_hbr3);
 		return icl_mg_phy_ddi_translations_hbr2_hbr3;
 	} else {
@@ -1100,17 +1106,19 @@ icl_get_mg_buf_trans_dp(struct intel_encoder *encoder, int type, int rate,
 }
 
 static const struct icl_mg_phy_ddi_buf_trans *
-icl_get_mg_buf_trans(struct intel_encoder *encoder, int type, int rate,
+icl_get_mg_buf_trans(struct intel_encoder *encoder,
+		     const struct intel_crtc_state *crtc_state,
 		     int *n_entries)
 {
-	if (type == INTEL_OUTPUT_HDMI)
-		return icl_get_mg_buf_trans_hdmi(encoder, type, rate, n_entries);
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+		return icl_get_mg_buf_trans_hdmi(encoder, crtc_state, n_entries);
 	else
-		return icl_get_mg_buf_trans_dp(encoder, type, rate, n_entries);
+		return icl_get_mg_buf_trans_dp(encoder, crtc_state, n_entries);
 }
 
 static const struct cnl_ddi_buf_trans *
-ehl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, int type, int rate,
+ehl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder,
+			     const struct intel_crtc_state *crtc_state,
 			     int *n_entries)
 {
 	*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
@@ -1118,7 +1126,8 @@ ehl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, int type, int rate,
 }
 
 static const struct cnl_ddi_buf_trans *
-ehl_get_combo_buf_trans_dp(struct intel_encoder *encoder, int type, int rate,
+ehl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
+			   const struct intel_crtc_state *crtc_state,
 			   int *n_entries)
 {
 	*n_entries = ARRAY_SIZE(ehl_combo_phy_ddi_translations_dp);
@@ -1126,13 +1135,14 @@ ehl_get_combo_buf_trans_dp(struct intel_encoder *encoder, int type, int rate,
 }
 
 static const struct cnl_ddi_buf_trans *
-ehl_get_combo_buf_trans_edp(struct intel_encoder *encoder, int type, int rate,
+ehl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
+			    const struct intel_crtc_state *crtc_state,
 			    int *n_entries)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
 	if (dev_priv->vbt.edp.low_vswing) {
-		if (rate > 540000) {
+		if (crtc_state->port_clock > 540000) {
 			*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
 			return icl_combo_phy_ddi_translations_edp_hbr3;
 		} else {
@@ -1141,23 +1151,25 @@ ehl_get_combo_buf_trans_edp(struct intel_encoder *encoder, int type, int rate,
 		}
 	}
 
-	return ehl_get_combo_buf_trans_dp(encoder, type, rate, n_entries);
+	return ehl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
 }
 
 static const struct cnl_ddi_buf_trans *
-ehl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
+ehl_get_combo_buf_trans(struct intel_encoder *encoder,
+			const struct intel_crtc_state *crtc_state,
 			int *n_entries)
 {
-	if (type == INTEL_OUTPUT_HDMI)
-		return ehl_get_combo_buf_trans_hdmi(encoder, type, rate, n_entries);
-	else if (type == INTEL_OUTPUT_EDP)
-		return ehl_get_combo_buf_trans_edp(encoder, type, rate, n_entries);
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+		return ehl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries);
+	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
+		return ehl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
 	else
-		return ehl_get_combo_buf_trans_dp(encoder, type, rate, n_entries);
+		return ehl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
 }
 
 static const struct cnl_ddi_buf_trans *
-tgl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, int type, int rate,
+tgl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder,
+			     const struct intel_crtc_state *crtc_state,
 			     int *n_entries)
 {
 	*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
@@ -1165,12 +1177,13 @@ tgl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, int type, int rate,
 }
 
 static const struct cnl_ddi_buf_trans *
-tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder, int type, int rate,
+tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
+			   const struct intel_crtc_state *crtc_state,
 			   int *n_entries)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
-	if (rate > 270000) {
+	if (crtc_state->port_clock > 270000) {
 		if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
 			*n_entries = ARRAY_SIZE(tgl_uy_combo_phy_ddi_translations_dp_hbr2);
 			return tgl_uy_combo_phy_ddi_translations_dp_hbr2;
@@ -1185,13 +1198,14 @@ tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder, int type, int rate,
 }
 
 static const struct cnl_ddi_buf_trans *
-tgl_get_combo_buf_trans_edp(struct intel_encoder *encoder, int type, int rate,
+tgl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
+			    const struct intel_crtc_state *crtc_state,
 			    int *n_entries)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 
-	if (rate > 540000) {
+	if (crtc_state->port_clock > 540000) {
 		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
 		return icl_combo_phy_ddi_translations_edp_hbr3;
 	} else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) {
@@ -1202,23 +1216,25 @@ tgl_get_combo_buf_trans_edp(struct intel_encoder *encoder, int type, int rate,
 		return icl_combo_phy_ddi_translations_edp_hbr2;
 	}
 
-	return tgl_get_combo_buf_trans_dp(encoder, type, rate, n_entries);
+	return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
 }
 
 static const struct cnl_ddi_buf_trans *
-tgl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
+tgl_get_combo_buf_trans(struct intel_encoder *encoder,
+			const struct intel_crtc_state *crtc_state,
 			int *n_entries)
 {
-	if (type == INTEL_OUTPUT_HDMI)
-		return tgl_get_combo_buf_trans_hdmi(encoder, type, rate, n_entries);
-	else if (type == INTEL_OUTPUT_EDP)
-		return tgl_get_combo_buf_trans_edp(encoder, type, rate, n_entries);
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+		return tgl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries);
+	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
+		return tgl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
 	else
-		return tgl_get_combo_buf_trans_dp(encoder, type, rate, n_entries);
+		return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
 }
 
 static const struct tgl_dkl_phy_ddi_buf_trans *
-tgl_get_dkl_buf_trans_hdmi(struct intel_encoder *encoder, int type, int rate,
+tgl_get_dkl_buf_trans_hdmi(struct intel_encoder *encoder,
+			   const struct intel_crtc_state *crtc_state,
 			   int *n_entries)
 {
 	*n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans);
@@ -1226,10 +1242,11 @@ tgl_get_dkl_buf_trans_hdmi(struct intel_encoder *encoder, int type, int rate,
 }
 
 static const struct tgl_dkl_phy_ddi_buf_trans *
-tgl_get_dkl_buf_trans_dp(struct intel_encoder *encoder, int type, int rate,
+tgl_get_dkl_buf_trans_dp(struct intel_encoder *encoder,
+			 const struct intel_crtc_state *crtc_state,
 			 int *n_entries)
 {
-	if (rate > 270000) {
+	if (crtc_state->port_clock > 270000) {
 		*n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans_hbr2);
 		return tgl_dkl_phy_dp_ddi_trans_hbr2;
 	} else {
@@ -1239,16 +1256,18 @@ tgl_get_dkl_buf_trans_dp(struct intel_encoder *encoder, int type, int rate,
 }
 
 static const struct tgl_dkl_phy_ddi_buf_trans *
-tgl_get_dkl_buf_trans(struct intel_encoder *encoder, int type, int rate,
+tgl_get_dkl_buf_trans(struct intel_encoder *encoder,
+		      const struct intel_crtc_state *crtc_state,
 		      int *n_entries)
 {
-	if (type == INTEL_OUTPUT_HDMI)
-		return tgl_get_dkl_buf_trans_hdmi(encoder, type, rate, n_entries);
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+		return tgl_get_dkl_buf_trans_hdmi(encoder, crtc_state, n_entries);
 	else
-		return tgl_get_dkl_buf_trans_dp(encoder, type, rate, n_entries);
+		return tgl_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries);
 }
 
-static int intel_ddi_hdmi_level(struct intel_encoder *encoder)
+static int intel_ddi_hdmi_level(struct intel_encoder *encoder,
+				const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	int n_entries, level, default_entry;
@@ -1256,19 +1275,15 @@ static int intel_ddi_hdmi_level(struct intel_encoder *encoder)
 
 	if (INTEL_GEN(dev_priv) >= 12) {
 		if (intel_phy_is_combo(dev_priv, phy))
-			tgl_get_combo_buf_trans(encoder, INTEL_OUTPUT_HDMI,
-						0, &n_entries);
+			tgl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries);
 		else
-			tgl_get_dkl_buf_trans(encoder, INTEL_OUTPUT_HDMI, 0,
-					      &n_entries);
+			tgl_get_dkl_buf_trans_hdmi(encoder, crtc_state, &n_entries);
 		default_entry = n_entries - 1;
 	} else if (INTEL_GEN(dev_priv) == 11) {
 		if (intel_phy_is_combo(dev_priv, phy))
-			icl_get_combo_buf_trans(encoder, INTEL_OUTPUT_HDMI,
-						0, &n_entries);
+			icl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries);
 		else
-			icl_get_mg_buf_trans(encoder, INTEL_OUTPUT_HDMI, 0,
-					     &n_entries);
+			icl_get_mg_buf_trans_hdmi(encoder, crtc_state, &n_entries);
 		default_entry = n_entries - 1;
 	} else if (IS_CANNONLAKE(dev_priv)) {
 		cnl_get_buf_trans_hdmi(encoder, &n_entries);
@@ -1595,14 +1610,15 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
 		       DP_TP_CTL_ENABLE);
 }
 
-static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
+static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
+				      const struct intel_crtc_state *crtc_state)
 {
 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 
 	intel_dp->DP = dig_port->saved_port_bits |
 		DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
-	intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
+	intel_dp->DP |= DDI_PORT_WIDTH(crtc_state->lane_count);
 }
 
 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
@@ -2266,13 +2282,14 @@ static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
 }
 
 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
-			       int level, enum intel_output_type type)
+			       const struct intel_crtc_state *crtc_state,
+			       int level)
 {
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	u8 iboost;
 
-	if (type == INTEL_OUTPUT_HDMI)
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
 		iboost = intel_bios_hdmi_boost_level(encoder);
 	else
 		iboost = intel_bios_dp_boost_level(encoder);
@@ -2281,14 +2298,12 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder,
 		const struct ddi_buf_trans *ddi_translations;
 		int n_entries;
 
-		if (type == INTEL_OUTPUT_HDMI)
+		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
 			ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
-		else if (type == INTEL_OUTPUT_EDP)
-			ddi_translations = intel_ddi_get_buf_trans_edp(encoder,
-								       &n_entries);
+		else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
+			ddi_translations = intel_ddi_get_buf_trans_edp(encoder, &n_entries);
 		else
-			ddi_translations = intel_ddi_get_buf_trans_dp(encoder,
-								      &n_entries);
+			ddi_translations = intel_ddi_get_buf_trans_dp(encoder, &n_entries);
 
 		if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
 			return;
@@ -2311,16 +2326,17 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder,
 }
 
 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
-				    int level, enum intel_output_type type)
+				    const struct intel_crtc_state *crtc_state,
+				    int level)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	const struct bxt_ddi_buf_trans *ddi_translations;
 	enum port port = encoder->port;
 	int n_entries;
 
-	if (type == INTEL_OUTPUT_HDMI)
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
 		ddi_translations = bxt_get_buf_trans_hdmi(encoder, &n_entries);
-	else if (type == INTEL_OUTPUT_EDP)
+	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 		ddi_translations = bxt_get_buf_trans_edp(encoder, &n_entries);
 	else
 		ddi_translations = bxt_get_buf_trans_dp(encoder, &n_entries);
@@ -2337,7 +2353,8 @@ static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
 				     ddi_translations[level].deemphasis);
 }
 
-static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp)
+static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp,
+				   const struct intel_crtc_state *crtc_state)
 {
 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -2347,33 +2364,28 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp)
 
 	if (INTEL_GEN(dev_priv) >= 12) {
 		if (intel_phy_is_combo(dev_priv, phy))
-			tgl_get_combo_buf_trans(encoder, encoder->type,
-						intel_dp->link_rate, &n_entries);
+			tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
 		else
-			tgl_get_dkl_buf_trans(encoder, encoder->type,
-					      intel_dp->link_rate, &n_entries);
+			tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
 	} else if (INTEL_GEN(dev_priv) == 11) {
 		if (IS_ELKHARTLAKE(dev_priv))
-			ehl_get_combo_buf_trans(encoder, encoder->type,
-						intel_dp->link_rate, &n_entries);
+			ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
 		else if (intel_phy_is_combo(dev_priv, phy))
-			icl_get_combo_buf_trans(encoder, encoder->type,
-						intel_dp->link_rate, &n_entries);
+			icl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
 		else
-			icl_get_mg_buf_trans(encoder, encoder->type,
-					     intel_dp->link_rate, &n_entries);
+			icl_get_mg_buf_trans(encoder, crtc_state, &n_entries);
 	} else if (IS_CANNONLAKE(dev_priv)) {
-		if (encoder->type == INTEL_OUTPUT_EDP)
+		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 			cnl_get_buf_trans_edp(encoder, &n_entries);
 		else
 			cnl_get_buf_trans_dp(encoder, &n_entries);
 	} else if (IS_GEN9_LP(dev_priv)) {
-		if (encoder->type == INTEL_OUTPUT_EDP)
+		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 			bxt_get_buf_trans_edp(encoder, &n_entries);
 		else
 			bxt_get_buf_trans_dp(encoder, &n_entries);
 	} else {
-		if (encoder->type == INTEL_OUTPUT_EDP)
+		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 			intel_ddi_get_buf_trans_edp(encoder, &n_entries);
 		else
 			intel_ddi_get_buf_trans_dp(encoder, &n_entries);
@@ -2400,7 +2412,8 @@ static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp)
 }
 
 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
-				   int level, enum intel_output_type type)
+				   const struct intel_crtc_state *crtc_state,
+				   int level)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	const struct cnl_ddi_buf_trans *ddi_translations;
@@ -2408,9 +2421,9 @@ static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
 	int n_entries, ln;
 	u32 val;
 
-	if (type == INTEL_OUTPUT_HDMI)
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
 		ddi_translations = cnl_get_buf_trans_hdmi(encoder, &n_entries);
-	else if (type == INTEL_OUTPUT_EDP)
+	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 		ddi_translations = cnl_get_buf_trans_edp(encoder, &n_entries);
 	else
 		ddi_translations = cnl_get_buf_trans_dp(encoder, &n_entries);
@@ -2464,22 +2477,16 @@ static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
 }
 
 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
-				    int level, enum intel_output_type type)
+				    const struct intel_crtc_state *crtc_state,
+				    int level)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum port port = encoder->port;
 	int width, rate, ln;
 	u32 val;
 
-	if (type == INTEL_OUTPUT_HDMI) {
-		width = 4;
-		rate = 0; /* Rate is always < than 6GHz for HDMI */
-	} else {
-		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-
-		width = intel_dp->lane_count;
-		rate = intel_dp->link_rate;
-	}
+	width = crtc_state->lane_count;
+	rate = crtc_state->port_clock;
 
 	/*
 	 * 1. If port type is eDP or DP,
@@ -2487,10 +2494,10 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
 	 * else clear to 0b.
 	 */
 	val = intel_de_read(dev_priv, CNL_PORT_PCS_DW1_LN0(port));
-	if (type != INTEL_OUTPUT_HDMI)
-		val |= COMMON_KEEPER_EN;
-	else
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
 		val &= ~COMMON_KEEPER_EN;
+	else
+		val |= COMMON_KEEPER_EN;
 	intel_de_write(dev_priv, CNL_PORT_PCS_DW1_GRP(port), val);
 
 	/* 2. Program loadgen select */
@@ -2522,7 +2529,7 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
 	intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
 
 	/* 5. Program swing and de-emphasis */
-	cnl_ddi_vswing_program(encoder, level, type);
+	cnl_ddi_vswing_program(encoder, crtc_state, level);
 
 	/* 6. Set training enable to trigger update */
 	val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
@@ -2531,23 +2538,21 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
 }
 
 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
-					 u32 level, int type, int rate)
+					 const struct intel_crtc_state *crtc_state,
+					 int level)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	const struct cnl_ddi_buf_trans *ddi_translations;
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
-	const struct cnl_ddi_buf_trans *ddi_translations = NULL;
-	u32 n_entries, val;
-	int ln;
+	int n_entries, ln;
+	u32 val;
 
 	if (INTEL_GEN(dev_priv) >= 12)
-		ddi_translations = tgl_get_combo_buf_trans(encoder, type, rate,
-							   &n_entries);
+		ddi_translations = tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
 	else if (IS_ELKHARTLAKE(dev_priv))
-		ddi_translations = ehl_get_combo_buf_trans(encoder, type, rate,
-							   &n_entries);
+		ddi_translations = ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
 	else
-		ddi_translations = icl_get_combo_buf_trans(encoder, type, rate,
-							   &n_entries);
+		ddi_translations = icl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
 	if (!ddi_translations)
 		return;
 
@@ -2558,7 +2563,7 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
 		level = n_entries - 1;
 	}
 
-	if (type == INTEL_OUTPUT_EDP) {
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
 		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 
 		val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED;
@@ -2606,25 +2611,16 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
 }
 
 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
-					      u32 level,
-					      enum intel_output_type type)
+					      const struct intel_crtc_state *crtc_state,
+					      int level)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
-	int width = 0;
-	int rate = 0;
+	int width, rate, ln;
 	u32 val;
-	int ln = 0;
 
-	if (type == INTEL_OUTPUT_HDMI) {
-		width = 4;
-		/* Rate is always < than 6GHz for HDMI */
-	} else {
-		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-
-		width = intel_dp->lane_count;
-		rate = intel_dp->link_rate;
-	}
+	width = crtc_state->lane_count;
+	rate = crtc_state->port_clock;
 
 	/*
 	 * 1. If port type is eDP or DP,
@@ -2632,7 +2628,7 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
 	 * else clear to 0b.
 	 */
 	val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy));
-	if (type == INTEL_OUTPUT_HDMI)
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
 		val &= ~COMMON_KEEPER_EN;
 	else
 		val |= COMMON_KEEPER_EN;
@@ -2667,7 +2663,7 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
 	intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
 
 	/* 5. Program swing and de-emphasis */
-	icl_ddi_combo_vswing_program(encoder, level, type, rate);
+	icl_ddi_combo_vswing_program(encoder, crtc_state, level);
 
 	/* 6. Set training enable to trigger update */
 	val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
@@ -2676,23 +2672,16 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
 }
 
 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
-					   int link_clock, u32 level,
-					   enum intel_output_type type)
+					   const struct intel_crtc_state *crtc_state,
+					   int level)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
 	const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
-	u32 n_entries, val;
-	int ln, rate = 0;
+	int n_entries, ln;
+	u32 val;
 
-	if (type != INTEL_OUTPUT_HDMI) {
-		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-
-		rate = intel_dp->link_rate;
-	}
-
-	ddi_translations = icl_get_mg_buf_trans(encoder, type, rate,
-						&n_entries);
+	ddi_translations = icl_get_mg_buf_trans(encoder, crtc_state, &n_entries);
 	/* The table does not have values for level 3 and level 9. */
 	if (level >= n_entries || level == 3 || level == 9) {
 		drm_dbg_kms(&dev_priv->drm,
@@ -2759,7 +2748,7 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
 	 */
 	for (ln = 0; ln < 2; ln++) {
 		val = intel_de_read(dev_priv, MG_CLKHUB(ln, tc_port));
-		if (link_clock < 300000)
+		if (crtc_state->port_clock < 300000)
 			val |= CFG_LOW_RATE_LKREN_EN;
 		else
 			val &= ~CFG_LOW_RATE_LKREN_EN;
@@ -2770,7 +2759,7 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
 	for (ln = 0; ln < 2; ln++) {
 		val = intel_de_read(dev_priv, MG_TX1_DCC(ln, tc_port));
 		val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
-		if (link_clock <= 500000) {
+		if (crtc_state->port_clock <= 500000) {
 			val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
 		} else {
 			val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
@@ -2780,7 +2769,7 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
 
 		val = intel_de_read(dev_priv, MG_TX2_DCC(ln, tc_port));
 		val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
-		if (link_clock <= 500000) {
+		if (crtc_state->port_clock <= 500000) {
 			val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
 		} else {
 			val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
@@ -2806,38 +2795,30 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
 }
 
 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
-				    int link_clock,
-				    u32 level,
-				    enum intel_output_type type)
+				    const struct intel_crtc_state *crtc_state,
+				    int level)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 
 	if (intel_phy_is_combo(dev_priv, phy))
-		icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
+		icl_combo_phy_ddi_vswing_sequence(encoder, crtc_state, level);
 	else
-		icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level,
-					       type);
+		icl_mg_phy_ddi_vswing_sequence(encoder, crtc_state, level);
 }
 
 static void
-tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock,
-				u32 level, enum intel_output_type type)
+tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
+				const struct intel_crtc_state *crtc_state,
+				int level)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
 	const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations;
-	u32 n_entries, val, ln, dpcnt_mask, dpcnt_val;
-	int rate = 0;
+	u32 val, dpcnt_mask, dpcnt_val;
+	int n_entries, ln;
 
-	if (type == INTEL_OUTPUT_HDMI) {
-		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-
-		rate = intel_dp->link_rate;
-	}
-
-	ddi_translations = tgl_get_dkl_buf_trans(encoder, encoder->type, rate,
-						 &n_entries);
+	ddi_translations = tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
 
 	if (level >= n_entries)
 		level = n_entries - 1;
@@ -2873,20 +2854,20 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock,
 }
 
 static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder,
-				    int link_clock,
-				    u32 level,
-				    enum intel_output_type type)
+				    const struct intel_crtc_state *crtc_state,
+				    int level)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 
 	if (intel_phy_is_combo(dev_priv, phy))
-		icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
+		icl_combo_phy_ddi_vswing_sequence(encoder, crtc_state, level);
 	else
-		tgl_dkl_phy_ddi_vswing_sequence(encoder, link_clock, level, type);
+		tgl_dkl_phy_ddi_vswing_sequence(encoder, crtc_state, level);
 }
 
-static u32 translate_signal_level(struct intel_dp *intel_dp, int signal_levels)
+static int translate_signal_level(struct intel_dp *intel_dp,
+				  u8 signal_levels)
 {
 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 	int i;
@@ -2903,55 +2884,58 @@ static u32 translate_signal_level(struct intel_dp *intel_dp, int signal_levels)
 	return 0;
 }
 
-static u32 intel_ddi_dp_level(struct intel_dp *intel_dp)
+static int intel_ddi_dp_level(struct intel_dp *intel_dp)
 {
 	u8 train_set = intel_dp->train_set[0];
-	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
-					 DP_TRAIN_PRE_EMPHASIS_MASK);
+	u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
+					DP_TRAIN_PRE_EMPHASIS_MASK);
 
 	return translate_signal_level(intel_dp, signal_levels);
 }
 
 static void
-tgl_set_signal_levels(struct intel_dp *intel_dp)
+tgl_set_signal_levels(struct intel_dp *intel_dp,
+		      const struct intel_crtc_state *crtc_state)
 {
 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 	int level = intel_ddi_dp_level(intel_dp);
 
-	tgl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
-				level, encoder->type);
+	tgl_ddi_vswing_sequence(encoder, crtc_state, level);
 }
 
 static void
-icl_set_signal_levels(struct intel_dp *intel_dp)
+icl_set_signal_levels(struct intel_dp *intel_dp,
+		      const struct intel_crtc_state *crtc_state)
 {
 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 	int level = intel_ddi_dp_level(intel_dp);
 
-	icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
-				level, encoder->type);
+	icl_ddi_vswing_sequence(encoder, crtc_state, level);
 }
 
 static void
-cnl_set_signal_levels(struct intel_dp *intel_dp)
+cnl_set_signal_levels(struct intel_dp *intel_dp,
+		      const struct intel_crtc_state *crtc_state)
 {
 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 	int level = intel_ddi_dp_level(intel_dp);
 
-	cnl_ddi_vswing_sequence(encoder, level, encoder->type);
+	cnl_ddi_vswing_sequence(encoder, crtc_state, level);
 }
 
 static void
-bxt_set_signal_levels(struct intel_dp *intel_dp)
+bxt_set_signal_levels(struct intel_dp *intel_dp,
+		      const struct intel_crtc_state *crtc_state)
 {
 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 	int level = intel_ddi_dp_level(intel_dp);
 
-	bxt_ddi_vswing_sequence(encoder, level, encoder->type);
+	bxt_ddi_vswing_sequence(encoder, crtc_state, level);
 }
 
 static void
-hsw_set_signal_levels(struct intel_dp *intel_dp)
+hsw_set_signal_levels(struct intel_dp *intel_dp,
+		      const struct intel_crtc_state *crtc_state)
 {
 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -2968,7 +2952,7 @@ hsw_set_signal_levels(struct intel_dp *intel_dp)
 	intel_dp->DP |= signal_levels;
 
 	if (IS_GEN9_BC(dev_priv))
-		skl_ddi_set_iboost(encoder, level, encoder->type);
+		skl_ddi_set_iboost(encoder, crtc_state, level);
 
 	intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
 	intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
@@ -3375,8 +3359,9 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
 	int level = intel_ddi_dp_level(intel_dp);
 	enum transcoder transcoder = crtc_state->cpu_transcoder;
 
-	intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
-				 crtc_state->lane_count, is_mst);
+	intel_dp_set_link_params(intel_dp,
+				 crtc_state->port_clock,
+				 crtc_state->lane_count);
 
 	intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder);
 	intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder);
@@ -3448,8 +3433,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
 	 */
 
 	/* 7.e Configure voltage swing and related IO settings */
-	tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level,
-				encoder->type);
+	tgl_ddi_vswing_sequence(encoder, crtc_state, level);
 
 	/*
 	 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up
@@ -3472,7 +3456,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
 	 * We only configure what the register value will be here.  Actual
 	 * enabling happens during link training farther down.
 	 */
-	intel_ddi_init_dp_buf_reg(encoder);
+	intel_ddi_init_dp_buf_reg(encoder, crtc_state);
 
 	if (!is_mst)
 		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
@@ -3492,11 +3476,11 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
 	 *     Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
 	 *     (timeout after 800 us)
 	 */
-	intel_dp_start_link_train(intel_dp);
+	intel_dp_start_link_train(intel_dp, crtc_state);
 
 	/* 7.k Set DP_TP_CTL link training to Normal */
 	if (!is_trans_port_sync_mode(crtc_state))
-		intel_dp_stop_link_train(intel_dp);
+		intel_dp_stop_link_train(intel_dp, crtc_state);
 
 	/* 7.l Configure and enable FEC if needed */
 	intel_ddi_enable_fec(encoder, crtc_state);
@@ -3522,8 +3506,9 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
 	else
 		drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A);
 
-	intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
-				 crtc_state->lane_count, is_mst);
+	intel_dp_set_link_params(intel_dp,
+				 crtc_state->port_clock,
+				 crtc_state->lane_count);
 
 	intel_edp_panel_on(intel_dp);
 
@@ -3537,12 +3522,11 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
 	icl_program_mg_dp_mode(dig_port, crtc_state);
 
 	if (INTEL_GEN(dev_priv) >= 11)
-		icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
-					level, encoder->type);
+		icl_ddi_vswing_sequence(encoder, crtc_state, level);
 	else if (IS_CANNONLAKE(dev_priv))
-		cnl_ddi_vswing_sequence(encoder, level, encoder->type);
+		cnl_ddi_vswing_sequence(encoder, crtc_state, level);
 	else if (IS_GEN9_LP(dev_priv))
-		bxt_ddi_vswing_sequence(encoder, level, encoder->type);
+		bxt_ddi_vswing_sequence(encoder, crtc_state, level);
 	else
 		intel_prepare_dp_ddi_buffers(encoder, crtc_state);
 
@@ -3555,17 +3539,17 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
 					       lane_reversal);
 	}
 
-	intel_ddi_init_dp_buf_reg(encoder);
+	intel_ddi_init_dp_buf_reg(encoder, crtc_state);
 	if (!is_mst)
 		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
 	intel_dp_configure_protocol_converter(intel_dp);
 	intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
 					      true);
 	intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
-	intel_dp_start_link_train(intel_dp);
+	intel_dp_start_link_train(intel_dp, crtc_state);
 	if ((port != PORT_A || INTEL_GEN(dev_priv) >= 9) &&
 	    !is_trans_port_sync_mode(crtc_state))
-		intel_dp_stop_link_train(intel_dp);
+		intel_dp_stop_link_train(intel_dp, crtc_state);
 
 	intel_ddi_enable_fec(encoder, crtc_state);
 
@@ -3605,7 +3589,7 @@ static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state,
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 	struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	int level = intel_ddi_hdmi_level(encoder);
+	int level = intel_ddi_hdmi_level(encoder, crtc_state);
 
 	intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
 	intel_ddi_clk_select(encoder, crtc_state);
@@ -3615,20 +3599,18 @@ static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state,
 	icl_program_mg_dp_mode(dig_port, crtc_state);
 
 	if (INTEL_GEN(dev_priv) >= 12)
-		tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
-					level, INTEL_OUTPUT_HDMI);
+		tgl_ddi_vswing_sequence(encoder, crtc_state, level);
 	else if (INTEL_GEN(dev_priv) == 11)
-		icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
-					level, INTEL_OUTPUT_HDMI);
+		icl_ddi_vswing_sequence(encoder, crtc_state, level);
 	else if (IS_CANNONLAKE(dev_priv))
-		cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
+		cnl_ddi_vswing_sequence(encoder, crtc_state, level);
 	else if (IS_GEN9_LP(dev_priv))
-		bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
+		bxt_ddi_vswing_sequence(encoder, crtc_state, level);
 	else
 		intel_prepare_hdmi_ddi_buffers(encoder, level);
 
 	if (IS_GEN9_BC(dev_priv))
-		skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
+		skl_ddi_set_iboost(encoder, crtc_state, level);
 
 	intel_ddi_enable_pipe_clock(encoder, crtc_state);
 
@@ -3918,12 +3900,14 @@ static void trans_port_sync_stop_link_train(struct intel_atomic_state *state,
 		    crtc_state->cpu_transcoder)
 			continue;
 
-		intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder));
+		intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder),
+					 slave_crtc_state);
 	}
 
 	usleep_range(200, 400);
 
-	intel_dp_stop_link_train(enc_to_intel_dp(encoder));
+	intel_dp_stop_link_train(enc_to_intel_dp(encoder),
+				 crtc_state);
 }
 
 static void intel_enable_ddi_dp(struct intel_atomic_state *state,
@@ -3936,7 +3920,7 @@ static void intel_enable_ddi_dp(struct intel_atomic_state *state,
 	enum port port = encoder->port;
 
 	if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
-		intel_dp_stop_link_train(intel_dp);
+		intel_dp_stop_link_train(intel_dp, crtc_state);
 
 	intel_edp_backlight_on(crtc_state, conn_state);
 	intel_psr_enable(intel_dp, crtc_state, conn_state);
@@ -4197,7 +4181,8 @@ intel_ddi_pre_pll_enable(struct intel_atomic_state *state,
 						crtc_state->lane_lat_optim_mask);
 }
 
-static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
+static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
+					   const struct intel_crtc_state *crtc_state)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
@@ -4225,9 +4210,9 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
 	}
 
 	dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1;
-	if (intel_dp->link_mst)
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
 		dp_tp_ctl |= DP_TP_CTL_MODE_MST;
-	else {
+	} else {
 		dp_tp_ctl |= DP_TP_CTL_MODE_SST;
 		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
 			dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
@@ -4243,6 +4228,7 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
 }
 
 static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
+				     const struct intel_crtc_state *crtc_state,
 				     u8 dp_train_pat)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -4273,7 +4259,8 @@ static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
 	intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, temp);
 }
 
-static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp)
+static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp,
+					  const struct intel_crtc_state *crtc_state)
 {
 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h
index f5fb62fc9400..9a2ac73164f8 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi.h
@@ -41,8 +41,10 @@ void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
 				    bool state);
 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
 					 struct intel_crtc_state *crtc_state);
-u32 bxt_signal_levels(struct intel_dp *intel_dp);
-u32 ddi_signal_levels(struct intel_dp *intel_dp);
+u32 bxt_signal_levels(struct intel_dp *intel_dp,
+		      const struct intel_crtc_state *crtc_state);
+u32 ddi_signal_levels(struct intel_dp *intel_dp,
+		      const struct intel_crtc_state *crtc_state);
 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
 				     enum transcoder cpu_transcoder,
 				     bool enable);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index e3339e41ddf7..66d197153c93 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1273,7 +1273,6 @@ struct intel_dp {
 	int link_rate;
 	u8 lane_count;
 	u8 sink_count;
-	bool link_mst;
 	bool link_trained;
 	bool has_hdmi_sink;
 	bool has_audio;
@@ -1366,13 +1365,19 @@ struct intel_dp {
 	i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
 
 	/* This is called before a link training is starterd */
-	void (*prepare_link_retrain)(struct intel_dp *intel_dp);
-	void (*set_link_train)(struct intel_dp *intel_dp, u8 dp_train_pat);
-	void (*set_idle_link_train)(struct intel_dp *intel_dp);
-	void (*set_signal_levels)(struct intel_dp *intel_dp);
+	void (*prepare_link_retrain)(struct intel_dp *intel_dp,
+				     const struct intel_crtc_state *crtc_state);
+	void (*set_link_train)(struct intel_dp *intel_dp,
+			       const struct intel_crtc_state *crtc_state,
+			       u8 dp_train_pat);
+	void (*set_idle_link_train)(struct intel_dp *intel_dp,
+				    const struct intel_crtc_state *crtc_state);
+	void (*set_signal_levels)(struct intel_dp *intel_dp,
+				  const struct intel_crtc_state *crtc_state);
 
 	u8 (*preemph_max)(struct intel_dp *intel_dp);
-	u8 (*voltage_max)(struct intel_dp *intel_dp);
+	u8 (*voltage_max)(struct intel_dp *intel_dp,
+			  const struct intel_crtc_state *crtc_state);
 
 	/* Displayport compliance testing */
 	struct intel_dp_compliance compliance;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 132b06a649d8..3715cf8c0a6a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2799,13 +2799,11 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 }
 
 void intel_dp_set_link_params(struct intel_dp *intel_dp,
-			      int link_rate, u8 lane_count,
-			      bool link_mst)
+			      int link_rate, int lane_count)
 {
 	intel_dp->link_trained = false;
 	intel_dp->link_rate = link_rate;
 	intel_dp->lane_count = lane_count;
-	intel_dp->link_mst = link_mst;
 }
 
 static void intel_dp_prepare(struct intel_encoder *encoder,
@@ -2817,10 +2815,9 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
 
-	intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
-				 pipe_config->lane_count,
-				 intel_crtc_has_type(pipe_config,
-						     INTEL_OUTPUT_DP_MST));
+	intel_dp_set_link_params(intel_dp,
+				 pipe_config->port_clock,
+				 pipe_config->lane_count);
 
 	/*
 	 * There are four kinds of DP registers:
@@ -3791,6 +3788,7 @@ static void chv_post_disable_dp(struct intel_atomic_state *state,
 
 static void
 cpt_set_link_train(struct intel_dp *intel_dp,
+		   const struct intel_crtc_state *crtc_state,
 		   u8 dp_train_pat)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -3821,6 +3819,7 @@ cpt_set_link_train(struct intel_dp *intel_dp,
 
 static void
 g4x_set_link_train(struct intel_dp *intel_dp,
+		   const struct intel_crtc_state *crtc_state,
 		   u8 dp_train_pat)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -3856,7 +3855,8 @@ static void intel_dp_enable_port(struct intel_dp *intel_dp,
 
 	/* enable with pattern 1 (as per spec) */
 
-	intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
+	intel_dp_program_link_training_pattern(intel_dp, crtc_state,
+					       DP_TRAINING_PATTERN_1);
 
 	/*
 	 * Magic for VLV/CHV. We _must_ first set up the register
@@ -3947,8 +3947,8 @@ static void intel_enable_dp(struct intel_atomic_state *state,
 
 	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
 	intel_dp_configure_protocol_converter(intel_dp);
-	intel_dp_start_link_train(intel_dp);
-	intel_dp_stop_link_train(intel_dp);
+	intel_dp_start_link_train(intel_dp, pipe_config);
+	intel_dp_stop_link_train(intel_dp, pipe_config);
 
 	if (pipe_config->has_audio) {
 		drm_dbg(&dev_priv->drm, "Enabling DP audio on pipe %c\n",
@@ -4157,12 +4157,14 @@ intel_dp_get_link_status(struct intel_dp *intel_dp, u8 link_status[DP_LINK_STATU
 				DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
 }
 
-static u8 intel_dp_voltage_max_2(struct intel_dp *intel_dp)
+static u8 intel_dp_voltage_max_2(struct intel_dp *intel_dp,
+				 const struct intel_crtc_state *crtc_state)
 {
 	return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
 }
 
-static u8 intel_dp_voltage_max_3(struct intel_dp *intel_dp)
+static u8 intel_dp_voltage_max_3(struct intel_dp *intel_dp,
+				 const struct intel_crtc_state *crtc_state)
 {
 	return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
 }
@@ -4177,7 +4179,8 @@ static u8 intel_dp_preemph_max_3(struct intel_dp *intel_dp)
 	return DP_TRAIN_PRE_EMPH_LEVEL_3;
 }
 
-static void vlv_set_signal_levels(struct intel_dp *intel_dp)
+static void vlv_set_signal_levels(struct intel_dp *intel_dp,
+				  const struct intel_crtc_state *crtc_state)
 {
 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 	unsigned long demph_reg_value, preemph_reg_value,
@@ -4257,11 +4260,13 @@ static void vlv_set_signal_levels(struct intel_dp *intel_dp)
 		return;
 	}
 
-	vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
+	vlv_set_phy_signal_level(encoder, crtc_state,
+				 demph_reg_value, preemph_reg_value,
 				 uniqtranscale_reg_value, 0);
 }
 
-static void chv_set_signal_levels(struct intel_dp *intel_dp)
+static void chv_set_signal_levels(struct intel_dp *intel_dp,
+				  const struct intel_crtc_state *crtc_state)
 {
 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 	u32 deemph_reg_value, margin_reg_value;
@@ -4338,8 +4343,9 @@ static void chv_set_signal_levels(struct intel_dp *intel_dp)
 		return;
 	}
 
-	chv_set_phy_signal_level(encoder, deemph_reg_value,
-				 margin_reg_value, uniq_trans_scale);
+	chv_set_phy_signal_level(encoder, crtc_state,
+				 deemph_reg_value, margin_reg_value,
+				 uniq_trans_scale);
 }
 
 static u32 g4x_signal_levels(u8 train_set)
@@ -4380,7 +4386,8 @@ static u32 g4x_signal_levels(u8 train_set)
 }
 
 static void
-g4x_set_signal_levels(struct intel_dp *intel_dp)
+g4x_set_signal_levels(struct intel_dp *intel_dp,
+		      const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	u8 train_set = intel_dp->train_set[0];
@@ -4427,7 +4434,8 @@ static u32 snb_cpu_edp_signal_levels(u8 train_set)
 }
 
 static void
-snb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp)
+snb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp,
+			      const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	u8 train_set = intel_dp->train_set[0];
@@ -4478,7 +4486,8 @@ static u32 ivb_cpu_edp_signal_levels(u8 train_set)
 }
 
 static void
-ivb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp)
+ivb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp,
+			      const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	u8 train_set = intel_dp->train_set[0];
@@ -4496,7 +4505,8 @@ ivb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp)
 	intel_de_posting_read(dev_priv, intel_dp->output_reg);
 }
 
-void intel_dp_set_signal_levels(struct intel_dp *intel_dp)
+void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
+				const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	u8 train_set = intel_dp->train_set[0];
@@ -4510,11 +4520,12 @@ void intel_dp_set_signal_levels(struct intel_dp *intel_dp)
 		    train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ?
 		    " (max)" : "");
 
-	intel_dp->set_signal_levels(intel_dp);
+	intel_dp->set_signal_levels(intel_dp, crtc_state);
 }
 
 void
 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
+				       const struct intel_crtc_state *crtc_state,
 				       u8 dp_train_pat)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -4525,13 +4536,14 @@ intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
 			    "Using DP training pattern TPS%d\n",
 			    dp_train_pat & train_pat_mask);
 
-	intel_dp->set_link_train(intel_dp, dp_train_pat);
+	intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat);
 }
 
-void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
+void intel_dp_set_idle_link_train(struct intel_dp *intel_dp,
+				  const struct intel_crtc_state *crtc_state)
 {
 	if (intel_dp->set_idle_link_train)
-		intel_dp->set_idle_link_train(intel_dp);
+		intel_dp->set_idle_link_train(intel_dp, crtc_state);
 }
 
 static void
@@ -5424,14 +5436,14 @@ static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
 	return test_result;
 }
 
-static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
+static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,
+					const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv =
 			to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
-	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_dp_phy_test_params *data =
 			&intel_dp->compliance.test_data.phytest;
-	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum pipe pipe = crtc->pipe;
 	u32 pattern_val;
 
@@ -5491,7 +5503,8 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
 }
 
 static void
-intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp)
+intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp,
+				  const struct intel_crtc_state *crtc_state)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_device *dev = dig_port->base.base.dev;
@@ -5517,7 +5530,8 @@ intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp)
 }
 
 static void
-intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, uint8_t lane_cnt)
+intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp,
+				 const struct intel_crtc_state *crtc_state)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_device *dev = dig_port->base.base.dev;
@@ -5543,7 +5557,8 @@ intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, uint8_t lane_cnt)
 		       trans_ddi_func_ctl_value);
 }
 
-static void intel_dp_process_phy_request(struct intel_dp *intel_dp)
+static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
+					 const struct intel_crtc_state *crtc_state)
 {
 	struct drm_dp_phy_test_params *data =
 		&intel_dp->compliance.test_data.phytest;
@@ -5555,15 +5570,15 @@ static void intel_dp_process_phy_request(struct intel_dp *intel_dp)
 	}
 
 	/* retrieve vswing & pre-emphasis setting */
-	intel_dp_get_adjust_train(intel_dp, link_status);
+	intel_dp_get_adjust_train(intel_dp, crtc_state, link_status);
 
-	intel_dp_autotest_phy_ddi_disable(intel_dp);
+	intel_dp_autotest_phy_ddi_disable(intel_dp, crtc_state);
 
-	intel_dp_set_signal_levels(intel_dp);
+	intel_dp_set_signal_levels(intel_dp, crtc_state);
 
-	intel_dp_phy_pattern_update(intel_dp);
+	intel_dp_phy_pattern_update(intel_dp, crtc_state);
 
-	intel_dp_autotest_phy_ddi_enable(intel_dp, data->num_lanes);
+	intel_dp_autotest_phy_ddi_enable(intel_dp, crtc_state);
 
 	drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
 				    link_status[DP_DPCD_REV]);
@@ -5719,6 +5734,10 @@ intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
 	/*
 	 * Validate the cached values of intel_dp->link_rate and
 	 * intel_dp->lane_count before attempting to retrain.
+	 *
+	 * FIXME would be nice to user the crtc state here, but since
+	 * we need to call this from the short HPD handler that seems
+	 * a bit hard.
 	 */
 	if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
 					intel_dp->lane_count))
@@ -5852,8 +5871,20 @@ int intel_dp_retrain_link(struct intel_encoder *encoder,
 							      intel_crtc_pch_transcoder(crtc), false);
 	}
 
-	intel_dp_start_link_train(intel_dp);
-	intel_dp_stop_link_train(intel_dp);
+	for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
+		const struct intel_crtc_state *crtc_state =
+			to_intel_crtc_state(crtc->base.state);
+
+		/* retrain on the MST master transcoder */
+		if (INTEL_GEN(dev_priv) >= 12 &&
+		    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
+		    !intel_dp_mst_is_master_trans(crtc_state))
+			continue;
+
+		intel_dp_start_link_train(intel_dp, crtc_state);
+		intel_dp_stop_link_train(intel_dp, crtc_state);
+		break;
+	}
 
 	for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
 		const struct intel_crtc_state *crtc_state =
@@ -5923,6 +5954,7 @@ static int intel_dp_do_phy_test(struct intel_encoder *encoder,
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+	struct intel_crtc *crtc;
 	u32 crtc_mask;
 	int ret;
 
@@ -5940,7 +5972,20 @@ static int intel_dp_do_phy_test(struct intel_encoder *encoder,
 
 	drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n",
 		    encoder->base.base.id, encoder->base.name);
-	intel_dp_process_phy_request(intel_dp);
+
+	for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
+		const struct intel_crtc_state *crtc_state =
+			to_intel_crtc_state(crtc->base.state);
+
+		/* test on the MST master transcoder */
+		if (INTEL_GEN(dev_priv) >= 12 &&
+		    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
+		    !intel_dp_mst_is_master_trans(crtc_state))
+			continue;
+
+		intel_dp_process_phy_request(intel_dp, crtc_state);
+		break;
+	}
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 60f44f41fd08..66854aab9887 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -45,8 +45,7 @@ bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
 bool intel_dp_init_connector(struct intel_digital_port *dig_port,
 			     struct intel_connector *intel_connector);
 void intel_dp_set_link_params(struct intel_dp *intel_dp,
-			      int link_rate, u8 lane_count,
-			      bool link_mst);
+			      int link_rate, int lane_count);
 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 					    int link_rate, u8 lane_count);
 int intel_dp_retrain_link(struct intel_encoder *encoder,
@@ -93,10 +92,13 @@ void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
 
 void
 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
+				       const struct intel_crtc_state *crtc_state,
 				       u8 dp_train_pat);
 void
-intel_dp_set_signal_levels(struct intel_dp *intel_dp);
-void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
+intel_dp_set_signal_levels(struct intel_dp *intel_dp,
+			   const struct intel_crtc_state *crtc_state);
+void intel_dp_set_idle_link_train(struct intel_dp *intel_dp,
+				  const struct intel_crtc_state *crtc_state);
 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
 			   u8 *link_bw, u8 *rate_select);
 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index f2c8b56be9ea..51e8d46d9b7f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -49,8 +49,10 @@ static u8 dp_voltage_max(u8 preemph)
 	}
 }
 
-void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
-			       const u8 link_status[DP_LINK_STATUS_SIZE])
+void
+intel_dp_get_adjust_train(struct intel_dp *intel_dp,
+			  const struct intel_crtc_state *crtc_state,
+			  const u8 link_status[DP_LINK_STATUS_SIZE])
 {
 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 	u8 v = 0;
@@ -59,7 +61,7 @@ void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
 	u8 voltage_max;
 	u8 preemph_max;
 
-	for (lane = 0; lane < intel_dp->lane_count; lane++) {
+	for (lane = 0; lane < crtc_state->lane_count; lane++) {
 		v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane));
 		p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane));
 	}
@@ -74,7 +76,7 @@ void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
 
 	v = min(v, dp_voltage_max(p));
 
-	voltage_max = intel_dp->voltage_max(intel_dp);
+	voltage_max = intel_dp->voltage_max(intel_dp, crtc_state);
 	drm_WARN_ON_ONCE(&i915->drm,
 			 voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_2 &&
 			 voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_3);
@@ -88,12 +90,14 @@ void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
 
 static bool
 intel_dp_set_link_train(struct intel_dp *intel_dp,
+			const struct intel_crtc_state *crtc_state,
 			u8 dp_train_pat)
 {
 	u8 buf[sizeof(intel_dp->train_set) + 1];
 	int ret, len;
 
-	intel_dp_program_link_training_pattern(intel_dp, dp_train_pat);
+	intel_dp_program_link_training_pattern(intel_dp, crtc_state,
+					       dp_train_pat);
 
 	buf[0] = dp_train_pat;
 	if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
@@ -102,8 +106,8 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
 		len = 1;
 	} else {
 		/* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
-		memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
-		len = intel_dp->lane_count + 1;
+		memcpy(buf + 1, intel_dp->train_set, crtc_state->lane_count);
+		len = crtc_state->lane_count + 1;
 	}
 
 	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
@@ -114,31 +118,34 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
 
 static bool
 intel_dp_reset_link_train(struct intel_dp *intel_dp,
-			u8 dp_train_pat)
+			  const struct intel_crtc_state *crtc_state,
+			  u8 dp_train_pat)
 {
 	memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
-	intel_dp_set_signal_levels(intel_dp);
-	return intel_dp_set_link_train(intel_dp, dp_train_pat);
+	intel_dp_set_signal_levels(intel_dp, crtc_state);
+	return intel_dp_set_link_train(intel_dp, crtc_state, dp_train_pat);
 }
 
 static bool
-intel_dp_update_link_train(struct intel_dp *intel_dp)
+intel_dp_update_link_train(struct intel_dp *intel_dp,
+			   const struct intel_crtc_state *crtc_state)
 {
 	int ret;
 
-	intel_dp_set_signal_levels(intel_dp);
+	intel_dp_set_signal_levels(intel_dp, crtc_state);
 
 	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
-				intel_dp->train_set, intel_dp->lane_count);
+				intel_dp->train_set, crtc_state->lane_count);
 
-	return ret == intel_dp->lane_count;
+	return ret == crtc_state->lane_count;
 }
 
-static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp)
+static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,
+					     const struct intel_crtc_state *crtc_state)
 {
 	int lane;
 
-	for (lane = 0; lane < intel_dp->lane_count; lane++)
+	for (lane = 0; lane < crtc_state->lane_count; lane++)
 		if ((intel_dp->train_set[lane] &
 		     DP_TRAIN_MAX_SWING_REACHED) == 0)
 			return false;
@@ -148,7 +155,8 @@ static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp)
 
 /* Enable corresponding port and start training pattern 1 */
 static bool
-intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
+intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
+				      const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 	u8 voltage;
@@ -158,9 +166,9 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
 	u8 link_bw, rate_select;
 
 	if (intel_dp->prepare_link_retrain)
-		intel_dp->prepare_link_retrain(intel_dp);
+		intel_dp->prepare_link_retrain(intel_dp, crtc_state);
 
-	intel_dp_compute_rate(intel_dp, intel_dp->link_rate,
+	intel_dp_compute_rate(intel_dp, crtc_state->port_clock,
 			      &link_bw, &rate_select);
 
 	if (link_bw)
@@ -172,7 +180,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
 
 	/* Write the link configuration data */
 	link_config[0] = link_bw;
-	link_config[1] = intel_dp->lane_count;
+	link_config[1] = crtc_state->lane_count;
 	if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
 		link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 	drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
@@ -189,7 +197,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
 	intel_dp->DP |= DP_PORT_EN;
 
 	/* clock recovery */
-	if (!intel_dp_reset_link_train(intel_dp,
+	if (!intel_dp_reset_link_train(intel_dp, crtc_state,
 				       DP_TRAINING_PATTERN_1 |
 				       DP_LINK_SCRAMBLING_DISABLE)) {
 		drm_err(&i915->drm, "failed to enable link training\n");
@@ -220,7 +228,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
 			return false;
 		}
 
-		if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
+		if (drm_dp_clock_recovery_ok(link_status, crtc_state->lane_count)) {
 			drm_dbg_kms(&i915->drm, "clock recovery OK\n");
 			return true;
 		}
@@ -239,8 +247,8 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
 		voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
 
 		/* Update training set as requested by target */
-		intel_dp_get_adjust_train(intel_dp, link_status);
-		if (!intel_dp_update_link_train(intel_dp)) {
+		intel_dp_get_adjust_train(intel_dp, crtc_state, link_status);
+		if (!intel_dp_update_link_train(intel_dp, crtc_state)) {
 			drm_err(&i915->drm,
 				"failed to update link training\n");
 			return false;
@@ -252,7 +260,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
 		else
 			voltage_tries = 1;
 
-		if (intel_dp_link_max_vswing_reached(intel_dp))
+		if (intel_dp_link_max_vswing_reached(intel_dp, crtc_state))
 			max_vswing_reached = true;
 
 	}
@@ -266,7 +274,8 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
  * or for 1.4 devices that support it, training Pattern 3 for HBR2
  * or 1.2 devices that support it, Training Pattern 2 otherwise.
  */
-static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
+static u32 intel_dp_training_pattern(struct intel_dp *intel_dp,
+				     const struct intel_crtc_state *crtc_state)
 {
 	bool source_tps3, sink_tps3, source_tps4, sink_tps4;
 
@@ -280,7 +289,7 @@ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
 	sink_tps4 = drm_dp_tps4_supported(intel_dp->dpcd);
 	if (source_tps4 && sink_tps4) {
 		return DP_TRAINING_PATTERN_4;
-	} else if (intel_dp->link_rate == 810000) {
+	} else if (crtc_state->port_clock == 810000) {
 		if (!source_tps4)
 			drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
 				    "8.1 Gbps link rate without source HBR3/TPS4 support\n");
@@ -297,7 +306,7 @@ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
 	sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd);
 	if (source_tps3 && sink_tps3) {
 		return  DP_TRAINING_PATTERN_3;
-	} else if (intel_dp->link_rate >= 540000) {
+	} else if (crtc_state->port_clock >= 540000) {
 		if (!source_tps3)
 			drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
 				    ">=5.4/6.48 Gbps link rate without source HBR2/TPS3 support\n");
@@ -310,7 +319,8 @@ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
 }
 
 static bool
-intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
+intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
+					    const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 	int tries;
@@ -318,13 +328,13 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
 	u8 link_status[DP_LINK_STATUS_SIZE];
 	bool channel_eq = false;
 
-	training_pattern = intel_dp_training_pattern(intel_dp);
+	training_pattern = intel_dp_training_pattern(intel_dp, crtc_state);
 	/* Scrambling is disabled for TPS2/3 and enabled for TPS4 */
 	if (training_pattern != DP_TRAINING_PATTERN_4)
 		training_pattern |= DP_LINK_SCRAMBLING_DISABLE;
 
 	/* channel equalization */
-	if (!intel_dp_set_link_train(intel_dp,
+	if (!intel_dp_set_link_train(intel_dp, crtc_state,
 				     training_pattern)) {
 		drm_err(&i915->drm, "failed to start channel equalization\n");
 		return false;
@@ -341,7 +351,7 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
 
 		/* Make sure clock is still ok */
 		if (!drm_dp_clock_recovery_ok(link_status,
-					      intel_dp->lane_count)) {
+					      crtc_state->lane_count)) {
 			intel_dp_dump_link_status(link_status);
 			drm_dbg_kms(&i915->drm,
 				    "Clock recovery check failed, cannot "
@@ -350,7 +360,7 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
 		}
 
 		if (drm_dp_channel_eq_ok(link_status,
-					 intel_dp->lane_count)) {
+					 crtc_state->lane_count)) {
 			channel_eq = true;
 			drm_dbg_kms(&i915->drm, "Channel EQ done. DP Training "
 				    "successful\n");
@@ -358,8 +368,8 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
 		}
 
 		/* Update training set as requested by target */
-		intel_dp_get_adjust_train(intel_dp, link_status);
-		if (!intel_dp_update_link_train(intel_dp)) {
+		intel_dp_get_adjust_train(intel_dp, crtc_state, link_status);
+		if (!intel_dp_update_link_train(intel_dp, crtc_state)) {
 			drm_err(&i915->drm,
 				"failed to update link training\n");
 			break;
@@ -373,35 +383,37 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
 			    "Channel equalization failed 5 times\n");
 	}
 
-	intel_dp_set_idle_link_train(intel_dp);
+	intel_dp_set_idle_link_train(intel_dp, crtc_state);
 
 	return channel_eq;
 
 }
 
-void intel_dp_stop_link_train(struct intel_dp *intel_dp)
+void intel_dp_stop_link_train(struct intel_dp *intel_dp,
+			      const struct intel_crtc_state *crtc_state)
 {
 	intel_dp->link_trained = true;
 
-	intel_dp_set_link_train(intel_dp,
+	intel_dp_set_link_train(intel_dp, crtc_state,
 				DP_TRAINING_PATTERN_DISABLE);
 }
 
 void
-intel_dp_start_link_train(struct intel_dp *intel_dp)
+intel_dp_start_link_train(struct intel_dp *intel_dp,
+			  const struct intel_crtc_state *crtc_state)
 {
 	struct intel_connector *intel_connector = intel_dp->attached_connector;
 
-	if (!intel_dp_link_training_clock_recovery(intel_dp))
+	if (!intel_dp_link_training_clock_recovery(intel_dp, crtc_state))
 		goto failure_handling;
-	if (!intel_dp_link_training_channel_equalization(intel_dp))
+	if (!intel_dp_link_training_channel_equalization(intel_dp, crtc_state))
 		goto failure_handling;
 
 	drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
 		    "[CONNECTOR:%d:%s] Link Training Passed at Link Rate = %d, Lane count = %d",
 		    intel_connector->base.base.id,
 		    intel_connector->base.name,
-		    intel_dp->link_rate, intel_dp->lane_count);
+		    crtc_state->port_clock, crtc_state->lane_count);
 	return;
 
  failure_handling:
@@ -409,15 +421,15 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
 		    "[CONNECTOR:%d:%s] Link Training failed at link rate = %d, lane count = %d",
 		    intel_connector->base.base.id,
 		    intel_connector->base.name,
-		    intel_dp->link_rate, intel_dp->lane_count);
+		    crtc_state->port_clock, crtc_state->lane_count);
 
 	if (intel_dp->hobl_active) {
 		drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
 			    "Link Training failed with HOBL active, not enabling it from now on");
 		intel_dp->hobl_failed = true;
 	} else if (intel_dp_get_link_train_fallback_values(intel_dp,
-							   intel_dp->link_rate,
-							   intel_dp->lane_count)) {
+							   crtc_state->port_clock,
+							   crtc_state->lane_count)) {
 		return;
 	}
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
index 01f1dabbb060..648a6d1f9fa2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
@@ -8,11 +8,15 @@
 
 #include <drm/drm_dp_helper.h>
 
+struct intel_crtc_state;
 struct intel_dp;
 
 void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
+			       const struct intel_crtc_state *crtc_state,
 			       const u8 link_status[DP_LINK_STATUS_SIZE]);
-void intel_dp_start_link_train(struct intel_dp *intel_dp);
-void intel_dp_stop_link_train(struct intel_dp *intel_dp);
+void intel_dp_start_link_train(struct intel_dp *intel_dp,
+			       const struct intel_crtc_state *crtc_state);
+void intel_dp_stop_link_train(struct intel_dp *intel_dp,
+			      const struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_DP_LINK_TRAINING_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index 7910522273b2..514c4a7adffc 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -644,16 +644,16 @@ bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
 	return mask;
 }
 
-
 void chv_set_phy_signal_level(struct intel_encoder *encoder,
+			      const struct intel_crtc_state *crtc_state,
 			      u32 deemph_reg_value, u32 margin_reg_value,
 			      bool uniq_trans_scale)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
-	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
-	enum pipe pipe = intel_crtc->pipe;
+	enum pipe pipe = crtc->pipe;
 	u32 val;
 	int i;
 
@@ -666,7 +666,7 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder,
 	val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
 
-	if (intel_crtc->config->lane_count > 2) {
+	if (crtc_state->lane_count > 2) {
 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
 		val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
 		val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
@@ -679,7 +679,7 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder,
 	val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
 
-	if (intel_crtc->config->lane_count > 2) {
+	if (crtc_state->lane_count > 2) {
 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
 		val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
 		val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
@@ -687,7 +687,7 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder,
 	}
 
 	/* Program swing deemph */
-	for (i = 0; i < intel_crtc->config->lane_count; i++) {
+	for (i = 0; i < crtc_state->lane_count; i++) {
 		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
 		val &= ~DPIO_SWING_DEEMPH9P5_MASK;
 		val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
@@ -695,7 +695,7 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder,
 	}
 
 	/* Program swing margin */
-	for (i = 0; i < intel_crtc->config->lane_count; i++) {
+	for (i = 0; i < crtc_state->lane_count; i++) {
 		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
 
 		val &= ~DPIO_SWING_MARGIN000_MASK;
@@ -718,7 +718,7 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder,
 	 * For now, for this unique transition scale selection, set bit
 	 * 27 for ch0 and ch1.
 	 */
-	for (i = 0; i < intel_crtc->config->lane_count; i++) {
+	for (i = 0; i < crtc_state->lane_count; i++) {
 		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
 		if (uniq_trans_scale)
 			val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
@@ -732,7 +732,7 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder,
 	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
 
-	if (intel_crtc->config->lane_count > 2) {
+	if (crtc_state->lane_count > 2) {
 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
 		val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
@@ -992,14 +992,15 @@ void chv_phy_post_pll_disable(struct intel_encoder *encoder,
 }
 
 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
+			      const struct intel_crtc_state *crtc_state,
 			      u32 demph_reg_value, u32 preemph_reg_value,
 			      u32 uniqtranscale_reg_value, u32 tx3_demph)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
-	enum pipe pipe = intel_crtc->pipe;
+	enum pipe pipe = crtc->pipe;
 
 	vlv_dpio_get(dev_priv);
 
diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.h b/drivers/gpu/drm/i915/display/intel_dpio_phy.h
index f418aab90b7e..6473440e7457 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.h
@@ -32,6 +32,7 @@ void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
 u8 bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
 
 void chv_set_phy_signal_level(struct intel_encoder *encoder,
+			      const struct intel_crtc_state *crtc_state,
 			      u32 deemph_reg_value, u32 margin_reg_value,
 			      bool uniq_trans_scale);
 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
@@ -46,6 +47,7 @@ void chv_phy_post_pll_disable(struct intel_encoder *encoder,
 			      const struct intel_crtc_state *old_crtc_state);
 
 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
+			      const struct intel_crtc_state *crtc_state,
 			      u32 demph_reg_value, u32 preemph_reg_value,
 			      u32 uniqtranscale_reg_value, u32 tx3_demph);
 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 3f2008d845c2..414a46a6b5f3 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2775,8 +2775,9 @@ static void vlv_hdmi_pre_enable(struct intel_atomic_state *state,
 	vlv_phy_pre_encoder_enable(encoder, pipe_config);
 
 	/* HDMI 1.0V-2dB */
-	vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
-				 0x2b247878);
+	vlv_set_phy_signal_level(encoder, pipe_config,
+				 0x2b245f5f, 0x00002000,
+				 0x5578b83a, 0x2b247878);
 
 	dig_port->set_infoframes(encoder,
 			      pipe_config->has_infoframe,
@@ -2853,7 +2854,7 @@ static void chv_hdmi_pre_enable(struct intel_atomic_state *state,
 
 	/* FIXME: Program the support xxx V-dB */
 	/* Use 800mV-0dB */
-	chv_set_phy_signal_level(encoder, 128, 102, false);
+	chv_set_phy_signal_level(encoder, pipe_config, 128, 102, false);
 
 	dig_port->set_infoframes(encoder,
 			      pipe_config->has_infoframe,
-- 
2.26.2

_______________________________________________
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^ permalink raw reply	[flat|nested] 37+ messages in thread

* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plumb crtc state to link training code (rev5)
  2020-09-29 23:34 [Intel-gfx] [PATCH v2 00/11] drm/i915: Plumb crtc state to link training code Ville Syrjala
                   ` (16 preceding siblings ...)
  2020-09-30 15:35 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Plumb crtc state to link training code (rev4) Patchwork
@ 2020-10-01 11:27 ` Patchwork
  2020-10-01 11:56 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
                   ` (2 subsequent siblings)
  20 siblings, 0 replies; 37+ messages in thread
From: Patchwork @ 2020-10-01 11:27 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

== Series Details ==

Series: drm/i915: Plumb crtc state to link training code (rev5)
URL   : https://patchwork.freedesktop.org/series/76993/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
d4651ba92742 drm/i915: s/pre_empemph/preemph/
d2dcd064491e drm/i915: s/old_crtc_state/crtc_state/
f40c6b9eb99a drm/i915: Make intel_dp_process_phy_request() static
582bcff90ebb drm/i915: Shove the PHY test into the hotplug work
5606e8d70bc2 drm/i915: Split ICL combo PHY buf trans per output type
a1ebc02e12c4 drm/i915: Split ICL MG PHY buf trans per output type
f41ab4bb8812 drm/i915: Split EHL combo PHY buf trans per output type
-:63: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or return
#63: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1138:
+			return icl_combo_phy_ddi_translations_edp_hbr3;
+		} else {

total: 0 errors, 1 warnings, 0 checks, 70 lines checked
cf80a68f2857 drm/i915: Split TGL combo PHY buf trans per output type
-:73: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or return
#73: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1177:
+			return tgl_uy_combo_phy_ddi_translations_dp_hbr2;
+		} else {

total: 0 errors, 1 warnings, 0 checks, 100 lines checked
2fa06f11cdf9 drm/i915: Split TGL DKL PHY buf trans per output type
680bf95e8d06 drm/i915: Plumb crtc_state to link training
17947177aa4e drm/i915: Eliminate intel_dp.regs.dp_tp_{ctl, status}


_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Plumb crtc state to link training code (rev5)
  2020-09-29 23:34 [Intel-gfx] [PATCH v2 00/11] drm/i915: Plumb crtc state to link training code Ville Syrjala
                   ` (17 preceding siblings ...)
  2020-10-01 11:27 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plumb crtc state to link training code (rev5) Patchwork
@ 2020-10-01 11:56 ` Patchwork
  2020-10-01 13:12 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
  2020-10-01 14:02 ` [Intel-gfx] [PATCH v2 00/11] drm/i915: Plumb crtc state to link training code Ville Syrjälä
  20 siblings, 0 replies; 37+ messages in thread
From: Patchwork @ 2020-10-01 11:56 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx


[-- Attachment #1.1: Type: text/plain, Size: 5765 bytes --]

== Series Details ==

Series: drm/i915: Plumb crtc state to link training code (rev5)
URL   : https://patchwork.freedesktop.org/series/76993/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9086 -> Patchwork_18606
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/index.html

Known issues
------------

  Here are the changes found in Patchwork_18606 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_flip@basic-flip-vs-wf_vblank@b-edp1:
    - fi-icl-u2:          [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) +1 similar issue
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vblank@b-edp1.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vblank@b-edp1.html

  
#### Possible fixes ####

  * igt@i915_module_load@reload:
    - fi-byt-j1900:       [DMESG-WARN][3] ([i915#1982]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/fi-byt-j1900/igt@i915_module_load@reload.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/fi-byt-j1900/igt@i915_module_load@reload.html
    - fi-icl-y:           [DMESG-WARN][5] ([i915#1982]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/fi-icl-y/igt@i915_module_load@reload.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/fi-icl-y/igt@i915_module_load@reload.html

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-kbl-7500u:       [DMESG-WARN][7] ([i915#2203]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html

  * igt@vgem_basic@unload:
    - fi-kbl-x1275:       [DMESG-WARN][9] ([i915#62] / [i915#92]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/fi-kbl-x1275/igt@vgem_basic@unload.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/fi-kbl-x1275/igt@vgem_basic@unload.html

  
#### Warnings ####

  * igt@gem_exec_suspend@basic-s0:
    - fi-kbl-x1275:       [DMESG-WARN][11] ([i915#1982] / [i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][12] ([i915#62] / [i915#92] / [i915#95])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html

  * igt@i915_pm_rpm@module-reload:
    - fi-kbl-x1275:       [SKIP][13] ([fdo#109271]) -> [DMESG-FAIL][14] ([i915#62])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html

  * igt@kms_flip@basic-flip-vs-dpms@a-dp1:
    - fi-kbl-x1275:       [DMESG-WARN][15] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][16] ([i915#62] / [i915#92]) +4 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-dpms@a-dp1.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-dpms@a-dp1.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - fi-kbl-x1275:       [DMESG-WARN][17] ([i915#62] / [i915#92]) -> [DMESG-WARN][18] ([i915#62] / [i915#92] / [i915#95]) +1 similar issue
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/fi-kbl-x1275/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/fi-kbl-x1275/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
  [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
  [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95


Participating hosts (45 -> 38)
------------------------------

  Additional (1): fi-tgl-dsi 
  Missing    (8): fi-ilk-m540 fi-hsw-4200u fi-tgl-u2 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_9086 -> Patchwork_18606

  CI-20190529: 20190529
  CI_DRM_9086: b86053f8eb427de294c64eea6b3554c78326bd10 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5796: 19ae9421a5af7b03a1c9a577c57f2cf8b16a0116 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_18606: 17947177aa4e93a32bad457c7225b1f59dbe611d @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

17947177aa4e drm/i915: Eliminate intel_dp.regs.dp_tp_{ctl, status}
680bf95e8d06 drm/i915: Plumb crtc_state to link training
2fa06f11cdf9 drm/i915: Split TGL DKL PHY buf trans per output type
cf80a68f2857 drm/i915: Split TGL combo PHY buf trans per output type
f41ab4bb8812 drm/i915: Split EHL combo PHY buf trans per output type
a1ebc02e12c4 drm/i915: Split ICL MG PHY buf trans per output type
5606e8d70bc2 drm/i915: Split ICL combo PHY buf trans per output type
582bcff90ebb drm/i915: Shove the PHY test into the hotplug work
f40c6b9eb99a drm/i915: Make intel_dp_process_phy_request() static
d2dcd064491e drm/i915: s/old_crtc_state/crtc_state/
d4651ba92742 drm/i915: s/pre_empemph/preemph/

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/index.html

[-- Attachment #1.2: Type: text/html, Size: 7860 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Plumb crtc state to link training code (rev5)
  2020-09-29 23:34 [Intel-gfx] [PATCH v2 00/11] drm/i915: Plumb crtc state to link training code Ville Syrjala
                   ` (18 preceding siblings ...)
  2020-10-01 11:56 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-10-01 13:12 ` Patchwork
  2020-10-01 14:02 ` [Intel-gfx] [PATCH v2 00/11] drm/i915: Plumb crtc state to link training code Ville Syrjälä
  20 siblings, 0 replies; 37+ messages in thread
From: Patchwork @ 2020-10-01 13:12 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx


[-- Attachment #1.1: Type: text/plain, Size: 14995 bytes --]

== Series Details ==

Series: drm/i915: Plumb crtc state to link training code (rev5)
URL   : https://patchwork.freedesktop.org/series/76993/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9086_full -> Patchwork_18606_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_18606_full:

### Piglit changes ###

#### Possible regressions ####

  * spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-bitor-neg-ivec4-int (NEW):
    - {pig-icl-1065g7}:   NOTRUN -> [INCOMPLETE][1] +7 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/pig-icl-1065g7/spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-bitor-neg-ivec4-int.html

  * spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-eq-mat2x3-mat2x3-using-if (NEW):
    - {pig-icl-1065g7}:   NOTRUN -> [CRASH][2]
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/pig-icl-1065g7/spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-eq-mat2x3-mat2x3-using-if.html

  
New tests
---------

  New tests have been introduced between CI_DRM_9086_full and Patchwork_18606_full:

### New Piglit tests (9) ###

  * spec@arb_tessellation_shader@execution@built-in-functions@tcs-ceil-vec2:
    - Statuses : 1 incomplete(s)
    - Exec time: [0.0] s

  * spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-bitor-neg-ivec4-int:
    - Statuses : 1 incomplete(s)
    - Exec time: [0.0] s

  * spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-bitor-not-ivec4-ivec4:
    - Statuses : 1 incomplete(s)
    - Exec time: [0.0] s

  * spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-bitxor-not-uvec3-uint:
    - Statuses : 1 incomplete(s)
    - Exec time: [0.0] s

  * spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-div-uvec2-uvec2:
    - Statuses : 1 incomplete(s)
    - Exec time: [0.0] s

  * spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-eq-mat2x3-mat2x3-using-if:
    - Statuses : 1 crash(s)
    - Exec time: [0.44] s

  * spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-ne-uvec4-uvec4:
    - Statuses : 1 incomplete(s)
    - Exec time: [0.0] s

  * spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-sub-uint-uint:
    - Statuses : 1 incomplete(s)
    - Exec time: [0.0] s

  * spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-sub-vec3-float:
    - Statuses : 1 incomplete(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in Patchwork_18606_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@feature_discovery@psr2:
    - shard-iclb:         [PASS][3] -> [SKIP][4] ([i915#658])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/shard-iclb2/igt@feature_discovery@psr2.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/shard-iclb8/igt@feature_discovery@psr2.html

  * igt@gem_ppgtt@flink-and-close-vma-leak:
    - shard-skl:          [PASS][5] -> [FAIL][6] ([i915#644])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/shard-skl7/igt@gem_ppgtt@flink-and-close-vma-leak.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/shard-skl1/igt@gem_ppgtt@flink-and-close-vma-leak.html

  * igt@i915_pm_dc@dc5-psr:
    - shard-iclb:         [PASS][7] -> [FAIL][8] ([i915#1899])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/shard-iclb2/igt@i915_pm_dc@dc5-psr.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/shard-iclb8/igt@i915_pm_dc@dc5-psr.html

  * igt@kms_cursor_crc@pipe-b-cursor-size-change:
    - shard-skl:          [PASS][9] -> [FAIL][10] ([i915#54])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/shard-skl4/igt@kms_cursor_crc@pipe-b-cursor-size-change.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/shard-skl6/igt@kms_cursor_crc@pipe-b-cursor-size-change.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
    - shard-glk:          [PASS][11] -> [FAIL][12] ([i915#72])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/shard-glk3/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/shard-glk8/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html

  * igt@kms_cursor_legacy@flip-vs-cursor-toggle:
    - shard-skl:          [PASS][13] -> [FAIL][14] ([i915#2346])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/shard-skl5/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/shard-skl9/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html

  * igt@kms_draw_crc@draw-method-xrgb2101010-pwrite-untiled:
    - shard-skl:          [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) +9 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/shard-skl7/igt@kms_draw_crc@draw-method-xrgb2101010-pwrite-untiled.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/shard-skl2/igt@kms_draw_crc@draw-method-xrgb2101010-pwrite-untiled.html

  * igt@kms_flip@flip-vs-suspend@b-vga1:
    - shard-snb:          [PASS][17] -> [DMESG-WARN][18] ([i915#42])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/shard-snb7/igt@kms_flip@flip-vs-suspend@b-vga1.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/shard-snb6/igt@kms_flip@flip-vs-suspend@b-vga1.html

  * igt@kms_flip@flip-vs-suspend@c-dp1:
    - shard-kbl:          [PASS][19] -> [DMESG-WARN][20] ([i915#180]) +4 similar issues
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/shard-kbl1/igt@kms_flip@flip-vs-suspend@c-dp1.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/shard-kbl6/igt@kms_flip@flip-vs-suspend@c-dp1.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1:
    - shard-skl:          [PASS][21] -> [FAIL][22] ([i915#2122])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/shard-skl8/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/shard-skl10/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt:
    - shard-tglb:         [PASS][23] -> [DMESG-WARN][24] ([i915#1982]) +1 similar issue
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/shard-tglb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-skl:          [PASS][25] -> [FAIL][26] ([i915#1188])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/shard-skl1/igt@kms_hdr@bpc-switch-dpms.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/shard-skl9/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
    - shard-skl:          [PASS][27] -> [FAIL][28] ([fdo#108145] / [i915#265])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html

  * igt@kms_psr@psr2_no_drrs:
    - shard-iclb:         [PASS][29] -> [SKIP][30] ([fdo#109441]) +1 similar issue
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/shard-iclb8/igt@kms_psr@psr2_no_drrs.html

  * igt@kms_vblank@pipe-b-accuracy-idle:
    - shard-skl:          [PASS][31] -> [FAIL][32] ([i915#43])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/shard-skl7/igt@kms_vblank@pipe-b-accuracy-idle.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/shard-skl2/igt@kms_vblank@pipe-b-accuracy-idle.html

  
#### Possible fixes ####

  * igt@gem_userptr_blits@sync-unmap-cycles:
    - shard-skl:          [TIMEOUT][33] ([i915#1958] / [i915#2424]) -> [PASS][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/shard-skl1/igt@gem_userptr_blits@sync-unmap-cycles.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/shard-skl9/igt@gem_userptr_blits@sync-unmap-cycles.html

  * igt@gem_workarounds@suspend-resume:
    - shard-skl:          [DMESG-WARN][35] ([i915#1982]) -> [PASS][36] +6 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/shard-skl6/igt@gem_workarounds@suspend-resume.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/shard-skl5/igt@gem_workarounds@suspend-resume.html

  * igt@i915_pciid:
    - shard-hsw:          [INCOMPLETE][37] ([i915#2377]) -> [PASS][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/shard-hsw8/igt@i915_pciid.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/shard-hsw4/igt@i915_pciid.html

  * {igt@kms_async_flips@alternate-sync-async-flip}:
    - shard-apl:          [DMESG-WARN][39] ([i915#1635] / [i915#1982]) -> [PASS][40] +2 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/shard-apl2/igt@kms_async_flips@alternate-sync-async-flip.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/shard-apl1/igt@kms_async_flips@alternate-sync-async-flip.html

  * igt@kms_flip@blocking-wf_vblank@a-edp1:
    - shard-tglb:         [DMESG-WARN][41] ([i915#1982]) -> [PASS][42] +2 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/shard-tglb7/igt@kms_flip@blocking-wf_vblank@a-edp1.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/shard-tglb8/igt@kms_flip@blocking-wf_vblank@a-edp1.html

  * igt@kms_flip@flip-vs-expired-vblank@c-edp1:
    - shard-skl:          [DMESG-FAIL][43] ([i915#1982] / [i915#79]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/shard-skl6/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/shard-skl5/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html

  * igt@kms_flip@plain-flip-ts-check-interruptible@a-dp1:
    - shard-kbl:          [FAIL][45] ([i915#2122]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/shard-kbl2/igt@kms_flip@plain-flip-ts-check-interruptible@a-dp1.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/shard-kbl2/igt@kms_flip@plain-flip-ts-check-interruptible@a-dp1.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-skl:          [FAIL][47] ([i915#1188]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/shard-skl2/igt@kms_hdr@bpc-switch-suspend.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/shard-skl7/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
    - shard-kbl:          [DMESG-WARN][49] ([i915#180]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/shard-kbl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/shard-kbl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html

  * igt@kms_psr@psr2_sprite_mmap_gtt:
    - shard-iclb:         [SKIP][51] ([fdo#109441]) -> [PASS][52] +1 similar issue
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/shard-iclb5/igt@kms_psr@psr2_sprite_mmap_gtt.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html

  * igt@kms_vblank@pipe-b-wait-idle:
    - shard-kbl:          [DMESG-WARN][53] ([i915#1982]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/shard-kbl6/igt@kms_vblank@pipe-b-wait-idle.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/shard-kbl4/igt@kms_vblank@pipe-b-wait-idle.html

  * igt@sysfs_heartbeat_interval@mixed@bcs0:
    - shard-skl:          [INCOMPLETE][55] ([i915#1731] / [i915#198]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/shard-skl2/igt@sysfs_heartbeat_interval@mixed@bcs0.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/shard-skl7/igt@sysfs_heartbeat_interval@mixed@bcs0.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
  [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
  [i915#1731]: https://gitlab.freedesktop.org/drm/intel/issues/1731
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1899]: https://gitlab.freedesktop.org/drm/intel/issues/1899
  [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958
  [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2377]: https://gitlab.freedesktop.org/drm/intel/issues/2377
  [i915#2424]: https://gitlab.freedesktop.org/drm/intel/issues/2424
  [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#42]: https://gitlab.freedesktop.org/drm/intel/issues/42
  [i915#43]: https://gitlab.freedesktop.org/drm/intel/issues/43
  [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
  [i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79


Participating hosts (12 -> 11)
------------------------------

  Missing    (1): pig-snb-2600 


Build changes
-------------

  * Linux: CI_DRM_9086 -> Patchwork_18606

  CI-20190529: 20190529
  CI_DRM_9086: b86053f8eb427de294c64eea6b3554c78326bd10 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5796: 19ae9421a5af7b03a1c9a577c57f2cf8b16a0116 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_18606: 17947177aa4e93a32bad457c7225b1f59dbe611d @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/index.html

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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

* Re: [Intel-gfx] [PATCH v2 00/11] drm/i915: Plumb crtc state to link training code
  2020-09-29 23:34 [Intel-gfx] [PATCH v2 00/11] drm/i915: Plumb crtc state to link training code Ville Syrjala
                   ` (19 preceding siblings ...)
  2020-10-01 13:12 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2020-10-01 14:02 ` Ville Syrjälä
  20 siblings, 0 replies; 37+ messages in thread
From: Ville Syrjälä @ 2020-10-01 14:02 UTC (permalink / raw)
  To: intel-gfx

On Wed, Sep 30, 2020 at 02:34:38AM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Another attempt at plumbing the crtc state to the depths of
> the link training code. This time I tried to preserve the
> PHY test stuff in a somewhat working condition.
> 
> The DDI buf trans stuff also started to bug me again so had 
> to toss in a few cleanups in that area. Still pretty messy,
> but with a bit more regular structure we could perhaps toss
> in a few vfuncs to get rid of some if ladders at least.
> Not entirely sure yet...

Pushed to dinq. Thanks for the reviews.

> 
> Ville Syrjälä (11):
>   drm/i915: s/pre_empemph/preemph/
>   drm/i915: s/old_crtc_state/crtc_state/
>   drm/i915: Make intel_dp_process_phy_request() static
>   drm/i915: Shove the PHY test into the hotplug work
>   drm/i915: Split ICL combo PHY buf trans per output type
>   drm/i915: Split ICL MG PHY buf trans per output type
>   drm/i915: Split EHL combo PHY buf trans per output type
>   drm/i915: Split TGL combo PHY buf trans per output type
>   drm/i915: Split TGL DKL PHY buf trans per output type
>   drm/i915: Plumb crtc_state to link training
>   drm/i915: Eliminate intel_dp.regs.dp_tp_{ctl,status}
> 
>  drivers/gpu/drm/i915/display/intel_ddi.c      | 677 ++++++++++--------
>  drivers/gpu/drm/i915/display/intel_ddi.h      |  11 +-
>  .../drm/i915/display/intel_display_types.h    |  25 +-
>  drivers/gpu/drm/i915/display/intel_dp.c       | 289 ++++++--
>  drivers/gpu/drm/i915/display/intel_dp.h       |  11 +-
>  .../drm/i915/display/intel_dp_link_training.c | 102 +--
>  .../drm/i915/display/intel_dp_link_training.h |   8 +-
>  drivers/gpu/drm/i915/display/intel_dp_mst.c   |  24 +-
>  drivers/gpu/drm/i915/display/intel_dpio_phy.c |  23 +-
>  drivers/gpu/drm/i915/display/intel_dpio_phy.h |   2 +
>  drivers/gpu/drm/i915/display/intel_hdmi.c     |   7 +-
>  11 files changed, 718 insertions(+), 461 deletions(-)
> 
> -- 
> 2.26.2

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

end of thread, other threads:[~2020-10-01 14:03 UTC | newest]

Thread overview: 37+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-09-29 23:34 [Intel-gfx] [PATCH v2 00/11] drm/i915: Plumb crtc state to link training code Ville Syrjala
2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 01/11] drm/i915: s/pre_empemph/preemph/ Ville Syrjala
2020-09-30 13:56   ` Imre Deak
2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 02/11] drm/i915: s/old_crtc_state/crtc_state/ Ville Syrjala
2020-09-30 13:57   ` Imre Deak
2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 03/11] drm/i915: Make intel_dp_process_phy_request() static Ville Syrjala
2020-09-30 13:58   ` Imre Deak
2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 04/11] drm/i915: Shove the PHY test into the hotplug work Ville Syrjala
2020-09-30  8:10   ` kernel test robot
2020-09-30 10:04   ` [Intel-gfx] [PATCH v3 " Ville Syrjala
2020-09-30 15:12     ` Imre Deak
2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 05/11] drm/i915: Split ICL combo PHY buf trans per output type Ville Syrjala
2020-09-30 15:19   ` Imre Deak
2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 06/11] drm/i915: Split ICL MG " Ville Syrjala
2020-09-30 15:21   ` Imre Deak
2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 07/11] drm/i915: Split EHL combo " Ville Syrjala
2020-09-30 15:24   ` Imre Deak
2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 08/11] drm/i915: Split TGL " Ville Syrjala
2020-09-30 15:29   ` Imre Deak
2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 09/11] drm/i915: Split TGL DKL " Ville Syrjala
2020-09-30 15:31   ` Imre Deak
2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 10/11] drm/i915: Plumb crtc_state to link training Ville Syrjala
2020-09-30 16:36   ` Imre Deak
2020-09-30 18:50     ` Ville Syrjälä
2020-10-01 11:10   ` [Intel-gfx] [PATCH v4 " Ville Syrjala
2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 11/11] drm/i915: Eliminate intel_dp.regs.dp_tp_{ctl, status} Ville Syrjala
2020-09-30 17:04   ` Imre Deak
2020-09-29 23:50 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plumb crtc state to link training code (rev3) Patchwork
2020-09-29 23:51 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-09-30  0:07 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-09-30 10:28 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plumb crtc state to link training code (rev4) Patchwork
2020-09-30 13:12 ` [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Plumb crtc state to link training code (rev3) Patchwork
2020-09-30 15:35 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Plumb crtc state to link training code (rev4) Patchwork
2020-10-01 11:27 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plumb crtc state to link training code (rev5) Patchwork
2020-10-01 11:56 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-01 13:12 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-10-01 14:02 ` [Intel-gfx] [PATCH v2 00/11] drm/i915: Plumb crtc state to link training code Ville Syrjälä

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