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* [igt-dev] [PATCH i-g-t 1/2] lib/intel_batchbuffer: Prepare batch to use in allocator infrastructure
@ 2020-09-30 12:09 Zbigniew Kempczyński
  2020-09-30 12:09 ` [igt-dev] [PATCH i-g-t 2/2] lib + tests: Remove possibility to use other than intel_bb context Zbigniew Kempczyński
                   ` (3 more replies)
  0 siblings, 4 replies; 9+ messages in thread
From: Zbigniew Kempczyński @ 2020-09-30 12:09 UTC (permalink / raw)
  To: igt-dev; +Cc: Chris Wilson

With upcoming of allocator code we need to ensure batch will execute
with appropriate context. If not mismatch between allocator data
and batch could lead to strange or wrong results. All functions which
could change context in execbuf called from intel_bb were removed.

As an allocator requires size (which was not previously required in
intel_bb) adding object to intel_bb is now mandatory.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 lib/intel_batchbuffer.c | 205 ++++++++++++++++++++--------------------
 lib/intel_batchbuffer.h |  18 ++--
 2 files changed, 110 insertions(+), 113 deletions(-)

diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index be764646..60dbfe26 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -1220,7 +1220,10 @@ static uint64_t gen8_canonical_addr(uint64_t address)
 	return (int64_t)(address << shift) >> shift;
 }
 
-static inline uint64_t __intel_bb_propose_offset(struct intel_bb *ibb)
+static inline uint64_t __intel_bb_get_offset(struct intel_bb *ibb,
+					     uint32_t handle,
+					     uint32_t size,
+					     uint32_t alignment)
 {
 	uint64_t offset;
 
@@ -1247,7 +1250,7 @@ static inline uint64_t __intel_bb_propose_offset(struct intel_bb *ibb)
  * Pointer the intel_bb, asserts on failure.
  */
 static struct intel_bb *
-__intel_bb_create(int i915, uint32_t size, bool do_relocs)
+__intel_bb_create(int i915, uint32_t ctx, uint32_t size, bool do_relocs)
 {
 	struct intel_bb *ibb = calloc(1, sizeof(*ibb));
 	uint64_t gtt_size;
@@ -1261,6 +1264,7 @@ __intel_bb_create(int i915, uint32_t size, bool do_relocs)
 	ibb->handle = gem_create(i915, size);
 	ibb->size = size;
 	ibb->alignment = 4096;
+	ibb->ctx = ctx;
 	ibb->batch = calloc(1, size);
 	igt_assert(ibb->batch);
 	ibb->ptr = ibb->batch;
@@ -1287,8 +1291,12 @@ __intel_bb_create(int i915, uint32_t size, bool do_relocs)
 	}
 	ibb->gtt_size = gtt_size;
 
-	ibb->batch_offset = __intel_bb_propose_offset(ibb);
-	intel_bb_add_object(ibb, ibb->handle, ibb->batch_offset, false);
+	ibb->batch_offset = __intel_bb_get_offset(ibb,
+						  ibb->handle,
+						  ibb->size,
+						  ibb->alignment);
+	intel_bb_add_object(ibb, ibb->handle, ibb->size,
+			    ibb->batch_offset, false);
 
 	ibb->refcount = 1;
 
@@ -1300,13 +1308,33 @@ __intel_bb_create(int i915, uint32_t size, bool do_relocs)
  * @i915: drm fd
  * @size: size of the batchbuffer
  *
+ * Creates bb with default context.
+ *
  * Returns:
  *
  * Pointer the intel_bb, asserts on failure.
  */
 struct intel_bb *intel_bb_create(int i915, uint32_t size)
 {
-	return __intel_bb_create(i915, size, false);
+	return __intel_bb_create(i915, 0, size, false);
+}
+
+/**
+ * intel_bb_create_with_context:
+ * @i915: drm fd
+ * @ctx: context
+ * @size: size of the batchbuffer
+ *
+ * Creates bb with context passed in @ctx.
+ *
+ * Returns:
+ *
+ * Pointer the intel_bb, asserts on failure.
+ */
+struct intel_bb *
+intel_bb_create_with_context(int i915, uint32_t ctx, uint32_t size)
+{
+	return __intel_bb_create(i915, ctx, size, false);
 }
 
 /**
@@ -1314,8 +1342,8 @@ struct intel_bb *intel_bb_create(int i915, uint32_t size)
  * @i915: drm fd
  * @size: size of the batchbuffer
  *
- * Disable passing or randomizing addresses. This will lead to relocations
- * when objects are not previously pinned.
+ * Creates bb which will disable passing addresses.
+ * This will lead to relocations when objects are not previously pinned.
  *
  * Returns:
  *
@@ -1323,7 +1351,26 @@ struct intel_bb *intel_bb_create(int i915, uint32_t size)
  */
 struct intel_bb *intel_bb_create_with_relocs(int i915, uint32_t size)
 {
-	return __intel_bb_create(i915, size, true);
+	return __intel_bb_create(i915, 0, size, true);
+}
+
+/**
+ * intel_bb_create_with_relocs_and_context:
+ * @i915: drm fd
+ * @ctx: context
+ * @size: size of the batchbuffer
+ *
+ * Creates bb with default context which will disable passing addresses.
+ * This will lead to relocations when objects are not previously pinned.
+ *
+ * Returns:
+ *
+ * Pointer the intel_bb, asserts on failure.
+ */
+struct intel_bb *
+intel_bb_create_with_relocs_and_context(int i915, uint32_t ctx, uint32_t size)
+{
+	return __intel_bb_create(i915, ctx, size, true);
 }
 
 static void __intel_bb_destroy_relocations(struct intel_bb *ibb)
@@ -1418,19 +1465,26 @@ void intel_bb_reset(struct intel_bb *ibb, bool purge_objects_cache)
 
 	if (purge_objects_cache) {
 		__intel_bb_destroy_cache(ibb);
-		ibb->batch_offset = __intel_bb_propose_offset(ibb);
+		ibb->batch_offset = __intel_bb_get_offset(ibb,
+							  ibb->handle,
+							  ibb->size,
+							  ibb->alignment);
 	} else {
 		struct drm_i915_gem_exec_object2 *object;
 
 		object = intel_bb_find_object(ibb, ibb->handle);
 		ibb->batch_offset = object ? object->offset :
-					     __intel_bb_propose_offset(ibb);
+					     __intel_bb_get_offset(ibb,
+								   ibb->handle,
+								   ibb->size,
+								   ibb->alignment);
 	}
 
 	gem_close(ibb->i915, ibb->handle);
 	ibb->handle = gem_create(ibb->i915, ibb->size);
 
-	intel_bb_add_object(ibb, ibb->handle, ibb->batch_offset, false);
+	intel_bb_add_object(ibb, ibb->handle, ibb->size,
+			    ibb->batch_offset, false);
 	ibb->ptr = ibb->batch;
 	memset(ibb->batch, 0, ibb->size);
 }
@@ -1580,6 +1634,7 @@ static void __add_to_objects(struct intel_bb *ibb,
  * intel_bb_add_object:
  * @ibb: pointer to intel_bb
  * @handle: which handle to add to objects array
+ * @size: object size
  * @offset: presumed offset of the object when no relocation is enforced
  * @write: does a handle is a render target
  *
@@ -1588,7 +1643,7 @@ static void __add_to_objects(struct intel_bb *ibb,
  * be marked with EXEC_OBJECT_WRITE flag.
  */
 struct drm_i915_gem_exec_object2 *
-intel_bb_add_object(struct intel_bb *ibb, uint32_t handle,
+intel_bb_add_object(struct intel_bb *ibb, uint32_t handle, uint32_t size,
 		    uint64_t offset, bool write)
 {
 	struct drm_i915_gem_exec_object2 *object;
@@ -1602,7 +1657,9 @@ intel_bb_add_object(struct intel_bb *ibb, uint32_t handle,
 		object->offset = gen8_canonical_addr(offset & (ibb->gtt_size - 1));
 
 	if (object->offset == INTEL_BUF_INVALID_ADDRESS)
-		object->offset = __intel_bb_propose_offset(ibb);
+		object->offset = __intel_bb_get_offset(ibb,
+						       handle, size,
+						       object->alignment);
 
 	if (write)
 		object->flags |= EXEC_OBJECT_WRITE;
@@ -1618,7 +1675,9 @@ intel_bb_add_intel_buf(struct intel_bb *ibb, struct intel_buf *buf, bool write)
 {
 	struct drm_i915_gem_exec_object2 *obj;
 
-	obj = intel_bb_add_object(ibb, buf->handle, buf->addr.offset, write);
+	obj = intel_bb_add_object(ibb, buf->handle,
+				  intel_buf_bo_size(buf),
+				  buf->addr.offset, write);
 
 	/* For compressed surfaces ensure address is aligned to 64KB */
 	if (ibb->gen >= 12 && buf->compression) {
@@ -1720,7 +1779,13 @@ static uint64_t intel_bb_add_reloc(struct intel_bb *ibb,
 	struct drm_i915_gem_exec_object2 *object, *to_object;
 	uint32_t i;
 
-	object = intel_bb_add_object(ibb, handle, presumed_offset, false);
+	if (ibb->enforce_relocs) {
+		object = intel_bb_add_object(ibb, handle, 0,
+					     presumed_offset, false);
+	} else {
+		object = intel_bb_find_object(ibb, handle);
+		igt_assert(object);
+	}
 
 	/* For ibb we have relocs allocated in chunks */
 	if (to_handle == ibb->handle) {
@@ -2030,7 +2095,6 @@ static void update_offsets(struct intel_bb *ibb,
  * @ibb: pointer to intel_bb
  * @end_offset: offset of the last instruction in the bb
  * @flags: flags passed directly to execbuf
- * @ctx: context
  * @sync: if true wait for execbuf completion, otherwise caller is responsible
  * to wait for completion
  *
@@ -2039,8 +2103,8 @@ static void update_offsets(struct intel_bb *ibb,
  * Note: In this step execobj for bb is allocated and inserted to the objects
  * array.
 */
-int __intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
-		    uint32_t ctx, uint64_t flags, bool sync)
+static int __intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
+			   uint64_t flags, bool sync)
 {
 	struct drm_i915_gem_execbuffer2 execbuf;
 	struct drm_i915_gem_exec_object2 *objects;
@@ -2057,7 +2121,7 @@ int __intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
 	execbuf.buffers_ptr = (uintptr_t) objects;
 	execbuf.buffer_count = ibb->num_objects;
 	execbuf.batch_len = end_offset;
-	execbuf.rsvd1 = ibb->ctx = ctx;
+	execbuf.rsvd1 = ibb->ctx;
 	execbuf.flags = flags | I915_EXEC_BATCH_FIRST | I915_EXEC_FENCE_OUT;
 	if (ibb->enforce_relocs)
 		execbuf.flags &= ~I915_EXEC_NO_RELOC;
@@ -2112,29 +2176,12 @@ int __intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
  * @sync: if true wait for execbuf completion, otherwise caller is responsible
  * to wait for completion
  *
- * Do execbuf with default context. Asserts on failure.
+ * Do execbuf on context selected during bb creation. Asserts on failure.
 */
 void intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
 		   uint64_t flags, bool sync)
 {
-	igt_assert_eq(__intel_bb_exec(ibb, end_offset, 0, flags, sync), 0);
-}
-
-/*
- * intel_bb_exec_with_context:
- * @ibb: pointer to intel_bb
- * @end_offset: offset of the last instruction in the bb
- * @flags: flags passed directly to execbuf
- * @ctx: context
- * @sync: if true wait for execbuf completion, otherwise caller is responsible
- * to wait for completion
- *
- * Do execbuf with context @context.
-*/
-void intel_bb_exec_with_context(struct intel_bb *ibb, uint32_t end_offset,
-				uint32_t ctx, uint64_t flags, bool sync)
-{
-	igt_assert_eq(__intel_bb_exec(ibb, end_offset, ctx, flags, sync), 0);
+	igt_assert_eq(__intel_bb_exec(ibb, end_offset, flags, sync), 0);
 }
 
 /**
@@ -2185,7 +2232,7 @@ bool intel_bb_object_offset_to_buf(struct intel_bb *ibb, struct intel_buf *buf)
 	found = tfind((void *)&object, &ibb->root, __compare_objects);
 	if (!found) {
 		buf->addr.offset = 0;
-		buf->addr.ctx = 0;
+		buf->addr.ctx = ibb->ctx;
 
 		return false;
 	}
@@ -2242,41 +2289,27 @@ uint32_t intel_bb_emit_flush_common(struct intel_bb *ibb)
 	return intel_bb_offset(ibb);
 }
 
-static void intel_bb_exec_with_context_ring(struct intel_bb *ibb,
-					    uint32_t ctx, uint32_t ring)
+static void intel_bb_exec_with_ring(struct intel_bb *ibb,uint32_t ring)
 {
-	intel_bb_exec_with_context(ibb, intel_bb_offset(ibb), ctx,
-				   ring | I915_EXEC_NO_RELOC,
-				   false);
+	intel_bb_exec(ibb, intel_bb_offset(ibb),
+		      ring | I915_EXEC_NO_RELOC, false);
 	intel_bb_reset(ibb, false);
 }
 
 /*
  * intel_bb_flush:
  * @ibb: batchbuffer
- * @ctx: context
  * @ring: ring
  *
- * If batch is not empty emit batch buffer end, execute on specified
- * context, ring then reset the batch.
+ * If batch is not empty emit batch buffer end, execute on ring,
+ * then reset the batch.
  */
-void intel_bb_flush(struct intel_bb *ibb, uint32_t ctx, uint32_t ring)
+void intel_bb_flush(struct intel_bb *ibb, uint32_t ring)
 {
 	if (intel_bb_emit_flush_common(ibb) == 0)
 		return;
 
-	intel_bb_exec_with_context_ring(ibb, ctx, ring);
-}
-
-static void __intel_bb_flush_render_with_context(struct intel_bb *ibb,
-						 uint32_t ctx)
-{
-	uint32_t ring = I915_EXEC_RENDER;
-
-	if (intel_bb_emit_flush_common(ibb) == 0)
-		return;
-
-	intel_bb_exec_with_context_ring(ibb, ctx, ring);
+	intel_bb_exec_with_ring(ibb, ring);
 }
 
 /*
@@ -2284,39 +2317,14 @@ static void __intel_bb_flush_render_with_context(struct intel_bb *ibb,
  * @ibb: batchbuffer
  *
  * If batch is not empty emit batch buffer end, execute on render ring
- * and reset the batch.
- * Context used to execute is previous batch context.
+ * and reset the batch. Context used to execute is batch context.
  */
 void intel_bb_flush_render(struct intel_bb *ibb)
 {
-	__intel_bb_flush_render_with_context(ibb, ibb->ctx);
-}
-
-/*
- * intel_bb_flush_render_with_context:
- * @ibb: batchbuffer
- * @ctx: context
- *
- * If batch is not empty emit batch buffer end, execute on render ring with @ctx
- * and reset the batch.
- */
-void intel_bb_flush_render_with_context(struct intel_bb *ibb, uint32_t ctx)
-{
-	__intel_bb_flush_render_with_context(ibb, ctx);
-}
-
-static void __intel_bb_flush_blit_with_context(struct intel_bb *ibb,
-					       uint32_t ctx)
-{
-	uint32_t ring = I915_EXEC_DEFAULT;
-
 	if (intel_bb_emit_flush_common(ibb) == 0)
 		return;
 
-	if (HAS_BLT_RING(ibb->devid))
-		ring = I915_EXEC_BLT;
-
-	intel_bb_exec_with_context_ring(ibb, ctx, ring);
+	intel_bb_exec_with_ring(ibb, I915_EXEC_RENDER);
 }
 
 /*
@@ -2325,24 +2333,19 @@ static void __intel_bb_flush_blit_with_context(struct intel_bb *ibb,
  *
  * If batch is not empty emit batch buffer end, execute on default/blit ring
  * (depends on gen) and reset the batch.
- * Context used to execute is previous batch context.
+ * Context used to execute is batch context.
  */
 void intel_bb_flush_blit(struct intel_bb *ibb)
 {
-	__intel_bb_flush_blit_with_context(ibb, ibb->ctx);
-}
+	uint32_t ring = I915_EXEC_DEFAULT;
 
-/*
- * intel_bb_flush_blit_with_context:
- * @ibb: batchbuffer
- * @ctx: context
- *
- * If batch is not empty emit batch buffer end, execute on default/blit ring
- * (depends on gen) with @ctx and reset the batch.
- */
-void intel_bb_flush_blit_with_context(struct intel_bb *ibb, uint32_t ctx)
-{
-	__intel_bb_flush_blit_with_context(ibb, ctx);
+	if (intel_bb_emit_flush_common(ibb) == 0)
+		return;
+
+	if (HAS_BLT_RING(ibb->devid))
+		ring = I915_EXEC_BLT;
+
+	intel_bb_exec_with_ring(ibb, ring);
 }
 
 /*
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index 8b9c1ed9..d20b4e66 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -341,7 +341,6 @@ struct intel_bb;
 struct intel_buf;
 
 typedef void (*igt_render_copyfunc_t)(struct intel_bb *ibb,
-				      uint32_t ctx,
 				      struct intel_buf *src,
 				      uint32_t src_x, uint32_t src_y,
 				      uint32_t width, uint32_t height,
@@ -478,7 +477,11 @@ struct intel_bb {
 };
 
 struct intel_bb *intel_bb_create(int i915, uint32_t size);
+struct intel_bb *
+intel_bb_create_with_context(int i915, uint32_t ctx, uint32_t size);
 struct intel_bb *intel_bb_create_with_relocs(int i915, uint32_t size);
+struct intel_bb *
+intel_bb_create_with_relocs_and_context(int i915, uint32_t ctx, uint32_t size);
 void intel_bb_destroy(struct intel_bb *ibb);
 
 static inline void intel_bb_ref(struct intel_bb *ibb)
@@ -562,9 +565,8 @@ static inline void intel_bb_out(struct intel_bb *ibb, uint32_t dword)
 	igt_assert(intel_bb_offset(ibb) <= ibb->size);
 }
 
-
 struct drm_i915_gem_exec_object2 *
-intel_bb_add_object(struct intel_bb *ibb, uint32_t handle,
+intel_bb_add_object(struct intel_bb *ibb, uint32_t handle, uint32_t size,
 		    uint64_t offset, bool write);
 struct drm_i915_gem_exec_object2 *
 intel_bb_add_intel_buf(struct intel_bb *ibb, struct intel_buf *buf, bool write);
@@ -615,25 +617,17 @@ uint64_t intel_bb_offset_reloc_to_object(struct intel_bb *ibb,
 					 uint32_t offset,
 					 uint64_t presumed_offset);
 
-int __intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
-		    uint32_t ctx, uint64_t flags, bool sync);
-
 void intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
 		   uint64_t flags, bool sync);
 
-void intel_bb_exec_with_context(struct intel_bb *ibb, uint32_t end_offset,
-				uint32_t ctx, uint64_t flags, bool sync);
-
 uint64_t intel_bb_get_object_offset(struct intel_bb *ibb, uint32_t handle);
 bool intel_bb_object_offset_to_buf(struct intel_bb *ibb, struct intel_buf *buf);
 
 uint32_t intel_bb_emit_bbe(struct intel_bb *ibb);
 uint32_t intel_bb_emit_flush_common(struct intel_bb *ibb);
-void intel_bb_flush(struct intel_bb *ibb, uint32_t ctx, uint32_t ring);
+void intel_bb_flush(struct intel_bb *ibb, uint32_t ring);
 void intel_bb_flush_render(struct intel_bb *ibb);
-void intel_bb_flush_render_with_context(struct intel_bb *ibb, uint32_t ctx);
 void intel_bb_flush_blit(struct intel_bb *ibb);
-void intel_bb_flush_blit_with_context(struct intel_bb *ibb, uint32_t ctx);
 
 uint32_t intel_bb_copy_data(struct intel_bb *ibb,
 			    const void *data, unsigned int bytes,
-- 
2.26.0

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^ permalink raw reply related	[flat|nested] 9+ messages in thread

* [igt-dev] [PATCH i-g-t 2/2] lib + tests: Remove possibility to use other than intel_bb context
  2020-09-30 12:09 [igt-dev] [PATCH i-g-t 1/2] lib/intel_batchbuffer: Prepare batch to use in allocator infrastructure Zbigniew Kempczyński
@ 2020-09-30 12:09 ` Zbigniew Kempczyński
  2020-09-30 13:20 ` [igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,1/2] lib/intel_batchbuffer: Prepare batch to use in allocator infrastructure Patchwork
                   ` (2 subsequent siblings)
  3 siblings, 0 replies; 9+ messages in thread
From: Zbigniew Kempczyński @ 2020-09-30 12:09 UTC (permalink / raw)
  To: igt-dev; +Cc: Chris Wilson

To avoid problems with addresses acquired from allocator in the
future we need to use intel_bb context. That's why all exec calls
which could pass different context id were removed. Update libraries
and tests to not to use that API anymore.

Depends on changes in intel_bb so must be merged together.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 lib/gpgpu_fill.c                      |  6 +--
 lib/igt_draw.c                        |  5 +-
 lib/igt_fb.c                          |  2 +-
 lib/media_fill.c                      | 17 ++++---
 lib/media_spin.c                      |  4 +-
 lib/rendercopy.h                      |  9 ----
 lib/rendercopy_gen4.c                 |  8 ++--
 lib/rendercopy_gen6.c                 |  8 ++--
 lib/rendercopy_gen7.c                 |  8 ++--
 lib/rendercopy_gen8.c                 |  8 ++--
 lib/rendercopy_gen9.c                 | 17 +++----
 lib/rendercopy_i830.c                 |  3 +-
 lib/rendercopy_i915.c                 |  3 +-
 lib/veboxcopy_gen12.c                 |  7 ++-
 tests/i915/api_intel_bb.c             | 55 ++++++++++++++-------
 tests/i915/gem_caching.c              |  3 ++
 tests/i915/gem_concurrent_all.c       |  2 +-
 tests/i915/gem_mmap_offset.c          |  4 +-
 tests/i915/gem_partial_pwrite_pread.c |  3 ++
 tests/i915/gem_ppgtt.c                |  9 ++--
 tests/i915/gem_read_read_speed.c      |  2 +-
 tests/i915/gem_render_copy.c          | 14 +++---
 tests/i915/gem_render_copy_redux.c    |  8 ++--
 tests/i915/gem_render_linear_blits.c  |  6 +--
 tests/i915/gem_render_tiled_blits.c   |  8 ++--
 tests/i915/gem_stress.c               |  2 +-
 tests/i915/perf.c                     | 69 ++++++++++++---------------
 tests/kms_big_fb.c                    |  2 +-
 tests/kms_psr.c                       |  2 +-
 29 files changed, 143 insertions(+), 151 deletions(-)

diff --git a/lib/gpgpu_fill.c b/lib/gpgpu_fill.c
index aa2ffa8d..0f031a52 100644
--- a/lib/gpgpu_fill.c
+++ b/lib/gpgpu_fill.c
@@ -140,7 +140,7 @@ gen7_gpgpu_fillfunc(int i915,
 	uint32_t curbe_buffer, interface_descriptor;
 
 	ibb = intel_bb_create(i915, PAGE_SIZE);
-	intel_bb_add_object(ibb, buf->handle, 0, true);
+	intel_bb_add_intel_buf(ibb, buf, true);
 
 	intel_bb_ptr_set(ibb, BATCH_STATE_SPLIT);
 
@@ -190,7 +190,7 @@ gen8_gpgpu_fillfunc(int i915,
 	uint32_t curbe_buffer, interface_descriptor;
 
 	ibb = intel_bb_create(i915, PAGE_SIZE);
-	intel_bb_add_object(ibb, buf->handle, 0, true);
+	intel_bb_add_intel_buf(ibb, buf, true);
 
 	intel_bb_ptr_set(ibb, BATCH_STATE_SPLIT);
 
@@ -239,7 +239,7 @@ __gen9_gpgpu_fillfunc(int i915,
 	uint32_t curbe_buffer, interface_descriptor;
 
 	ibb = intel_bb_create(i915, PAGE_SIZE);
-	intel_bb_add_object(ibb, buf->handle, 0, true);
+	intel_bb_add_intel_buf(ibb, buf, true);
 
 	intel_bb_ptr_set(ibb, BATCH_STATE_SPLIT);
 
diff --git a/lib/igt_draw.c b/lib/igt_draw.c
index 7a30340f..353467a2 100644
--- a/lib/igt_draw.c
+++ b/lib/igt_draw.c
@@ -601,10 +601,9 @@ static void draw_rect_render(int fd, struct cmd_data *cmd_data,
 
 	src = create_buf(fd, cmd_data->bops, &tmp, I915_TILING_NONE);
 	dst = create_buf(fd, cmd_data->bops, buf, tiling);
-	ibb = intel_bb_create(fd, PAGE_SIZE);
+	ibb = intel_bb_create_with_context(fd, cmd_data->ctx, PAGE_SIZE);
 
-	rendercopy(ibb, cmd_data->ctx, src, 0, 0, rect->w,
-		   rect->h, dst, rect->x, rect->y);
+	rendercopy(ibb, src, 0, 0, rect->w, rect->h, dst, rect->x, rect->y);
 
 	intel_bb_destroy(ibb);
 	intel_buf_destroy(src);
diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index c6c35ace..8f20463c 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
@@ -2267,7 +2267,7 @@ static void copy_with_engine(struct fb_blit_upload *blit,
 			   dst_fb->plane_width[0], dst_fb->plane_height[0],
 			   dst);
 	else
-		render_copy(blit->ibb, 0,
+		render_copy(blit->ibb,
 			    src,
 			    0, 0,
 			    dst_fb->plane_width[0], dst_fb->plane_height[0],
diff --git a/lib/media_fill.c b/lib/media_fill.c
index c21de54b..8e4da4ec 100644
--- a/lib/media_fill.c
+++ b/lib/media_fill.c
@@ -155,7 +155,7 @@ gen7_media_fillfunc(int i915,
 	uint32_t curbe_buffer, interface_descriptor;
 
 	ibb = intel_bb_create(i915, PAGE_SIZE);
-	intel_bb_add_object(ibb, buf->handle, 0, true);
+	intel_bb_add_intel_buf(ibb, buf, true);
 
 	intel_bb_ptr_set(ibb, BATCH_STATE_SPLIT);
 
@@ -198,7 +198,7 @@ gen8_media_fillfunc(int i915,
 	uint32_t curbe_buffer, interface_descriptor;
 
 	ibb = intel_bb_create(i915, PAGE_SIZE);
-	intel_bb_add_object(ibb, buf->handle, 0, true);
+	intel_bb_add_intel_buf(ibb, buf, true);
 
 	intel_bb_ptr_set(ibb, BATCH_STATE_SPLIT);
 
@@ -242,7 +242,7 @@ __gen9_media_fillfunc(int i915,
 	uint32_t curbe_buffer, interface_descriptor;
 
 	ibb = intel_bb_create(i915, PAGE_SIZE);
-	intel_bb_add_object(ibb, buf->handle, 0, true);
+	intel_bb_add_intel_buf(ibb, buf, true);
 
 	/* setup states */
 	intel_bb_ptr_set(ibb, BATCH_STATE_SPLIT);
@@ -310,9 +310,9 @@ __gen11_media_vme_func(int i915,
 	struct intel_bb *ibb;
 	uint32_t curbe_buffer, interface_descriptor;
 
-	ibb = intel_bb_create(i915, PAGE_SIZE);
-	intel_bb_add_object(ibb, dst->handle, 0, true);
-	intel_bb_add_object(ibb, src->handle, 0, false);
+	ibb = intel_bb_create_with_context(i915, ctx, PAGE_SIZE);
+	intel_bb_add_intel_buf(ibb, dst, true);
+	intel_bb_add_intel_buf(ibb, src, false);
 
 	/* setup states */
 	intel_bb_ptr_set(ibb, BATCH_STATE_SPLIT);
@@ -351,9 +351,8 @@ __gen11_media_vme_func(int i915,
 	intel_bb_out(ibb, MI_BATCH_BUFFER_END);
 	intel_bb_ptr_align(ibb, 32);
 
-	intel_bb_exec_with_context(ibb, intel_bb_offset(ibb), ctx,
-				   I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC,
-				   false);
+	intel_bb_exec(ibb, intel_bb_offset(ibb),
+		      I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, false);
 	intel_bb_destroy(ibb);
 }
 
diff --git a/lib/media_spin.c b/lib/media_spin.c
index 6e81a13d..5da469a5 100644
--- a/lib/media_spin.c
+++ b/lib/media_spin.c
@@ -102,7 +102,7 @@ gen8_media_spinfunc(int i915, struct intel_buf *buf, uint32_t spins)
 	uint32_t curbe_buffer, interface_descriptor;
 
 	ibb = intel_bb_create(i915, PAGE_SIZE);
-	intel_bb_add_object(ibb, buf->handle, 0, true);
+	intel_bb_add_intel_buf(ibb, buf, true);
 
 	/* setup states */
 	intel_bb_ptr_set(ibb, BATCH_STATE_SPLIT);
@@ -143,7 +143,7 @@ gen9_media_spinfunc(int i915, struct intel_buf *buf, uint32_t spins)
 	uint32_t curbe_buffer, interface_descriptor;
 
 	ibb = intel_bb_create(i915, PAGE_SIZE);
-	intel_bb_add_object(ibb, buf->handle, 0, true);
+	intel_bb_add_intel_buf(ibb, buf, true);
 
 	/* setup states */
 	intel_bb_ptr_set(ibb, BATCH_STATE_SPLIT);
diff --git a/lib/rendercopy.h b/lib/rendercopy.h
index 1bf8859c..7d5f0802 100644
--- a/lib/rendercopy.h
+++ b/lib/rendercopy.h
@@ -24,47 +24,38 @@ static inline void emit_vertex_normalized(struct intel_bb *ibb,
 }
 
 void gen12_render_copyfunc(struct intel_bb *ibb,
-			   uint32_t ctx,
 			   struct intel_buf *src, uint32_t src_x, uint32_t src_y,
 			   uint32_t width, uint32_t height,
 			   struct intel_buf *dst, uint32_t dst_x, uint32_t dst_y);
 void gen11_render_copyfunc(struct intel_bb *ibb,
-			  uint32_t ctx,
 			  struct intel_buf *src, uint32_t src_x, uint32_t src_y,
 			  uint32_t width, uint32_t height,
 			  struct intel_buf *dst, uint32_t dst_x, uint32_t dst_y);
 void gen9_render_copyfunc(struct intel_bb *ibb,
-			  uint32_t ctx,
 			  struct intel_buf *src, uint32_t src_x, uint32_t src_y,
 			  uint32_t width, uint32_t height,
 			  struct intel_buf *dst, uint32_t dst_x, uint32_t dst_y);
 void gen8_render_copyfunc(struct intel_bb *ibb,
-			  uint32_t ctx,
 			  struct intel_buf *src, uint32_t src_x, uint32_t src_y,
 			  uint32_t width, uint32_t height,
 			  struct intel_buf *dst, uint32_t dst_x, uint32_t dst_y);
 void gen7_render_copyfunc(struct intel_bb *ibb,
-			  uint32_t ctx,
 			  struct intel_buf *src, uint32_t src_x, uint32_t src_y,
 			  uint32_t width, uint32_t height,
 			  struct intel_buf *dst, uint32_t dst_x, uint32_t dst_y);
 void gen6_render_copyfunc(struct intel_bb *ibb,
-			  uint32_t ctx,
 			  struct intel_buf *src, uint32_t src_x, uint32_t src_y,
 			  uint32_t width, uint32_t height,
 			  struct intel_buf *dst, uint32_t dst_x, uint32_t dst_y);
 void gen4_render_copyfunc(struct intel_bb *ibb,
-			  uint32_t ctx,
 			  struct intel_buf *src, uint32_t src_x, uint32_t src_y,
 			  uint32_t width, uint32_t height,
 			  struct intel_buf *dst, uint32_t dst_x, uint32_t dst_y);
 void gen3_render_copyfunc(struct intel_bb *ibb,
-			  uint32_t ctx,
 			  struct intel_buf *src, uint32_t src_x, uint32_t src_y,
 			  uint32_t width, uint32_t height,
 			  struct intel_buf *dst, uint32_t dst_x, uint32_t dst_y);
 void gen2_render_copyfunc(struct intel_bb *ibb,
-			  uint32_t ctx,
 			  struct intel_buf *src, uint32_t src_x, uint32_t src_y,
 			  uint32_t width, uint32_t height,
 			  struct intel_buf *dst, uint32_t dst_x, uint32_t dst_y);
diff --git a/lib/rendercopy_gen4.c b/lib/rendercopy_gen4.c
index 279067ce..8536d6b6 100644
--- a/lib/rendercopy_gen4.c
+++ b/lib/rendercopy_gen4.c
@@ -626,7 +626,6 @@ static uint32_t gen4_emit_primitive(struct intel_bb *ibb)
 }
 
 void gen4_render_copyfunc(struct intel_bb *ibb,
-			  uint32_t ctx,
 			  struct intel_buf *src,
 			  uint32_t src_x, uint32_t src_y,
 			  uint32_t width, uint32_t height,
@@ -641,7 +640,7 @@ void gen4_render_copyfunc(struct intel_bb *ibb,
 
 	igt_assert(src->bpp == dst->bpp);
 
-	intel_bb_flush_render_with_context(ibb, ctx);
+	intel_bb_flush_render(ibb);
 
 	intel_bb_add_intel_buf(ibb, dst, true);
 	intel_bb_add_intel_buf(ibb, src, false);
@@ -699,8 +698,7 @@ void gen4_render_copyfunc(struct intel_bb *ibb,
 	/* Position to valid batch end position for batch reuse */
 	intel_bb_ptr_set(ibb, batch_end);
 
-	intel_bb_exec_with_context(ibb, batch_end, ctx,
-				   I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC,
-				   false);
+	intel_bb_exec(ibb, batch_end,
+		      I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, false);
 	intel_bb_reset(ibb, false);
 }
diff --git a/lib/rendercopy_gen6.c b/lib/rendercopy_gen6.c
index 4b7ed966..e941257e 100644
--- a/lib/rendercopy_gen6.c
+++ b/lib/rendercopy_gen6.c
@@ -510,7 +510,6 @@ static uint32_t gen6_emit_primitive(struct intel_bb *ibb)
 }
 
 void gen6_render_copyfunc(struct intel_bb *ibb,
-			  uint32_t ctx,
 			  struct intel_buf *src,
 			  uint32_t src_x, uint32_t src_y,
 			  uint32_t width, uint32_t height,
@@ -523,7 +522,7 @@ void gen6_render_copyfunc(struct intel_bb *ibb,
 
 	igt_assert(src->bpp == dst->bpp);
 
-	intel_bb_flush_render_with_context(ibb, ctx);
+	intel_bb_flush_render(ibb);
 
 	intel_bb_add_intel_buf(ibb, dst, true);
 	intel_bb_add_intel_buf(ibb, src, false);
@@ -585,8 +584,7 @@ void gen6_render_copyfunc(struct intel_bb *ibb,
 	/* Position to valid batch end position for batch reuse */
 	intel_bb_ptr_set(ibb, batch_end);
 
-	intel_bb_exec_with_context(ibb, batch_end, ctx,
-				   I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC,
-				   false);
+	intel_bb_exec(ibb, batch_end,
+		      I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, false);
 	intel_bb_reset(ibb, false);
 }
diff --git a/lib/rendercopy_gen7.c b/lib/rendercopy_gen7.c
index 62ef4325..267f6f80 100644
--- a/lib/rendercopy_gen7.c
+++ b/lib/rendercopy_gen7.c
@@ -507,7 +507,6 @@ gen7_emit_null_depth_buffer(struct intel_bb *ibb)
 
 #define BATCH_STATE_SPLIT 2048
 void gen7_render_copyfunc(struct intel_bb *ibb,
-			  uint32_t ctx,
 			  struct intel_buf *src,
 			  uint32_t src_x, uint32_t src_y,
 			  uint32_t width, uint32_t height,
@@ -520,7 +519,7 @@ void gen7_render_copyfunc(struct intel_bb *ibb,
 
 	igt_assert(src->bpp == dst->bpp);
 
-	intel_bb_flush_render_with_context(ibb, ctx);
+	intel_bb_flush_render(ibb);
 
 	intel_bb_add_intel_buf(ibb, dst, true);
 	intel_bb_add_intel_buf(ibb, src, false);
@@ -575,9 +574,8 @@ void gen7_render_copyfunc(struct intel_bb *ibb,
 	intel_bb_out(ibb, 0);   /* index buffer offset, ignored */
 
 	intel_bb_emit_bbe(ibb);
-	intel_bb_exec_with_context(ibb, intel_bb_offset(ibb), ctx,
-				   I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC,
-				   false);
+	intel_bb_exec(ibb, intel_bb_offset(ibb),
+		      I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, false);
 	dump_batch(ibb);
 	intel_bb_reset(ibb, false);
 }
diff --git a/lib/rendercopy_gen8.c b/lib/rendercopy_gen8.c
index 95c3c497..ba7897fb 100644
--- a/lib/rendercopy_gen8.c
+++ b/lib/rendercopy_gen8.c
@@ -780,7 +780,6 @@ static void gen8_emit_primitive(struct intel_bb *ibb, uint32_t offset)
 #define BATCH_STATE_SPLIT 2048
 
 void gen8_render_copyfunc(struct intel_bb *ibb,
-			  uint32_t ctx,
 			  struct intel_buf *src,
 			  unsigned int src_x, unsigned int src_y,
 			  unsigned int width, unsigned int height,
@@ -793,7 +792,7 @@ void gen8_render_copyfunc(struct intel_bb *ibb,
 
 	igt_assert(src->bpp == dst->bpp);
 
-	intel_bb_flush_render_with_context(ibb, ctx);
+	intel_bb_flush_render(ibb);
 
 	intel_bb_add_intel_buf(ibb, dst, true);
 	intel_bb_add_intel_buf(ibb, src, false);
@@ -874,9 +873,8 @@ void gen8_render_copyfunc(struct intel_bb *ibb,
 	gen8_emit_primitive(ibb, vertex_buffer);
 
 	intel_bb_emit_bbe(ibb);
-	intel_bb_exec_with_context(ibb, intel_bb_offset(ibb), ctx,
-				   I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC,
-				   false);
+	intel_bb_exec(ibb, intel_bb_offset(ibb),
+		      I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, false);
 	dump_batch(ibb);
 	intel_bb_reset(ibb, false);
 }
diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
index 6bad7bb6..ef6855c9 100644
--- a/lib/rendercopy_gen9.c
+++ b/lib/rendercopy_gen9.c
@@ -877,7 +877,6 @@ static void gen8_emit_primitive(struct intel_bb *ibb, uint32_t offset)
 
 static
 void _gen9_render_copyfunc(struct intel_bb *ibb,
-			   uint32_t ctx,
 			   struct intel_buf *src,
 			   unsigned int src_x, unsigned int src_y,
 			   unsigned int width, unsigned int height,
@@ -894,7 +893,7 @@ void _gen9_render_copyfunc(struct intel_bb *ibb,
 
 	igt_assert(src->bpp == dst->bpp);
 
-	intel_bb_flush_render_with_context(ibb, ctx);
+	intel_bb_flush_render(ibb);
 
 	intel_bb_add_intel_buf(ibb, dst, true);
 	intel_bb_add_intel_buf(ibb, src, false);
@@ -978,15 +977,13 @@ void _gen9_render_copyfunc(struct intel_bb *ibb,
 	gen8_emit_primitive(ibb, vertex_buffer);
 
 	intel_bb_emit_bbe(ibb);
-	intel_bb_exec_with_context(ibb, intel_bb_offset(ibb), ctx,
-				   I915_EXEC_RENDER | I915_EXEC_NO_RELOC,
-				   false);
+	intel_bb_exec(ibb, intel_bb_offset(ibb),
+		      I915_EXEC_RENDER | I915_EXEC_NO_RELOC, false);
 	dump_batch(ibb);
 	intel_bb_reset(ibb, false);
 }
 
 void gen9_render_copyfunc(struct intel_bb *ibb,
-			  uint32_t ctx,
 			  struct intel_buf *src,
 			  unsigned int src_x, unsigned int src_y,
 			  unsigned int width, unsigned int height,
@@ -994,26 +991,24 @@ void gen9_render_copyfunc(struct intel_bb *ibb,
 			  unsigned int dst_x, unsigned int dst_y)
 
 {
-	_gen9_render_copyfunc(ibb, ctx, src, src_x, src_y,
+	_gen9_render_copyfunc(ibb, src, src_x, src_y,
 			  width, height, dst, dst_x, dst_y, NULL,
 			  ps_kernel_gen9, sizeof(ps_kernel_gen9));
 }
 
 void gen11_render_copyfunc(struct intel_bb *ibb,
-			   uint32_t ctx,
 			   struct intel_buf *src,
 			   unsigned int src_x, unsigned int src_y,
 			   unsigned int width, unsigned int height,
 			   struct intel_buf *dst,
 			   unsigned int dst_x, unsigned int dst_y)
 {
-	_gen9_render_copyfunc(ibb, ctx, src, src_x, src_y,
+	_gen9_render_copyfunc(ibb, src, src_x, src_y,
 			  width, height, dst, dst_x, dst_y, NULL,
 			  ps_kernel_gen11, sizeof(ps_kernel_gen11));
 }
 
 void gen12_render_copyfunc(struct intel_bb *ibb,
-			   uint32_t ctx,
 			   struct intel_buf *src,
 			   unsigned int src_x, unsigned int src_y,
 			   unsigned int width, unsigned int height,
@@ -1024,7 +1019,7 @@ void gen12_render_copyfunc(struct intel_bb *ibb,
 
 	gen12_aux_pgtable_init(&pgtable_info, ibb, src, dst);
 
-	_gen9_render_copyfunc(ibb, ctx, src, src_x, src_y,
+	_gen9_render_copyfunc(ibb, src, src_x, src_y,
 			  width, height, dst, dst_x, dst_y,
 			  pgtable_info.pgtable_buf,
 			  gen12_render_copy,
diff --git a/lib/rendercopy_i830.c b/lib/rendercopy_i830.c
index e755706e..4c427149 100644
--- a/lib/rendercopy_i830.c
+++ b/lib/rendercopy_i830.c
@@ -235,7 +235,6 @@ static void gen2_emit_copy_pipeline(struct intel_bb *ibb)
 }
 
 void gen2_render_copyfunc(struct intel_bb *ibb,
-			  uint32_t ctx,
 			  struct intel_buf *src,
 			  uint32_t src_x, uint32_t src_y,
 			  uint32_t width, uint32_t height,
@@ -277,5 +276,5 @@ void gen2_render_copyfunc(struct intel_bb *ibb,
 	emit_vertex_normalized(ibb, src_x, intel_buf_width(src));
 	emit_vertex_normalized(ibb, src_y, intel_buf_height(src));
 
-	intel_bb_flush_blit_with_context(ibb, ctx);
+	intel_bb_flush_blit(ibb);
 }
diff --git a/lib/rendercopy_i915.c b/lib/rendercopy_i915.c
index b16d4f12..3e421301 100644
--- a/lib/rendercopy_i915.c
+++ b/lib/rendercopy_i915.c
@@ -20,7 +20,6 @@
 #include "rendercopy.h"
 
 void gen3_render_copyfunc(struct intel_bb *ibb,
-			  uint32_t ctx,
 			  struct intel_buf *src,
 			  uint32_t src_x, uint32_t src_y,
 			  uint32_t width, uint32_t height,
@@ -229,5 +228,5 @@ void gen3_render_copyfunc(struct intel_bb *ibb,
 	emit_vertex(ibb, src_x);
 	emit_vertex(ibb, src_y);
 
-	intel_bb_flush_blit_with_context(ibb, ctx);
+	intel_bb_flush_blit(ibb);
 }
diff --git a/lib/veboxcopy_gen12.c b/lib/veboxcopy_gen12.c
index a44e2bff..b4cd7bdd 100644
--- a/lib/veboxcopy_gen12.c
+++ b/lib/veboxcopy_gen12.c
@@ -248,7 +248,7 @@ void gen12_vebox_copyfunc(struct intel_bb *ibb,
 
 	igt_assert(src->bpp == dst->bpp);
 
-	intel_bb_flush(ibb, ibb->ctx, I915_EXEC_VEBOX);
+	intel_bb_flush(ibb, I915_EXEC_VEBOX);
 
 	intel_bb_add_intel_buf(ibb, dst, true);
 	intel_bb_add_intel_buf(ibb, src, false);
@@ -304,9 +304,8 @@ void gen12_vebox_copyfunc(struct intel_bb *ibb,
 	intel_bb_out(ibb, MI_BATCH_BUFFER_END);
 	intel_bb_ptr_align(ibb, 8);
 
-	intel_bb_exec_with_context(ibb, intel_bb_offset(ibb), 0,
-				   I915_EXEC_VEBOX | I915_EXEC_NO_RELOC,
-				   false);
+	intel_bb_exec(ibb, intel_bb_offset(ibb),
+		      I915_EXEC_VEBOX | I915_EXEC_NO_RELOC, false);
 
 	intel_bb_reset(ibb, false);
 
diff --git a/tests/i915/api_intel_bb.c b/tests/i915/api_intel_bb.c
index dacf05c0..965a7dde 100644
--- a/tests/i915/api_intel_bb.c
+++ b/tests/i915/api_intel_bb.c
@@ -158,10 +158,15 @@ static void simple_bb(struct buf_ops *bops, bool use_context)
 	intel_bb_out(ibb, MI_BATCH_BUFFER_END);
 	intel_bb_ptr_align(ibb, 8);
 
-	if (use_context)
-		intel_bb_exec_with_context(ibb, intel_bb_offset(ibb), ctx,
-					   I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC,
-					   true);
+	if (use_context) {
+		intel_bb_destroy(ibb);
+		ibb = intel_bb_create_with_context(i915, ctx, PAGE_SIZE);
+		intel_bb_out(ibb, MI_BATCH_BUFFER_END);
+		intel_bb_ptr_align(ibb, 8);
+		intel_bb_exec(ibb, intel_bb_offset(ibb),
+			      I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC,
+			      true);
+	}
 
 	intel_bb_destroy(ibb);
 	if (use_context)
@@ -429,6 +434,10 @@ static void blit(struct buf_ops *bops,
 	if (debug_bb)
 		intel_bb_set_debug(ibb, true);
 
+
+	intel_bb_add_intel_buf(ibb, src, false);
+	intel_bb_add_intel_buf(ibb, dst, true);
+
 	__emit_blit(ibb, src, dst);
 
 	/* We expect initial addresses are zeroed for relocs */
@@ -458,6 +467,11 @@ static void blit(struct buf_ops *bops,
 	fill_buf(src, COLOR_77);
 	fill_buf(dst, COLOR_00);
 
+	if (purge_cache && !do_relocs) {
+		intel_bb_add_intel_buf(ibb, src, false);
+		intel_bb_add_intel_buf(ibb, dst, true);
+	}
+
 	__emit_blit(ibb, src, dst);
 
 	poff2_bb = intel_bb_get_object_offset(ibb, ibb->handle);
@@ -478,8 +492,8 @@ static void blit(struct buf_ops *bops,
 			igt_assert(poff2_dst == 0);
 		} else {
 			igt_assert(poff_bb != poff2_bb);
-			igt_assert(poff_src != poff2_src);
-			igt_assert(poff_dst != poff2_dst);
+			igt_assert(poff_src == poff2_src);
+			igt_assert(poff_dst == poff2_dst);
 		}
 	} else {
 		igt_assert(poff_bb == poff2_bb);
@@ -781,9 +795,12 @@ static void offset_control(struct buf_ops *bops)
 	dst1 = create_buf(bops, WIDTH, HEIGHT, COLOR_00);
 	dst2 = create_buf(bops, WIDTH, HEIGHT, COLOR_77);
 
-	intel_bb_add_object(ibb, src->handle, src->addr.offset, false);
-	intel_bb_add_object(ibb, dst1->handle, dst1->addr.offset, true);
-	intel_bb_add_object(ibb, dst2->handle, dst2->addr.offset, true);
+	intel_bb_add_object(ibb, src->handle, intel_buf_bo_size(src),
+			    src->addr.offset, false);
+	intel_bb_add_object(ibb, dst1->handle, intel_buf_bo_size(dst1),
+			    dst1->addr.offset, true);
+	intel_bb_add_object(ibb, dst2->handle, intel_buf_bo_size(dst2),
+			    dst2->addr.offset, true);
 
 	intel_bb_out(ibb, MI_BATCH_BUFFER_END);
 	intel_bb_ptr_align(ibb, 8);
@@ -806,10 +823,14 @@ static void offset_control(struct buf_ops *bops)
 	intel_bb_reset(ibb, true);
 
 	dst3 = create_buf(bops, WIDTH, HEIGHT, COLOR_33);
-	intel_bb_add_object(ibb, dst3->handle, dst3->addr.offset, true);
-	intel_bb_add_object(ibb, src->handle, src->addr.offset, false);
-	intel_bb_add_object(ibb, dst1->handle, dst1->addr.offset, true);
-	intel_bb_add_object(ibb, dst2->handle, dst2->addr.offset, true);
+	intel_bb_add_object(ibb, dst3->handle, intel_buf_bo_size(dst3),
+			    dst3->addr.offset, true);
+	intel_bb_add_object(ibb, src->handle, intel_buf_bo_size(src),
+			    src->addr.offset, false);
+	intel_bb_add_object(ibb, dst1->handle, intel_buf_bo_size(dst1),
+			    dst1->addr.offset, true);
+	intel_bb_add_object(ibb, dst2->handle, intel_buf_bo_size(dst2),
+			    dst2->addr.offset, true);
 
 	intel_bb_out(ibb, MI_BATCH_BUFFER_END);
 	intel_bb_ptr_align(ibb, 8);
@@ -902,13 +923,13 @@ static int render(struct buf_ops *bops, uint32_t tiling, bool do_reloc,
 	render_copy = igt_get_render_copyfunc(devid);
 	igt_assert(render_copy);
 
-	render_copy(ibb, 0,
+	render_copy(ibb,
 		    &src,
 		    0, 0, width, height,
 		    &dst,
 		    0, 0);
 
-	render_copy(ibb, 0,
+	render_copy(ibb,
 		    &dst,
 		    0, 0, width, height,
 		    &final,
@@ -1003,13 +1024,13 @@ static void render_ccs(struct buf_ops *bops)
 				 0, 0, width, height,
 				 0, 0, width, height, 0);
 
-	render_copy(ibb, 0,
+	render_copy(ibb,
 		    &src,
 		    0, 0, width, height,
 		    &dst,
 		    0, 0);
 
-	render_copy(ibb, 0,
+	render_copy(ibb,
 		    &dst,
 		    0, 0, width, height,
 		    &final,
diff --git a/tests/i915/gem_caching.c b/tests/i915/gem_caching.c
index c178c98e..bdaff68a 100644
--- a/tests/i915/gem_caching.c
+++ b/tests/i915/gem_caching.c
@@ -79,6 +79,9 @@ copy_bo(struct intel_bb *ibb, struct intel_buf *src, struct intel_buf *dst)
 
 	has_64b_reloc = ibb->gen >= 8;
 
+	intel_bb_add_intel_buf(ibb, src, false);
+	intel_bb_add_intel_buf(ibb, dst, true);
+
 	intel_bb_out(ibb,
 		     XY_SRC_COPY_BLT_CMD |
 		     XY_SRC_COPY_BLT_WRITE_ALPHA |
diff --git a/tests/i915/gem_concurrent_all.c b/tests/i915/gem_concurrent_all.c
index 6609e1df..865da3f8 100644
--- a/tests/i915/gem_concurrent_all.c
+++ b/tests/i915/gem_concurrent_all.c
@@ -874,7 +874,7 @@ typedef igt_hang_t (*do_hang)(void);
 static void render_copy_bo(struct buffers *b, struct intel_buf *dst,
 			   struct intel_buf *src)
 {
-	rendercopy(b->ibb, 0,
+	rendercopy(b->ibb,
 		   src, 0, 0,
 		   b->width, b->height,
 		   dst, 0, 0);
diff --git a/tests/i915/gem_mmap_offset.c b/tests/i915/gem_mmap_offset.c
index 82203bce..8b29d0a0 100644
--- a/tests/i915/gem_mmap_offset.c
+++ b/tests/i915/gem_mmap_offset.c
@@ -614,8 +614,8 @@ static void blt_coherency(int i915)
 	dst = create_bo(bops, 1, width, height);
 	size = src->surface[0].size;
 
-	intel_bb_add_object(ibb, src->handle, src->addr.offset, false);
-	intel_bb_add_object(ibb, dst->handle, dst->addr.offset, true);
+	intel_bb_add_object(ibb, src->handle, size, src->addr.offset, false);
+	intel_bb_add_object(ibb, dst->handle, size, dst->addr.offset, true);
 
 	intel_bb_blt_copy(ibb,
 			  src, 0, 0, src->surface[0].stride,
diff --git a/tests/i915/gem_partial_pwrite_pread.c b/tests/i915/gem_partial_pwrite_pread.c
index b1028472..72c33539 100644
--- a/tests/i915/gem_partial_pwrite_pread.c
+++ b/tests/i915/gem_partial_pwrite_pread.c
@@ -83,6 +83,9 @@ static void copy_bo(struct intel_buf *src, struct intel_buf *dst)
 
 	has_64b_reloc = ibb->gen >= 8;
 
+	intel_bb_add_intel_buf(ibb, src, false);
+	intel_bb_add_intel_buf(ibb, dst, true);
+
 	intel_bb_out(ibb,
 		     XY_SRC_COPY_BLT_CMD |
 		     XY_SRC_COPY_BLT_WRITE_ALPHA |
diff --git a/tests/i915/gem_ppgtt.c b/tests/i915/gem_ppgtt.c
index e81620ac..73bd19c5 100644
--- a/tests/i915/gem_ppgtt.c
+++ b/tests/i915/gem_ppgtt.c
@@ -110,16 +110,17 @@ static void fork_rcs_copy(int timeout, uint32_t final,
 		struct intel_buf *src;
 		unsigned long i;
 
-		ibb = intel_bb_create(buf_ops_get_fd(dst[child]->bops), 4096);
-
 		if (flags & CREATE_CONTEXT)
 			ctx = gem_context_create(buf_ops_get_fd(dst[child]->bops));
 
+		ibb = intel_bb_create_with_context(buf_ops_get_fd(dst[child]->bops),
+						   ctx, 4096);
+
 		i = 0;
 		igt_until_timeout(timeout) {
 			src = create_bo(dst[child]->bops,
 					i++ | child << 16);
-			render_copy(ibb, ctx,
+			render_copy(ibb,
 				    src, 0, 0,
 				    WIDTH, HEIGHT,
 				    dst[child], 0, 0);
@@ -129,7 +130,7 @@ static void fork_rcs_copy(int timeout, uint32_t final,
 
 		src = create_bo(dst[child]->bops,
 				final | child << 16);
-		render_copy(ibb, ctx,
+		render_copy(ibb,
 			    src, 0, 0,
 			    WIDTH, HEIGHT,
 			    dst[child], 0, 0);
diff --git a/tests/i915/gem_read_read_speed.c b/tests/i915/gem_read_read_speed.c
index 40494566..7c5c90f7 100644
--- a/tests/i915/gem_read_read_speed.c
+++ b/tests/i915/gem_read_read_speed.c
@@ -66,7 +66,7 @@ static struct intel_bb *rcs_copy_bo(struct intel_buf *dst,
 	/* enforce batch won't be recreated after execution */
 	intel_bb_ref(ibb);
 
-	rendercopy(ibb, 0,
+	rendercopy(ibb,
 		   src, 0, 0,
 		   width, height,
 		   dst, 0, 0);
diff --git a/tests/i915/gem_render_copy.c b/tests/i915/gem_render_copy.c
index 7f425dcd..ae6e1833 100644
--- a/tests/i915/gem_render_copy.c
+++ b/tests/i915/gem_render_copy.c
@@ -456,12 +456,12 @@ static void test(data_t *data, uint32_t src_tiling, uint32_t dst_tiling,
 	 */
 	if (src_mixed_tiled) {
 		if (dst_compressed)
-			data->render_copy(data->ibb, 0,
+			data->render_copy(data->ibb,
 					  &dst, 0, 0, WIDTH, HEIGHT,
 					  &dst_ccs, 0, 0);
 
 		for (int i = 0; i < num_src; i++) {
-			data->render_copy(data->ibb, 0,
+			data->render_copy(data->ibb,
 					  &src[i].buf,
 					  WIDTH/4, HEIGHT/4, WIDTH/2-2, HEIGHT/2-2,
 					  dst_compressed ? &dst_ccs : &dst,
@@ -469,13 +469,13 @@ static void test(data_t *data, uint32_t src_tiling, uint32_t dst_tiling,
 		}
 
 		if (dst_compressed)
-			data->render_copy(data->ibb, 0,
+			data->render_copy(data->ibb,
 					  &dst_ccs, 0, 0, WIDTH, HEIGHT,
 					  &dst, 0, 0);
 
 	} else {
 		if (src_compression == I915_COMPRESSION_RENDER) {
-			data->render_copy(data->ibb, 0,
+			data->render_copy(data->ibb,
 					  &src_tiled, 0, 0, WIDTH, HEIGHT,
 					  &src_ccs,
 					  0, 0);
@@ -498,13 +498,13 @@ static void test(data_t *data, uint32_t src_tiling, uint32_t dst_tiling,
 		}
 
 		if (dst_compression == I915_COMPRESSION_RENDER) {
-			data->render_copy(data->ibb, 0,
+			data->render_copy(data->ibb,
 					  src_compressed ? &src_ccs : &src_tiled,
 					  0, 0, WIDTH, HEIGHT,
 					  &dst_ccs,
 					  0, 0);
 
-			data->render_copy(data->ibb, 0,
+			data->render_copy(data->ibb,
 					  &dst_ccs,
 					  0, 0, WIDTH, HEIGHT,
 					  &dst,
@@ -525,7 +525,7 @@ static void test(data_t *data, uint32_t src_tiling, uint32_t dst_tiling,
 					 WIDTH, HEIGHT,
 					 &dst);
 		} else {
-			data->render_copy(data->ibb, 0,
+			data->render_copy(data->ibb,
 					  src_compressed ? &src_ccs : &src_tiled,
 					  0, 0, WIDTH, HEIGHT,
 					  &dst,
diff --git a/tests/i915/gem_render_copy_redux.c b/tests/i915/gem_render_copy_redux.c
index 3f9f926c..8e633567 100644
--- a/tests/i915/gem_render_copy_redux.c
+++ b/tests/i915/gem_render_copy_redux.c
@@ -134,7 +134,7 @@ static void copy(data_t *data)
 	scratch_buf_check(data, &src, WIDTH / 2, HEIGHT / 2, SRC_COLOR);
 	scratch_buf_check(data, &dst, WIDTH / 2, HEIGHT / 2, DST_COLOR);
 
-	data->render_copy(data->ibb, 0,
+	data->render_copy(data->ibb,
 			  &src, 0, 0, WIDTH, HEIGHT,
 			  &dst, WIDTH / 2, HEIGHT / 2);
 
@@ -158,14 +158,14 @@ static void copy_flink(data_t *data)
 	scratch_buf_init(data, &src, WIDTH, HEIGHT, STRIDE, 0);
 	scratch_buf_init(data, &dst, WIDTH, HEIGHT, STRIDE, DST_COLOR);
 
-	data->render_copy(data->ibb, 0,
+	data->render_copy(data->ibb,
 			  &src, 0, 0, WIDTH, HEIGHT,
 			  &dst, WIDTH, HEIGHT);
 
 	scratch_buf_init(&local, &local_src, WIDTH, HEIGHT, STRIDE, 0);
 	scratch_buf_init(&local, &local_dst, WIDTH, HEIGHT, STRIDE, SRC_COLOR);
 
-	local.render_copy(local.ibb, 0,
+	local.render_copy(local.ibb,
 			  &local_src, 0, 0, WIDTH, HEIGHT,
 			  &local_dst, WIDTH, HEIGHT);
 
@@ -173,7 +173,7 @@ static void copy_flink(data_t *data)
 	flink = local_dst;
 	flink.handle = gem_open(data->fd, name);
 
-	data->render_copy(data->ibb, 0,
+	data->render_copy(data->ibb,
 			  &flink, 0, 0, WIDTH, HEIGHT,
 			  &dst, WIDTH / 2, HEIGHT / 2);
 
diff --git a/tests/i915/gem_render_linear_blits.c b/tests/i915/gem_render_linear_blits.c
index 8d044e9e..8e646127 100644
--- a/tests/i915/gem_render_linear_blits.c
+++ b/tests/i915/gem_render_linear_blits.c
@@ -111,7 +111,7 @@ static void run_test (int fd, int count)
 		src = &bufs[i % count];
 		dst = &bufs[(i + 1) % count];
 
-		render_copy(ibb, 0, src, 0, 0, WIDTH, HEIGHT, dst, 0, 0);
+		render_copy(ibb, src, 0, 0, WIDTH, HEIGHT, dst, 0, 0);
 		start_val[(i + 1) % count] = start_val[i % count];
 	}
 
@@ -128,7 +128,7 @@ static void run_test (int fd, int count)
 		src = &bufs[(i + 1) % count];
 		dst = &bufs[i % count];
 
-		render_copy(ibb, 0, src, 0, 0, WIDTH, HEIGHT, dst, 0, 0);
+		render_copy(ibb, src, 0, 0, WIDTH, HEIGHT, dst, 0, 0);
 		start_val[i % count] = start_val[(i + 1) % count];
 	}
 	for (i = 0; i < count; i++)
@@ -146,7 +146,7 @@ static void run_test (int fd, int count)
 		src = &bufs[s];
 		dst = &bufs[d];
 
-		render_copy(ibb, 0, src, 0, 0, WIDTH, HEIGHT, dst, 0, 0);
+		render_copy(ibb, src, 0, 0, WIDTH, HEIGHT, dst, 0, 0);
 		start_val[d] = start_val[s];
 	}
 	for (i = 0; i < count; i++)
diff --git a/tests/i915/gem_render_tiled_blits.c b/tests/i915/gem_render_tiled_blits.c
index 5a92a471..187714d6 100644
--- a/tests/i915/gem_render_tiled_blits.c
+++ b/tests/i915/gem_render_tiled_blits.c
@@ -66,7 +66,7 @@ check_buf(struct intel_bb *ibb, struct intel_buf *buf, uint32_t val)
 	uint32_t *ptr;
 	int i;
 
-	render_copy(ibb, 0, buf, 0, 0, WIDTH, HEIGHT, &linear, 0, 0);
+	render_copy(ibb, buf, 0, 0, WIDTH, HEIGHT, &linear, 0, 0);
 
 	if (snoop) {
 		ptr = gem_mmap__cpu_coherent(i915, linear.handle, 0,
@@ -148,7 +148,7 @@ static void run_test (int fd, int count)
 		int src = i % count;
 		int dst = (i + 1) % count;
 
-		render_copy(ibb, 0, &bufs[src], 0, 0, WIDTH, HEIGHT,
+		render_copy(ibb, &bufs[src], 0, 0, WIDTH, HEIGHT,
 			    &bufs[dst], 0, 0);
 		start_val[dst] = start_val[src];
 	}
@@ -161,7 +161,7 @@ static void run_test (int fd, int count)
 		int src = (i + 1) % count;
 		int dst = i % count;
 
-		render_copy(ibb, 0, &bufs[src], 0, 0, WIDTH, HEIGHT,
+		render_copy(ibb, &bufs[src], 0, 0, WIDTH, HEIGHT,
 			    &bufs[dst], 0, 0);
 		start_val[dst] = start_val[src];
 	}
@@ -176,7 +176,7 @@ static void run_test (int fd, int count)
 		if (src == dst)
 			continue;
 
-		render_copy(ibb, 0, &bufs[src], 0, 0, WIDTH, HEIGHT,
+		render_copy(ibb, &bufs[src], 0, 0, WIDTH, HEIGHT,
 			    &bufs[dst], 0, 0);
 		start_val[dst] = start_val[src];
 	}
diff --git a/tests/i915/gem_stress.c b/tests/i915/gem_stress.c
index 0d513709..3e4d4907 100644
--- a/tests/i915/gem_stress.c
+++ b/tests/i915/gem_stress.c
@@ -377,7 +377,7 @@ static void render_copyfunc(struct intel_buf *src, unsigned src_x, unsigned src_
 		 */
 		intel_bb_flush_blit(ibb);
 
-		rendercopy(ibb, 0, src, src_x, src_y,
+		rendercopy(ibb, src, src_x, src_y,
 		     options.tile_size, options.tile_size,
 		     dst, dst_x, dst_y);
 	} else
diff --git a/tests/i915/perf.c b/tests/i915/perf.c
index 474c3388..a5c4adc3 100644
--- a/tests/i915/perf.c
+++ b/tests/i915/perf.c
@@ -1538,7 +1538,6 @@ static void load_helper_run(enum load load)
 
 		while (!lh.exit) {
 			render_copy(lh.ibb,
-				    lh.context_id,
 				    &lh.src, 0, 0, 1920, 1080,
 				    &lh.dst, 0, 0);
 
@@ -1572,7 +1571,7 @@ static void load_helper_init(void)
 	lh.context_id = gem_context_create(drm_fd);
 	igt_assert_neq(lh.context_id, 0xffffffff);
 
-	lh.ibb = intel_bb_create(drm_fd, BATCH_SZ);
+	lh.ibb = intel_bb_create_with_context(drm_fd, lh.context_id, BATCH_SZ);
 
 	scratch_buf_init(lh.bops, &lh.dst, 1920, 1080, 0);
 	scratch_buf_init(lh.bops, &lh.src, 1920, 1080, 0);
@@ -2915,7 +2914,7 @@ gen12_test_mi_rpc(void)
 	igt_assert_neq(ctx_id, INVALID_CTX_ID);
 	properties[1] = ctx_id;
 
-	ibb = intel_bb_create(drm_fd, BATCH_SZ);
+	ibb = intel_bb_create_with_context(drm_fd, ctx_id, BATCH_SZ);
 	buf = intel_buf_create(bops, 4096, 1, 8, 64,
 			       I915_TILING_NONE, I915_COMPRESSION_NONE);
 
@@ -2931,7 +2930,7 @@ gen12_test_mi_rpc(void)
 			       buf,
 			       REPORT_OFFSET,
 			       REPORT_ID);
-	intel_bb_flush_render_with_context(ibb, ctx_id);
+	intel_bb_flush_render(ibb);
 	intel_bb_sync(ibb);
 
 	intel_buf_cpu_map(buf, false);
@@ -2994,7 +2993,7 @@ test_mi_rpc(void)
 
 	ctx_id = gem_context_create(drm_fd);
 
-	ibb = intel_bb_create(drm_fd, BATCH_SZ);
+	ibb = intel_bb_create_with_context(drm_fd, ctx_id, BATCH_SZ);
 	buf = intel_buf_create(bops, 4096, 1, 8, 64,
 			       I915_TILING_NONE, I915_COMPRESSION_NONE);
 
@@ -3007,7 +3006,7 @@ test_mi_rpc(void)
 			       0, /* dst offset in bytes */
 			       0xdeadbeef); /* report ID */
 
-	intel_bb_flush_render_with_context(ibb, ctx_id);
+	intel_bb_flush_render(ibb);
 	intel_bb_sync(ibb);
 
 	intel_buf_cpu_map(buf, false);
@@ -3119,10 +3118,10 @@ hsw_test_single_ctx_counters(void)
 		 * We currently cache addresses for buffers within
 		 * intel_bb, so use separate batches for different contexts
 		 */
-		ibb0 = intel_bb_create(drm_fd, BATCH_SZ);
-		ibb1 = intel_bb_create(drm_fd, BATCH_SZ);
 		context0_id = gem_context_create(drm_fd);
 		context1_id = gem_context_create(drm_fd);
+		ibb0 = intel_bb_create_with_context(drm_fd, context0_id, BATCH_SZ);
+		ibb1 = intel_bb_create_with_context(drm_fd, context1_id,  BATCH_SZ);
 
 		igt_debug("submitting warm up render_copy\n");
 
@@ -3147,13 +3146,12 @@ hsw_test_single_ctx_counters(void)
 		 * hook callback.
 		 */
 		render_copy(ibb0,
-			    context0_id,
 			    &src[0], 0, 0, width, height,
 			    &dst[0], 0, 0);
 
 		properties[1] = context0_id;
 
-		intel_bb_flush_render_with_context(ibb0, context0_id);
+		intel_bb_flush_render(ibb0);
 		intel_bb_sync(ibb0);
 
 		scratch_buf_memset(&src[0], width, height, 0xff0000ff);
@@ -3181,32 +3179,29 @@ hsw_test_single_ctx_counters(void)
 		 * that the PIPE_CONTROL + MI_RPC commands will be in a
 		 * separate batch from the copy.
 		 */
-		intel_bb_flush_render_with_context(ibb0, context0_id);
+		intel_bb_flush_render(ibb0);
 
 		render_copy(ibb0,
-			    context0_id,
 			    &src[0], 0, 0, width, height,
 			    &dst[0], 0, 0);
 
 		/* Another redundant flush to clarify batch bo is free to reuse */
-		intel_bb_flush_render_with_context(ibb0, context0_id);
+		intel_bb_flush_render(ibb0);
 
 		/* submit two copies on the other context to avoid a false
 		 * positive in case the driver somehow ended up filtering for
 		 * context1
 		 */
 		render_copy(ibb1,
-			    context1_id,
 			    &src[1], 0, 0, width, height,
 			    &dst[1], 0, 0);
 
 		render_copy(ibb1,
-			    context1_id,
 			    &src[2], 0, 0, width, height,
 			    &dst[2], 0, 0);
 
 		/* And another */
-		intel_bb_flush_render_with_context(ibb1, context1_id);
+		intel_bb_flush_render(ibb1);
 
 		emit_stall_timestamp_and_rpc(ibb0,
 					     dst_buf,
@@ -3214,7 +3209,7 @@ hsw_test_single_ctx_counters(void)
 					     256, /* report dst offset */
 					     0xbeefbeef); /* report id */
 
-		intel_bb_flush_render_with_context(ibb0, context0_id);
+		intel_bb_flush_render(ibb0);
 		intel_bb_sync(ibb0);
 
 		intel_buf_cpu_map(dst_buf, false /* write enable */);
@@ -3367,10 +3362,10 @@ gen8_test_single_ctx_render_target_writes_a_counter(void)
 				scratch_buf_init(bops, &dst[i], width, height, 0x00ff00ff);
 			}
 
-			ibb0 = intel_bb_create(drm_fd, BATCH_SZ);
-			ibb1 = intel_bb_create(drm_fd, BATCH_SZ);
 			context0_id = gem_context_create(drm_fd);
 			context1_id = gem_context_create(drm_fd);
+			ibb0 = intel_bb_create_with_context(drm_fd, context0_id, BATCH_SZ);
+			ibb1 = intel_bb_create_with_context(drm_fd, context1_id, BATCH_SZ);
 
 			igt_debug("submitting warm up render_copy\n");
 
@@ -3395,7 +3390,6 @@ gen8_test_single_ctx_render_target_writes_a_counter(void)
 			 * hook callback.
 			 */
 			render_copy(ibb0,
-				    context0_id,
 				    &src[0], 0, 0, width, height,
 				    &dst[0], 0, 0);
 			intel_bb_sync(ibb0);
@@ -3427,32 +3421,29 @@ gen8_test_single_ctx_render_target_writes_a_counter(void)
 			 * that the PIPE_CONTROL + MI_RPC commands will be in a
 			 * separate batch from the copy.
 			 */
-			intel_bb_flush_render_with_context(ibb0, context0_id);
+			intel_bb_flush_render(ibb0);
 
 			render_copy(ibb0,
-				    context0_id,
 				    &src[0], 0, 0, width, height,
 				    &dst[0], 0, 0);
 
 			/* Another redundant flush to clarify batch bo is free to reuse */
-			intel_bb_flush_render_with_context(ibb0, context0_id);
+			intel_bb_flush_render(ibb0);
 
 			/* submit two copies on the other context to avoid a false
 			 * positive in case the driver somehow ended up filtering for
 			 * context1
 			 */
 			render_copy(ibb1,
-				    context1_id,
 				    &src[1], 0, 0, width, height,
 				    &dst[1], 0, 0);
 
 			render_copy(ibb1,
-				    context1_id,
 				    &src[2], 0, 0, width, height,
 				    &dst[2], 0, 0);
 
 			/* And another */
-			intel_bb_flush_render_with_context(ibb1, context1_id);
+			intel_bb_flush_render(ibb1);
 
 			emit_stall_timestamp_and_rpc(ibb1,
 						     dst_buf,
@@ -3460,7 +3451,7 @@ gen8_test_single_ctx_render_target_writes_a_counter(void)
 						     256, /* report dst offset */
 						     0xbeefbeef); /* report id */
 
-			intel_bb_flush_render_with_context(ibb1, context1_id);
+			intel_bb_flush_render(ibb1);
 			intel_bb_sync(ibb1);
 			intel_bb_sync(ibb0);
 
@@ -3774,10 +3765,10 @@ static void gen12_single_ctx_helper(void)
 		scratch_buf_init(bops, &dst[i], width, height, 0x00ff00ff);
 	}
 
-	ibb0 = intel_bb_create(drm_fd, BATCH_SZ);
-	ibb1 = intel_bb_create(drm_fd, BATCH_SZ);
 	context0_id = gem_context_create(drm_fd);
 	context1_id = gem_context_create(drm_fd);
+	ibb0 = intel_bb_create_with_context(drm_fd, context0_id, BATCH_SZ);
+	ibb1 = intel_bb_create_with_context(drm_fd, context1_id, BATCH_SZ);
 
 	igt_debug("submitting warm up render_copy\n");
 
@@ -3801,7 +3792,7 @@ static void gen12_single_ctx_helper(void)
 	 * up pinning the context since there won't ever be a pinning
 	 * hook callback.
 	 */
-	render_copy(ibb0, context0_id,
+	render_copy(ibb0,
 		    &src[0], 0, 0, width, height,
 		    &dst[0], 0, 0);
 
@@ -3830,13 +3821,13 @@ static void gen12_single_ctx_helper(void)
 				     BO_TIMESTAMP_OFFSET0,
 				     BO_REPORT_OFFSET0,
 				     BO_REPORT_ID0);
-	intel_bb_flush_render_with_context(ibb0, context0_id);
+	intel_bb_flush_render(ibb0);
 
 	/* This is the work/context that is measured for counter increments */
-	render_copy(ibb0, context0_id,
+	render_copy(ibb0,
 		    &src[0], 0, 0, width, height,
 		    &dst[0], 0, 0);
-	intel_bb_flush_render_with_context(ibb0, context0_id);
+	intel_bb_flush_render(ibb0);
 
 	/* Submit an mi-rpc to context1 before work
 	 *
@@ -3852,20 +3843,20 @@ static void gen12_single_ctx_helper(void)
 				     BO_TIMESTAMP_OFFSET2,
 				     BO_REPORT_OFFSET2,
 				     BO_REPORT_ID2);
-	intel_bb_flush_render_with_context(ibb1, context1_id);
+	intel_bb_flush_render(ibb1);
 
 	/* Submit two copies on the other context to avoid a false
 	 * positive in case the driver somehow ended up filtering for
 	 * context1
 	 */
-	render_copy(ibb1, context1_id,
+	render_copy(ibb1,
 		    &src[1], 0, 0, width, height,
 		    &dst[1], 0, 0);
 
-	render_copy(ibb1, context1_id,
+	render_copy(ibb1,
 		    &src[2], 0, 0, width, height,
 		    &dst[2], 0, 0);
-	intel_bb_flush_render_with_context(ibb1, context1_id);
+	intel_bb_flush_render(ibb1);
 
 	/* Submit an mi-rpc to context1 after all work */
 #define BO_TIMESTAMP_OFFSET3 1048
@@ -3876,7 +3867,7 @@ static void gen12_single_ctx_helper(void)
 				     BO_TIMESTAMP_OFFSET3,
 				     BO_REPORT_OFFSET3,
 				     BO_REPORT_ID3);
-	intel_bb_flush_render_with_context(ibb1, context1_id);
+	intel_bb_flush_render(ibb1);
 
 	/* Submit an mi-rpc to context0 after all measurable work */
 #define BO_TIMESTAMP_OFFSET1 1032
@@ -3887,7 +3878,7 @@ static void gen12_single_ctx_helper(void)
 				     BO_TIMESTAMP_OFFSET1,
 				     BO_REPORT_OFFSET1,
 				     BO_REPORT_ID1);
-	intel_bb_flush_render_with_context(ibb0, context0_id);
+	intel_bb_flush_render(ibb0);
 	intel_bb_sync(ibb0);
 	intel_bb_sync(ibb1);
 
diff --git a/tests/kms_big_fb.c b/tests/kms_big_fb.c
index 175ffa88..02e9915b 100644
--- a/tests/kms_big_fb.c
+++ b/tests/kms_big_fb.c
@@ -102,7 +102,7 @@ static void copy_pattern(data_t *data,
 	 * rendered with the blitter/render engine.
 	 */
 	if (data->render_copy) {
-		data->render_copy(data->ibb, 0, src, sx, sy, w, h, dst, dx, dy);
+		data->render_copy(data->ibb, src, sx, sy, w, h, dst, dx, dy);
 	} else {
 		w = min(w, src_fb->width - sx);
 		w = min(w, dst_fb->width - dx);
diff --git a/tests/kms_psr.c b/tests/kms_psr.c
index 1448d24d..af81a259 100644
--- a/tests/kms_psr.c
+++ b/tests/kms_psr.c
@@ -203,7 +203,7 @@ static void fill_render(data_t *data, const struct igt_fb *fb,
 			       0, tiling, 0);
 	gem_write(data->drm_fd, src->handle, 0, buf, 4);
 
-	rendercopy(ibb, 0,
+	rendercopy(ibb,
 		   src, 0, 0, 0xff, 0xff,
 		   dst, 0, 0);
 
-- 
2.26.0

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply related	[flat|nested] 9+ messages in thread

* [igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,1/2] lib/intel_batchbuffer: Prepare batch to use in allocator infrastructure
  2020-09-30 12:09 [igt-dev] [PATCH i-g-t 1/2] lib/intel_batchbuffer: Prepare batch to use in allocator infrastructure Zbigniew Kempczyński
  2020-09-30 12:09 ` [igt-dev] [PATCH i-g-t 2/2] lib + tests: Remove possibility to use other than intel_bb context Zbigniew Kempczyński
@ 2020-09-30 13:20 ` Patchwork
  2020-09-30 17:13 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
  2020-10-01  7:19 ` [igt-dev] ✓ Fi.CI.IGT: success " Patchwork
  3 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2020-09-30 13:20 UTC (permalink / raw)
  To: Zbigniew Kempczyński; +Cc: igt-dev


[-- Attachment #1.1: Type: text/plain, Size: 7122 bytes --]

== Series Details ==

Series: series starting with [i-g-t,1/2] lib/intel_batchbuffer: Prepare batch to use in allocator infrastructure
URL   : https://patchwork.freedesktop.org/series/82257/
State : success

== Summary ==

CI Bug Log - changes from IGT_5794 -> IGTPW_5032
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/index.html

Known issues
------------

  Here are the changes found in IGTPW_5032 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_module_load@reload:
    - fi-byt-j1900:       [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/fi-byt-j1900/igt@i915_module_load@reload.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/fi-byt-j1900/igt@i915_module_load@reload.html

  * igt@i915_pm_rpm@module-reload:
    - fi-skl-lmem:        [PASS][3] -> [INCOMPLETE][4] ([i915#151])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - fi-bsw-kefka:       [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) +1 similar issue
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@vgem_basic@unload:
    - fi-skl-guc:         [PASS][7] -> [DMESG-WARN][8] ([i915#2203]) +1 similar issue
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/fi-skl-guc/igt@vgem_basic@unload.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/fi-skl-guc/igt@vgem_basic@unload.html
    - fi-bsw-n3050:       [PASS][9] -> [DMESG-WARN][10] ([i915#2344])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/fi-bsw-n3050/igt@vgem_basic@unload.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/fi-bsw-n3050/igt@vgem_basic@unload.html

  
#### Possible fixes ####

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - fi-byt-j1900:       [DMESG-WARN][11] ([i915#1982]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/fi-byt-j1900/igt@i915_pm_rpm@basic-pci-d3-state.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/fi-byt-j1900/igt@i915_pm_rpm@basic-pci-d3-state.html

  * igt@i915_selftest@live@active:
    - fi-bsw-n3050:       [DMESG-FAIL][13] ([i915#541]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/fi-bsw-n3050/igt@i915_selftest@live@active.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/fi-bsw-n3050/igt@i915_selftest@live@active.html

  * igt@kms_chamelium@dp-crc-fast:
    - fi-kbl-7500u:       [FAIL][15] ([i915#1161] / [i915#262]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - fi-bsw-n3050:       [DMESG-WARN][17] ([i915#1982]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
    - {fi-kbl-7560u}:     [DMESG-WARN][19] ([i915#1982]) -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/fi-kbl-7560u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/fi-kbl-7560u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1:
    - fi-icl-u2:          [DMESG-WARN][21] ([i915#1982]) -> [PASS][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html

  
#### Warnings ####

  * igt@i915_pm_rpm@module-reload:
    - fi-kbl-x1275:       [DMESG-FAIL][23] ([i915#62]) -> [DMESG-FAIL][24] ([i915#62] / [i915#95])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html

  * igt@kms_force_connector_basic@force-edid:
    - fi-kbl-x1275:       [DMESG-WARN][25] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][26] ([i915#62] / [i915#92]) +4 similar issues
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/fi-kbl-x1275/igt@kms_force_connector_basic@force-edid.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/fi-kbl-x1275/igt@kms_force_connector_basic@force-edid.html

  * igt@kms_force_connector_basic@prune-stale-modes:
    - fi-kbl-x1275:       [DMESG-WARN][27] ([i915#62] / [i915#92]) -> [DMESG-WARN][28] ([i915#62] / [i915#92] / [i915#95]) +8 similar issues
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/fi-kbl-x1275/igt@kms_force_connector_basic@prune-stale-modes.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/fi-kbl-x1275/igt@kms_force_connector_basic@prune-stale-modes.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#1161]: https://gitlab.freedesktop.org/drm/intel/issues/1161
  [i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
  [i915#2344]: https://gitlab.freedesktop.org/drm/intel/issues/2344
  [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
  [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
  [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
  [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95


Participating hosts (45 -> 37)
------------------------------

  Missing    (8): fi-ilk-m540 fi-bdw-5557u fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_5794 -> IGTPW_5032

  CI-20190529: 20190529
  CI_DRM_9077: ae1f3f7de609df105aeceed2655656ffc838d720 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_5032: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/index.html
  IGT_5794: eeccb2a17453f90ad92d1ab6f81ad7d344119d72 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/index.html

[-- Attachment #1.2: Type: text/html, Size: 9040 bytes --]

[-- Attachment #2: Type: text/plain, Size: 154 bytes --]

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply	[flat|nested] 9+ messages in thread

* [igt-dev] ✗ Fi.CI.IGT: failure for series starting with [i-g-t,1/2] lib/intel_batchbuffer: Prepare batch to use in allocator infrastructure
  2020-09-30 12:09 [igt-dev] [PATCH i-g-t 1/2] lib/intel_batchbuffer: Prepare batch to use in allocator infrastructure Zbigniew Kempczyński
  2020-09-30 12:09 ` [igt-dev] [PATCH i-g-t 2/2] lib + tests: Remove possibility to use other than intel_bb context Zbigniew Kempczyński
  2020-09-30 13:20 ` [igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,1/2] lib/intel_batchbuffer: Prepare batch to use in allocator infrastructure Patchwork
@ 2020-09-30 17:13 ` Patchwork
  2020-10-01  5:28   ` Zbigniew Kempczyński
  2020-10-01  7:19 ` [igt-dev] ✓ Fi.CI.IGT: success " Patchwork
  3 siblings, 1 reply; 9+ messages in thread
From: Patchwork @ 2020-09-30 17:13 UTC (permalink / raw)
  To: Zbigniew Kempczyński; +Cc: igt-dev


[-- Attachment #1.1: Type: text/plain, Size: 13326 bytes --]

== Series Details ==

Series: series starting with [i-g-t,1/2] lib/intel_batchbuffer: Prepare batch to use in allocator infrastructure
URL   : https://patchwork.freedesktop.org/series/82257/
State : failure

== Summary ==

CI Bug Log - changes from IGT_5794_full -> IGTPW_5032_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_5032_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_5032_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_5032_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-edp1:
    - shard-iclb:         [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-iclb4/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-edp1.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-iclb3/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-edp1.html

  
Known issues
------------

  Here are the changes found in IGTPW_5032_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_eio@kms:
    - shard-snb:          [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-snb6/igt@gem_eio@kms.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-snb2/igt@gem_eio@kms.html

  * igt@gem_exec_reloc@basic-many-active@rcs0:
    - shard-apl:          [PASS][5] -> [FAIL][6] ([i915#1635] / [i915#2389])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-apl1/igt@gem_exec_reloc@basic-many-active@rcs0.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-apl1/igt@gem_exec_reloc@basic-many-active@rcs0.html

  * igt@gem_exec_whisper@basic-queues-priority:
    - shard-glk:          [PASS][7] -> [DMESG-WARN][8] ([i915#118] / [i915#95])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-glk5/igt@gem_exec_whisper@basic-queues-priority.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-glk4/igt@gem_exec_whisper@basic-queues-priority.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-iclb:         [PASS][9] -> [FAIL][10] ([i915#454])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-iclb5/igt@i915_pm_dc@dc6-psr.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-iclb4/igt@i915_pm_dc@dc6-psr.html

  * igt@i915_suspend@debugfs-reader:
    - shard-kbl:          [PASS][11] -> [DMESG-WARN][12] ([i915#180])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-kbl6/igt@i915_suspend@debugfs-reader.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-kbl6/igt@i915_suspend@debugfs-reader.html

  * igt@kms_big_fb@x-tiled-64bpp-rotate-0:
    - shard-iclb:         [PASS][13] -> [DMESG-WARN][14] ([i915#1982])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-iclb1/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-iclb3/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html

  * igt@kms_flip@flip-vs-suspend-interruptible@b-vga1:
    - shard-snb:          [PASS][15] -> [DMESG-WARN][16] ([i915#42])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-snb2/igt@kms_flip@flip-vs-suspend-interruptible@b-vga1.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-snb6/igt@kms_flip@flip-vs-suspend-interruptible@b-vga1.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-onoff:
    - shard-tglb:         [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) +5 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-onoff.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-onoff.html

  * igt@kms_psr@psr2_cursor_blt:
    - shard-iclb:         [PASS][19] -> [SKIP][20] ([fdo#109441]) +2 similar issues
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-iclb6/igt@kms_psr@psr2_cursor_blt.html

  * igt@kms_setmode@basic:
    - shard-apl:          [PASS][21] -> [FAIL][22] ([i915#1635] / [i915#31])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-apl3/igt@kms_setmode@basic.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-apl2/igt@kms_setmode@basic.html

  
#### Possible fixes ####

  * {igt@core_hotunplug@unbind-rebind}:
    - shard-tglb:         [INCOMPLETE][23] ([i915#1602]) -> [PASS][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-tglb2/igt@core_hotunplug@unbind-rebind.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-tglb5/igt@core_hotunplug@unbind-rebind.html
    - shard-iclb:         [INCOMPLETE][25] -> [PASS][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-iclb1/igt@core_hotunplug@unbind-rebind.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-iclb6/igt@core_hotunplug@unbind-rebind.html

  * igt@feature_discovery@psr2:
    - shard-iclb:         [SKIP][27] ([i915#658]) -> [PASS][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-iclb6/igt@feature_discovery@psr2.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-iclb2/igt@feature_discovery@psr2.html

  * igt@gem_exec_nop@basic-parallel:
    - shard-glk:          [DMESG-WARN][29] ([i915#118] / [i915#95]) -> [PASS][30] +1 similar issue
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-glk8/igt@gem_exec_nop@basic-parallel.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-glk3/igt@gem_exec_nop@basic-parallel.html

  * igt@kms_color@pipe-b-legacy-gamma:
    - shard-kbl:          [FAIL][31] ([i915#71]) -> [PASS][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-kbl1/igt@kms_color@pipe-b-legacy-gamma.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-kbl1/igt@kms_color@pipe-b-legacy-gamma.html
    - shard-apl:          [FAIL][33] ([i915#1635] / [i915#71]) -> [PASS][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-apl8/igt@kms_color@pipe-b-legacy-gamma.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-apl6/igt@kms_color@pipe-b-legacy-gamma.html

  * igt@kms_cursor_crc@pipe-c-cursor-64x64-onscreen:
    - shard-kbl:          [DMESG-WARN][35] ([i915#78]) -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-kbl2/igt@kms_cursor_crc@pipe-c-cursor-64x64-onscreen.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-kbl2/igt@kms_cursor_crc@pipe-c-cursor-64x64-onscreen.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
    - shard-kbl:          [DMESG-WARN][37] ([i915#180]) -> [PASS][38] +4 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-kbl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html

  * igt@kms_flip@modeset-vs-vblank-race@a-hdmi-a1:
    - shard-glk:          [FAIL][39] ([i915#407]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-glk5/igt@kms_flip@modeset-vs-vblank-race@a-hdmi-a1.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-glk7/igt@kms_flip@modeset-vs-vblank-race@a-hdmi-a1.html

  * igt@kms_frontbuffer_tracking@fbc-stridechange:
    - shard-tglb:         [DMESG-WARN][41] ([i915#1982]) -> [PASS][42] +1 similar issue
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-tglb2/igt@kms_frontbuffer_tracking@fbc-stridechange.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-tglb6/igt@kms_frontbuffer_tracking@fbc-stridechange.html
    - shard-glk:          [DMESG-WARN][43] ([i915#1982]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-glk7/igt@kms_frontbuffer_tracking@fbc-stridechange.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-glk3/igt@kms_frontbuffer_tracking@fbc-stridechange.html

  * igt@kms_psr@psr2_cursor_plane_move:
    - shard-iclb:         [SKIP][45] ([fdo#109441]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-iclb7/igt@kms_psr@psr2_cursor_plane_move.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html

  * igt@kms_setmode@basic:
    - shard-glk:          [FAIL][47] ([i915#31]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-glk5/igt@kms_setmode@basic.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-glk5/igt@kms_setmode@basic.html

  * igt@perf_pmu@busy-hang@vecs0:
    - shard-iclb:         [DMESG-WARN][49] ([i915#1982]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-iclb2/igt@perf_pmu@busy-hang@vecs0.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-iclb7/igt@perf_pmu@busy-hang@vecs0.html

  * igt@sysfs_heartbeat_interval@mixed@bcs0:
    - shard-kbl:          [INCOMPLETE][51] ([i915#1731]) -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-kbl4/igt@sysfs_heartbeat_interval@mixed@bcs0.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-kbl7/igt@sysfs_heartbeat_interval@mixed@bcs0.html

  
#### Warnings ####

  * igt@i915_pm_dc@dc3co-vpb-simulation:
    - shard-tglb:         [DMESG-WARN][53] ([i915#2411]) -> [SKIP][54] ([i915#1904])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-tglb6/igt@i915_pm_dc@dc3co-vpb-simulation.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-tglb6/igt@i915_pm_dc@dc3co-vpb-simulation.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-apl:          [TIMEOUT][55] ([i915#1319] / [i915#1635] / [i915#1958]) -> [FAIL][56] ([fdo#110321] / [fdo#110336] / [i915#1635])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-apl2/igt@kms_content_protection@atomic-dpms.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-apl3/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_frontbuffer_tracking@psr-suspend:
    - shard-tglb:         [DMESG-WARN][57] ([i915#2411]) -> [DMESG-WARN][58] ([i915#1982] / [i915#2411])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-tglb1/igt@kms_frontbuffer_tracking@psr-suspend.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-tglb2/igt@kms_frontbuffer_tracking@psr-suspend.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321
  [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336
  [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
  [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
  [i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
  [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
  [i915#1731]: https://gitlab.freedesktop.org/drm/intel/issues/1731
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1904]: https://gitlab.freedesktop.org/drm/intel/issues/1904
  [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389
  [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
  [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
  [i915#407]: https://gitlab.freedesktop.org/drm/intel/issues/407
  [i915#42]: https://gitlab.freedesktop.org/drm/intel/issues/42
  [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#71]: https://gitlab.freedesktop.org/drm/intel/issues/71
  [i915#78]: https://gitlab.freedesktop.org/drm/intel/issues/78
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95


Participating hosts (8 -> 8)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_5794 -> IGTPW_5032

  CI-20190529: 20190529
  CI_DRM_9077: ae1f3f7de609df105aeceed2655656ffc838d720 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_5032: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/index.html
  IGT_5794: eeccb2a17453f90ad92d1ab6f81ad7d344119d72 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/index.html

[-- Attachment #1.2: Type: text/html, Size: 15840 bytes --]

[-- Attachment #2: Type: text/plain, Size: 154 bytes --]

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [igt-dev] ✗ Fi.CI.IGT: failure for series starting with [i-g-t,1/2] lib/intel_batchbuffer: Prepare batch to use in allocator infrastructure
  2020-09-30 17:13 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
@ 2020-10-01  5:28   ` Zbigniew Kempczyński
  2020-10-01  6:48     ` Petri Latvala
  0 siblings, 1 reply; 9+ messages in thread
From: Zbigniew Kempczyński @ 2020-10-01  5:28 UTC (permalink / raw)
  To: igt-dev

On Wed, Sep 30, 2020 at 05:13:00PM +0000, Patchwork wrote:
>    Patch Details
> 
>    Series:  series starting with [i-g-t,1/2] lib/intel_batchbuffer: Prepare   
>             batch to use in allocator infrastructure                          
>    URL:     https://patchwork.freedesktop.org/series/82257/                   
>    State:   failure                                                           
>    Details: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/index.html    
> 
>            CI Bug Log - changes from IGT_5794_full -> IGTPW_5032_full
> 
> Summary
> 
>    FAILURE
> 
>    Serious unknown changes coming with IGTPW_5032_full absolutely need to be
>    verified manually.
> 
>    If you think the reported changes have nothing to do with the changes
>    introduced in IGTPW_5032_full, please notify your bug team to allow them
>    to document this new failure mode, which will reduce false positives in
>    CI.
> 
>    External URL:
>    https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/index.html
> 
> Possible new issues
> 
>    Here are the unknown changes that may have been introduced in
>    IGTPW_5032_full:
> 
>   IGT changes
> 
>     Possible regressions
> 
>      * igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-edp1:
>           * shard-iclb: PASS -> INCOMPLETE

Series don't touch above and it is unrelated to above.

--
Zbigniew

> 
> Known issues
> 
>    Here are the changes found in IGTPW_5032_full that come from known issues:
> 
>   IGT changes
> 
>     Issues hit
> 
>      * igt@gem_eio@kms:
> 
>           * shard-snb: PASS -> DMESG-WARN (i915#1982)
>      * igt@gem_exec_reloc@basic-many-active@rcs0:
> 
>           * shard-apl: PASS -> FAIL (i915#1635 / i915#2389)
>      * igt@gem_exec_whisper@basic-queues-priority:
> 
>           * shard-glk: PASS -> DMESG-WARN (i915#118 / i915#95)
>      * igt@i915_pm_dc@dc6-psr:
> 
>           * shard-iclb: PASS -> FAIL (i915#454)
>      * igt@i915_suspend@debugfs-reader:
> 
>           * shard-kbl: PASS -> DMESG-WARN (i915#180)
>      * igt@kms_big_fb@x-tiled-64bpp-rotate-0:
> 
>           * shard-iclb: PASS -> DMESG-WARN (i915#1982)
>      * igt@kms_flip@flip-vs-suspend-interruptible@b-vga1:
> 
>           * shard-snb: PASS -> DMESG-WARN (i915#42)
>      * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-onoff:
> 
>           * shard-tglb: PASS -> DMESG-WARN (i915#1982) +5 similar issues
>      * igt@kms_psr@psr2_cursor_blt:
> 
>           * shard-iclb: PASS -> SKIP (fdo#109441) +2 similar issues
>      * igt@kms_setmode@basic:
> 
>           * shard-apl: PASS -> FAIL (i915#1635 / i915#31)
> 
>     Possible fixes
> 
>      * {igt@core_hotunplug@unbind-rebind}:
> 
>           * shard-tglb: INCOMPLETE (i915#1602) -> PASS
> 
>           * shard-iclb: INCOMPLETE -> PASS
> 
>      * igt@feature_discovery@psr2:
> 
>           * shard-iclb: SKIP (i915#658) -> PASS
>      * igt@gem_exec_nop@basic-parallel:
> 
>           * shard-glk: DMESG-WARN (i915#118 / i915#95) -> PASS +1 similar
>             issue
>      * igt@kms_color@pipe-b-legacy-gamma:
> 
>           * shard-kbl: FAIL (i915#71) -> PASS
> 
>           * shard-apl: FAIL (i915#1635 / i915#71) -> PASS
> 
>      * igt@kms_cursor_crc@pipe-c-cursor-64x64-onscreen:
> 
>           * shard-kbl: DMESG-WARN (i915#78) -> PASS
>      * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
> 
>           * shard-kbl: DMESG-WARN (i915#180) -> PASS +4 similar issues
>      * igt@kms_flip@modeset-vs-vblank-race@a-hdmi-a1:
> 
>           * shard-glk: FAIL (i915#407) -> PASS
>      * igt@kms_frontbuffer_tracking@fbc-stridechange:
> 
>           * shard-tglb: DMESG-WARN (i915#1982) -> PASS +1 similar issue
> 
>           * shard-glk: DMESG-WARN (i915#1982) -> PASS
> 
>      * igt@kms_psr@psr2_cursor_plane_move:
> 
>           * shard-iclb: SKIP (fdo#109441) -> PASS
>      * igt@kms_setmode@basic:
> 
>           * shard-glk: FAIL (i915#31) -> PASS
>      * igt@perf_pmu@busy-hang@vecs0:
> 
>           * shard-iclb: DMESG-WARN (i915#1982) -> PASS
>      * igt@sysfs_heartbeat_interval@mixed@bcs0:
> 
>           * shard-kbl: INCOMPLETE (i915#1731) -> PASS
> 
>     Warnings
> 
>      * igt@i915_pm_dc@dc3co-vpb-simulation:
> 
>           * shard-tglb: DMESG-WARN (i915#2411) -> SKIP (i915#1904)
>      * igt@kms_content_protection@atomic-dpms:
> 
>           * shard-apl: TIMEOUT (i915#1319 / i915#1635 / i915#1958) -> FAIL
>             (fdo#110321 / fdo#110336 / i915#1635)
>      * igt@kms_frontbuffer_tracking@psr-suspend:
> 
>           * shard-tglb: DMESG-WARN (i915#2411) -> DMESG-WARN (i915#1982 /
>             i915#2411)
> 
>    {name}: This element is suppressed. This means it is ignored when
>    computing
>    the status of the difference (SUCCESS, WARNING, or FAILURE).
> 
> Participating hosts (8 -> 8)
> 
>    No changes in participating hosts
> 
> Build changes
> 
>      * CI: CI-20190529 -> None
>      * IGT: IGT_5794 -> IGTPW_5032
> 
>    CI-20190529: 20190529
>    CI_DRM_9077: ae1f3f7de609df105aeceed2655656ffc838d720 @
>    git://anongit.freedesktop.org/gfx-ci/linux
>    IGTPW_5032: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/index.html
>    IGT_5794: eeccb2a17453f90ad92d1ab6f81ad7d344119d72 @
>    git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [igt-dev] ✗ Fi.CI.IGT: failure for series starting with [i-g-t,1/2] lib/intel_batchbuffer: Prepare batch to use in allocator infrastructure
  2020-10-01  5:28   ` Zbigniew Kempczyński
@ 2020-10-01  6:48     ` Petri Latvala
  2020-10-01  7:20       ` Vudum, Lakshminarayana
  0 siblings, 1 reply; 9+ messages in thread
From: Petri Latvala @ 2020-10-01  6:48 UTC (permalink / raw)
  To: Zbigniew Kempczyński, Lakshminarayana Vudum; +Cc: igt-dev

On Thu, Oct 01, 2020 at 07:28:24AM +0200, Zbigniew Kempczyński wrote:
> On Wed, Sep 30, 2020 at 05:13:00PM +0000, Patchwork wrote:
> >    Patch Details
> > 
> >    Series:  series starting with [i-g-t,1/2] lib/intel_batchbuffer: Prepare   
> >             batch to use in allocator infrastructure                          
> >    URL:     https://patchwork.freedesktop.org/series/82257/                   
> >    State:   failure                                                           
> >    Details: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/index.html    
> > 
> >            CI Bug Log - changes from IGT_5794_full -> IGTPW_5032_full
> > 
> > Summary
> > 
> >    FAILURE
> > 
> >    Serious unknown changes coming with IGTPW_5032_full absolutely need to be
> >    verified manually.
> > 
> >    If you think the reported changes have nothing to do with the changes
> >    introduced in IGTPW_5032_full, please notify your bug team to allow them
> >    to document this new failure mode, which will reduce false positives in
> >    CI.
> > 
> >    External URL:
> >    https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/index.html
> > 
> > Possible new issues
> > 
> >    Here are the unknown changes that may have been introduced in
> >    IGTPW_5032_full:
> > 
> >   IGT changes
> > 
> >     Possible regressions
> > 
> >      * igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-edp1:
> >           * shard-iclb: PASS -> INCOMPLETE
> 
> Series don't touch above and it is unrelated to above.

Yep. One for you, Lakshmi.


-- 
Petri Latvala



> 
> --
> Zbigniew
> 
> > 
> > Known issues
> > 
> >    Here are the changes found in IGTPW_5032_full that come from known issues:
> > 
> >   IGT changes
> > 
> >     Issues hit
> > 
> >      * igt@gem_eio@kms:
> > 
> >           * shard-snb: PASS -> DMESG-WARN (i915#1982)
> >      * igt@gem_exec_reloc@basic-many-active@rcs0:
> > 
> >           * shard-apl: PASS -> FAIL (i915#1635 / i915#2389)
> >      * igt@gem_exec_whisper@basic-queues-priority:
> > 
> >           * shard-glk: PASS -> DMESG-WARN (i915#118 / i915#95)
> >      * igt@i915_pm_dc@dc6-psr:
> > 
> >           * shard-iclb: PASS -> FAIL (i915#454)
> >      * igt@i915_suspend@debugfs-reader:
> > 
> >           * shard-kbl: PASS -> DMESG-WARN (i915#180)
> >      * igt@kms_big_fb@x-tiled-64bpp-rotate-0:
> > 
> >           * shard-iclb: PASS -> DMESG-WARN (i915#1982)
> >      * igt@kms_flip@flip-vs-suspend-interruptible@b-vga1:
> > 
> >           * shard-snb: PASS -> DMESG-WARN (i915#42)
> >      * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-onoff:
> > 
> >           * shard-tglb: PASS -> DMESG-WARN (i915#1982) +5 similar issues
> >      * igt@kms_psr@psr2_cursor_blt:
> > 
> >           * shard-iclb: PASS -> SKIP (fdo#109441) +2 similar issues
> >      * igt@kms_setmode@basic:
> > 
> >           * shard-apl: PASS -> FAIL (i915#1635 / i915#31)
> > 
> >     Possible fixes
> > 
> >      * {igt@core_hotunplug@unbind-rebind}:
> > 
> >           * shard-tglb: INCOMPLETE (i915#1602) -> PASS
> > 
> >           * shard-iclb: INCOMPLETE -> PASS
> > 
> >      * igt@feature_discovery@psr2:
> > 
> >           * shard-iclb: SKIP (i915#658) -> PASS
> >      * igt@gem_exec_nop@basic-parallel:
> > 
> >           * shard-glk: DMESG-WARN (i915#118 / i915#95) -> PASS +1 similar
> >             issue
> >      * igt@kms_color@pipe-b-legacy-gamma:
> > 
> >           * shard-kbl: FAIL (i915#71) -> PASS
> > 
> >           * shard-apl: FAIL (i915#1635 / i915#71) -> PASS
> > 
> >      * igt@kms_cursor_crc@pipe-c-cursor-64x64-onscreen:
> > 
> >           * shard-kbl: DMESG-WARN (i915#78) -> PASS
> >      * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
> > 
> >           * shard-kbl: DMESG-WARN (i915#180) -> PASS +4 similar issues
> >      * igt@kms_flip@modeset-vs-vblank-race@a-hdmi-a1:
> > 
> >           * shard-glk: FAIL (i915#407) -> PASS
> >      * igt@kms_frontbuffer_tracking@fbc-stridechange:
> > 
> >           * shard-tglb: DMESG-WARN (i915#1982) -> PASS +1 similar issue
> > 
> >           * shard-glk: DMESG-WARN (i915#1982) -> PASS
> > 
> >      * igt@kms_psr@psr2_cursor_plane_move:
> > 
> >           * shard-iclb: SKIP (fdo#109441) -> PASS
> >      * igt@kms_setmode@basic:
> > 
> >           * shard-glk: FAIL (i915#31) -> PASS
> >      * igt@perf_pmu@busy-hang@vecs0:
> > 
> >           * shard-iclb: DMESG-WARN (i915#1982) -> PASS
> >      * igt@sysfs_heartbeat_interval@mixed@bcs0:
> > 
> >           * shard-kbl: INCOMPLETE (i915#1731) -> PASS
> > 
> >     Warnings
> > 
> >      * igt@i915_pm_dc@dc3co-vpb-simulation:
> > 
> >           * shard-tglb: DMESG-WARN (i915#2411) -> SKIP (i915#1904)
> >      * igt@kms_content_protection@atomic-dpms:
> > 
> >           * shard-apl: TIMEOUT (i915#1319 / i915#1635 / i915#1958) -> FAIL
> >             (fdo#110321 / fdo#110336 / i915#1635)
> >      * igt@kms_frontbuffer_tracking@psr-suspend:
> > 
> >           * shard-tglb: DMESG-WARN (i915#2411) -> DMESG-WARN (i915#1982 /
> >             i915#2411)
> > 
> >    {name}: This element is suppressed. This means it is ignored when
> >    computing
> >    the status of the difference (SUCCESS, WARNING, or FAILURE).
> > 
> > Participating hosts (8 -> 8)
> > 
> >    No changes in participating hosts
> > 
> > Build changes
> > 
> >      * CI: CI-20190529 -> None
> >      * IGT: IGT_5794 -> IGTPW_5032
> > 
> >    CI-20190529: 20190529
> >    CI_DRM_9077: ae1f3f7de609df105aeceed2655656ffc838d720 @
> >    git://anongit.freedesktop.org/gfx-ci/linux
> >    IGTPW_5032: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/index.html
> >    IGT_5794: eeccb2a17453f90ad92d1ab6f81ad7d344119d72 @
> >    git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply	[flat|nested] 9+ messages in thread

* [igt-dev] ✓ Fi.CI.IGT: success for series starting with [i-g-t,1/2] lib/intel_batchbuffer: Prepare batch to use in allocator infrastructure
  2020-09-30 12:09 [igt-dev] [PATCH i-g-t 1/2] lib/intel_batchbuffer: Prepare batch to use in allocator infrastructure Zbigniew Kempczyński
                   ` (2 preceding siblings ...)
  2020-09-30 17:13 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
@ 2020-10-01  7:19 ` Patchwork
  3 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2020-10-01  7:19 UTC (permalink / raw)
  To: Zbigniew Kempczyński; +Cc: igt-dev


[-- Attachment #1.1: Type: text/plain, Size: 12928 bytes --]

== Series Details ==

Series: series starting with [i-g-t,1/2] lib/intel_batchbuffer: Prepare batch to use in allocator infrastructure
URL   : https://patchwork.freedesktop.org/series/82257/
State : success

== Summary ==

CI Bug Log - changes from IGT_5794_full -> IGTPW_5032_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/index.html

Known issues
------------

  Here are the changes found in IGTPW_5032_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_eio@kms:
    - shard-snb:          [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-snb6/igt@gem_eio@kms.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-snb2/igt@gem_eio@kms.html

  * igt@gem_exec_reloc@basic-many-active@rcs0:
    - shard-apl:          [PASS][3] -> [FAIL][4] ([i915#1635] / [i915#2389])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-apl1/igt@gem_exec_reloc@basic-many-active@rcs0.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-apl1/igt@gem_exec_reloc@basic-many-active@rcs0.html

  * igt@gem_exec_whisper@basic-queues-priority:
    - shard-glk:          [PASS][5] -> [DMESG-WARN][6] ([i915#118] / [i915#95])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-glk5/igt@gem_exec_whisper@basic-queues-priority.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-glk4/igt@gem_exec_whisper@basic-queues-priority.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-iclb:         [PASS][7] -> [FAIL][8] ([i915#454])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-iclb5/igt@i915_pm_dc@dc6-psr.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-iclb4/igt@i915_pm_dc@dc6-psr.html

  * igt@i915_suspend@debugfs-reader:
    - shard-kbl:          [PASS][9] -> [DMESG-WARN][10] ([i915#180])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-kbl6/igt@i915_suspend@debugfs-reader.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-kbl6/igt@i915_suspend@debugfs-reader.html

  * igt@kms_big_fb@x-tiled-64bpp-rotate-0:
    - shard-iclb:         [PASS][11] -> [DMESG-WARN][12] ([i915#1982])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-iclb1/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-iclb3/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-edp1:
    - shard-iclb:         [PASS][13] -> [INCOMPLETE][14] ([i915#1211])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-iclb4/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-edp1.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-iclb3/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-edp1.html

  * igt@kms_flip@flip-vs-suspend-interruptible@b-vga1:
    - shard-snb:          [PASS][15] -> [DMESG-WARN][16] ([i915#42])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-snb2/igt@kms_flip@flip-vs-suspend-interruptible@b-vga1.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-snb6/igt@kms_flip@flip-vs-suspend-interruptible@b-vga1.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-onoff:
    - shard-tglb:         [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) +5 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-onoff.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-onoff.html

  * igt@kms_psr@psr2_cursor_blt:
    - shard-iclb:         [PASS][19] -> [SKIP][20] ([fdo#109441]) +2 similar issues
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-iclb6/igt@kms_psr@psr2_cursor_blt.html

  * igt@kms_setmode@basic:
    - shard-apl:          [PASS][21] -> [FAIL][22] ([i915#1635] / [i915#31])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-apl3/igt@kms_setmode@basic.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-apl2/igt@kms_setmode@basic.html

  
#### Possible fixes ####

  * {igt@core_hotunplug@unbind-rebind}:
    - shard-tglb:         [INCOMPLETE][23] ([i915#1602]) -> [PASS][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-tglb2/igt@core_hotunplug@unbind-rebind.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-tglb5/igt@core_hotunplug@unbind-rebind.html
    - shard-iclb:         [INCOMPLETE][25] -> [PASS][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-iclb1/igt@core_hotunplug@unbind-rebind.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-iclb6/igt@core_hotunplug@unbind-rebind.html

  * igt@feature_discovery@psr2:
    - shard-iclb:         [SKIP][27] ([i915#658]) -> [PASS][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-iclb6/igt@feature_discovery@psr2.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-iclb2/igt@feature_discovery@psr2.html

  * igt@gem_exec_nop@basic-parallel:
    - shard-glk:          [DMESG-WARN][29] ([i915#118] / [i915#95]) -> [PASS][30] +1 similar issue
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-glk8/igt@gem_exec_nop@basic-parallel.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-glk3/igt@gem_exec_nop@basic-parallel.html

  * igt@kms_color@pipe-b-legacy-gamma:
    - shard-kbl:          [FAIL][31] ([i915#71]) -> [PASS][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-kbl1/igt@kms_color@pipe-b-legacy-gamma.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-kbl1/igt@kms_color@pipe-b-legacy-gamma.html
    - shard-apl:          [FAIL][33] ([i915#1635] / [i915#71]) -> [PASS][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-apl8/igt@kms_color@pipe-b-legacy-gamma.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-apl6/igt@kms_color@pipe-b-legacy-gamma.html

  * igt@kms_cursor_crc@pipe-c-cursor-64x64-onscreen:
    - shard-kbl:          [DMESG-WARN][35] ([i915#78]) -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-kbl2/igt@kms_cursor_crc@pipe-c-cursor-64x64-onscreen.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-kbl2/igt@kms_cursor_crc@pipe-c-cursor-64x64-onscreen.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
    - shard-kbl:          [DMESG-WARN][37] ([i915#180]) -> [PASS][38] +4 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-kbl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html

  * igt@kms_flip@modeset-vs-vblank-race@a-hdmi-a1:
    - shard-glk:          [FAIL][39] ([i915#407]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-glk5/igt@kms_flip@modeset-vs-vblank-race@a-hdmi-a1.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-glk7/igt@kms_flip@modeset-vs-vblank-race@a-hdmi-a1.html

  * igt@kms_frontbuffer_tracking@fbc-stridechange:
    - shard-tglb:         [DMESG-WARN][41] ([i915#1982]) -> [PASS][42] +1 similar issue
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-tglb2/igt@kms_frontbuffer_tracking@fbc-stridechange.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-tglb6/igt@kms_frontbuffer_tracking@fbc-stridechange.html
    - shard-glk:          [DMESG-WARN][43] ([i915#1982]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-glk7/igt@kms_frontbuffer_tracking@fbc-stridechange.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-glk3/igt@kms_frontbuffer_tracking@fbc-stridechange.html

  * igt@kms_psr@psr2_cursor_plane_move:
    - shard-iclb:         [SKIP][45] ([fdo#109441]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-iclb7/igt@kms_psr@psr2_cursor_plane_move.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html

  * igt@kms_setmode@basic:
    - shard-glk:          [FAIL][47] ([i915#31]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-glk5/igt@kms_setmode@basic.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-glk5/igt@kms_setmode@basic.html

  * igt@perf_pmu@busy-hang@vecs0:
    - shard-iclb:         [DMESG-WARN][49] ([i915#1982]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-iclb2/igt@perf_pmu@busy-hang@vecs0.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-iclb7/igt@perf_pmu@busy-hang@vecs0.html

  * igt@sysfs_heartbeat_interval@mixed@bcs0:
    - shard-kbl:          [INCOMPLETE][51] ([i915#1731]) -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-kbl4/igt@sysfs_heartbeat_interval@mixed@bcs0.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-kbl7/igt@sysfs_heartbeat_interval@mixed@bcs0.html

  
#### Warnings ####

  * igt@i915_pm_dc@dc3co-vpb-simulation:
    - shard-tglb:         [DMESG-WARN][53] ([i915#2411]) -> [SKIP][54] ([i915#1904])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-tglb6/igt@i915_pm_dc@dc3co-vpb-simulation.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-tglb6/igt@i915_pm_dc@dc3co-vpb-simulation.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-apl:          [TIMEOUT][55] ([i915#1319] / [i915#1635] / [i915#1958]) -> [FAIL][56] ([fdo#110321] / [fdo#110336] / [i915#1635])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-apl2/igt@kms_content_protection@atomic-dpms.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-apl3/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_frontbuffer_tracking@psr-suspend:
    - shard-tglb:         [DMESG-WARN][57] ([i915#2411]) -> [DMESG-WARN][58] ([i915#1982] / [i915#2411])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5794/shard-tglb1/igt@kms_frontbuffer_tracking@psr-suspend.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/shard-tglb2/igt@kms_frontbuffer_tracking@psr-suspend.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321
  [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336
  [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
  [i915#1211]: https://gitlab.freedesktop.org/drm/intel/issues/1211
  [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
  [i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
  [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
  [i915#1731]: https://gitlab.freedesktop.org/drm/intel/issues/1731
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1904]: https://gitlab.freedesktop.org/drm/intel/issues/1904
  [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389
  [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
  [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
  [i915#407]: https://gitlab.freedesktop.org/drm/intel/issues/407
  [i915#42]: https://gitlab.freedesktop.org/drm/intel/issues/42
  [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#71]: https://gitlab.freedesktop.org/drm/intel/issues/71
  [i915#78]: https://gitlab.freedesktop.org/drm/intel/issues/78
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95


Participating hosts (8 -> 8)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_5794 -> IGTPW_5032

  CI-20190529: 20190529
  CI_DRM_9077: ae1f3f7de609df105aeceed2655656ffc838d720 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_5032: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/index.html
  IGT_5794: eeccb2a17453f90ad92d1ab6f81ad7d344119d72 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/index.html

[-- Attachment #1.2: Type: text/html, Size: 15430 bytes --]

[-- Attachment #2: Type: text/plain, Size: 154 bytes --]

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [igt-dev] ✗ Fi.CI.IGT: failure for series starting with [i-g-t,1/2] lib/intel_batchbuffer: Prepare batch to use in allocator infrastructure
  2020-10-01  6:48     ` Petri Latvala
@ 2020-10-01  7:20       ` Vudum, Lakshminarayana
  0 siblings, 0 replies; 9+ messages in thread
From: Vudum, Lakshminarayana @ 2020-10-01  7:20 UTC (permalink / raw)
  To: Latvala, Petri, Kempczynski, Zbigniew; +Cc: igt-dev

Re-reported.

-----Original Message-----
From: Petri Latvala <petri.latvala@intel.com> 
Sent: Wednesday, September 30, 2020 11:49 PM
To: Kempczynski, Zbigniew <zbigniew.kempczynski@intel.com>; Vudum, Lakshminarayana <lakshminarayana.vudum@intel.com>
Cc: igt-dev@lists.freedesktop.org
Subject: Re: [igt-dev] ✗ Fi.CI.IGT: failure for series starting with [i-g-t,1/2] lib/intel_batchbuffer: Prepare batch to use in allocator infrastructure

On Thu, Oct 01, 2020 at 07:28:24AM +0200, Zbigniew Kempczyński wrote:
> On Wed, Sep 30, 2020 at 05:13:00PM +0000, Patchwork wrote:
> >    Patch Details
> > 
> >    Series:  series starting with [i-g-t,1/2] lib/intel_batchbuffer: Prepare   
> >             batch to use in allocator infrastructure                          
> >    URL:     https://patchwork.freedesktop.org/series/82257/                   
> >    State:   failure                                                           
> >    Details: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/index.html    
> > 
> >            CI Bug Log - changes from IGT_5794_full -> IGTPW_5032_full
> > 
> > Summary
> > 
> >    FAILURE
> > 
> >    Serious unknown changes coming with IGTPW_5032_full absolutely need to be
> >    verified manually.
> > 
> >    If you think the reported changes have nothing to do with the changes
> >    introduced in IGTPW_5032_full, please notify your bug team to allow them
> >    to document this new failure mode, which will reduce false positives in
> >    CI.
> > 
> >    External URL:
> >    https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/index.html
> > 
> > Possible new issues
> > 
> >    Here are the unknown changes that may have been introduced in
> >    IGTPW_5032_full:
> > 
> >   IGT changes
> > 
> >     Possible regressions
> > 
> >      * igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-edp1:
> >           * shard-iclb: PASS -> INCOMPLETE
> 
> Series don't touch above and it is unrelated to above.

Yep. One for you, Lakshmi.


-- 
Petri Latvala



> 
> --
> Zbigniew
> 
> > 
> > Known issues
> > 
> >    Here are the changes found in IGTPW_5032_full that come from known issues:
> > 
> >   IGT changes
> > 
> >     Issues hit
> > 
> >      * igt@gem_eio@kms:
> > 
> >           * shard-snb: PASS -> DMESG-WARN (i915#1982)
> >      * igt@gem_exec_reloc@basic-many-active@rcs0:
> > 
> >           * shard-apl: PASS -> FAIL (i915#1635 / i915#2389)
> >      * igt@gem_exec_whisper@basic-queues-priority:
> > 
> >           * shard-glk: PASS -> DMESG-WARN (i915#118 / i915#95)
> >      * igt@i915_pm_dc@dc6-psr:
> > 
> >           * shard-iclb: PASS -> FAIL (i915#454)
> >      * igt@i915_suspend@debugfs-reader:
> > 
> >           * shard-kbl: PASS -> DMESG-WARN (i915#180)
> >      * igt@kms_big_fb@x-tiled-64bpp-rotate-0:
> > 
> >           * shard-iclb: PASS -> DMESG-WARN (i915#1982)
> >      * igt@kms_flip@flip-vs-suspend-interruptible@b-vga1:
> > 
> >           * shard-snb: PASS -> DMESG-WARN (i915#42)
> >      * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-onoff:
> > 
> >           * shard-tglb: PASS -> DMESG-WARN (i915#1982) +5 similar issues
> >      * igt@kms_psr@psr2_cursor_blt:
> > 
> >           * shard-iclb: PASS -> SKIP (fdo#109441) +2 similar issues
> >      * igt@kms_setmode@basic:
> > 
> >           * shard-apl: PASS -> FAIL (i915#1635 / i915#31)
> > 
> >     Possible fixes
> > 
> >      * {igt@core_hotunplug@unbind-rebind}:
> > 
> >           * shard-tglb: INCOMPLETE (i915#1602) -> PASS
> > 
> >           * shard-iclb: INCOMPLETE -> PASS
> > 
> >      * igt@feature_discovery@psr2:
> > 
> >           * shard-iclb: SKIP (i915#658) -> PASS
> >      * igt@gem_exec_nop@basic-parallel:
> > 
> >           * shard-glk: DMESG-WARN (i915#118 / i915#95) -> PASS +1 similar
> >             issue
> >      * igt@kms_color@pipe-b-legacy-gamma:
> > 
> >           * shard-kbl: FAIL (i915#71) -> PASS
> > 
> >           * shard-apl: FAIL (i915#1635 / i915#71) -> PASS
> > 
> >      * igt@kms_cursor_crc@pipe-c-cursor-64x64-onscreen:
> > 
> >           * shard-kbl: DMESG-WARN (i915#78) -> PASS
> >      * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
> > 
> >           * shard-kbl: DMESG-WARN (i915#180) -> PASS +4 similar issues
> >      * igt@kms_flip@modeset-vs-vblank-race@a-hdmi-a1:
> > 
> >           * shard-glk: FAIL (i915#407) -> PASS
> >      * igt@kms_frontbuffer_tracking@fbc-stridechange:
> > 
> >           * shard-tglb: DMESG-WARN (i915#1982) -> PASS +1 similar issue
> > 
> >           * shard-glk: DMESG-WARN (i915#1982) -> PASS
> > 
> >      * igt@kms_psr@psr2_cursor_plane_move:
> > 
> >           * shard-iclb: SKIP (fdo#109441) -> PASS
> >      * igt@kms_setmode@basic:
> > 
> >           * shard-glk: FAIL (i915#31) -> PASS
> >      * igt@perf_pmu@busy-hang@vecs0:
> > 
> >           * shard-iclb: DMESG-WARN (i915#1982) -> PASS
> >      * igt@sysfs_heartbeat_interval@mixed@bcs0:
> > 
> >           * shard-kbl: INCOMPLETE (i915#1731) -> PASS
> > 
> >     Warnings
> > 
> >      * igt@i915_pm_dc@dc3co-vpb-simulation:
> > 
> >           * shard-tglb: DMESG-WARN (i915#2411) -> SKIP (i915#1904)
> >      * igt@kms_content_protection@atomic-dpms:
> > 
> >           * shard-apl: TIMEOUT (i915#1319 / i915#1635 / i915#1958) -> FAIL
> >             (fdo#110321 / fdo#110336 / i915#1635)
> >      * igt@kms_frontbuffer_tracking@psr-suspend:
> > 
> >           * shard-tglb: DMESG-WARN (i915#2411) -> DMESG-WARN (i915#1982 /
> >             i915#2411)
> > 
> >    {name}: This element is suppressed. This means it is ignored when
> >    computing
> >    the status of the difference (SUCCESS, WARNING, or FAILURE).
> > 
> > Participating hosts (8 -> 8)
> > 
> >    No changes in participating hosts
> > 
> > Build changes
> > 
> >      * CI: CI-20190529 -> None
> >      * IGT: IGT_5794 -> IGTPW_5032
> > 
> >    CI-20190529: 20190529
> >    CI_DRM_9077: ae1f3f7de609df105aeceed2655656ffc838d720 @
> >    git://anongit.freedesktop.org/gfx-ci/linux
> >    IGTPW_5032: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5032/index.html
> >    IGT_5794: eeccb2a17453f90ad92d1ab6f81ad7d344119d72 @
> >    git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply	[flat|nested] 9+ messages in thread

* [igt-dev] [PATCH i-g-t 1/2] lib/intel_batchbuffer: Prepare batch to use in allocator infrastructure
@ 2020-09-30 10:38 Zbigniew Kempczyński
  0 siblings, 0 replies; 9+ messages in thread
From: Zbigniew Kempczyński @ 2020-09-30 10:38 UTC (permalink / raw)
  To: igt-dev; +Cc: Chris Wilson

With upcoming of allocator code we need to ensure batch will execute
with appropriate context. If not mismatch between allocator data
and batch could lead to strange or wrong results. All functions which
could change context in execbuf called from intel_bb were removed.

As an allocator requires size (which was not previously required in
intel_bb) adding object to intel_bb is now mandatory.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 lib/intel_batchbuffer.c | 205 ++++++++++++++++++++--------------------
 lib/intel_batchbuffer.h |  18 ++--
 2 files changed, 110 insertions(+), 113 deletions(-)

diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index be764646..60dbfe26 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -1220,7 +1220,10 @@ static uint64_t gen8_canonical_addr(uint64_t address)
 	return (int64_t)(address << shift) >> shift;
 }
 
-static inline uint64_t __intel_bb_propose_offset(struct intel_bb *ibb)
+static inline uint64_t __intel_bb_get_offset(struct intel_bb *ibb,
+					     uint32_t handle,
+					     uint32_t size,
+					     uint32_t alignment)
 {
 	uint64_t offset;
 
@@ -1247,7 +1250,7 @@ static inline uint64_t __intel_bb_propose_offset(struct intel_bb *ibb)
  * Pointer the intel_bb, asserts on failure.
  */
 static struct intel_bb *
-__intel_bb_create(int i915, uint32_t size, bool do_relocs)
+__intel_bb_create(int i915, uint32_t ctx, uint32_t size, bool do_relocs)
 {
 	struct intel_bb *ibb = calloc(1, sizeof(*ibb));
 	uint64_t gtt_size;
@@ -1261,6 +1264,7 @@ __intel_bb_create(int i915, uint32_t size, bool do_relocs)
 	ibb->handle = gem_create(i915, size);
 	ibb->size = size;
 	ibb->alignment = 4096;
+	ibb->ctx = ctx;
 	ibb->batch = calloc(1, size);
 	igt_assert(ibb->batch);
 	ibb->ptr = ibb->batch;
@@ -1287,8 +1291,12 @@ __intel_bb_create(int i915, uint32_t size, bool do_relocs)
 	}
 	ibb->gtt_size = gtt_size;
 
-	ibb->batch_offset = __intel_bb_propose_offset(ibb);
-	intel_bb_add_object(ibb, ibb->handle, ibb->batch_offset, false);
+	ibb->batch_offset = __intel_bb_get_offset(ibb,
+						  ibb->handle,
+						  ibb->size,
+						  ibb->alignment);
+	intel_bb_add_object(ibb, ibb->handle, ibb->size,
+			    ibb->batch_offset, false);
 
 	ibb->refcount = 1;
 
@@ -1300,13 +1308,33 @@ __intel_bb_create(int i915, uint32_t size, bool do_relocs)
  * @i915: drm fd
  * @size: size of the batchbuffer
  *
+ * Creates bb with default context.
+ *
  * Returns:
  *
  * Pointer the intel_bb, asserts on failure.
  */
 struct intel_bb *intel_bb_create(int i915, uint32_t size)
 {
-	return __intel_bb_create(i915, size, false);
+	return __intel_bb_create(i915, 0, size, false);
+}
+
+/**
+ * intel_bb_create_with_context:
+ * @i915: drm fd
+ * @ctx: context
+ * @size: size of the batchbuffer
+ *
+ * Creates bb with context passed in @ctx.
+ *
+ * Returns:
+ *
+ * Pointer the intel_bb, asserts on failure.
+ */
+struct intel_bb *
+intel_bb_create_with_context(int i915, uint32_t ctx, uint32_t size)
+{
+	return __intel_bb_create(i915, ctx, size, false);
 }
 
 /**
@@ -1314,8 +1342,8 @@ struct intel_bb *intel_bb_create(int i915, uint32_t size)
  * @i915: drm fd
  * @size: size of the batchbuffer
  *
- * Disable passing or randomizing addresses. This will lead to relocations
- * when objects are not previously pinned.
+ * Creates bb which will disable passing addresses.
+ * This will lead to relocations when objects are not previously pinned.
  *
  * Returns:
  *
@@ -1323,7 +1351,26 @@ struct intel_bb *intel_bb_create(int i915, uint32_t size)
  */
 struct intel_bb *intel_bb_create_with_relocs(int i915, uint32_t size)
 {
-	return __intel_bb_create(i915, size, true);
+	return __intel_bb_create(i915, 0, size, true);
+}
+
+/**
+ * intel_bb_create_with_relocs_and_context:
+ * @i915: drm fd
+ * @ctx: context
+ * @size: size of the batchbuffer
+ *
+ * Creates bb with default context which will disable passing addresses.
+ * This will lead to relocations when objects are not previously pinned.
+ *
+ * Returns:
+ *
+ * Pointer the intel_bb, asserts on failure.
+ */
+struct intel_bb *
+intel_bb_create_with_relocs_and_context(int i915, uint32_t ctx, uint32_t size)
+{
+	return __intel_bb_create(i915, ctx, size, true);
 }
 
 static void __intel_bb_destroy_relocations(struct intel_bb *ibb)
@@ -1418,19 +1465,26 @@ void intel_bb_reset(struct intel_bb *ibb, bool purge_objects_cache)
 
 	if (purge_objects_cache) {
 		__intel_bb_destroy_cache(ibb);
-		ibb->batch_offset = __intel_bb_propose_offset(ibb);
+		ibb->batch_offset = __intel_bb_get_offset(ibb,
+							  ibb->handle,
+							  ibb->size,
+							  ibb->alignment);
 	} else {
 		struct drm_i915_gem_exec_object2 *object;
 
 		object = intel_bb_find_object(ibb, ibb->handle);
 		ibb->batch_offset = object ? object->offset :
-					     __intel_bb_propose_offset(ibb);
+					     __intel_bb_get_offset(ibb,
+								   ibb->handle,
+								   ibb->size,
+								   ibb->alignment);
 	}
 
 	gem_close(ibb->i915, ibb->handle);
 	ibb->handle = gem_create(ibb->i915, ibb->size);
 
-	intel_bb_add_object(ibb, ibb->handle, ibb->batch_offset, false);
+	intel_bb_add_object(ibb, ibb->handle, ibb->size,
+			    ibb->batch_offset, false);
 	ibb->ptr = ibb->batch;
 	memset(ibb->batch, 0, ibb->size);
 }
@@ -1580,6 +1634,7 @@ static void __add_to_objects(struct intel_bb *ibb,
  * intel_bb_add_object:
  * @ibb: pointer to intel_bb
  * @handle: which handle to add to objects array
+ * @size: object size
  * @offset: presumed offset of the object when no relocation is enforced
  * @write: does a handle is a render target
  *
@@ -1588,7 +1643,7 @@ static void __add_to_objects(struct intel_bb *ibb,
  * be marked with EXEC_OBJECT_WRITE flag.
  */
 struct drm_i915_gem_exec_object2 *
-intel_bb_add_object(struct intel_bb *ibb, uint32_t handle,
+intel_bb_add_object(struct intel_bb *ibb, uint32_t handle, uint32_t size,
 		    uint64_t offset, bool write)
 {
 	struct drm_i915_gem_exec_object2 *object;
@@ -1602,7 +1657,9 @@ intel_bb_add_object(struct intel_bb *ibb, uint32_t handle,
 		object->offset = gen8_canonical_addr(offset & (ibb->gtt_size - 1));
 
 	if (object->offset == INTEL_BUF_INVALID_ADDRESS)
-		object->offset = __intel_bb_propose_offset(ibb);
+		object->offset = __intel_bb_get_offset(ibb,
+						       handle, size,
+						       object->alignment);
 
 	if (write)
 		object->flags |= EXEC_OBJECT_WRITE;
@@ -1618,7 +1675,9 @@ intel_bb_add_intel_buf(struct intel_bb *ibb, struct intel_buf *buf, bool write)
 {
 	struct drm_i915_gem_exec_object2 *obj;
 
-	obj = intel_bb_add_object(ibb, buf->handle, buf->addr.offset, write);
+	obj = intel_bb_add_object(ibb, buf->handle,
+				  intel_buf_bo_size(buf),
+				  buf->addr.offset, write);
 
 	/* For compressed surfaces ensure address is aligned to 64KB */
 	if (ibb->gen >= 12 && buf->compression) {
@@ -1720,7 +1779,13 @@ static uint64_t intel_bb_add_reloc(struct intel_bb *ibb,
 	struct drm_i915_gem_exec_object2 *object, *to_object;
 	uint32_t i;
 
-	object = intel_bb_add_object(ibb, handle, presumed_offset, false);
+	if (ibb->enforce_relocs) {
+		object = intel_bb_add_object(ibb, handle, 0,
+					     presumed_offset, false);
+	} else {
+		object = intel_bb_find_object(ibb, handle);
+		igt_assert(object);
+	}
 
 	/* For ibb we have relocs allocated in chunks */
 	if (to_handle == ibb->handle) {
@@ -2030,7 +2095,6 @@ static void update_offsets(struct intel_bb *ibb,
  * @ibb: pointer to intel_bb
  * @end_offset: offset of the last instruction in the bb
  * @flags: flags passed directly to execbuf
- * @ctx: context
  * @sync: if true wait for execbuf completion, otherwise caller is responsible
  * to wait for completion
  *
@@ -2039,8 +2103,8 @@ static void update_offsets(struct intel_bb *ibb,
  * Note: In this step execobj for bb is allocated and inserted to the objects
  * array.
 */
-int __intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
-		    uint32_t ctx, uint64_t flags, bool sync)
+static int __intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
+			   uint64_t flags, bool sync)
 {
 	struct drm_i915_gem_execbuffer2 execbuf;
 	struct drm_i915_gem_exec_object2 *objects;
@@ -2057,7 +2121,7 @@ int __intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
 	execbuf.buffers_ptr = (uintptr_t) objects;
 	execbuf.buffer_count = ibb->num_objects;
 	execbuf.batch_len = end_offset;
-	execbuf.rsvd1 = ibb->ctx = ctx;
+	execbuf.rsvd1 = ibb->ctx;
 	execbuf.flags = flags | I915_EXEC_BATCH_FIRST | I915_EXEC_FENCE_OUT;
 	if (ibb->enforce_relocs)
 		execbuf.flags &= ~I915_EXEC_NO_RELOC;
@@ -2112,29 +2176,12 @@ int __intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
  * @sync: if true wait for execbuf completion, otherwise caller is responsible
  * to wait for completion
  *
- * Do execbuf with default context. Asserts on failure.
+ * Do execbuf on context selected during bb creation. Asserts on failure.
 */
 void intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
 		   uint64_t flags, bool sync)
 {
-	igt_assert_eq(__intel_bb_exec(ibb, end_offset, 0, flags, sync), 0);
-}
-
-/*
- * intel_bb_exec_with_context:
- * @ibb: pointer to intel_bb
- * @end_offset: offset of the last instruction in the bb
- * @flags: flags passed directly to execbuf
- * @ctx: context
- * @sync: if true wait for execbuf completion, otherwise caller is responsible
- * to wait for completion
- *
- * Do execbuf with context @context.
-*/
-void intel_bb_exec_with_context(struct intel_bb *ibb, uint32_t end_offset,
-				uint32_t ctx, uint64_t flags, bool sync)
-{
-	igt_assert_eq(__intel_bb_exec(ibb, end_offset, ctx, flags, sync), 0);
+	igt_assert_eq(__intel_bb_exec(ibb, end_offset, flags, sync), 0);
 }
 
 /**
@@ -2185,7 +2232,7 @@ bool intel_bb_object_offset_to_buf(struct intel_bb *ibb, struct intel_buf *buf)
 	found = tfind((void *)&object, &ibb->root, __compare_objects);
 	if (!found) {
 		buf->addr.offset = 0;
-		buf->addr.ctx = 0;
+		buf->addr.ctx = ibb->ctx;
 
 		return false;
 	}
@@ -2242,41 +2289,27 @@ uint32_t intel_bb_emit_flush_common(struct intel_bb *ibb)
 	return intel_bb_offset(ibb);
 }
 
-static void intel_bb_exec_with_context_ring(struct intel_bb *ibb,
-					    uint32_t ctx, uint32_t ring)
+static void intel_bb_exec_with_ring(struct intel_bb *ibb,uint32_t ring)
 {
-	intel_bb_exec_with_context(ibb, intel_bb_offset(ibb), ctx,
-				   ring | I915_EXEC_NO_RELOC,
-				   false);
+	intel_bb_exec(ibb, intel_bb_offset(ibb),
+		      ring | I915_EXEC_NO_RELOC, false);
 	intel_bb_reset(ibb, false);
 }
 
 /*
  * intel_bb_flush:
  * @ibb: batchbuffer
- * @ctx: context
  * @ring: ring
  *
- * If batch is not empty emit batch buffer end, execute on specified
- * context, ring then reset the batch.
+ * If batch is not empty emit batch buffer end, execute on ring,
+ * then reset the batch.
  */
-void intel_bb_flush(struct intel_bb *ibb, uint32_t ctx, uint32_t ring)
+void intel_bb_flush(struct intel_bb *ibb, uint32_t ring)
 {
 	if (intel_bb_emit_flush_common(ibb) == 0)
 		return;
 
-	intel_bb_exec_with_context_ring(ibb, ctx, ring);
-}
-
-static void __intel_bb_flush_render_with_context(struct intel_bb *ibb,
-						 uint32_t ctx)
-{
-	uint32_t ring = I915_EXEC_RENDER;
-
-	if (intel_bb_emit_flush_common(ibb) == 0)
-		return;
-
-	intel_bb_exec_with_context_ring(ibb, ctx, ring);
+	intel_bb_exec_with_ring(ibb, ring);
 }
 
 /*
@@ -2284,39 +2317,14 @@ static void __intel_bb_flush_render_with_context(struct intel_bb *ibb,
  * @ibb: batchbuffer
  *
  * If batch is not empty emit batch buffer end, execute on render ring
- * and reset the batch.
- * Context used to execute is previous batch context.
+ * and reset the batch. Context used to execute is batch context.
  */
 void intel_bb_flush_render(struct intel_bb *ibb)
 {
-	__intel_bb_flush_render_with_context(ibb, ibb->ctx);
-}
-
-/*
- * intel_bb_flush_render_with_context:
- * @ibb: batchbuffer
- * @ctx: context
- *
- * If batch is not empty emit batch buffer end, execute on render ring with @ctx
- * and reset the batch.
- */
-void intel_bb_flush_render_with_context(struct intel_bb *ibb, uint32_t ctx)
-{
-	__intel_bb_flush_render_with_context(ibb, ctx);
-}
-
-static void __intel_bb_flush_blit_with_context(struct intel_bb *ibb,
-					       uint32_t ctx)
-{
-	uint32_t ring = I915_EXEC_DEFAULT;
-
 	if (intel_bb_emit_flush_common(ibb) == 0)
 		return;
 
-	if (HAS_BLT_RING(ibb->devid))
-		ring = I915_EXEC_BLT;
-
-	intel_bb_exec_with_context_ring(ibb, ctx, ring);
+	intel_bb_exec_with_ring(ibb, I915_EXEC_RENDER);
 }
 
 /*
@@ -2325,24 +2333,19 @@ static void __intel_bb_flush_blit_with_context(struct intel_bb *ibb,
  *
  * If batch is not empty emit batch buffer end, execute on default/blit ring
  * (depends on gen) and reset the batch.
- * Context used to execute is previous batch context.
+ * Context used to execute is batch context.
  */
 void intel_bb_flush_blit(struct intel_bb *ibb)
 {
-	__intel_bb_flush_blit_with_context(ibb, ibb->ctx);
-}
+	uint32_t ring = I915_EXEC_DEFAULT;
 
-/*
- * intel_bb_flush_blit_with_context:
- * @ibb: batchbuffer
- * @ctx: context
- *
- * If batch is not empty emit batch buffer end, execute on default/blit ring
- * (depends on gen) with @ctx and reset the batch.
- */
-void intel_bb_flush_blit_with_context(struct intel_bb *ibb, uint32_t ctx)
-{
-	__intel_bb_flush_blit_with_context(ibb, ctx);
+	if (intel_bb_emit_flush_common(ibb) == 0)
+		return;
+
+	if (HAS_BLT_RING(ibb->devid))
+		ring = I915_EXEC_BLT;
+
+	intel_bb_exec_with_ring(ibb, ring);
 }
 
 /*
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index 8b9c1ed9..d20b4e66 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -341,7 +341,6 @@ struct intel_bb;
 struct intel_buf;
 
 typedef void (*igt_render_copyfunc_t)(struct intel_bb *ibb,
-				      uint32_t ctx,
 				      struct intel_buf *src,
 				      uint32_t src_x, uint32_t src_y,
 				      uint32_t width, uint32_t height,
@@ -478,7 +477,11 @@ struct intel_bb {
 };
 
 struct intel_bb *intel_bb_create(int i915, uint32_t size);
+struct intel_bb *
+intel_bb_create_with_context(int i915, uint32_t ctx, uint32_t size);
 struct intel_bb *intel_bb_create_with_relocs(int i915, uint32_t size);
+struct intel_bb *
+intel_bb_create_with_relocs_and_context(int i915, uint32_t ctx, uint32_t size);
 void intel_bb_destroy(struct intel_bb *ibb);
 
 static inline void intel_bb_ref(struct intel_bb *ibb)
@@ -562,9 +565,8 @@ static inline void intel_bb_out(struct intel_bb *ibb, uint32_t dword)
 	igt_assert(intel_bb_offset(ibb) <= ibb->size);
 }
 
-
 struct drm_i915_gem_exec_object2 *
-intel_bb_add_object(struct intel_bb *ibb, uint32_t handle,
+intel_bb_add_object(struct intel_bb *ibb, uint32_t handle, uint32_t size,
 		    uint64_t offset, bool write);
 struct drm_i915_gem_exec_object2 *
 intel_bb_add_intel_buf(struct intel_bb *ibb, struct intel_buf *buf, bool write);
@@ -615,25 +617,17 @@ uint64_t intel_bb_offset_reloc_to_object(struct intel_bb *ibb,
 					 uint32_t offset,
 					 uint64_t presumed_offset);
 
-int __intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
-		    uint32_t ctx, uint64_t flags, bool sync);
-
 void intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
 		   uint64_t flags, bool sync);
 
-void intel_bb_exec_with_context(struct intel_bb *ibb, uint32_t end_offset,
-				uint32_t ctx, uint64_t flags, bool sync);
-
 uint64_t intel_bb_get_object_offset(struct intel_bb *ibb, uint32_t handle);
 bool intel_bb_object_offset_to_buf(struct intel_bb *ibb, struct intel_buf *buf);
 
 uint32_t intel_bb_emit_bbe(struct intel_bb *ibb);
 uint32_t intel_bb_emit_flush_common(struct intel_bb *ibb);
-void intel_bb_flush(struct intel_bb *ibb, uint32_t ctx, uint32_t ring);
+void intel_bb_flush(struct intel_bb *ibb, uint32_t ring);
 void intel_bb_flush_render(struct intel_bb *ibb);
-void intel_bb_flush_render_with_context(struct intel_bb *ibb, uint32_t ctx);
 void intel_bb_flush_blit(struct intel_bb *ibb);
-void intel_bb_flush_blit_with_context(struct intel_bb *ibb, uint32_t ctx);
 
 uint32_t intel_bb_copy_data(struct intel_bb *ibb,
 			    const void *data, unsigned int bytes,
-- 
2.26.0

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^ permalink raw reply related	[flat|nested] 9+ messages in thread

end of thread, other threads:[~2020-10-01  7:20 UTC | newest]

Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-09-30 12:09 [igt-dev] [PATCH i-g-t 1/2] lib/intel_batchbuffer: Prepare batch to use in allocator infrastructure Zbigniew Kempczyński
2020-09-30 12:09 ` [igt-dev] [PATCH i-g-t 2/2] lib + tests: Remove possibility to use other than intel_bb context Zbigniew Kempczyński
2020-09-30 13:20 ` [igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,1/2] lib/intel_batchbuffer: Prepare batch to use in allocator infrastructure Patchwork
2020-09-30 17:13 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
2020-10-01  5:28   ` Zbigniew Kempczyński
2020-10-01  6:48     ` Petri Latvala
2020-10-01  7:20       ` Vudum, Lakshminarayana
2020-10-01  7:19 ` [igt-dev] ✓ Fi.CI.IGT: success " Patchwork
  -- strict thread matches above, loose matches on Subject: below --
2020-09-30 10:38 [igt-dev] [PATCH i-g-t 1/2] " Zbigniew Kempczyński

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