* [Intel-gfx] [PATCH v2 0/3] Gen12 forcewake and multicast updates
@ 2020-10-09 19:44 Matt Roper
2020-10-09 19:44 ` [Intel-gfx] [PATCH v2 1/3] drm/i915: Rename FORCEWAKE_BLITTER to FORCEWAKE_GT Matt Roper
` (6 more replies)
0 siblings, 7 replies; 11+ messages in thread
From: Matt Roper @ 2020-10-09 19:44 UTC (permalink / raw)
To: intel-gfx
The hardware architects have finally provided an updated MMIO table for
gen12 platforms (TGL, RKL, DG1). We should update our driver's
forcewake and MCR programming accordingly.
v2:
- Include a rename of FORCEWAKE_BLITTER to FORCEWAKE_GT
- Add comments to aggregated forcewake ranges showing the sub-ranges
that we've combined. (Jose)
Bspec: 66696
Cc: Caz Yokoyama <caz.yokoyama@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Matt Roper (3):
drm/i915: Rename FORCEWAKE_BLITTER to FORCEWAKE_GT
drm/i915: Update gen12 forcewake table
drm/i915: Update gen12 multicast register ranges
drivers/gpu/drm/i915/gt/intel_workarounds.c | 28 ++-
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 6 +-
drivers/gpu/drm/i915/gvt/handlers.c | 8 +-
drivers/gpu/drm/i915/gvt/reg.h | 4 +-
drivers/gpu/drm/i915/i915_reg.h | 4 +-
drivers/gpu/drm/i915/intel_uncore.c | 203 +++++++++++++-------
drivers/gpu/drm/i915/intel_uncore.h | 4 +-
7 files changed, 171 insertions(+), 86 deletions(-)
--
2.24.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread* [Intel-gfx] [PATCH v2 1/3] drm/i915: Rename FORCEWAKE_BLITTER to FORCEWAKE_GT 2020-10-09 19:44 [Intel-gfx] [PATCH v2 0/3] Gen12 forcewake and multicast updates Matt Roper @ 2020-10-09 19:44 ` Matt Roper 2020-10-09 22:09 ` Souza, Jose 2020-10-09 19:44 ` [Intel-gfx] [PATCH v2 2/3] drm/i915: Update gen12 forcewake table Matt Roper ` (5 subsequent siblings) 6 siblings, 1 reply; 11+ messages in thread From: Matt Roper @ 2020-10-09 19:44 UTC (permalink / raw) To: intel-gfx The power well that we've been referring to as the 'blitter' well is actually more of a general GT power well which contains a lot of things other than the blitter engine registers. The FORCEWAKE_BLITTER name in the code was used for historic reasons, but no longer matches how the bspec describes this power well and just causes confusion for people not familiar with this area of the code. Let's rename it to FORCEWAKE_GT to more accurately describe the roll of the power well and match how the modern bspec refers to it. v2: - Add a comment noting that the GT power well includes the blitter engine. (Jose) Bspec: 66696, 66534, 67609 Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> --- drivers/gpu/drm/i915/gt/uc/intel_guc.c | 6 +- drivers/gpu/drm/i915/gvt/handlers.c | 8 +- drivers/gpu/drm/i915/gvt/reg.h | 4 +- drivers/gpu/drm/i915/i915_reg.h | 4 +- drivers/gpu/drm/i915/intel_uncore.c | 100 ++++++++++++------------- drivers/gpu/drm/i915/intel_uncore.h | 4 +- 6 files changed, 63 insertions(+), 63 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c index 942c7c187adb..e4aaa5f29796 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c @@ -312,18 +312,18 @@ void intel_guc_write_params(struct intel_guc *guc) int i; /* - * All SOFT_SCRATCH registers are in FORCEWAKE_BLITTER domain and + * All SOFT_SCRATCH registers are in FORCEWAKE_GT domain and * they are power context saved so it's ok to release forcewake * when we are done here and take it again at xfer time. */ - intel_uncore_forcewake_get(uncore, FORCEWAKE_BLITTER); + intel_uncore_forcewake_get(uncore, FORCEWAKE_GT); intel_uncore_write(uncore, SOFT_SCRATCH(0), 0); for (i = 0; i < GUC_CTL_MAX_DWORDS; i++) intel_uncore_write(uncore, SOFT_SCRATCH(1 + i), guc->params[i]); - intel_uncore_forcewake_put(uncore, FORCEWAKE_BLITTER); + intel_uncore_forcewake_put(uncore, FORCEWAKE_GT); } int intel_guc_init(struct intel_guc *guc) diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 3be37e6fe33d..e0edc9d1f357 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -290,8 +290,8 @@ static int mul_force_wake_write(struct intel_vgpu *vgpu, case FORCEWAKE_RENDER_GEN9_REG: ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG; break; - case FORCEWAKE_BLITTER_GEN9_REG: - ack_reg_offset = FORCEWAKE_ACK_BLITTER_GEN9_REG; + case FORCEWAKE_GT_GEN9_REG: + ack_reg_offset = FORCEWAKE_ACK_GT_GEN9_REG; break; case FORCEWAKE_MEDIA_GEN9_REG: ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG; @@ -2901,8 +2901,8 @@ static int init_skl_mmio_info(struct intel_gvt *gvt) MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL); - MMIO_DH(FORCEWAKE_BLITTER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); - MMIO_DH(FORCEWAKE_ACK_BLITTER_GEN9, D_SKL_PLUS, NULL, NULL); + MMIO_DH(FORCEWAKE_GT_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); + MMIO_DH(FORCEWAKE_ACK_GT_GEN9, D_SKL_PLUS, NULL, NULL); MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL); diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h index b88e033cbed4..b58860dee970 100644 --- a/drivers/gpu/drm/i915/gvt/reg.h +++ b/drivers/gpu/drm/i915/gvt/reg.h @@ -101,8 +101,8 @@ #define FORCEWAKE_RENDER_GEN9_REG 0xa278 #define FORCEWAKE_ACK_RENDER_GEN9_REG 0x0D84 -#define FORCEWAKE_BLITTER_GEN9_REG 0xa188 -#define FORCEWAKE_ACK_BLITTER_GEN9_REG 0x130044 +#define FORCEWAKE_GT_GEN9_REG 0xa188 +#define FORCEWAKE_ACK_GT_GEN9_REG 0x130044 #define FORCEWAKE_MEDIA_GEN9_REG 0xa270 #define FORCEWAKE_ACK_MEDIA_GEN9_REG 0x0D88 #define FORCEWAKE_ACK_HSW_REG 0x130044 diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 6ad9ee4243a0..04c966a524ce 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8958,12 +8958,12 @@ enum { #define FORCEWAKE_MEDIA_VDBOX_GEN11(n) _MMIO(0xa540 + (n) * 4) #define FORCEWAKE_MEDIA_VEBOX_GEN11(n) _MMIO(0xa560 + (n) * 4) #define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278) -#define FORCEWAKE_BLITTER_GEN9 _MMIO(0xa188) +#define FORCEWAKE_GT_GEN9 _MMIO(0xa188) #define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0x0D88) #define FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n) _MMIO(0x0D50 + (n) * 4) #define FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n) _MMIO(0x0D70 + (n) * 4) #define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0x0D84) -#define FORCEWAKE_ACK_BLITTER_GEN9 _MMIO(0x130044) +#define FORCEWAKE_ACK_GT_GEN9 _MMIO(0x130044) #define FORCEWAKE_KERNEL BIT(0) #define FORCEWAKE_USER BIT(1) #define FORCEWAKE_KERNEL_FALLBACK BIT(15) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 54e201fdeba4..ede3a5393d51 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -1051,37 +1051,37 @@ static const struct intel_forcewake_range __chv_fw_ranges[] = { /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */ static const struct intel_forcewake_range __gen9_fw_ranges[] = { - GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_GT), GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */ GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER), - GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT), GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER), - GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT), GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), - GEN_FW_RANGE(0x8000, 0x812f, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0x8000, 0x812f, FORCEWAKE_GT), GEN_FW_RANGE(0x8130, 0x813f, FORCEWAKE_MEDIA), GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER), - GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_GT), GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), - GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_GT), GEN_FW_RANGE(0x8800, 0x89ff, FORCEWAKE_MEDIA), - GEN_FW_RANGE(0x8a00, 0x8bff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0x8a00, 0x8bff, FORCEWAKE_GT), GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER), - GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_GT), GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), - GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_GT), GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER), - GEN_FW_RANGE(0xb480, 0xcfff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0xb480, 0xcfff, FORCEWAKE_GT), GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA), - GEN_FW_RANGE(0xd800, 0xdfff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0xd800, 0xdfff, FORCEWAKE_GT), GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER), - GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_GT), GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA), - GEN_FW_RANGE(0x14000, 0x19fff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0x14000, 0x19fff, FORCEWAKE_GT), GEN_FW_RANGE(0x1a000, 0x1e9ff, FORCEWAKE_MEDIA), - GEN_FW_RANGE(0x1ea00, 0x243ff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0x1ea00, 0x243ff, FORCEWAKE_GT), GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER), - GEN_FW_RANGE(0x24800, 0x2ffff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0x24800, 0x2ffff, FORCEWAKE_GT), GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA), }; @@ -1089,33 +1089,33 @@ static const struct intel_forcewake_range __gen9_fw_ranges[] = { static const struct intel_forcewake_range __gen11_fw_ranges[] = { GEN_FW_RANGE(0x0, 0x1fff, 0), /* uncore range */ GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER), - GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT), GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER), - GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT), GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), - GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT), GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER), - GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_GT), GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), - GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_GT), GEN_FW_RANGE(0x8800, 0x8bff, 0), GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER), - GEN_FW_RANGE(0x8d00, 0x94cf, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0x8d00, 0x94cf, FORCEWAKE_GT), GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER), GEN_FW_RANGE(0x9560, 0x95ff, 0), - GEN_FW_RANGE(0x9600, 0xafff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0x9600, 0xafff, FORCEWAKE_GT), GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER), - GEN_FW_RANGE(0xb480, 0xdeff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0xb480, 0xdeff, FORCEWAKE_GT), GEN_FW_RANGE(0xdf00, 0xe8ff, FORCEWAKE_RENDER), - GEN_FW_RANGE(0xe900, 0x16dff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0xe900, 0x16dff, FORCEWAKE_GT), GEN_FW_RANGE(0x16e00, 0x19fff, FORCEWAKE_RENDER), - GEN_FW_RANGE(0x1a000, 0x23fff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0x1a000, 0x23fff, FORCEWAKE_GT), GEN_FW_RANGE(0x24000, 0x2407f, 0), - GEN_FW_RANGE(0x24080, 0x2417f, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0x24080, 0x2417f, FORCEWAKE_GT), GEN_FW_RANGE(0x24180, 0x242ff, FORCEWAKE_RENDER), - GEN_FW_RANGE(0x24300, 0x243ff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0x24300, 0x243ff, FORCEWAKE_GT), GEN_FW_RANGE(0x24400, 0x24fff, FORCEWAKE_RENDER), - GEN_FW_RANGE(0x25000, 0x3ffff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0x25000, 0x3ffff, FORCEWAKE_GT), GEN_FW_RANGE(0x40000, 0x1bffff, 0), GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), GEN_FW_RANGE(0x1c4000, 0x1c7fff, 0), @@ -1126,39 +1126,39 @@ static const struct intel_forcewake_range __gen11_fw_ranges[] = { /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */ static const struct intel_forcewake_range __gen12_fw_ranges[] = { - GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_GT), GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */ GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER), - GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT), GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER), - GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT), GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), - GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT), GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER), - GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_GT), GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), - GEN_FW_RANGE(0x8500, 0x8bff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0x8500, 0x8bff, FORCEWAKE_GT), GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER), - GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_GT), GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_ALL), - GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_GT), GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER), - GEN_FW_RANGE(0xb480, 0xdfff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0xb480, 0xdfff, FORCEWAKE_GT), GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER), - GEN_FW_RANGE(0xe900, 0x147ff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0xe900, 0x147ff, FORCEWAKE_GT), GEN_FW_RANGE(0x14800, 0x148ff, FORCEWAKE_RENDER), - GEN_FW_RANGE(0x14900, 0x19fff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0x14900, 0x19fff, FORCEWAKE_GT), GEN_FW_RANGE(0x1a000, 0x1a7ff, FORCEWAKE_RENDER), - GEN_FW_RANGE(0x1a800, 0x1afff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0x1a800, 0x1afff, FORCEWAKE_GT), GEN_FW_RANGE(0x1b000, 0x1bfff, FORCEWAKE_RENDER), - GEN_FW_RANGE(0x1c000, 0x243ff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0x1c000, 0x243ff, FORCEWAKE_GT), GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER), - GEN_FW_RANGE(0x24800, 0x3ffff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0x24800, 0x3ffff, FORCEWAKE_GT), GEN_FW_RANGE(0x40000, 0x1bffff, 0), GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), GEN_FW_RANGE(0x1c4000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX1), GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0), - GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_GT), GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2), GEN_FW_RANGE(0x1d4000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX3), GEN_FW_RANGE(0x1d8000, 0x1dbfff, FORCEWAKE_MEDIA_VEBOX1) @@ -1469,7 +1469,7 @@ static int __fw_domain_init(struct intel_uncore *uncore, d->id = domain_id; BUILD_BUG_ON(FORCEWAKE_RENDER != (1 << FW_DOMAIN_ID_RENDER)); - BUILD_BUG_ON(FORCEWAKE_BLITTER != (1 << FW_DOMAIN_ID_BLITTER)); + BUILD_BUG_ON(FORCEWAKE_GT != (1 << FW_DOMAIN_ID_GT)); BUILD_BUG_ON(FORCEWAKE_MEDIA != (1 << FW_DOMAIN_ID_MEDIA)); BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX0)); BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX1)); @@ -1538,9 +1538,9 @@ static int intel_uncore_fw_domains_init(struct intel_uncore *uncore) fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, FORCEWAKE_RENDER_GEN9, FORCEWAKE_ACK_RENDER_GEN9); - fw_domain_init(uncore, FW_DOMAIN_ID_BLITTER, - FORCEWAKE_BLITTER_GEN9, - FORCEWAKE_ACK_BLITTER_GEN9); + fw_domain_init(uncore, FW_DOMAIN_ID_GT, + FORCEWAKE_GT_GEN9, + FORCEWAKE_ACK_GT_GEN9); for (i = 0; i < I915_MAX_VCS; i++) { if (!__HAS_ENGINE(emask, _VCS(i))) @@ -1564,9 +1564,9 @@ static int intel_uncore_fw_domains_init(struct intel_uncore *uncore) fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, FORCEWAKE_RENDER_GEN9, FORCEWAKE_ACK_RENDER_GEN9); - fw_domain_init(uncore, FW_DOMAIN_ID_BLITTER, - FORCEWAKE_BLITTER_GEN9, - FORCEWAKE_ACK_BLITTER_GEN9); + fw_domain_init(uncore, FW_DOMAIN_ID_GT, + FORCEWAKE_GT_GEN9, + FORCEWAKE_ACK_GT_GEN9); fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA, FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9); } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h index c4b22d9d0b45..bd2467284295 100644 --- a/drivers/gpu/drm/i915/intel_uncore.h +++ b/drivers/gpu/drm/i915/intel_uncore.h @@ -46,7 +46,7 @@ struct intel_uncore_mmio_debug { enum forcewake_domain_id { FW_DOMAIN_ID_RENDER = 0, - FW_DOMAIN_ID_BLITTER, + FW_DOMAIN_ID_GT, /* also includes blitter engine */ FW_DOMAIN_ID_MEDIA, FW_DOMAIN_ID_MEDIA_VDBOX0, FW_DOMAIN_ID_MEDIA_VDBOX1, @@ -60,7 +60,7 @@ enum forcewake_domain_id { enum forcewake_domains { FORCEWAKE_RENDER = BIT(FW_DOMAIN_ID_RENDER), - FORCEWAKE_BLITTER = BIT(FW_DOMAIN_ID_BLITTER), + FORCEWAKE_GT = BIT(FW_DOMAIN_ID_GT), FORCEWAKE_MEDIA = BIT(FW_DOMAIN_ID_MEDIA), FORCEWAKE_MEDIA_VDBOX0 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX0), FORCEWAKE_MEDIA_VDBOX1 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX1), -- 2.24.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH v2 1/3] drm/i915: Rename FORCEWAKE_BLITTER to FORCEWAKE_GT 2020-10-09 19:44 ` [Intel-gfx] [PATCH v2 1/3] drm/i915: Rename FORCEWAKE_BLITTER to FORCEWAKE_GT Matt Roper @ 2020-10-09 22:09 ` Souza, Jose 0 siblings, 0 replies; 11+ messages in thread From: Souza, Jose @ 2020-10-09 22:09 UTC (permalink / raw) To: Roper, Matthew D, intel-gfx On Fri, 2020-10-09 at 12:44 -0700, Matt Roper wrote: > The power well that we've been referring to as the 'blitter' well is > actually more of a general GT power well which contains a lot of things > other than the blitter engine registers. The FORCEWAKE_BLITTER name in > the code was used for historic reasons, but no longer matches how the > bspec describes this power well and just causes confusion for people not > familiar with this area of the code. Let's rename it to FORCEWAKE_GT to > more accurately describe the roll of the power well and match how the > modern bspec refers to it. > > v2: > - Add a comment noting that the GT power well includes the blitter > engine. (Jose) > Reviewed-by: José Roberto de Souza <jose.souza@intel.com> > Bspec: 66696, 66534, 67609 > Cc: José Roberto de Souza <jose.souza@intel.com> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> > --- > drivers/gpu/drm/i915/gt/uc/intel_guc.c | 6 +- > drivers/gpu/drm/i915/gvt/handlers.c | 8 +- > drivers/gpu/drm/i915/gvt/reg.h | 4 +- > drivers/gpu/drm/i915/i915_reg.h | 4 +- > drivers/gpu/drm/i915/intel_uncore.c | 100 ++++++++++++------------- > drivers/gpu/drm/i915/intel_uncore.h | 4 +- > 6 files changed, 63 insertions(+), 63 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c > index 942c7c187adb..e4aaa5f29796 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c > @@ -312,18 +312,18 @@ void intel_guc_write_params(struct intel_guc *guc) > int i; > > > > > /* > - * All SOFT_SCRATCH registers are in FORCEWAKE_BLITTER domain and > + * All SOFT_SCRATCH registers are in FORCEWAKE_GT domain and > * they are power context saved so it's ok to release forcewake > * when we are done here and take it again at xfer time. > */ > - intel_uncore_forcewake_get(uncore, FORCEWAKE_BLITTER); > + intel_uncore_forcewake_get(uncore, FORCEWAKE_GT); > > > > > intel_uncore_write(uncore, SOFT_SCRATCH(0), 0); > > > > > for (i = 0; i < GUC_CTL_MAX_DWORDS; i++) > intel_uncore_write(uncore, SOFT_SCRATCH(1 + i), guc->params[i]); > > > > > - intel_uncore_forcewake_put(uncore, FORCEWAKE_BLITTER); > + intel_uncore_forcewake_put(uncore, FORCEWAKE_GT); > } > > > > > int intel_guc_init(struct intel_guc *guc) > diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c > index 3be37e6fe33d..e0edc9d1f357 100644 > --- a/drivers/gpu/drm/i915/gvt/handlers.c > +++ b/drivers/gpu/drm/i915/gvt/handlers.c > @@ -290,8 +290,8 @@ static int mul_force_wake_write(struct intel_vgpu *vgpu, > case FORCEWAKE_RENDER_GEN9_REG: > ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG; > break; > - case FORCEWAKE_BLITTER_GEN9_REG: > - ack_reg_offset = FORCEWAKE_ACK_BLITTER_GEN9_REG; > + case FORCEWAKE_GT_GEN9_REG: > + ack_reg_offset = FORCEWAKE_ACK_GT_GEN9_REG; > break; > case FORCEWAKE_MEDIA_GEN9_REG: > ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG; > @@ -2901,8 +2901,8 @@ static int init_skl_mmio_info(struct intel_gvt *gvt) > > > > > MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); > MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL); > - MMIO_DH(FORCEWAKE_BLITTER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); > - MMIO_DH(FORCEWAKE_ACK_BLITTER_GEN9, D_SKL_PLUS, NULL, NULL); > + MMIO_DH(FORCEWAKE_GT_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); > + MMIO_DH(FORCEWAKE_ACK_GT_GEN9, D_SKL_PLUS, NULL, NULL); > MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); > MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL); > > > > > diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h > index b88e033cbed4..b58860dee970 100644 > --- a/drivers/gpu/drm/i915/gvt/reg.h > +++ b/drivers/gpu/drm/i915/gvt/reg.h > @@ -101,8 +101,8 @@ > > > > > #define FORCEWAKE_RENDER_GEN9_REG 0xa278 > #define FORCEWAKE_ACK_RENDER_GEN9_REG 0x0D84 > -#define FORCEWAKE_BLITTER_GEN9_REG 0xa188 > -#define FORCEWAKE_ACK_BLITTER_GEN9_REG 0x130044 > +#define FORCEWAKE_GT_GEN9_REG 0xa188 > +#define FORCEWAKE_ACK_GT_GEN9_REG 0x130044 > #define FORCEWAKE_MEDIA_GEN9_REG 0xa270 > #define FORCEWAKE_ACK_MEDIA_GEN9_REG 0x0D88 > #define FORCEWAKE_ACK_HSW_REG 0x130044 > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 6ad9ee4243a0..04c966a524ce 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -8958,12 +8958,12 @@ enum { > #define FORCEWAKE_MEDIA_VDBOX_GEN11(n) _MMIO(0xa540 + (n) * 4) > #define FORCEWAKE_MEDIA_VEBOX_GEN11(n) _MMIO(0xa560 + (n) * 4) > #define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278) > -#define FORCEWAKE_BLITTER_GEN9 _MMIO(0xa188) > +#define FORCEWAKE_GT_GEN9 _MMIO(0xa188) > #define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0x0D88) > #define FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n) _MMIO(0x0D50 + (n) * 4) > #define FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n) _MMIO(0x0D70 + (n) * 4) > #define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0x0D84) > -#define FORCEWAKE_ACK_BLITTER_GEN9 _MMIO(0x130044) > +#define FORCEWAKE_ACK_GT_GEN9 _MMIO(0x130044) > #define FORCEWAKE_KERNEL BIT(0) > #define FORCEWAKE_USER BIT(1) > #define FORCEWAKE_KERNEL_FALLBACK BIT(15) > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c > index 54e201fdeba4..ede3a5393d51 100644 > --- a/drivers/gpu/drm/i915/intel_uncore.c > +++ b/drivers/gpu/drm/i915/intel_uncore.c > @@ -1051,37 +1051,37 @@ static const struct intel_forcewake_range __chv_fw_ranges[] = { > > > > > /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */ > static const struct intel_forcewake_range __gen9_fw_ranges[] = { > - GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER), > + GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_GT), > GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */ > GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER), > - GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER), > + GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT), > GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER), > - GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER), > + GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT), > GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), > - GEN_FW_RANGE(0x8000, 0x812f, FORCEWAKE_BLITTER), > + GEN_FW_RANGE(0x8000, 0x812f, FORCEWAKE_GT), > GEN_FW_RANGE(0x8130, 0x813f, FORCEWAKE_MEDIA), > GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER), > - GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER), > + GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_GT), > GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), > - GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_BLITTER), > + GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_GT), > GEN_FW_RANGE(0x8800, 0x89ff, FORCEWAKE_MEDIA), > - GEN_FW_RANGE(0x8a00, 0x8bff, FORCEWAKE_BLITTER), > + GEN_FW_RANGE(0x8a00, 0x8bff, FORCEWAKE_GT), > GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER), > - GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER), > + GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_GT), > GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), > - GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER), > + GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_GT), > GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER), > - GEN_FW_RANGE(0xb480, 0xcfff, FORCEWAKE_BLITTER), > + GEN_FW_RANGE(0xb480, 0xcfff, FORCEWAKE_GT), > GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA), > - GEN_FW_RANGE(0xd800, 0xdfff, FORCEWAKE_BLITTER), > + GEN_FW_RANGE(0xd800, 0xdfff, FORCEWAKE_GT), > GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER), > - GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_BLITTER), > + GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_GT), > GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA), > - GEN_FW_RANGE(0x14000, 0x19fff, FORCEWAKE_BLITTER), > + GEN_FW_RANGE(0x14000, 0x19fff, FORCEWAKE_GT), > GEN_FW_RANGE(0x1a000, 0x1e9ff, FORCEWAKE_MEDIA), > - GEN_FW_RANGE(0x1ea00, 0x243ff, FORCEWAKE_BLITTER), > + GEN_FW_RANGE(0x1ea00, 0x243ff, FORCEWAKE_GT), > GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER), > - GEN_FW_RANGE(0x24800, 0x2ffff, FORCEWAKE_BLITTER), > + GEN_FW_RANGE(0x24800, 0x2ffff, FORCEWAKE_GT), > GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA), > }; > > > > > @@ -1089,33 +1089,33 @@ static const struct intel_forcewake_range __gen9_fw_ranges[] = { > static const struct intel_forcewake_range __gen11_fw_ranges[] = { > GEN_FW_RANGE(0x0, 0x1fff, 0), /* uncore range */ > GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER), > - GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER), > + GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT), > GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER), > - GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER), > + GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT), > GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), > - GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_BLITTER), > + GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT), > GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER), > - GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER), > + GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_GT), > GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), > - GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_BLITTER), > + GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_GT), > GEN_FW_RANGE(0x8800, 0x8bff, 0), > GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER), > - GEN_FW_RANGE(0x8d00, 0x94cf, FORCEWAKE_BLITTER), > + GEN_FW_RANGE(0x8d00, 0x94cf, FORCEWAKE_GT), > GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER), > GEN_FW_RANGE(0x9560, 0x95ff, 0), > - GEN_FW_RANGE(0x9600, 0xafff, FORCEWAKE_BLITTER), > + GEN_FW_RANGE(0x9600, 0xafff, FORCEWAKE_GT), > GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER), > - GEN_FW_RANGE(0xb480, 0xdeff, FORCEWAKE_BLITTER), > + GEN_FW_RANGE(0xb480, 0xdeff, FORCEWAKE_GT), > GEN_FW_RANGE(0xdf00, 0xe8ff, FORCEWAKE_RENDER), > - GEN_FW_RANGE(0xe900, 0x16dff, FORCEWAKE_BLITTER), > + GEN_FW_RANGE(0xe900, 0x16dff, FORCEWAKE_GT), > GEN_FW_RANGE(0x16e00, 0x19fff, FORCEWAKE_RENDER), > - GEN_FW_RANGE(0x1a000, 0x23fff, FORCEWAKE_BLITTER), > + GEN_FW_RANGE(0x1a000, 0x23fff, FORCEWAKE_GT), > GEN_FW_RANGE(0x24000, 0x2407f, 0), > - GEN_FW_RANGE(0x24080, 0x2417f, FORCEWAKE_BLITTER), > + GEN_FW_RANGE(0x24080, 0x2417f, FORCEWAKE_GT), > GEN_FW_RANGE(0x24180, 0x242ff, FORCEWAKE_RENDER), > - GEN_FW_RANGE(0x24300, 0x243ff, FORCEWAKE_BLITTER), > + GEN_FW_RANGE(0x24300, 0x243ff, FORCEWAKE_GT), > GEN_FW_RANGE(0x24400, 0x24fff, FORCEWAKE_RENDER), > - GEN_FW_RANGE(0x25000, 0x3ffff, FORCEWAKE_BLITTER), > + GEN_FW_RANGE(0x25000, 0x3ffff, FORCEWAKE_GT), > GEN_FW_RANGE(0x40000, 0x1bffff, 0), > GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), > GEN_FW_RANGE(0x1c4000, 0x1c7fff, 0), > @@ -1126,39 +1126,39 @@ static const struct intel_forcewake_range __gen11_fw_ranges[] = { > > > > > /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */ > static const struct intel_forcewake_range __gen12_fw_ranges[] = { > - GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER), > + GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_GT), > GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */ > GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER), > - GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER), > + GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT), > GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER), > - GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER), > + GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT), > GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), > - GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_BLITTER), > + GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT), > GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER), > - GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER), > + GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_GT), > GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), > - GEN_FW_RANGE(0x8500, 0x8bff, FORCEWAKE_BLITTER), > + GEN_FW_RANGE(0x8500, 0x8bff, FORCEWAKE_GT), > GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER), > - GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER), > + GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_GT), > GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_ALL), > - GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER), > + GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_GT), > GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER), > - GEN_FW_RANGE(0xb480, 0xdfff, FORCEWAKE_BLITTER), > + GEN_FW_RANGE(0xb480, 0xdfff, FORCEWAKE_GT), > GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER), > - GEN_FW_RANGE(0xe900, 0x147ff, FORCEWAKE_BLITTER), > + GEN_FW_RANGE(0xe900, 0x147ff, FORCEWAKE_GT), > GEN_FW_RANGE(0x14800, 0x148ff, FORCEWAKE_RENDER), > - GEN_FW_RANGE(0x14900, 0x19fff, FORCEWAKE_BLITTER), > + GEN_FW_RANGE(0x14900, 0x19fff, FORCEWAKE_GT), > GEN_FW_RANGE(0x1a000, 0x1a7ff, FORCEWAKE_RENDER), > - GEN_FW_RANGE(0x1a800, 0x1afff, FORCEWAKE_BLITTER), > + GEN_FW_RANGE(0x1a800, 0x1afff, FORCEWAKE_GT), > GEN_FW_RANGE(0x1b000, 0x1bfff, FORCEWAKE_RENDER), > - GEN_FW_RANGE(0x1c000, 0x243ff, FORCEWAKE_BLITTER), > + GEN_FW_RANGE(0x1c000, 0x243ff, FORCEWAKE_GT), > GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER), > - GEN_FW_RANGE(0x24800, 0x3ffff, FORCEWAKE_BLITTER), > + GEN_FW_RANGE(0x24800, 0x3ffff, FORCEWAKE_GT), > GEN_FW_RANGE(0x40000, 0x1bffff, 0), > GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), > GEN_FW_RANGE(0x1c4000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX1), > GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0), > - GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_BLITTER), > + GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_GT), > GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2), > GEN_FW_RANGE(0x1d4000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX3), > GEN_FW_RANGE(0x1d8000, 0x1dbfff, FORCEWAKE_MEDIA_VEBOX1) > @@ -1469,7 +1469,7 @@ static int __fw_domain_init(struct intel_uncore *uncore, > d->id = domain_id; > > > > > BUILD_BUG_ON(FORCEWAKE_RENDER != (1 << FW_DOMAIN_ID_RENDER)); > - BUILD_BUG_ON(FORCEWAKE_BLITTER != (1 << FW_DOMAIN_ID_BLITTER)); > + BUILD_BUG_ON(FORCEWAKE_GT != (1 << FW_DOMAIN_ID_GT)); > BUILD_BUG_ON(FORCEWAKE_MEDIA != (1 << FW_DOMAIN_ID_MEDIA)); > BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX0)); > BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX1)); > @@ -1538,9 +1538,9 @@ static int intel_uncore_fw_domains_init(struct intel_uncore *uncore) > fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, > FORCEWAKE_RENDER_GEN9, > FORCEWAKE_ACK_RENDER_GEN9); > - fw_domain_init(uncore, FW_DOMAIN_ID_BLITTER, > - FORCEWAKE_BLITTER_GEN9, > - FORCEWAKE_ACK_BLITTER_GEN9); > + fw_domain_init(uncore, FW_DOMAIN_ID_GT, > + FORCEWAKE_GT_GEN9, > + FORCEWAKE_ACK_GT_GEN9); > > > > > for (i = 0; i < I915_MAX_VCS; i++) { > if (!__HAS_ENGINE(emask, _VCS(i))) > @@ -1564,9 +1564,9 @@ static int intel_uncore_fw_domains_init(struct intel_uncore *uncore) > fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, > FORCEWAKE_RENDER_GEN9, > FORCEWAKE_ACK_RENDER_GEN9); > - fw_domain_init(uncore, FW_DOMAIN_ID_BLITTER, > - FORCEWAKE_BLITTER_GEN9, > - FORCEWAKE_ACK_BLITTER_GEN9); > + fw_domain_init(uncore, FW_DOMAIN_ID_GT, > + FORCEWAKE_GT_GEN9, > + FORCEWAKE_ACK_GT_GEN9); > fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA, > FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9); > } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { > diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h > index c4b22d9d0b45..bd2467284295 100644 > --- a/drivers/gpu/drm/i915/intel_uncore.h > +++ b/drivers/gpu/drm/i915/intel_uncore.h > @@ -46,7 +46,7 @@ struct intel_uncore_mmio_debug { > > > > > enum forcewake_domain_id { > FW_DOMAIN_ID_RENDER = 0, > - FW_DOMAIN_ID_BLITTER, > + FW_DOMAIN_ID_GT, /* also includes blitter engine */ > FW_DOMAIN_ID_MEDIA, > FW_DOMAIN_ID_MEDIA_VDBOX0, > FW_DOMAIN_ID_MEDIA_VDBOX1, > @@ -60,7 +60,7 @@ enum forcewake_domain_id { > > > > > enum forcewake_domains { > FORCEWAKE_RENDER = BIT(FW_DOMAIN_ID_RENDER), > - FORCEWAKE_BLITTER = BIT(FW_DOMAIN_ID_BLITTER), > + FORCEWAKE_GT = BIT(FW_DOMAIN_ID_GT), > FORCEWAKE_MEDIA = BIT(FW_DOMAIN_ID_MEDIA), > FORCEWAKE_MEDIA_VDBOX0 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX0), > FORCEWAKE_MEDIA_VDBOX1 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX1), _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH v2 2/3] drm/i915: Update gen12 forcewake table 2020-10-09 19:44 [Intel-gfx] [PATCH v2 0/3] Gen12 forcewake and multicast updates Matt Roper 2020-10-09 19:44 ` [Intel-gfx] [PATCH v2 1/3] drm/i915: Rename FORCEWAKE_BLITTER to FORCEWAKE_GT Matt Roper @ 2020-10-09 19:44 ` Matt Roper 2020-10-09 22:21 ` Souza, Jose 2020-10-09 19:44 ` [Intel-gfx] [PATCH v2 3/3] drm/i915: Update gen12 multicast register ranges Matt Roper ` (4 subsequent siblings) 6 siblings, 1 reply; 11+ messages in thread From: Matt Roper @ 2020-10-09 19:44 UTC (permalink / raw) To: intel-gfx The bspec's forcewake page was very stale and out of date for recent platforms. The hardware team finally provided us with an updated gen12 table (which applies to TGL, RKL, and DG1) and there are a lot of changes. v2: - Add comments showing the subregions of ranges that we've combined for ease of code review. (Jose) - Rebase on the s/FORCEWAKE_BLITTER/FORCEWAKE_GT/ patch Bspec: 66696 Cc: Caz Yokoyama <caz.yokoyama@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> --- drivers/gpu/drm/i915/intel_uncore.c | 129 +++++++++++++++++++++------- 1 file changed, 99 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index ede3a5393d51..1332dde6ff99 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -1124,44 +1124,113 @@ static const struct intel_forcewake_range __gen11_fw_ranges[] = { GEN_FW_RANGE(0x1d4000, 0x1dbfff, 0) }; -/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */ +/* + * *Must* be sorted by offset ranges! See intel_fw_table_check(). + * + * Note that the spec lists several reserved/unused ranges that don't + * actually contain any registers. In the table below we'll combine those + * reserved ranges with either the preceding or following range to keep the + * table small and lookups fast. + */ static const struct intel_forcewake_range __gen12_fw_ranges[] = { - GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_GT), - GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */ + GEN_FW_RANGE(0x0, 0x1fff, 0), /* + 0x0 - 0xaff: reserved + 0xb00 - 0x1fff: always on */ GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER), - GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT), + GEN_FW_RANGE(0x2700, 0x27ff, FORCEWAKE_GT), + GEN_FW_RANGE(0x2800, 0x2aff, FORCEWAKE_RENDER), + GEN_FW_RANGE(0x2b00, 0x2fff, FORCEWAKE_GT), GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER), - GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT), - GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), + GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT), /* + 0x4000 - 0x48ff: gt + 0x4900 - 0x51ff: reserved */ + GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), /* + 0x5200 - 0x53ff: render + 0x5400 - 0x54ff: reserved + 0x5500 - 0x7fff: render */ GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT), GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER), - GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_GT), + GEN_FW_RANGE(0x8160, 0x81ff, 0), /* + 0x8160 - 0x817f: reserved + 0x8180 - 0x81ff: always on */ + GEN_FW_RANGE(0x8200, 0x82ff, FORCEWAKE_GT), GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), - GEN_FW_RANGE(0x8500, 0x8bff, FORCEWAKE_GT), - GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER), - GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_GT), - GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_ALL), + GEN_FW_RANGE(0x8500, 0x94cf, FORCEWAKE_GT), /* + 0x8500 - 0x87ff: gt + 0x8800 - 0x8fff: reserved + 0x9000 - 0x947f: gt + 0x9480 - 0x94cf: reserved */ + GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER), + GEN_FW_RANGE(0x9560, 0x97ff, 0), /* + 0x9560 - 0x95ff: always on + 0x9600 - 0x97ff: reserved */ GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_GT), - GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER), - GEN_FW_RANGE(0xb480, 0xdfff, FORCEWAKE_GT), - GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER), - GEN_FW_RANGE(0xe900, 0x147ff, FORCEWAKE_GT), - GEN_FW_RANGE(0x14800, 0x148ff, FORCEWAKE_RENDER), - GEN_FW_RANGE(0x14900, 0x19fff, FORCEWAKE_GT), - GEN_FW_RANGE(0x1a000, 0x1a7ff, FORCEWAKE_RENDER), - GEN_FW_RANGE(0x1a800, 0x1afff, FORCEWAKE_GT), - GEN_FW_RANGE(0x1b000, 0x1bfff, FORCEWAKE_RENDER), - GEN_FW_RANGE(0x1c000, 0x243ff, FORCEWAKE_GT), - GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER), - GEN_FW_RANGE(0x24800, 0x3ffff, FORCEWAKE_GT), + GEN_FW_RANGE(0xb000, 0xb3ff, FORCEWAKE_RENDER), + GEN_FW_RANGE(0xb400, 0xcfff, FORCEWAKE_GT), /* + 0xb400 - 0xbf7f: gt + 0xb480 - 0xbfff: reserved + 0xc000 - 0xcfff: gt */ + GEN_FW_RANGE(0xd000, 0xd7ff, 0), + GEN_FW_RANGE(0xd800, 0xd8ff, FORCEWAKE_RENDER), + GEN_FW_RANGE(0xd900, 0xdbff, FORCEWAKE_GT), + GEN_FW_RANGE(0xdc00, 0xefff, FORCEWAKE_RENDER), /* + 0xdc00 - 0xddff: render + 0xde00 - 0xde7f: reserved + 0xde80 - 0xe8ff: render + 0xe900 - 0xefff: reserved */ + GEN_FW_RANGE(0xf000, 0x147ff, FORCEWAKE_GT), /* + 0xf000 - 0xffff: gt + 0x10000 - 0x147ff: reserved */ + GEN_FW_RANGE(0x14800, 0x1ffff, FORCEWAKE_RENDER), /* + 0x14800 - 0x14fff: render + 0x15000 - 0x16dff: reserved + 0x16e00 - 0x1bfff: render + 0x1c000 - 0x1ffff: reserved */ + GEN_FW_RANGE(0x20000, 0x20fff, FORCEWAKE_MEDIA_VDBOX0), + GEN_FW_RANGE(0x21000, 0x21fff, FORCEWAKE_MEDIA_VDBOX2), + GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT), + GEN_FW_RANGE(0x24000, 0x2417f, 0), /* + 0x24000 - 0x2407f: always on + 0x24080 - 0x2417f: reserved */ + GEN_FW_RANGE(0x24180, 0x249ff, FORCEWAKE_GT), /* + 0x24180 - 0x241ff: gt + 0x24200 - 0x249ff: reserved */ + GEN_FW_RANGE(0x24a00, 0x251ff, FORCEWAKE_RENDER), /* + 0x24a00 - 0x24a7f: render + 0x24a80 - 0x251ff: reserved */ + GEN_FW_RANGE(0x25200, 0x255ff, FORCEWAKE_GT), /* + 0x25200 - 0x252ff: gt + 0x25300 - 0x255ff: reserved */ + GEN_FW_RANGE(0x25600, 0x2567f, FORCEWAKE_MEDIA_VDBOX0), + GEN_FW_RANGE(0x25680, 0x259ff, FORCEWAKE_MEDIA_VDBOX2), /* + 0x25680 - 0x256ff: VD2 + 0x25700 - 0x259ff: reserved */ + GEN_FW_RANGE(0x25a00, 0x25a7f, FORCEWAKE_MEDIA_VDBOX0), + GEN_FW_RANGE(0x25a80, 0x2ffff, FORCEWAKE_MEDIA_VDBOX2), /* + 0x25a80 - 0x25aff: VD2 + 0x25b00 - 0x2ffff: reserved */ + GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_GT), GEN_FW_RANGE(0x40000, 0x1bffff, 0), - GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), - GEN_FW_RANGE(0x1c4000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX1), - GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0), - GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_GT), - GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2), - GEN_FW_RANGE(0x1d4000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX3), - GEN_FW_RANGE(0x1d8000, 0x1dbfff, FORCEWAKE_MEDIA_VEBOX1) + GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), /* + 0x1c0000 - 0x1c2bff: VD0 + 0x1c2c00 - 0x1c2cff: reserved + 0x1c2d00 - 0x1c2dff: VD0 + 0x1c2e00 - 0x1c3eff: reserved + 0x1c3f00 - 0x1c3fff: VD0 */ + GEN_FW_RANGE(0x1c4000, 0x1c7fff, 0), + GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0), /* + 0x1c8000 - 0x1ca0ff: VE0 + 0x1ca100 - 0x1cbeff: reserved + 0x1cbf00 - 0x1cbfff: VE0 */ + GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_MEDIA_VDBOX0), /* + 0x1cc000 - 0x1ccfff: VD0 + 0x1cd000 - 0x1cffff: reserved */ + GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2), /* + 0x1d0000 - 0x1d2bff: VD2 + 0x1d2c00 - 0x1d2cff: reserved + 0x1d2d00 - 0x1d2dff: VD2 + 0x1d2e00 - 0x1d3eff: reserved + 0x1d3f00 - 0x1d3fff: VD2 */ }; static void -- 2.24.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH v2 2/3] drm/i915: Update gen12 forcewake table 2020-10-09 19:44 ` [Intel-gfx] [PATCH v2 2/3] drm/i915: Update gen12 forcewake table Matt Roper @ 2020-10-09 22:21 ` Souza, Jose 0 siblings, 0 replies; 11+ messages in thread From: Souza, Jose @ 2020-10-09 22:21 UTC (permalink / raw) To: Roper, Matthew D, intel-gfx On Fri, 2020-10-09 at 12:44 -0700, Matt Roper wrote: > The bspec's forcewake page was very stale and out of date for recent > platforms. The hardware team finally provided us with an updated gen12 > table (which applies to TGL, RKL, and DG1) and there are a lot of > changes. > > v2: > - Add comments showing the subregions of ranges that we've combined for > ease of code review. (Jose) > - Rebase on the s/FORCEWAKE_BLITTER/FORCEWAKE_GT/ patch Reviewed-by: José Roberto de Souza <jose.souza@intel.com> > > Bspec: 66696 > Cc: Caz Yokoyama <caz.yokoyama@intel.com> > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > Cc: José Roberto de Souza <jose.souza@intel.com> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> > --- > drivers/gpu/drm/i915/intel_uncore.c | 129 +++++++++++++++++++++------- > 1 file changed, 99 insertions(+), 30 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c > index ede3a5393d51..1332dde6ff99 100644 > --- a/drivers/gpu/drm/i915/intel_uncore.c > +++ b/drivers/gpu/drm/i915/intel_uncore.c > @@ -1124,44 +1124,113 @@ static const struct intel_forcewake_range __gen11_fw_ranges[] = { > GEN_FW_RANGE(0x1d4000, 0x1dbfff, 0) > }; > > > > > -/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */ > +/* > + * *Must* be sorted by offset ranges! See intel_fw_table_check(). > + * > + * Note that the spec lists several reserved/unused ranges that don't > + * actually contain any registers. In the table below we'll combine those > + * reserved ranges with either the preceding or following range to keep the > + * table small and lookups fast. > + */ > static const struct intel_forcewake_range __gen12_fw_ranges[] = { > - GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_GT), > - GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */ > + GEN_FW_RANGE(0x0, 0x1fff, 0), /* > + 0x0 - 0xaff: reserved > + 0xb00 - 0x1fff: always on */ > GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER), > - GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT), > + GEN_FW_RANGE(0x2700, 0x27ff, FORCEWAKE_GT), > + GEN_FW_RANGE(0x2800, 0x2aff, FORCEWAKE_RENDER), > + GEN_FW_RANGE(0x2b00, 0x2fff, FORCEWAKE_GT), > GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER), > - GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT), > - GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), > + GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT), /* > + 0x4000 - 0x48ff: gt > + 0x4900 - 0x51ff: reserved */ > + GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), /* > + 0x5200 - 0x53ff: render > + 0x5400 - 0x54ff: reserved > + 0x5500 - 0x7fff: render */ > GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT), > GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER), > - GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_GT), > + GEN_FW_RANGE(0x8160, 0x81ff, 0), /* > + 0x8160 - 0x817f: reserved > + 0x8180 - 0x81ff: always on */ > + GEN_FW_RANGE(0x8200, 0x82ff, FORCEWAKE_GT), > GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), > - GEN_FW_RANGE(0x8500, 0x8bff, FORCEWAKE_GT), > - GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER), > - GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_GT), > - GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_ALL), > + GEN_FW_RANGE(0x8500, 0x94cf, FORCEWAKE_GT), /* > + 0x8500 - 0x87ff: gt > + 0x8800 - 0x8fff: reserved > + 0x9000 - 0x947f: gt > + 0x9480 - 0x94cf: reserved */ > + GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER), > + GEN_FW_RANGE(0x9560, 0x97ff, 0), /* > + 0x9560 - 0x95ff: always on > + 0x9600 - 0x97ff: reserved */ > GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_GT), > - GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER), > - GEN_FW_RANGE(0xb480, 0xdfff, FORCEWAKE_GT), > - GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER), > - GEN_FW_RANGE(0xe900, 0x147ff, FORCEWAKE_GT), > - GEN_FW_RANGE(0x14800, 0x148ff, FORCEWAKE_RENDER), > - GEN_FW_RANGE(0x14900, 0x19fff, FORCEWAKE_GT), > - GEN_FW_RANGE(0x1a000, 0x1a7ff, FORCEWAKE_RENDER), > - GEN_FW_RANGE(0x1a800, 0x1afff, FORCEWAKE_GT), > - GEN_FW_RANGE(0x1b000, 0x1bfff, FORCEWAKE_RENDER), > - GEN_FW_RANGE(0x1c000, 0x243ff, FORCEWAKE_GT), > - GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER), > - GEN_FW_RANGE(0x24800, 0x3ffff, FORCEWAKE_GT), > + GEN_FW_RANGE(0xb000, 0xb3ff, FORCEWAKE_RENDER), > + GEN_FW_RANGE(0xb400, 0xcfff, FORCEWAKE_GT), /* > + 0xb400 - 0xbf7f: gt > + 0xb480 - 0xbfff: reserved > + 0xc000 - 0xcfff: gt */ > + GEN_FW_RANGE(0xd000, 0xd7ff, 0), > + GEN_FW_RANGE(0xd800, 0xd8ff, FORCEWAKE_RENDER), > + GEN_FW_RANGE(0xd900, 0xdbff, FORCEWAKE_GT), > + GEN_FW_RANGE(0xdc00, 0xefff, FORCEWAKE_RENDER), /* > + 0xdc00 - 0xddff: render > + 0xde00 - 0xde7f: reserved > + 0xde80 - 0xe8ff: render > + 0xe900 - 0xefff: reserved */ > + GEN_FW_RANGE(0xf000, 0x147ff, FORCEWAKE_GT), /* > + 0xf000 - 0xffff: gt > + 0x10000 - 0x147ff: reserved */ > + GEN_FW_RANGE(0x14800, 0x1ffff, FORCEWAKE_RENDER), /* > + 0x14800 - 0x14fff: render > + 0x15000 - 0x16dff: reserved > + 0x16e00 - 0x1bfff: render > + 0x1c000 - 0x1ffff: reserved */ > + GEN_FW_RANGE(0x20000, 0x20fff, FORCEWAKE_MEDIA_VDBOX0), > + GEN_FW_RANGE(0x21000, 0x21fff, FORCEWAKE_MEDIA_VDBOX2), > + GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT), > + GEN_FW_RANGE(0x24000, 0x2417f, 0), /* > + 0x24000 - 0x2407f: always on > + 0x24080 - 0x2417f: reserved */ > + GEN_FW_RANGE(0x24180, 0x249ff, FORCEWAKE_GT), /* > + 0x24180 - 0x241ff: gt > + 0x24200 - 0x249ff: reserved */ > + GEN_FW_RANGE(0x24a00, 0x251ff, FORCEWAKE_RENDER), /* > + 0x24a00 - 0x24a7f: render > + 0x24a80 - 0x251ff: reserved */ > + GEN_FW_RANGE(0x25200, 0x255ff, FORCEWAKE_GT), /* > + 0x25200 - 0x252ff: gt > + 0x25300 - 0x255ff: reserved */ > + GEN_FW_RANGE(0x25600, 0x2567f, FORCEWAKE_MEDIA_VDBOX0), > + GEN_FW_RANGE(0x25680, 0x259ff, FORCEWAKE_MEDIA_VDBOX2), /* > + 0x25680 - 0x256ff: VD2 > + 0x25700 - 0x259ff: reserved */ > + GEN_FW_RANGE(0x25a00, 0x25a7f, FORCEWAKE_MEDIA_VDBOX0), > + GEN_FW_RANGE(0x25a80, 0x2ffff, FORCEWAKE_MEDIA_VDBOX2), /* > + 0x25a80 - 0x25aff: VD2 > + 0x25b00 - 0x2ffff: reserved */ > + GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_GT), > GEN_FW_RANGE(0x40000, 0x1bffff, 0), > - GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), > - GEN_FW_RANGE(0x1c4000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX1), > - GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0), > - GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_GT), > - GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2), > - GEN_FW_RANGE(0x1d4000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX3), > - GEN_FW_RANGE(0x1d8000, 0x1dbfff, FORCEWAKE_MEDIA_VEBOX1) > + GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), /* > + 0x1c0000 - 0x1c2bff: VD0 > + 0x1c2c00 - 0x1c2cff: reserved > + 0x1c2d00 - 0x1c2dff: VD0 > + 0x1c2e00 - 0x1c3eff: reserved > + 0x1c3f00 - 0x1c3fff: VD0 */ > + GEN_FW_RANGE(0x1c4000, 0x1c7fff, 0), > + GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0), /* > + 0x1c8000 - 0x1ca0ff: VE0 > + 0x1ca100 - 0x1cbeff: reserved > + 0x1cbf00 - 0x1cbfff: VE0 */ > + GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_MEDIA_VDBOX0), /* > + 0x1cc000 - 0x1ccfff: VD0 > + 0x1cd000 - 0x1cffff: reserved */ > + GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2), /* > + 0x1d0000 - 0x1d2bff: VD2 > + 0x1d2c00 - 0x1d2cff: reserved > + 0x1d2d00 - 0x1d2dff: VD2 > + 0x1d2e00 - 0x1d3eff: reserved > + 0x1d3f00 - 0x1d3fff: VD2 */ > }; > > > > > static void _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH v2 3/3] drm/i915: Update gen12 multicast register ranges 2020-10-09 19:44 [Intel-gfx] [PATCH v2 0/3] Gen12 forcewake and multicast updates Matt Roper 2020-10-09 19:44 ` [Intel-gfx] [PATCH v2 1/3] drm/i915: Rename FORCEWAKE_BLITTER to FORCEWAKE_GT Matt Roper 2020-10-09 19:44 ` [Intel-gfx] [PATCH v2 2/3] drm/i915: Update gen12 forcewake table Matt Roper @ 2020-10-09 19:44 ` Matt Roper 2020-10-09 20:40 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Gen12 forcewake and multicast updates (rev2) Patchwork ` (3 subsequent siblings) 6 siblings, 0 replies; 11+ messages in thread From: Matt Roper @ 2020-10-09 19:44 UTC (permalink / raw) To: intel-gfx The updated bspec forcewake table also provides us with new multicast ranges that should be reflected in our workaround code. Note that there are different types of multicast registers with different styles of replication and different steering registers. The i915 MCR range lists we're updating here are only used to ensure we can verify workarounds properly (i.e., if we can't steer register reads we don't want to verify workarounds where an unsteered read might hit a fused-off instance of the unit). Because of this, we don't need to include any of the multicast ranges where all instances of the register will always present and fusing doesn't play a role. Specifically, that means that we are not including the MCR ranges designated as "SQIDI" in the bspec. Bspec: 66696 Cc: Caz Yokoyama <caz.yokoyama@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 28 ++++++++++++++++----- 1 file changed, 22 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 6c580d0d9ea8..78c5480c6401 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2031,10 +2031,12 @@ create_scratch(struct i915_address_space *vm, int count) return ERR_PTR(err); } -static const struct { +struct mcr_range { u32 start; u32 end; -} mcr_ranges_gen8[] = { +}; + +static const struct mcr_range mcr_ranges_gen8[] = { { .start = 0x5500, .end = 0x55ff }, { .start = 0x7000, .end = 0x7fff }, { .start = 0x9400, .end = 0x97ff }, @@ -2043,11 +2045,25 @@ static const struct { {}, }; +static const struct mcr_range mcr_ranges_gen12[] = { + { .start = 0x8150, .end = 0x815f }, + { .start = 0x9520, .end = 0x955f }, + { .start = 0xb100, .end = 0xb3ff }, + { .start = 0xde80, .end = 0xe8ff }, + { .start = 0x24a00, .end = 0x24a7f }, + {}, +}; + static bool mcr_range(struct drm_i915_private *i915, u32 offset) { + const struct mcr_range *mcr_ranges; int i; - if (INTEL_GEN(i915) < 8) + if (INTEL_GEN(i915) >= 12) + mcr_ranges = mcr_ranges_gen12; + else if (INTEL_GEN(i915) >= 8) + mcr_ranges = mcr_ranges_gen8; + else return false; /* @@ -2055,9 +2071,9 @@ static bool mcr_range(struct drm_i915_private *i915, u32 offset) * which only controls CPU initiated MMIO. Routing does not * work for CS access so we cannot verify them on this path. */ - for (i = 0; mcr_ranges_gen8[i].start; i++) - if (offset >= mcr_ranges_gen8[i].start && - offset <= mcr_ranges_gen8[i].end) + for (i = 0; mcr_ranges[i].start; i++) + if (offset >= mcr_ranges[i].start && + offset <= mcr_ranges[i].end) return true; return false; -- 2.24.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Gen12 forcewake and multicast updates (rev2) 2020-10-09 19:44 [Intel-gfx] [PATCH v2 0/3] Gen12 forcewake and multicast updates Matt Roper ` (2 preceding siblings ...) 2020-10-09 19:44 ` [Intel-gfx] [PATCH v2 3/3] drm/i915: Update gen12 multicast register ranges Matt Roper @ 2020-10-09 20:40 ` Patchwork 2020-10-09 20:41 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork ` (2 subsequent siblings) 6 siblings, 0 replies; 11+ messages in thread From: Patchwork @ 2020-10-09 20:40 UTC (permalink / raw) To: Matt Roper; +Cc: intel-gfx == Series Details == Series: Gen12 forcewake and multicast updates (rev2) URL : https://patchwork.freedesktop.org/series/82359/ State : warning == Summary == $ dim checkpatch origin/drm-tip 008bd21e710f drm/i915: Rename FORCEWAKE_BLITTER to FORCEWAKE_GT 14beef5e5c93 drm/i915: Update gen12 forcewake table -:46: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines #46: FILE: drivers/gpu/drm/i915/intel_uncore.c:1137: + GEN_FW_RANGE(0x0, 0x1fff, 0), /* + 0x0 - 0xaff: reserved -:47: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line #47: FILE: drivers/gpu/drm/i915/intel_uncore.c:1138: + 0xb00 - 0x1fff: always on */ -:57: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines #57: FILE: drivers/gpu/drm/i915/intel_uncore.c:1145: + GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT), /* + 0x4000 - 0x48ff: gt -:58: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line #58: FILE: drivers/gpu/drm/i915/intel_uncore.c:1146: + 0x4900 - 0x51ff: reserved */ -:60: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines #60: FILE: drivers/gpu/drm/i915/intel_uncore.c:1148: + GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), /* + 0x5200 - 0x53ff: render -:62: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line #62: FILE: drivers/gpu/drm/i915/intel_uncore.c:1150: + 0x5500 - 0x7fff: render */ -:67: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines #67: FILE: drivers/gpu/drm/i915/intel_uncore.c:1154: + GEN_FW_RANGE(0x8160, 0x81ff, 0), /* + 0x8160 - 0x817f: reserved -:68: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line #68: FILE: drivers/gpu/drm/i915/intel_uncore.c:1155: + 0x8180 - 0x81ff: always on */ -:76: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines #76: FILE: drivers/gpu/drm/i915/intel_uncore.c:1159: + GEN_FW_RANGE(0x8500, 0x94cf, FORCEWAKE_GT), /* + 0x8500 - 0x87ff: gt -:79: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line #79: FILE: drivers/gpu/drm/i915/intel_uncore.c:1162: + 0x9480 - 0x94cf: reserved */ -:82: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines #82: FILE: drivers/gpu/drm/i915/intel_uncore.c:1165: + GEN_FW_RANGE(0x9560, 0x97ff, 0), /* + 0x9560 - 0x95ff: always on -:83: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line #83: FILE: drivers/gpu/drm/i915/intel_uncore.c:1166: + 0x9600 - 0x97ff: reserved */ -:99: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines #99: FILE: drivers/gpu/drm/i915/intel_uncore.c:1170: + GEN_FW_RANGE(0xb400, 0xcfff, FORCEWAKE_GT), /* + 0xb400 - 0xbf7f: gt -:101: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line #101: FILE: drivers/gpu/drm/i915/intel_uncore.c:1172: + 0xc000 - 0xcfff: gt */ -:106: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines #106: FILE: drivers/gpu/drm/i915/intel_uncore.c:1177: + GEN_FW_RANGE(0xdc00, 0xefff, FORCEWAKE_RENDER), /* + 0xdc00 - 0xddff: render -:109: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line #109: FILE: drivers/gpu/drm/i915/intel_uncore.c:1180: + 0xe900 - 0xefff: reserved */ -:111: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines #111: FILE: drivers/gpu/drm/i915/intel_uncore.c:1182: + GEN_FW_RANGE(0xf000, 0x147ff, FORCEWAKE_GT), /* + 0xf000 - 0xffff: gt -:112: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line #112: FILE: drivers/gpu/drm/i915/intel_uncore.c:1183: + 0x10000 - 0x147ff: reserved */ -:114: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines #114: FILE: drivers/gpu/drm/i915/intel_uncore.c:1185: + GEN_FW_RANGE(0x14800, 0x1ffff, FORCEWAKE_RENDER), /* + 0x14800 - 0x14fff: render -:117: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line #117: FILE: drivers/gpu/drm/i915/intel_uncore.c:1188: + 0x1c000 - 0x1ffff: reserved */ -:122: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines #122: FILE: drivers/gpu/drm/i915/intel_uncore.c:1193: + GEN_FW_RANGE(0x24000, 0x2417f, 0), /* + 0x24000 - 0x2407f: always on -:123: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line #123: FILE: drivers/gpu/drm/i915/intel_uncore.c:1194: + 0x24080 - 0x2417f: reserved */ -:125: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines #125: FILE: drivers/gpu/drm/i915/intel_uncore.c:1196: + GEN_FW_RANGE(0x24180, 0x249ff, FORCEWAKE_GT), /* + 0x24180 - 0x241ff: gt -:126: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line #126: FILE: drivers/gpu/drm/i915/intel_uncore.c:1197: + 0x24200 - 0x249ff: reserved */ -:128: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines #128: FILE: drivers/gpu/drm/i915/intel_uncore.c:1199: + GEN_FW_RANGE(0x24a00, 0x251ff, FORCEWAKE_RENDER), /* + 0x24a00 - 0x24a7f: render -:129: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line #129: FILE: drivers/gpu/drm/i915/intel_uncore.c:1200: + 0x24a80 - 0x251ff: reserved */ -:131: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines #131: FILE: drivers/gpu/drm/i915/intel_uncore.c:1202: + GEN_FW_RANGE(0x25200, 0x255ff, FORCEWAKE_GT), /* + 0x25200 - 0x252ff: gt -:132: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line #132: FILE: drivers/gpu/drm/i915/intel_uncore.c:1203: + 0x25300 - 0x255ff: reserved */ -:135: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines #135: FILE: drivers/gpu/drm/i915/intel_uncore.c:1206: + GEN_FW_RANGE(0x25680, 0x259ff, FORCEWAKE_MEDIA_VDBOX2), /* + 0x25680 - 0x256ff: VD2 -:136: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line #136: FILE: drivers/gpu/drm/i915/intel_uncore.c:1207: + 0x25700 - 0x259ff: reserved */ -:139: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines #139: FILE: drivers/gpu/drm/i915/intel_uncore.c:1210: + GEN_FW_RANGE(0x25a80, 0x2ffff, FORCEWAKE_MEDIA_VDBOX2), /* + 0x25a80 - 0x25aff: VD2 -:140: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line #140: FILE: drivers/gpu/drm/i915/intel_uncore.c:1211: + 0x25b00 - 0x2ffff: reserved */ -:151: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines #151: FILE: drivers/gpu/drm/i915/intel_uncore.c:1215: + GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), /* + 0x1c0000 - 0x1c2bff: VD0 -:155: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line #155: FILE: drivers/gpu/drm/i915/intel_uncore.c:1219: + 0x1c3f00 - 0x1c3fff: VD0 */ -:158: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines #158: FILE: drivers/gpu/drm/i915/intel_uncore.c:1222: + GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0), /* + 0x1c8000 - 0x1ca0ff: VE0 -:160: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line #160: FILE: drivers/gpu/drm/i915/intel_uncore.c:1224: + 0x1cbf00 - 0x1cbfff: VE0 */ -:162: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines #162: FILE: drivers/gpu/drm/i915/intel_uncore.c:1226: + GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_MEDIA_VDBOX0), /* + 0x1cc000 - 0x1ccfff: VD0 -:163: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line #163: FILE: drivers/gpu/drm/i915/intel_uncore.c:1227: + 0x1cd000 - 0x1cffff: reserved */ -:165: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines #165: FILE: drivers/gpu/drm/i915/intel_uncore.c:1229: + GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2), /* + 0x1d0000 - 0x1d2bff: VD2 -:169: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line #169: FILE: drivers/gpu/drm/i915/intel_uncore.c:1233: + 0x1d3f00 - 0x1d3fff: VD2 */ total: 0 errors, 40 warnings, 0 checks, 143 lines checked 74565d868b44 drm/i915: Update gen12 multicast register ranges _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Gen12 forcewake and multicast updates (rev2) 2020-10-09 19:44 [Intel-gfx] [PATCH v2 0/3] Gen12 forcewake and multicast updates Matt Roper ` (3 preceding siblings ...) 2020-10-09 20:40 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Gen12 forcewake and multicast updates (rev2) Patchwork @ 2020-10-09 20:41 ` Patchwork 2020-10-09 21:02 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2020-10-10 0:06 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 6 siblings, 0 replies; 11+ messages in thread From: Patchwork @ 2020-10-09 20:41 UTC (permalink / raw) To: Matt Roper; +Cc: intel-gfx == Series Details == Series: Gen12 forcewake and multicast updates (rev2) URL : https://patchwork.freedesktop.org/series/82359/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_reset.c:1312:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gvt/mmio.c:290:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1440:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1494:15: warning: memset with byte count of 16777216 +./include/linux/seqlock.h:752:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:778:16: warning: trying to copy expression type 31 +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Gen12 forcewake and multicast updates (rev2) 2020-10-09 19:44 [Intel-gfx] [PATCH v2 0/3] Gen12 forcewake and multicast updates Matt Roper ` (4 preceding siblings ...) 2020-10-09 20:41 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork @ 2020-10-09 21:02 ` Patchwork 2020-10-10 0:06 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 6 siblings, 0 replies; 11+ messages in thread From: Patchwork @ 2020-10-09 21:02 UTC (permalink / raw) To: Matt Roper; +Cc: intel-gfx [-- Attachment #1.1: Type: text/plain, Size: 4689 bytes --] == Series Details == Series: Gen12 forcewake and multicast updates (rev2) URL : https://patchwork.freedesktop.org/series/82359/ State : success == Summary == CI Bug Log - changes from CI_DRM_9121 -> Patchwork_18668 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/index.html Known issues ------------ Here are the changes found in Patchwork_18668 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@kms_busy@basic@flip: - fi-kbl-x1275: [PASS][1] -> [DMESG-WARN][2] ([i915#62] / [i915#92] / [i915#95]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/fi-kbl-x1275/igt@kms_busy@basic@flip.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/fi-kbl-x1275/igt@kms_busy@basic@flip.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-icl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html #### Possible fixes #### * igt@kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-icl-u2: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html #### Warnings #### * igt@gem_exec_suspend@basic-s3: - fi-kbl-x1275: [DMESG-WARN][7] ([i915#1982] / [i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][8] ([i915#62] / [i915#92] / [i915#95]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/fi-kbl-x1275/igt@gem_exec_suspend@basic-s3.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/fi-kbl-x1275/igt@gem_exec_suspend@basic-s3.html * igt@kms_flip@basic-flip-vs-wf_vblank@a-dp1: - fi-kbl-x1275: [DMESG-WARN][9] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][10] ([i915#62] / [i915#92]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-wf_vblank@a-dp1.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-wf_vblank@a-dp1.html * igt@kms_force_connector_basic@prune-stale-modes: - fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92]) -> [DMESG-WARN][12] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/fi-kbl-x1275/igt@kms_force_connector_basic@prune-stale-modes.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/fi-kbl-x1275/igt@kms_force_connector_basic@prune-stale-modes.html * igt@vgem_basic@unload: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92]) -> [DMESG-WARN][14] ([i915#95]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/fi-kbl-x1275/igt@vgem_basic@unload.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/fi-kbl-x1275/igt@vgem_basic@unload.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (46 -> 39) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_9121 -> Patchwork_18668 CI-20190529: 20190529 CI_DRM_9121: d78555afe196c8a1329c9813ab7fe7538263ffde @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5806: 6adb80cd84310b6d90a5259768d03ebb2c30fe50 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18668: 74565d868b44da1883b376654ac2d8e8202c49af @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 74565d868b44 drm/i915: Update gen12 multicast register ranges 14beef5e5c93 drm/i915: Update gen12 forcewake table 008bd21e710f drm/i915: Rename FORCEWAKE_BLITTER to FORCEWAKE_GT == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/index.html [-- Attachment #1.2: Type: text/html, Size: 6821 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for Gen12 forcewake and multicast updates (rev2) 2020-10-09 19:44 [Intel-gfx] [PATCH v2 0/3] Gen12 forcewake and multicast updates Matt Roper ` (5 preceding siblings ...) 2020-10-09 21:02 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork @ 2020-10-10 0:06 ` Patchwork 2020-10-10 1:59 ` Matt Roper 6 siblings, 1 reply; 11+ messages in thread From: Patchwork @ 2020-10-10 0:06 UTC (permalink / raw) To: Matt Roper; +Cc: intel-gfx [-- Attachment #1.1: Type: text/plain, Size: 13520 bytes --] == Series Details == Series: Gen12 forcewake and multicast updates (rev2) URL : https://patchwork.freedesktop.org/series/82359/ State : success == Summary == CI Bug Log - changes from CI_DRM_9121_full -> Patchwork_18668_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_18668_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@feature_discovery@psr2: - shard-iclb: [PASS][1] -> [SKIP][2] ([i915#658]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-iclb2/igt@feature_discovery@psr2.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-iclb5/igt@feature_discovery@psr2.html * igt@gem_exec_balancer@nop: - shard-apl: [PASS][3] -> [INCOMPLETE][4] ([i915#1635] / [i915#2377]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-apl2/igt@gem_exec_balancer@nop.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-apl4/igt@gem_exec_balancer@nop.html * igt@gem_huc_copy@huc-copy: - shard-tglb: [PASS][5] -> [SKIP][6] ([i915#2190]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-tglb1/igt@gem_huc_copy@huc-copy.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-tglb6/igt@gem_huc_copy@huc-copy.html * igt@gem_userptr_blits@unsync-unmap-cycles: - shard-skl: [PASS][7] -> [TIMEOUT][8] ([i915#2424]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-skl10/igt@gem_userptr_blits@unsync-unmap-cycles.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-skl2/igt@gem_userptr_blits@unsync-unmap-cycles.html * igt@kms_big_fb@yf-tiled-16bpp-rotate-180: - shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-kbl7/igt@kms_big_fb@yf-tiled-16bpp-rotate-180.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-kbl6/igt@kms_big_fb@yf-tiled-16bpp-rotate-180.html * igt@kms_cursor_edge_walk@pipe-c-128x128-left-edge: - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([i915#1635] / [i915#1982]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-apl4/igt@kms_cursor_edge_walk@pipe-c-128x128-left-edge.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-apl1/igt@kms_cursor_edge_walk@pipe-c-128x128-left-edge.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-skl: [PASS][13] -> [FAIL][14] ([i915#2346]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html * igt@kms_flip@flip-vs-suspend-interruptible@c-dp1: - shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([i915#180]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-kbl6/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html * igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack: - shard-glk: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-glk8/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-glk3/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-gtt: - shard-snb: [PASS][19] -> [FAIL][20] ([i915#2546]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-snb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-gtt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-snb4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-gtt.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-wc: - shard-tglb: [PASS][21] -> [DMESG-WARN][22] ([i915#1982]) +3 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-wc.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-wc.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt: - shard-skl: [PASS][23] -> [DMESG-WARN][24] ([i915#1982]) +15 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-skl6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-skl1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt.html * igt@kms_hdr@bpc-switch-dpms: - shard-skl: [PASS][25] -> [FAIL][26] ([i915#1188]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-skl1/igt@kms_hdr@bpc-switch-dpms.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-skl3/igt@kms_hdr@bpc-switch-dpms.html * igt@kms_plane_lowres@pipe-b-tiling-none: - shard-iclb: [PASS][27] -> [FAIL][28] ([i915#899]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-iclb4/igt@kms_plane_lowres@pipe-b-tiling-none.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-iclb8/igt@kms_plane_lowres@pipe-b-tiling-none.html * igt@kms_psr@psr2_sprite_plane_onoff: - shard-iclb: [PASS][29] -> [SKIP][30] ([fdo#109441]) +1 similar issue [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-iclb2/igt@kms_psr@psr2_sprite_plane_onoff.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-iclb6/igt@kms_psr@psr2_sprite_plane_onoff.html #### Possible fixes #### * {igt@core_hotunplug@unbind-rebind}: - shard-iclb: [DMESG-WARN][31] ([i915#1982]) -> [PASS][32] +1 similar issue [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-iclb6/igt@core_hotunplug@unbind-rebind.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-iclb2/igt@core_hotunplug@unbind-rebind.html * igt@gem_exec_reloc@basic-many-active@vecs0: - shard-glk: [FAIL][33] ([i915#2389]) -> [PASS][34] +2 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-glk1/igt@gem_exec_reloc@basic-many-active@vecs0.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-glk6/igt@gem_exec_reloc@basic-many-active@vecs0.html * igt@kms_cursor_legacy@all-pipes-torture-move: - shard-iclb: [DMESG-WARN][35] ([i915#128]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-iclb5/igt@kms_cursor_legacy@all-pipes-torture-move.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-iclb7/igt@kms_cursor_legacy@all-pipes-torture-move.html * igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size: - shard-skl: [DMESG-WARN][37] ([i915#1982]) -> [PASS][38] +2 similar issues [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-skl8/igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-skl8/igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size.html * igt@kms_cursor_legacy@basic-flip-before-cursor-atomic: - shard-apl: [DMESG-WARN][39] ([i915#1635] / [i915#1982]) -> [PASS][40] +1 similar issue [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-apl3/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-apl7/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1: - shard-kbl: [DMESG-WARN][41] ([i915#180]) -> [PASS][42] +5 similar issues [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-kbl6/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move: - shard-tglb: [DMESG-WARN][43] ([i915#1982]) -> [PASS][44] +1 similar issue [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-tglb8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [FAIL][45] ([fdo#108145] / [i915#265]) -> [PASS][46] +1 similar issue [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-skl5/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt@kms_psr@psr2_cursor_plane_move: - shard-iclb: [SKIP][47] ([fdo#109441]) -> [PASS][48] +1 similar issue [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-iclb7/igt@kms_psr@psr2_cursor_plane_move.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html * igt@kms_setmode@basic: - shard-apl: [FAIL][49] ([i915#1635] / [i915#31]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-apl1/igt@kms_setmode@basic.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-apl2/igt@kms_setmode@basic.html #### Warnings #### * igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled: - shard-apl: [FAIL][51] ([i915#1635]) -> [FAIL][52] ([i915#1635] / [i915#2541]) [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-apl6/igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-apl8/igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled.html * igt@kms_content_protection@lic: - shard-apl: [TIMEOUT][53] ([i915#1319] / [i915#1635]) -> [FAIL][54] ([fdo#110321] / [i915#1635]) [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-apl2/igt@kms_content_protection@lic.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-apl7/igt@kms_content_protection@lic.html * igt@kms_flip@flip-vs-expired-vblank@a-edp1: - shard-skl: [DMESG-FAIL][55] ([i915#1982]) -> [DMESG-WARN][56] ([i915#1982]) [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-skl2/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-skl10/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346 [i915#2377]: https://gitlab.freedesktop.org/drm/intel/issues/2377 [i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389 [i915#2424]: https://gitlab.freedesktop.org/drm/intel/issues/2424 [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521 [i915#2541]: https://gitlab.freedesktop.org/drm/intel/issues/2541 [i915#2546]: https://gitlab.freedesktop.org/drm/intel/issues/2546 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#899]: https://gitlab.freedesktop.org/drm/intel/issues/899 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_9121 -> Patchwork_18668 CI-20190529: 20190529 CI_DRM_9121: d78555afe196c8a1329c9813ab7fe7538263ffde @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5806: 6adb80cd84310b6d90a5259768d03ebb2c30fe50 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18668: 74565d868b44da1883b376654ac2d8e8202c49af @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/index.html [-- Attachment #1.2: Type: text/html, Size: 16012 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] ✓ Fi.CI.IGT: success for Gen12 forcewake and multicast updates (rev2) 2020-10-10 0:06 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork @ 2020-10-10 1:59 ` Matt Roper 0 siblings, 0 replies; 11+ messages in thread From: Matt Roper @ 2020-10-10 1:59 UTC (permalink / raw) To: intel-gfx On Sat, Oct 10, 2020 at 12:06:43AM +0000, Patchwork wrote: > == Series Details == > > Series: Gen12 forcewake and multicast updates (rev2) > URL : https://patchwork.freedesktop.org/series/82359/ > State : success > > == Summary == > > CI Bug Log - changes from CI_DRM_9121_full -> Patchwork_18668_full > ==================================================== > > Summary > ------- > > **SUCCESS** > > No regressions found. > Applied to dinq; thanks Jose for the review. Matt > > > Known issues > ------------ > > Here are the changes found in Patchwork_18668_full that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt@feature_discovery@psr2: > - shard-iclb: [PASS][1] -> [SKIP][2] ([i915#658]) > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-iclb2/igt@feature_discovery@psr2.html > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-iclb5/igt@feature_discovery@psr2.html > > * igt@gem_exec_balancer@nop: > - shard-apl: [PASS][3] -> [INCOMPLETE][4] ([i915#1635] / [i915#2377]) > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-apl2/igt@gem_exec_balancer@nop.html > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-apl4/igt@gem_exec_balancer@nop.html > > * igt@gem_huc_copy@huc-copy: > - shard-tglb: [PASS][5] -> [SKIP][6] ([i915#2190]) > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-tglb1/igt@gem_huc_copy@huc-copy.html > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-tglb6/igt@gem_huc_copy@huc-copy.html > > * igt@gem_userptr_blits@unsync-unmap-cycles: > - shard-skl: [PASS][7] -> [TIMEOUT][8] ([i915#2424]) > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-skl10/igt@gem_userptr_blits@unsync-unmap-cycles.html > [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-skl2/igt@gem_userptr_blits@unsync-unmap-cycles.html > > * igt@kms_big_fb@yf-tiled-16bpp-rotate-180: > - shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) +2 similar issues > [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-kbl7/igt@kms_big_fb@yf-tiled-16bpp-rotate-180.html > [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-kbl6/igt@kms_big_fb@yf-tiled-16bpp-rotate-180.html > > * igt@kms_cursor_edge_walk@pipe-c-128x128-left-edge: > - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([i915#1635] / [i915#1982]) > [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-apl4/igt@kms_cursor_edge_walk@pipe-c-128x128-left-edge.html > [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-apl1/igt@kms_cursor_edge_walk@pipe-c-128x128-left-edge.html > > * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions: > - shard-skl: [PASS][13] -> [FAIL][14] ([i915#2346]) > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html > [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html > > * igt@kms_flip@flip-vs-suspend-interruptible@c-dp1: > - shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([i915#180]) +1 similar issue > [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-kbl6/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html > [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html > > * igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack: > - shard-glk: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) > [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-glk8/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack.html > [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-glk3/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack.html > > * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-gtt: > - shard-snb: [PASS][19] -> [FAIL][20] ([i915#2546]) > [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-snb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-gtt.html > [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-snb4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-gtt.html > > * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-wc: > - shard-tglb: [PASS][21] -> [DMESG-WARN][22] ([i915#1982]) +3 similar issues > [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-wc.html > [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-wc.html > > * igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt: > - shard-skl: [PASS][23] -> [DMESG-WARN][24] ([i915#1982]) +15 similar issues > [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-skl6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt.html > [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-skl1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt.html > > * igt@kms_hdr@bpc-switch-dpms: > - shard-skl: [PASS][25] -> [FAIL][26] ([i915#1188]) > [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-skl1/igt@kms_hdr@bpc-switch-dpms.html > [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-skl3/igt@kms_hdr@bpc-switch-dpms.html > > * igt@kms_plane_lowres@pipe-b-tiling-none: > - shard-iclb: [PASS][27] -> [FAIL][28] ([i915#899]) > [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-iclb4/igt@kms_plane_lowres@pipe-b-tiling-none.html > [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-iclb8/igt@kms_plane_lowres@pipe-b-tiling-none.html > > * igt@kms_psr@psr2_sprite_plane_onoff: > - shard-iclb: [PASS][29] -> [SKIP][30] ([fdo#109441]) +1 similar issue > [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-iclb2/igt@kms_psr@psr2_sprite_plane_onoff.html > [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-iclb6/igt@kms_psr@psr2_sprite_plane_onoff.html > > > #### Possible fixes #### > > * {igt@core_hotunplug@unbind-rebind}: > - shard-iclb: [DMESG-WARN][31] ([i915#1982]) -> [PASS][32] +1 similar issue > [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-iclb6/igt@core_hotunplug@unbind-rebind.html > [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-iclb2/igt@core_hotunplug@unbind-rebind.html > > * igt@gem_exec_reloc@basic-many-active@vecs0: > - shard-glk: [FAIL][33] ([i915#2389]) -> [PASS][34] +2 similar issues > [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-glk1/igt@gem_exec_reloc@basic-many-active@vecs0.html > [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-glk6/igt@gem_exec_reloc@basic-many-active@vecs0.html > > * igt@kms_cursor_legacy@all-pipes-torture-move: > - shard-iclb: [DMESG-WARN][35] ([i915#128]) -> [PASS][36] > [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-iclb5/igt@kms_cursor_legacy@all-pipes-torture-move.html > [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-iclb7/igt@kms_cursor_legacy@all-pipes-torture-move.html > > * igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size: > - shard-skl: [DMESG-WARN][37] ([i915#1982]) -> [PASS][38] +2 similar issues > [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-skl8/igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size.html > [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-skl8/igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size.html > > * igt@kms_cursor_legacy@basic-flip-before-cursor-atomic: > - shard-apl: [DMESG-WARN][39] ([i915#1635] / [i915#1982]) -> [PASS][40] +1 similar issue > [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-apl3/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html > [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-apl7/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html > > * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1: > - shard-kbl: [DMESG-WARN][41] ([i915#180]) -> [PASS][42] +5 similar issues > [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-kbl6/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html > [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html > > * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move: > - shard-tglb: [DMESG-WARN][43] ([i915#1982]) -> [PASS][44] +1 similar issue > [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-tglb8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html > [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html > > * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: > - shard-skl: [FAIL][45] ([fdo#108145] / [i915#265]) -> [PASS][46] +1 similar issue > [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html > [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-skl5/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html > > * igt@kms_psr@psr2_cursor_plane_move: > - shard-iclb: [SKIP][47] ([fdo#109441]) -> [PASS][48] +1 similar issue > [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-iclb7/igt@kms_psr@psr2_cursor_plane_move.html > [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html > > * igt@kms_setmode@basic: > - shard-apl: [FAIL][49] ([i915#1635] / [i915#31]) -> [PASS][50] > [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-apl1/igt@kms_setmode@basic.html > [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-apl2/igt@kms_setmode@basic.html > > > #### Warnings #### > > * igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled: > - shard-apl: [FAIL][51] ([i915#1635]) -> [FAIL][52] ([i915#1635] / [i915#2541]) > [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-apl6/igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled.html > [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-apl8/igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled.html > > * igt@kms_content_protection@lic: > - shard-apl: [TIMEOUT][53] ([i915#1319] / [i915#1635]) -> [FAIL][54] ([fdo#110321] / [i915#1635]) > [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-apl2/igt@kms_content_protection@lic.html > [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-apl7/igt@kms_content_protection@lic.html > > * igt@kms_flip@flip-vs-expired-vblank@a-edp1: > - shard-skl: [DMESG-FAIL][55] ([i915#1982]) -> [DMESG-WARN][56] ([i915#1982]) > [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9121/shard-skl2/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html > [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/shard-skl10/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html > > > {name}: This element is suppressed. This means it is ignored when computing > the status of the difference (SUCCESS, WARNING, or FAILURE). > > [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 > [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 > [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 > [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 > [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 > [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 > [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 > [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 > [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 > [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 > [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346 > [i915#2377]: https://gitlab.freedesktop.org/drm/intel/issues/2377 > [i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389 > [i915#2424]: https://gitlab.freedesktop.org/drm/intel/issues/2424 > [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521 > [i915#2541]: https://gitlab.freedesktop.org/drm/intel/issues/2541 > [i915#2546]: https://gitlab.freedesktop.org/drm/intel/issues/2546 > [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 > [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 > [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 > [i915#899]: https://gitlab.freedesktop.org/drm/intel/issues/899 > > > Participating hosts (11 -> 11) > ------------------------------ > > No changes in participating hosts > > > Build changes > ------------- > > * Linux: CI_DRM_9121 -> Patchwork_18668 > > CI-20190529: 20190529 > CI_DRM_9121: d78555afe196c8a1329c9813ab7fe7538263ffde @ git://anongit.freedesktop.org/gfx-ci/linux > IGT_5806: 6adb80cd84310b6d90a5259768d03ebb2c30fe50 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > Patchwork_18668: 74565d868b44da1883b376654ac2d8e8202c49af @ git://anongit.freedesktop.org/gfx-ci/linux > piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18668/index.html -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2020-10-10 1:59 UTC | newest] Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-10-09 19:44 [Intel-gfx] [PATCH v2 0/3] Gen12 forcewake and multicast updates Matt Roper 2020-10-09 19:44 ` [Intel-gfx] [PATCH v2 1/3] drm/i915: Rename FORCEWAKE_BLITTER to FORCEWAKE_GT Matt Roper 2020-10-09 22:09 ` Souza, Jose 2020-10-09 19:44 ` [Intel-gfx] [PATCH v2 2/3] drm/i915: Update gen12 forcewake table Matt Roper 2020-10-09 22:21 ` Souza, Jose 2020-10-09 19:44 ` [Intel-gfx] [PATCH v2 3/3] drm/i915: Update gen12 multicast register ranges Matt Roper 2020-10-09 20:40 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Gen12 forcewake and multicast updates (rev2) Patchwork 2020-10-09 20:41 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2020-10-09 21:02 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2020-10-10 0:06 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 2020-10-10 1:59 ` Matt Roper
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.