* [PATCH] target/riscv: Fix implementation of HLVX.WU instruction
@ 2020-10-13 17:22 Georg Kotheimer
2020-10-13 19:42 ` Philippe Mathieu-Daudé
2020-10-14 19:41 ` Alistair Francis
0 siblings, 2 replies; 4+ messages in thread
From: Georg Kotheimer @ 2020-10-13 17:22 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: Georg Kotheimer
The HLVX.WU instruction is supposed to read a machine word,
but prior to this change it read a byte instead.
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
---
target/riscv/op_helper.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 9b9ada45a9..3b7bd6ee88 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -334,12 +334,12 @@ target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address,
riscv_cpu_set_two_stage_lookup(env, true);
switch (memop) {
- case MO_TEUL:
- pte = cpu_ldub_data_ra(env, address, GETPC());
- break;
case MO_TEUW:
pte = cpu_lduw_data_ra(env, address, GETPC());
break;
+ case MO_TEUL:
+ pte = cpu_ldl_data_ra(env, address, GETPC());
+ break;
default:
g_assert_not_reached();
}
--
2.25.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] target/riscv: Fix implementation of HLVX.WU instruction
2020-10-13 17:22 [PATCH] target/riscv: Fix implementation of HLVX.WU instruction Georg Kotheimer
@ 2020-10-13 19:42 ` Philippe Mathieu-Daudé
2020-10-14 19:41 ` Alistair Francis
1 sibling, 0 replies; 4+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-10-13 19:42 UTC (permalink / raw)
To: Georg Kotheimer, qemu-devel, qemu-riscv
On 10/13/20 7:22 PM, Georg Kotheimer wrote:
> The HLVX.WU instruction is supposed to read a machine word,
> but prior to this change it read a byte instead.
>
Fixes: 8c5362acb57 ("target/riscv: Allow generating hlv/hlvx/hsv
instructions")
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
> ---
> target/riscv/op_helper.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index 9b9ada45a9..3b7bd6ee88 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -334,12 +334,12 @@ target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address,
> riscv_cpu_set_two_stage_lookup(env, true);
>
> switch (memop) {
> - case MO_TEUL:
> - pte = cpu_ldub_data_ra(env, address, GETPC());
> - break;
> case MO_TEUW:
> pte = cpu_lduw_data_ra(env, address, GETPC());
> break;
> + case MO_TEUL:
> + pte = cpu_ldl_data_ra(env, address, GETPC());
> + break;
> default:
> g_assert_not_reached();
> }
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] target/riscv: Fix implementation of HLVX.WU instruction
2020-10-13 17:22 [PATCH] target/riscv: Fix implementation of HLVX.WU instruction Georg Kotheimer
@ 2020-10-14 19:41 ` Alistair Francis
2020-10-14 19:41 ` Alistair Francis
1 sibling, 0 replies; 4+ messages in thread
From: Alistair Francis @ 2020-10-14 19:41 UTC (permalink / raw)
To: Georg Kotheimer; +Cc: open list:RISC-V, qemu-devel@nongnu.org Developers
On Tue, Oct 13, 2020 at 10:23 AM Georg Kotheimer
<georg.kotheimer@kernkonzept.com> wrote:
>
> The HLVX.WU instruction is supposed to read a machine word,
> but prior to this change it read a byte instead.
>
> Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/op_helper.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index 9b9ada45a9..3b7bd6ee88 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -334,12 +334,12 @@ target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address,
> riscv_cpu_set_two_stage_lookup(env, true);
>
> switch (memop) {
> - case MO_TEUL:
> - pte = cpu_ldub_data_ra(env, address, GETPC());
> - break;
> case MO_TEUW:
> pte = cpu_lduw_data_ra(env, address, GETPC());
> break;
> + case MO_TEUL:
> + pte = cpu_ldl_data_ra(env, address, GETPC());
> + break;
> default:
> g_assert_not_reached();
> }
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] target/riscv: Fix implementation of HLVX.WU instruction
@ 2020-10-14 19:41 ` Alistair Francis
0 siblings, 0 replies; 4+ messages in thread
From: Alistair Francis @ 2020-10-14 19:41 UTC (permalink / raw)
To: Georg Kotheimer; +Cc: qemu-devel@nongnu.org Developers, open list:RISC-V
On Tue, Oct 13, 2020 at 10:23 AM Georg Kotheimer
<georg.kotheimer@kernkonzept.com> wrote:
>
> The HLVX.WU instruction is supposed to read a machine word,
> but prior to this change it read a byte instead.
>
> Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/op_helper.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index 9b9ada45a9..3b7bd6ee88 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -334,12 +334,12 @@ target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address,
> riscv_cpu_set_two_stage_lookup(env, true);
>
> switch (memop) {
> - case MO_TEUL:
> - pte = cpu_ldub_data_ra(env, address, GETPC());
> - break;
> case MO_TEUW:
> pte = cpu_lduw_data_ra(env, address, GETPC());
> break;
> + case MO_TEUL:
> + pte = cpu_ldl_data_ra(env, address, GETPC());
> + break;
> default:
> g_assert_not_reached();
> }
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2020-10-14 19:54 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2020-10-13 17:22 [PATCH] target/riscv: Fix implementation of HLVX.WU instruction Georg Kotheimer
2020-10-13 19:42 ` Philippe Mathieu-Daudé
2020-10-14 19:41 ` Alistair Francis
2020-10-14 19:41 ` Alistair Francis
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