* [PATCH 1/2] drm:amdgpu: check before setting hw priority
@ 2020-10-14 13:52 Nirmoy Das
2020-10-14 13:52 ` [PATCH 2/2] drm/amdgpu: enable only one compute queue for raven Nirmoy Das
2020-10-16 2:01 ` [PATCH 1/2] drm:amdgpu: check before setting hw priority Liu, Aaron
0 siblings, 2 replies; 6+ messages in thread
From: Nirmoy Das @ 2020-10-14 13:52 UTC (permalink / raw)
To: amd-gfx
Cc: alexander.deucher, Nirmoy Das, Christian.Koenig, Guchun.Chen, Aaron.Liu
Check validity of drm_gpu_scheduler before setting hw priority.
Also fix a minor indentation issue.
Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index a03398c87344..c8da0978d4f6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -504,9 +504,9 @@ struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
}
static void amdgpu_ctx_set_entity_priority(struct amdgpu_ctx *ctx,
- struct amdgpu_ctx_entity *aentity,
- int hw_ip,
- enum drm_sched_priority priority)
+ struct amdgpu_ctx_entity *aentity,
+ int hw_ip,
+ enum drm_sched_priority priority)
{
struct amdgpu_device *adev = ctx->adev;
unsigned int hw_prio;
@@ -523,6 +523,9 @@ static void amdgpu_ctx_set_entity_priority(struct amdgpu_ctx *ctx,
hw_prio = array_index_nospec(hw_prio, AMDGPU_RING_PRIO_MAX);
scheds = adev->gpu_sched[hw_ip][hw_prio].sched;
num_scheds = adev->gpu_sched[hw_ip][hw_prio].num_scheds;
+ if (!scheds || !num_scheds)
+ return;
+
drm_sched_entity_modify_sched(&aentity->entity, scheds,
num_scheds);
}
--
2.28.0
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/2] drm/amdgpu: enable only one compute queue for raven
2020-10-14 13:52 [PATCH 1/2] drm:amdgpu: check before setting hw priority Nirmoy Das
@ 2020-10-14 13:52 ` Nirmoy Das
2020-10-14 15:46 ` Nirmoy
2020-10-16 13:56 ` Alex Deucher
2020-10-16 2:01 ` [PATCH 1/2] drm:amdgpu: check before setting hw priority Liu, Aaron
1 sibling, 2 replies; 6+ messages in thread
From: Nirmoy Das @ 2020-10-14 13:52 UTC (permalink / raw)
To: amd-gfx
Cc: alexander.deucher, Nirmoy Das, Christian.Koenig, Guchun.Chen, Aaron.Liu
Because of firmware bug, Raven asics can't handle jobs
scheduled to multiple compute queues. So enable only one
compute queue till we have a firmware fix.
Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 4 ++++
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 11 ++++++++++-
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 8c9bacfdbc30..ca2ac985b300 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -195,6 +195,10 @@ static bool amdgpu_gfx_is_multipipe_capable(struct amdgpu_device *adev)
bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
int queue)
{
+ /* We only enable one compute queue for Raven */
+ if (adev->asic_type == CHIP_RAVEN)
+ return false;
+
/* Policy: make queue 0 of each pipe as high priority compute queue */
return (queue == 0);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 0d8e203b10ef..f3fc9ad8bc20 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -4633,7 +4633,16 @@ static int gfx_v9_0_early_init(void *handle)
adev->gfx.num_gfx_rings = 0;
else
adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
- adev->gfx.num_compute_rings = amdgpu_num_kcq;
+
+ /* raven firmware currently can not load balance jobs
+ * among multiple compute queues. Enable only one
+ * compute queue till we have a firmware fix.
+ */
+ if (adev->asic_type == CHIP_RAVEN)
+ adev->gfx.num_compute_rings = 1;
+ else
+ adev->gfx.num_compute_rings = amdgpu_num_kcq;
+
gfx_v9_0_set_kiq_pm4_funcs(adev);
gfx_v9_0_set_ring_funcs(adev);
gfx_v9_0_set_irq_funcs(adev);
--
2.28.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] drm/amdgpu: enable only one compute queue for raven
2020-10-14 13:52 ` [PATCH 2/2] drm/amdgpu: enable only one compute queue for raven Nirmoy Das
@ 2020-10-14 15:46 ` Nirmoy
2020-10-16 13:56 ` Alex Deucher
1 sibling, 0 replies; 6+ messages in thread
From: Nirmoy @ 2020-10-14 15:46 UTC (permalink / raw)
To: Nirmoy Das, amd-gfx
Cc: alexander.deucher, Christian.Koenig, Guchun.Chen, Aaron.Liu
Please ignore this patch, it didn't workaround the fw bug.
Regards,
Nirmoy
On 10/14/20 3:52 PM, Nirmoy Das wrote:
> Because of firmware bug, Raven asics can't handle jobs
> scheduled to multiple compute queues. So enable only one
> compute queue till we have a firmware fix.
>
> Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 4 ++++
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 11 ++++++++++-
> 2 files changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> index 8c9bacfdbc30..ca2ac985b300 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> @@ -195,6 +195,10 @@ static bool amdgpu_gfx_is_multipipe_capable(struct amdgpu_device *adev)
> bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
> int queue)
> {
> + /* We only enable one compute queue for Raven */
> + if (adev->asic_type == CHIP_RAVEN)
> + return false;
> +
> /* Policy: make queue 0 of each pipe as high priority compute queue */
> return (queue == 0);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 0d8e203b10ef..f3fc9ad8bc20 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -4633,7 +4633,16 @@ static int gfx_v9_0_early_init(void *handle)
> adev->gfx.num_gfx_rings = 0;
> else
> adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
> - adev->gfx.num_compute_rings = amdgpu_num_kcq;
> +
> + /* raven firmware currently can not load balance jobs
> + * among multiple compute queues. Enable only one
> + * compute queue till we have a firmware fix.
> + */
> + if (adev->asic_type == CHIP_RAVEN)
> + adev->gfx.num_compute_rings = 1;
> + else
> + adev->gfx.num_compute_rings = amdgpu_num_kcq;
> +
> gfx_v9_0_set_kiq_pm4_funcs(adev);
> gfx_v9_0_set_ring_funcs(adev);
> gfx_v9_0_set_irq_funcs(adev);
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH 1/2] drm:amdgpu: check before setting hw priority
2020-10-14 13:52 [PATCH 1/2] drm:amdgpu: check before setting hw priority Nirmoy Das
2020-10-14 13:52 ` [PATCH 2/2] drm/amdgpu: enable only one compute queue for raven Nirmoy Das
@ 2020-10-16 2:01 ` Liu, Aaron
1 sibling, 0 replies; 6+ messages in thread
From: Liu, Aaron @ 2020-10-16 2:01 UTC (permalink / raw)
To: Das, Nirmoy, amd-gfx; +Cc: Deucher, Alexander, Koenig, Christian, Chen, Guchun
[AMD Public Use]
Series is:
Tested-by: Aaron Liu <aaron.liu@amd.com>
--
Best Regards
Aaron Liu
-----Original Message-----
From: Das, Nirmoy <Nirmoy.Das@amd.com>
Sent: Wednesday, October 14, 2020 9:53 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>; Chen, Guchun <Guchun.Chen@amd.com>; Liu, Aaron <Aaron.Liu@amd.com>; Das, Nirmoy <Nirmoy.Das@amd.com>
Subject: [PATCH 1/2] drm:amdgpu: check before setting hw priority
Check validity of drm_gpu_scheduler before setting hw priority.
Also fix a minor indentation issue.
Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index a03398c87344..c8da0978d4f6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -504,9 +504,9 @@ struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, }
static void amdgpu_ctx_set_entity_priority(struct amdgpu_ctx *ctx,
- struct amdgpu_ctx_entity *aentity,
- int hw_ip,
- enum drm_sched_priority priority)
+ struct amdgpu_ctx_entity *aentity,
+ int hw_ip,
+ enum drm_sched_priority priority)
{
struct amdgpu_device *adev = ctx->adev;
unsigned int hw_prio;
@@ -523,6 +523,9 @@ static void amdgpu_ctx_set_entity_priority(struct amdgpu_ctx *ctx,
hw_prio = array_index_nospec(hw_prio, AMDGPU_RING_PRIO_MAX);
scheds = adev->gpu_sched[hw_ip][hw_prio].sched;
num_scheds = adev->gpu_sched[hw_ip][hw_prio].num_scheds;
+ if (!scheds || !num_scheds)
+ return;
+
drm_sched_entity_modify_sched(&aentity->entity, scheds,
num_scheds);
}
--
2.28.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] drm/amdgpu: enable only one compute queue for raven
2020-10-14 13:52 ` [PATCH 2/2] drm/amdgpu: enable only one compute queue for raven Nirmoy Das
2020-10-14 15:46 ` Nirmoy
@ 2020-10-16 13:56 ` Alex Deucher
2020-10-16 14:33 ` Nirmoy
1 sibling, 1 reply; 6+ messages in thread
From: Alex Deucher @ 2020-10-16 13:56 UTC (permalink / raw)
To: Nirmoy Das
Cc: Deucher, Alexander, Aaron Liu, Christian Koenig, amd-gfx list,
Chen, Guchun
On Wed, Oct 14, 2020 at 9:53 AM Nirmoy Das <nirmoy.das@amd.com> wrote:
>
> Because of firmware bug, Raven asics can't handle jobs
> scheduled to multiple compute queues. So enable only one
> compute queue till we have a firmware fix.
>
> Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 4 ++++
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 11 ++++++++++-
> 2 files changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> index 8c9bacfdbc30..ca2ac985b300 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> @@ -195,6 +195,10 @@ static bool amdgpu_gfx_is_multipipe_capable(struct amdgpu_device *adev)
> bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
> int queue)
> {
> + /* We only enable one compute queue for Raven */
> + if (adev->asic_type == CHIP_RAVEN)
> + return false;
> +
> /* Policy: make queue 0 of each pipe as high priority compute queue */
> return (queue == 0);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 0d8e203b10ef..f3fc9ad8bc20 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -4633,7 +4633,16 @@ static int gfx_v9_0_early_init(void *handle)
> adev->gfx.num_gfx_rings = 0;
> else
> adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
> - adev->gfx.num_compute_rings = amdgpu_num_kcq;
> +
> + /* raven firmware currently can not load balance jobs
> + * among multiple compute queues. Enable only one
> + * compute queue till we have a firmware fix.
> + */
> + if (adev->asic_type == CHIP_RAVEN)
> + adev->gfx.num_compute_rings = 1;
> + else
> + adev->gfx.num_compute_rings = amdgpu_num_kcq;
> +
I would suggest something like this instead so we can override easily
for testing:
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index abddcd9dab3d..a2954b41e59d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1376,6 +1376,12 @@ static int amdgpu_device_check_arguments(struct
amdgpu_device *adev)
if (amdgpu_num_kcq == -1) {
amdgpu_num_kcq = 8;
+ /* raven firmware currently can not load balance jobs
+ * among multiple compute queues. Enable only one
+ * compute queue till we have a firmware fix.
+ */
+ if (adev->asic_type == CHIP_RAVEN)
+ amdgpu_num_kcq = 1;
} else if (amdgpu_num_kcq > 8 || amdgpu_num_kcq < 0) {
amdgpu_num_kcq = 8;
dev_warn(adev->dev, "set kernel compute queue number
to 8 due to invalid parameter provided by user\n");
Alex
> gfx_v9_0_set_kiq_pm4_funcs(adev);
> gfx_v9_0_set_ring_funcs(adev);
> gfx_v9_0_set_irq_funcs(adev);
> --
> 2.28.0
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] drm/amdgpu: enable only one compute queue for raven
2020-10-16 13:56 ` Alex Deucher
@ 2020-10-16 14:33 ` Nirmoy
0 siblings, 0 replies; 6+ messages in thread
From: Nirmoy @ 2020-10-16 14:33 UTC (permalink / raw)
To: Alex Deucher, Nirmoy Das
Cc: Deucher, Alexander, Aaron Liu, Christian Koenig, amd-gfx list,
Chen, Guchun
On 10/16/20 3:56 PM, Alex Deucher wrote:
> On Wed, Oct 14, 2020 at 9:53 AM Nirmoy Das <nirmoy.das@amd.com> wrote:
>> Because of firmware bug, Raven asics can't handle jobs
>> scheduled to multiple compute queues. So enable only one
>> compute queue till we have a firmware fix.
>>
>> Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 4 ++++
>> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 11 ++++++++++-
>> 2 files changed, 14 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
>> index 8c9bacfdbc30..ca2ac985b300 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
>> @@ -195,6 +195,10 @@ static bool amdgpu_gfx_is_multipipe_capable(struct amdgpu_device *adev)
>> bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
>> int queue)
>> {
>> + /* We only enable one compute queue for Raven */
>> + if (adev->asic_type == CHIP_RAVEN)
>> + return false;
>> +
>> /* Policy: make queue 0 of each pipe as high priority compute queue */
>> return (queue == 0);
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> index 0d8e203b10ef..f3fc9ad8bc20 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> @@ -4633,7 +4633,16 @@ static int gfx_v9_0_early_init(void *handle)
>> adev->gfx.num_gfx_rings = 0;
>> else
>> adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
>> - adev->gfx.num_compute_rings = amdgpu_num_kcq;
>> +
>> + /* raven firmware currently can not load balance jobs
>> + * among multiple compute queues. Enable only one
>> + * compute queue till we have a firmware fix.
>> + */
>> + if (adev->asic_type == CHIP_RAVEN)
>> + adev->gfx.num_compute_rings = 1;
>> + else
>> + adev->gfx.num_compute_rings = amdgpu_num_kcq;
>> +
> I would suggest something like this instead so we can override easily
> for testing:
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index abddcd9dab3d..a2954b41e59d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1376,6 +1376,12 @@ static int amdgpu_device_check_arguments(struct
> amdgpu_device *adev)
>
> if (amdgpu_num_kcq == -1) {
> amdgpu_num_kcq = 8;
> + /* raven firmware currently can not load balance jobs
> + * among multiple compute queues. Enable only one
> + * compute queue till we have a firmware fix.
> + */
> + if (adev->asic_type == CHIP_RAVEN)
> + amdgpu_num_kcq = 1;
> } else if (amdgpu_num_kcq > 8 || amdgpu_num_kcq < 0) {
> amdgpu_num_kcq = 8;
> dev_warn(adev->dev, "set kernel compute queue number
> to 8 due to invalid parameter provided by user\n");
>
Thanks, this looks much better,
I will update.
Nirmoy
> Alex
>
>> gfx_v9_0_set_kiq_pm4_funcs(adev);
>> gfx_v9_0_set_ring_funcs(adev);
>> gfx_v9_0_set_irq_funcs(adev);
>> --
>> 2.28.0
>>
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=04%7C01%7Cnirmoy.das%40amd.com%7Cc3012ca19bf149cb880608d871db5494%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637384534119165172%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=Rcd6aMUMxxvDcwi695IYNvvhHfpKAq74KAOT9Vpzvmo%3D&reserved=0
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-10-16 14:34 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-10-14 13:52 [PATCH 1/2] drm:amdgpu: check before setting hw priority Nirmoy Das
2020-10-14 13:52 ` [PATCH 2/2] drm/amdgpu: enable only one compute queue for raven Nirmoy Das
2020-10-14 15:46 ` Nirmoy
2020-10-16 13:56 ` Alex Deucher
2020-10-16 14:33 ` Nirmoy
2020-10-16 2:01 ` [PATCH 1/2] drm:amdgpu: check before setting hw priority Liu, Aaron
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