* [Intel-gfx] [PATCH v10 01/11] HAX to make DSC work on the icelake test system
@ 2020-10-08 21:45 Manasi Navare
2020-10-08 21:45 ` [Intel-gfx] [PATCH v10 02/11] drm/i915/display: Rename pipe_timings to transcoder_timings Manasi Navare
` (17 more replies)
0 siblings, 18 replies; 50+ messages in thread
From: Manasi Navare @ 2020-10-08 21:45 UTC (permalink / raw)
To: intel-gfx
From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
DSC is available on the display emulator, but not set in DPCD.
Override the entries to allow bigjoiner testing.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
drivers/gpu/drm/drm_dp_helper.c | 4 ++--
include/drm/drm_dp_helper.h | 1 +
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 478dd51f738d..7f355c1c49c0 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1987,7 +1987,7 @@ u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
return 4;
if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
- return 2;
+ return 4;
if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
return 1;
} else {
@@ -2011,7 +2011,7 @@ u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
return 4;
if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
- return 2;
+ return 4;
if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
return 1;
}
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 159191c1ae75..1eeffb670ad9 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1502,6 +1502,7 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SI
static inline bool
drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
{
+ return dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT];
return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] &
DP_DSC_DECOMPRESSION_IS_SUPPORTED;
}
--
2.19.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Intel-gfx] [PATCH v10 02/11] drm/i915/display: Rename pipe_timings to transcoder_timings
2020-10-08 21:45 [Intel-gfx] [PATCH v10 01/11] HAX to make DSC work on the icelake test system Manasi Navare
@ 2020-10-08 21:45 ` Manasi Navare
2020-10-08 21:45 ` [Intel-gfx] [PATCH v10 03/11] drm/i915: Add hw.pipe_mode to allow bigjoiner pipe/transcoder split Manasi Navare
` (16 subsequent siblings)
17 siblings, 0 replies; 50+ messages in thread
From: Manasi Navare @ 2020-10-08 21:45 UTC (permalink / raw)
To: intel-gfx
No functional changes in this patch.
With Bigjoiner, there are 2 pipes driving 2 halfs of 1
transcoder. The transcoder_mode has the full timings, and is used
for configuring the transcoder with the intended mode after
joining the 2 halves.
To clear the confusion, we rename intel_set_pipe_timings to
intel_set_transcoder_timings
v2:
* Split the renaming into separate patch (Ville)
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 22 ++++++++++----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 907e1d155443..9274ffa6e03a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -154,7 +154,7 @@ static void ilk_pch_clock_get(struct intel_crtc *crtc,
static int intel_framebuffer_init(struct intel_framebuffer *ifb,
struct drm_i915_gem_object *obj,
struct drm_mode_fb_cmd2 *mode_cmd);
-static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state);
+static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
const struct intel_link_m_n *m_n,
@@ -7003,7 +7003,7 @@ static void ilk_crtc_enable(struct intel_atomic_state *state,
if (intel_crtc_has_dp_encoder(new_crtc_state))
intel_dp_set_m_n(new_crtc_state, M1_N1);
- intel_set_pipe_timings(new_crtc_state);
+ intel_set_transcoder_timings(new_crtc_state);
intel_set_pipe_src_size(new_crtc_state);
if (new_crtc_state->has_pch_encoder)
@@ -7148,7 +7148,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
intel_encoders_pre_enable(state, crtc);
if (!transcoder_is_dsi(cpu_transcoder))
- intel_set_pipe_timings(new_crtc_state);
+ intel_set_transcoder_timings(new_crtc_state);
intel_set_pipe_src_size(new_crtc_state);
@@ -7543,7 +7543,7 @@ static void valleyview_crtc_enable(struct intel_atomic_state *state,
if (intel_crtc_has_dp_encoder(new_crtc_state))
intel_dp_set_m_n(new_crtc_state, M1_N1);
- intel_set_pipe_timings(new_crtc_state);
+ intel_set_transcoder_timings(new_crtc_state);
intel_set_pipe_src_size(new_crtc_state);
if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
@@ -7611,7 +7611,7 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state,
if (intel_crtc_has_dp_encoder(new_crtc_state))
intel_dp_set_m_n(new_crtc_state, M1_N1);
- intel_set_pipe_timings(new_crtc_state);
+ intel_set_transcoder_timings(new_crtc_state);
intel_set_pipe_src_size(new_crtc_state);
i9xx_set_pipeconf(new_crtc_state);
@@ -8865,7 +8865,7 @@ static void i8xx_compute_dpll(struct intel_crtc *crtc,
crtc_state->dpll_hw_state.dpll = dpll;
}
-static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state)
+static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -8951,8 +8951,8 @@ static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK;
}
-static void intel_get_pipe_timings(struct intel_crtc *crtc,
- struct intel_crtc_state *pipe_config)
+static void intel_get_transcoder_timings(struct intel_crtc *crtc,
+ struct intel_crtc_state *pipe_config)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -9575,7 +9575,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
if (INTEL_GEN(dev_priv) < 4)
pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
- intel_get_pipe_timings(crtc, pipe_config);
+ intel_get_transcoder_timings(crtc, pipe_config);
intel_get_pipe_src_size(crtc, pipe_config);
i9xx_get_pfit_config(pipe_config);
@@ -10856,7 +10856,7 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc,
pipe_config->pixel_multiplier = 1;
}
- intel_get_pipe_timings(crtc, pipe_config);
+ intel_get_transcoder_timings(crtc, pipe_config);
intel_get_pipe_src_size(crtc, pipe_config);
ilk_get_pfit_config(pipe_config);
@@ -11273,7 +11273,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
INTEL_GEN(dev_priv) >= 11) {
hsw_get_ddi_port_state(crtc, pipe_config);
- intel_get_pipe_timings(crtc, pipe_config);
+ intel_get_transcoder_timings(crtc, pipe_config);
}
intel_get_pipe_src_size(crtc, pipe_config);
--
2.19.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Intel-gfx] [PATCH v10 03/11] drm/i915: Add hw.pipe_mode to allow bigjoiner pipe/transcoder split
2020-10-08 21:45 [Intel-gfx] [PATCH v10 01/11] HAX to make DSC work on the icelake test system Manasi Navare
2020-10-08 21:45 ` [Intel-gfx] [PATCH v10 02/11] drm/i915/display: Rename pipe_timings to transcoder_timings Manasi Navare
@ 2020-10-08 21:45 ` Manasi Navare
2020-10-08 21:45 ` [Intel-gfx] [PATCH v10 04/11] drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3 Manasi Navare
` (15 subsequent siblings)
17 siblings, 0 replies; 50+ messages in thread
From: Manasi Navare @ 2020-10-08 21:45 UTC (permalink / raw)
To: intel-gfx
From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
With bigjoiner, there will be 2 pipes driving 2 halfs of 1 transcoder,
because of this, we need a pipe_mode for various calculations, including
for example watermarks, plane clipping, etc.
v6:
* renaming in separate function, only pipe_mode here (Ville)
* Add description (Maarten)
v5:
* Rebase (Manasi)
v4:
* Manual rebase (Manasi)
v3:
* Change state to crtc_state, fix rebase err (Manasi)
v2:
* Manual Rebase (Manasi)
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 40 +++++-----
.../drm/i915/display/intel_display_types.h | 11 ++-
drivers/gpu/drm/i915/intel_pm.c | 76 +++++++++----------
3 files changed, 69 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 9274ffa6e03a..723766b1eae3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6166,18 +6166,16 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
static int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state)
{
- const struct drm_display_mode *adjusted_mode =
- &crtc_state->hw.adjusted_mode;
+ const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
int width, height;
if (crtc_state->pch_pfit.enabled) {
width = drm_rect_width(&crtc_state->pch_pfit.dst);
height = drm_rect_height(&crtc_state->pch_pfit.dst);
} else {
- width = adjusted_mode->crtc_hdisplay;
- height = adjusted_mode->crtc_vdisplay;
+ width = pipe_mode->crtc_hdisplay;
+ height = pipe_mode->crtc_vdisplay;
}
-
return skl_update_scaler(crtc_state, !crtc_state->hw.active,
SKL_CRTC_INDEX,
&crtc_state->scaler_state.scaler_id,
@@ -8085,7 +8083,7 @@ static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
{
- u32 pixel_rate = crtc_state->hw.adjusted_mode.crtc_clock;
+ u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock;
unsigned int pipe_w, pipe_h, pfit_w, pfit_h;
/*
@@ -8122,7 +8120,7 @@ static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
if (HAS_GMCH(dev_priv))
/* FIXME calculate proper pipe pixel rate for GMCH pfit */
crtc_state->pixel_rate =
- crtc_state->hw.adjusted_mode.crtc_clock;
+ crtc_state->hw.pipe_mode.crtc_clock;
else
crtc_state->pixel_rate =
ilk_pipe_pixel_rate(crtc_state);
@@ -8132,7 +8130,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
+ const struct drm_display_mode *pipe_mode = &pipe_config->hw.pipe_mode;
int clock_limit = dev_priv->max_dotclk_freq;
if (INTEL_GEN(dev_priv) < 4) {
@@ -8143,16 +8141,16 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
* is > 90% of the (display) core speed.
*/
if (intel_crtc_supports_double_wide(crtc) &&
- adjusted_mode->crtc_clock > clock_limit) {
+ pipe_mode->crtc_clock > clock_limit) {
clock_limit = dev_priv->max_dotclk_freq;
pipe_config->double_wide = true;
}
}
- if (adjusted_mode->crtc_clock > clock_limit) {
+ if (pipe_mode->crtc_clock > clock_limit) {
drm_dbg_kms(&dev_priv->drm,
"requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
- adjusted_mode->crtc_clock, clock_limit,
+ pipe_mode->crtc_clock, clock_limit,
yesno(pipe_config->double_wide));
return -EINVAL;
}
@@ -8195,7 +8193,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
* WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
*/
if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
- adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
+ pipe_mode->crtc_hsync_start == pipe_mode->crtc_hdisplay)
return -EINVAL;
intel_crtc_compute_pixel_rate(pipe_config);
@@ -12719,15 +12717,15 @@ static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
{
- const struct drm_display_mode *adjusted_mode =
- &crtc_state->hw.adjusted_mode;
+ const struct drm_display_mode *pipe_mode =
+ &crtc_state->hw.pipe_mode;
int linetime_wm;
if (!crtc_state->hw.enable)
return 0;
- linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
- adjusted_mode->crtc_clock);
+ linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
+ pipe_mode->crtc_clock);
return min(linetime_wm, 0x1ff);
}
@@ -13354,7 +13352,7 @@ intel_crtc_copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state)
crtc_state->hw.enable = crtc_state->uapi.enable;
crtc_state->hw.active = crtc_state->uapi.active;
crtc_state->hw.mode = crtc_state->uapi.mode;
- crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
+ crtc_state->hw.pipe_mode = crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
intel_crtc_copy_uapi_to_hw_state_nomodeset(crtc_state);
}
@@ -13456,7 +13454,7 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
* computation to clearly distinguish it from the adjusted mode, which
* can be changed by the connectors in the below retry loop.
*/
- drm_mode_get_hv_timing(&pipe_config->hw.mode,
+ drm_mode_get_hv_timing(&pipe_config->hw.pipe_mode,
&pipe_config->pipe_src_w,
&pipe_config->pipe_src_h);
@@ -13550,6 +13548,9 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
"hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
+ /* without bigjoiner, pipe_mode == adjusted_mode */
+ pipe_config->hw.pipe_mode = pipe_config->hw.adjusted_mode;
+
return 0;
}
@@ -18801,6 +18802,9 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
*/
crtc_state->inherited = true;
+ /* initialize pipe_mode */
+ crtc_state->hw.pipe_mode = crtc_state->hw.adjusted_mode;
+
intel_crtc_compute_pixel_rate(crtc_state);
intel_crtc_update_active_timings(crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 65ae2070576f..513576217d14 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -811,15 +811,22 @@ struct intel_crtc_state {
* The following members are used to verify the hardware state:
* - enable
* - active
- * - mode / adjusted_mode
+ * - mode/adjusted_mode
* - color property blobs.
*
* During initial hw readout, they need to be copied to uapi.
+ *
+ * Bigjoiner will allow a transcoder mode that spans 2 pipes;
+ * Use the pipe_mode for calculations like watermarks, pipe
+ * scaler, and bandwidth.
+ *
+ * Use adjusted_mode for things that need to know the full
+ * mode on the transcoder, which spans all pipes.
*/
struct {
bool active, enable;
struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
- struct drm_display_mode mode, adjusted_mode;
+ struct drm_display_mode mode, pipe_mode, adjusted_mode;
} hw;
/**
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8cd62402d597..1b9fd02f49b4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -899,12 +899,12 @@ static void pnv_update_wm(struct intel_crtc *unused_crtc)
crtc = single_enabled_crtc(dev_priv);
if (crtc) {
- const struct drm_display_mode *adjusted_mode =
- &crtc->config->hw.adjusted_mode;
+ const struct drm_display_mode *pipe_mode =
+ &crtc->config->hw.pipe_mode;
const struct drm_framebuffer *fb =
crtc->base.primary->state->fb;
int cpp = fb->format->cpp[0];
- int clock = adjusted_mode->crtc_clock;
+ int clock = pipe_mode->crtc_clock;
/* Display SR */
wm = intel_calculate_wm(clock, &pnv_display_wm,
@@ -1135,8 +1135,8 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
{
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
- const struct drm_display_mode *adjusted_mode =
- &crtc_state->hw.adjusted_mode;
+ const struct drm_display_mode *pipe_mode =
+ &crtc_state->hw.pipe_mode;
unsigned int latency = dev_priv->wm.pri_latency[level] * 10;
unsigned int clock, htotal, cpp, width, wm;
@@ -1163,8 +1163,8 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
level != G4X_WM_LEVEL_NORMAL)
cpp = max(cpp, 4u);
- clock = adjusted_mode->crtc_clock;
- htotal = adjusted_mode->crtc_htotal;
+ clock = pipe_mode->crtc_clock;
+ htotal = pipe_mode->crtc_htotal;
width = drm_rect_width(&plane_state->uapi.dst);
@@ -1660,8 +1660,8 @@ static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
{
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
- const struct drm_display_mode *adjusted_mode =
- &crtc_state->hw.adjusted_mode;
+ const struct drm_display_mode *pipe_mode =
+ &crtc_state->hw.pipe_mode;
unsigned int clock, htotal, cpp, width, wm;
if (dev_priv->wm.pri_latency[level] == 0)
@@ -1671,8 +1671,8 @@ static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
return 0;
cpp = plane_state->hw.fb->format->cpp[0];
- clock = adjusted_mode->crtc_clock;
- htotal = adjusted_mode->crtc_htotal;
+ clock = pipe_mode->crtc_clock;
+ htotal = pipe_mode->crtc_htotal;
width = crtc_state->pipe_src_w;
if (plane->id == PLANE_CURSOR) {
@@ -2261,12 +2261,12 @@ static void i965_update_wm(struct intel_crtc *unused_crtc)
if (crtc) {
/* self-refresh has much higher latency */
static const int sr_latency_ns = 12000;
- const struct drm_display_mode *adjusted_mode =
- &crtc->config->hw.adjusted_mode;
+ const struct drm_display_mode *pipe_mode =
+ &crtc->config->hw.pipe_mode;
const struct drm_framebuffer *fb =
crtc->base.primary->state->fb;
- int clock = adjusted_mode->crtc_clock;
- int htotal = adjusted_mode->crtc_htotal;
+ int clock = pipe_mode->crtc_clock;
+ int htotal = pipe_mode->crtc_htotal;
int hdisplay = crtc->config->pipe_src_w;
int cpp = fb->format->cpp[0];
int entries;
@@ -2345,8 +2345,8 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_A);
crtc = intel_get_crtc_for_plane(dev_priv, PLANE_A);
if (intel_crtc_active(crtc)) {
- const struct drm_display_mode *adjusted_mode =
- &crtc->config->hw.adjusted_mode;
+ const struct drm_display_mode *pipe_mode =
+ &crtc->config->hw.pipe_mode;
const struct drm_framebuffer *fb =
crtc->base.primary->state->fb;
int cpp;
@@ -2356,7 +2356,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
else
cpp = fb->format->cpp[0];
- planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
+ planea_wm = intel_calculate_wm(pipe_mode->crtc_clock,
wm_info, fifo_size, cpp,
pessimal_latency_ns);
enabled = crtc;
@@ -2372,8 +2372,8 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_B);
crtc = intel_get_crtc_for_plane(dev_priv, PLANE_B);
if (intel_crtc_active(crtc)) {
- const struct drm_display_mode *adjusted_mode =
- &crtc->config->hw.adjusted_mode;
+ const struct drm_display_mode *pipe_mode =
+ &crtc->config->hw.pipe_mode;
const struct drm_framebuffer *fb =
crtc->base.primary->state->fb;
int cpp;
@@ -2383,7 +2383,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
else
cpp = fb->format->cpp[0];
- planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
+ planeb_wm = intel_calculate_wm(pipe_mode->crtc_clock,
wm_info, fifo_size, cpp,
pessimal_latency_ns);
if (enabled == NULL)
@@ -2421,12 +2421,12 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
if (HAS_FW_BLC(dev_priv) && enabled) {
/* self-refresh has much higher latency */
static const int sr_latency_ns = 6000;
- const struct drm_display_mode *adjusted_mode =
- &enabled->config->hw.adjusted_mode;
+ const struct drm_display_mode *pipe_mode =
+ &enabled->config->hw.pipe_mode;
const struct drm_framebuffer *fb =
enabled->base.primary->state->fb;
- int clock = adjusted_mode->crtc_clock;
- int htotal = adjusted_mode->crtc_htotal;
+ int clock = pipe_mode->crtc_clock;
+ int htotal = pipe_mode->crtc_htotal;
int hdisplay = enabled->config->pipe_src_w;
int cpp;
int entries;
@@ -2474,7 +2474,7 @@ static void i845_update_wm(struct intel_crtc *unused_crtc)
{
struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
struct intel_crtc *crtc;
- const struct drm_display_mode *adjusted_mode;
+ const struct drm_display_mode *pipe_mode;
u32 fwater_lo;
int planea_wm;
@@ -2482,8 +2482,8 @@ static void i845_update_wm(struct intel_crtc *unused_crtc)
if (crtc == NULL)
return;
- adjusted_mode = &crtc->config->hw.adjusted_mode;
- planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
+ pipe_mode = &crtc->config->hw.pipe_mode;
+ planea_wm = intel_calculate_wm(pipe_mode->crtc_clock,
&i845_wm_info,
dev_priv->display.get_fifo_size(dev_priv, PLANE_A),
4, pessimal_latency_ns);
@@ -2573,7 +2573,7 @@ static u32 ilk_compute_pri_wm(const struct intel_crtc_state *crtc_state,
return method1;
method2 = ilk_wm_method2(crtc_state->pixel_rate,
- crtc_state->hw.adjusted_mode.crtc_htotal,
+ crtc_state->hw.pipe_mode.crtc_htotal,
drm_rect_width(&plane_state->uapi.dst),
cpp, mem_value);
@@ -2601,7 +2601,7 @@ static u32 ilk_compute_spr_wm(const struct intel_crtc_state *crtc_state,
method1 = ilk_wm_method1(crtc_state->pixel_rate, cpp, mem_value);
method2 = ilk_wm_method2(crtc_state->pixel_rate,
- crtc_state->hw.adjusted_mode.crtc_htotal,
+ crtc_state->hw.pipe_mode.crtc_htotal,
drm_rect_width(&plane_state->uapi.dst),
cpp, mem_value);
return min(method1, method2);
@@ -2626,7 +2626,7 @@ static u32 ilk_compute_cur_wm(const struct intel_crtc_state *crtc_state,
cpp = plane_state->hw.fb->format->cpp[0];
return ilk_wm_method2(crtc_state->pixel_rate,
- crtc_state->hw.adjusted_mode.crtc_htotal,
+ crtc_state->hw.pipe_mode.crtc_htotal,
drm_rect_width(&plane_state->uapi.dst),
cpp, mem_value);
}
@@ -3883,7 +3883,7 @@ static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
if (!crtc_state->hw.active)
return true;
- if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
+ if (crtc_state->hw.pipe_mode.flags & DRM_MODE_FLAG_INTERLACE)
return false;
intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
@@ -4174,8 +4174,8 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
*/
total_slice_mask = dbuf_slice_mask;
for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
- const struct drm_display_mode *adjusted_mode =
- &crtc_state->hw.adjusted_mode;
+ const struct drm_display_mode *pipe_mode =
+ &crtc_state->hw.pipe_mode;
enum pipe pipe = crtc->pipe;
int hdisplay, vdisplay;
u32 pipe_dbuf_slice_mask;
@@ -4205,7 +4205,7 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
if (dbuf_slice_mask != pipe_dbuf_slice_mask)
continue;
- drm_mode_get_hv_timing(adjusted_mode, &hdisplay, &vdisplay);
+ drm_mode_get_hv_timing(pipe_mode, &hdisplay, &vdisplay);
total_width_in_range += hdisplay;
@@ -5093,7 +5093,7 @@ intel_get_linetime_us(const struct intel_crtc_state *crtc_state)
if (drm_WARN_ON(&dev_priv->drm, pixel_rate == 0))
return u32_to_fixed16(0);
- crtc_htotal = crtc_state->hw.adjusted_mode.crtc_htotal;
+ crtc_htotal = crtc_state->hw.pipe_mode.crtc_htotal;
linetime_us = div_fixed16(crtc_htotal * 1000, pixel_rate);
return linetime_us;
@@ -5282,14 +5282,14 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
method1 = skl_wm_method1(dev_priv, wp->plane_pixel_rate,
wp->cpp, latency, wp->dbuf_block_size);
method2 = skl_wm_method2(wp->plane_pixel_rate,
- crtc_state->hw.adjusted_mode.crtc_htotal,
+ crtc_state->hw.pipe_mode.crtc_htotal,
latency,
wp->plane_blocks_per_line);
if (wp->y_tiled) {
selected_result = max_fixed16(method2, wp->y_tile_minimum);
} else {
- if ((wp->cpp * crtc_state->hw.adjusted_mode.crtc_htotal /
+ if ((wp->cpp * crtc_state->hw.pipe_mode.crtc_htotal /
wp->dbuf_block_size < 1) &&
(wp->plane_bytes_per_line / wp->dbuf_block_size < 1)) {
selected_result = method2;
--
2.19.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Intel-gfx] [PATCH v10 04/11] drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.
2020-10-08 21:45 [Intel-gfx] [PATCH v10 01/11] HAX to make DSC work on the icelake test system Manasi Navare
2020-10-08 21:45 ` [Intel-gfx] [PATCH v10 02/11] drm/i915/display: Rename pipe_timings to transcoder_timings Manasi Navare
2020-10-08 21:45 ` [Intel-gfx] [PATCH v10 03/11] drm/i915: Add hw.pipe_mode to allow bigjoiner pipe/transcoder split Manasi Navare
@ 2020-10-08 21:45 ` Manasi Navare
2020-10-14 11:26 ` Ville Syrjälä
2020-10-20 18:39 ` Ville Syrjälä
2020-10-08 21:45 ` [Intel-gfx] [PATCH v10 05/11] drm/i915: Try to make bigjoiner work in atomic check Manasi Navare
` (14 subsequent siblings)
17 siblings, 2 replies; 50+ messages in thread
From: Manasi Navare @ 2020-10-08 21:45 UTC (permalink / raw)
To: intel-gfx
From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Small changes to intel_dp_mode_valid(), allow listing modes that
can only be supported in the bigjoiner configuration, which is
not supported yet.
eDP does not support bigjoiner, so do not expose bigjoiner only
modes on the eDP port.
v7:
* Add can_bigjoiner() helper (Ville)
* Pass bigjoiner to plane_size validation (Ville)
v6:
* Rebase after dp_downstream mode valid changes (Manasi)
v5:
* Increase max plane width to support 8K with bigjoiner (Maarten)
v4:
* Rebase (Manasi)
Changes since v1:
- Disallow bigjoiner on eDP.
Changes since v2:
- Rename intel_dp_downstream_max_dotclock to intel_dp_max_dotclock,
and split off the downstream and source checking to its own function.
(Ville)
v3:
* Rebase (Manasi)
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +-
drivers/gpu/drm/i915/display/intel_display.h | 3 +-
drivers/gpu/drm/i915/display/intel_dp.c | 126 +++++++++++++++----
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
drivers/gpu/drm/i915/display/intel_dsi.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
6 files changed, 111 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 723766b1eae3..cc540c7b7dcd 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -17642,7 +17642,8 @@ intel_mode_valid(struct drm_device *dev,
enum drm_mode_status
intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
- const struct drm_display_mode *mode)
+ const struct drm_display_mode *mode,
+ bool bigjoiner)
{
int plane_width_max, plane_height_max;
@@ -17659,7 +17660,7 @@ intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
* too big for that.
*/
if (INTEL_GEN(dev_priv) >= 11) {
- plane_width_max = 5120;
+ plane_width_max = 5120 << bigjoiner;
plane_height_max = 4320;
} else {
plane_width_max = 5120;
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index d10b7c8cde3f..3d860a9da8fe 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -496,7 +496,8 @@ u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
enum drm_mode_status
intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
- const struct drm_display_mode *mode);
+ const struct drm_display_mode *mode,
+ bool bigjoiner);
enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 8a522edd7386..af2ff425e5d5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -247,6 +247,29 @@ intel_dp_max_data_rate(int max_link_clock, int max_lanes)
return max_link_clock * max_lanes;
}
+static int source_max_dotclock(struct intel_dp *intel_dp, bool allow_bigjoiner)
+{
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct intel_encoder *encoder = &intel_dig_port->base;
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
+ if (allow_bigjoiner && INTEL_GEN(dev_priv) >= 11 && !intel_dp_is_edp(intel_dp))
+ return 2 * dev_priv->max_dotclk_freq;
+
+ return dev_priv->max_dotclk_freq;
+}
+
+static int
+intel_dp_max_dotclock(struct intel_dp *intel_dp, bool allow_bigjoiner)
+{
+ int max_dotclk = source_max_dotclock(intel_dp, allow_bigjoiner);
+
+ if (intel_dp->dfp.max_dotclock)
+ return min(max_dotclk, intel_dp->dfp.max_dotclock);
+
+ return max_dotclk;
+}
+
static int cnl_max_source_rate(struct intel_dp *intel_dp)
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
@@ -512,7 +535,8 @@ small_joiner_ram_size_bits(struct drm_i915_private *i915)
static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
u32 link_clock, u32 lane_count,
- u32 mode_clock, u32 mode_hdisplay)
+ u32 mode_clock, u32 mode_hdisplay,
+ bool bigjoiner)
{
u32 bits_per_pixel, max_bpp_small_joiner_ram;
int i;
@@ -530,6 +554,10 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
/* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
mode_hdisplay;
+
+ if (bigjoiner)
+ max_bpp_small_joiner_ram *= 2;
+
drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n",
max_bpp_small_joiner_ram);
@@ -539,6 +567,15 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
*/
bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
+ if (bigjoiner) {
+ u32 max_bpp_bigjoiner =
+ i915->max_cdclk_freq * 48 /
+ intel_dp_mode_to_fec_clock(mode_clock);
+
+ DRM_DEBUG_KMS("Max big joiner bpp: %u\n", max_bpp_bigjoiner);
+ bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
+ }
+
/* Error out if the max bpp is less than smallest allowed valid bpp */
if (bits_per_pixel < valid_dsc_bpp[0]) {
drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
@@ -561,7 +598,8 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
}
static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
- int mode_clock, int mode_hdisplay)
+ int mode_clock, int mode_hdisplay,
+ bool bigjoiner)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
u8 min_slice_count, i;
@@ -588,12 +626,20 @@ static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
/* Find the closest match to the valid slice count values */
for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
- if (valid_dsc_slicecount[i] >
- drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
- false))
+ u8 test_slice_count = bigjoiner ?
+ 2 * valid_dsc_slicecount[i] :
+ valid_dsc_slicecount[i];
+
+ if (test_slice_count >
+ drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, false))
break;
- if (min_slice_count <= valid_dsc_slicecount[i])
- return valid_dsc_slicecount[i];
+
+ /* big joiner needs small joiner to be enabled */
+ if (bigjoiner && test_slice_count < 4)
+ continue;
+
+ if (min_slice_count <= test_slice_count)
+ return test_slice_count;
}
drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
@@ -676,10 +722,6 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector,
const struct drm_display_info *info = &connector->base.display_info;
int tmds_clock;
- if (intel_dp->dfp.max_dotclock &&
- target_clock > intel_dp->dfp.max_dotclock)
- return MODE_CLOCK_HIGH;
-
/* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
tmds_clock = target_clock;
if (drm_mode_is_420_only(info, mode))
@@ -695,6 +737,16 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector,
return MODE_OK;
}
+static bool intel_dp_can_bigjoiner(struct drm_connector *connector)
+{
+ struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
+ struct drm_i915_private *dev_priv = to_i915(connector->dev);
+
+ return INTEL_GEN(dev_priv) >= 12 ||
+ (INTEL_GEN(dev_priv) == 11 &&
+ encoder->port != PORT_A);
+}
+
static enum drm_mode_status
intel_dp_mode_valid(struct drm_connector *connector,
struct drm_display_mode *mode)
@@ -709,10 +761,16 @@ intel_dp_mode_valid(struct drm_connector *connector,
u16 dsc_max_output_bpp = 0;
u8 dsc_slice_count = 0;
enum drm_mode_status status;
+ bool dsc = false, bigjoiner = false;
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
return MODE_NO_DBLESCAN;
+ if (mode->flags & DRM_MODE_FLAG_DBLCLK)
+ return MODE_H_ILLEGAL;
+
+ max_dotclk = intel_dp_max_dotclock(intel_dp, false);
+
if (intel_dp_is_edp(intel_dp) && fixed_mode) {
if (mode->hdisplay > fixed_mode->hdisplay)
return MODE_PANEL;
@@ -723,6 +781,21 @@ intel_dp_mode_valid(struct drm_connector *connector,
target_clock = fixed_mode->clock;
}
+ if (mode->clock < 10000)
+ return MODE_CLOCK_LOW;
+
+ if (target_clock > max_dotclk) {
+ if (intel_dp_is_edp(intel_dp))
+ return MODE_CLOCK_HIGH;
+
+ max_dotclk = intel_dp_max_dotclock(intel_dp, true);
+
+ if (target_clock > max_dotclk)
+ return MODE_CLOCK_HIGH;
+
+ bigjoiner = intel_dp_can_bigjoiner(connector);
+ }
+
max_link_clock = intel_dp_max_link_rate(intel_dp);
max_lanes = intel_dp_max_lane_count(intel_dp);
@@ -751,30 +824,35 @@ intel_dp_mode_valid(struct drm_connector *connector,
max_link_clock,
max_lanes,
target_clock,
- mode->hdisplay) >> 4;
+ mode->hdisplay,
+ bigjoiner) >> 4;
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
target_clock,
- mode->hdisplay);
+ mode->hdisplay,
+ bigjoiner);
}
+
+ dsc = dsc_max_output_bpp && dsc_slice_count;
}
- if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) ||
- target_clock > max_dotclk)
+ /* big joiner configuration needs DSC */
+ if (bigjoiner && !dsc) {
+ DRM_DEBUG_KMS("Link clock needs bigjoiner, but DSC or FEC not available\n");
return MODE_CLOCK_HIGH;
+ }
- if (mode->clock < 10000)
- return MODE_CLOCK_LOW;
-
- if (mode->flags & DRM_MODE_FLAG_DBLCLK)
- return MODE_H_ILLEGAL;
+ if (mode_rate > max_rate && !dsc) {
+ DRM_DEBUG_KMS("Cannot drive without DSC\n");
+ return MODE_CLOCK_HIGH;
+ }
status = intel_dp_mode_valid_downstream(intel_connector,
mode, target_clock);
if (status != MODE_OK)
return status;
- return intel_mode_valid_max_plane_size(dev_priv, mode);
+ return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
}
u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
@@ -2324,11 +2402,13 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
pipe_config->port_clock,
pipe_config->lane_count,
adjusted_mode->crtc_clock,
- adjusted_mode->crtc_hdisplay);
+ adjusted_mode->crtc_hdisplay,
+ false);
dsc_dp_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
adjusted_mode->crtc_clock,
- adjusted_mode->crtc_hdisplay);
+ adjusted_mode->crtc_hdisplay,
+ false);
if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
drm_dbg_kms(&dev_priv->drm,
"Compressed BPP/Slice Count not supported\n");
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index e948aacbd4ab..0fe2a3929ce6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -714,7 +714,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
return 0;
}
- *status = intel_mode_valid_max_plane_size(dev_priv, mode);
+ *status = intel_mode_valid_max_plane_size(dev_priv, mode, true);
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_dsi.c b/drivers/gpu/drm/i915/display/intel_dsi.c
index afa4e6817e8c..f453ceb8d149 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi.c
@@ -75,7 +75,7 @@ enum drm_mode_status intel_dsi_mode_valid(struct drm_connector *connector,
return MODE_CLOCK_HIGH;
}
- return intel_mode_valid_max_plane_size(dev_priv, mode);
+ return intel_mode_valid_max_plane_size(dev_priv, mode, false);
}
struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index f90838bc74fb..82674a8853c6 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2274,7 +2274,7 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
if (status != MODE_OK)
return status;
- return intel_mode_valid_max_plane_size(dev_priv, mode);
+ return intel_mode_valid_max_plane_size(dev_priv, mode, false);
}
bool intel_hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
--
2.19.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Intel-gfx] [PATCH v10 05/11] drm/i915: Try to make bigjoiner work in atomic check
2020-10-08 21:45 [Intel-gfx] [PATCH v10 01/11] HAX to make DSC work on the icelake test system Manasi Navare
` (2 preceding siblings ...)
2020-10-08 21:45 ` [Intel-gfx] [PATCH v10 04/11] drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3 Manasi Navare
@ 2020-10-08 21:45 ` Manasi Navare
2020-10-11 11:18 ` kernel test robot
2020-10-14 11:33 ` Ville Syrjälä
2020-10-08 21:45 ` [Intel-gfx] [PATCH v10 06/11] drm/i915: Enable big joiner support in enable and disable sequences Manasi Navare
` (13 subsequent siblings)
17 siblings, 2 replies; 50+ messages in thread
From: Manasi Navare @ 2020-10-08 21:45 UTC (permalink / raw)
To: intel-gfx
From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
When the clock is higher than the dotclock, try with 2 pipes enabled.
If we can enable 2, then we will go into big joiner mode, and steal
the adjacent crtc.
This only links the crtc's in software, no hardware or plane
programming is done yet. Blobs are also copied from the master's
crtc_state, so it doesn't depend at commit time on the other
crtc_state.
v4:
* Fixes in intel_crtc_compute_config (Ville)
v3:
* Manual Rebase (Manasi)
Changes since v1:
- Rename pipe timings to transcoder timings, as they are now different.
Changes since v2:
- Rework bigjoiner checks; always disable slave when recalculating
master. No need to have a separate bigjoiner pass any more.
- Use pipe_mode instead of transcoder_mode, to clean up the code.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
drivers/gpu/drm/i915/display/intel_atomic.c | 9 +-
drivers/gpu/drm/i915/display/intel_atomic.h | 3 +-
drivers/gpu/drm/i915/display/intel_display.c | 202 ++++++++++++++++--
.../drm/i915/display/intel_display_types.h | 9 +
drivers/gpu/drm/i915/display/intel_dp.c | 22 +-
5 files changed, 211 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
index 86be032bcf96..e243ce97b534 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -270,14 +270,15 @@ void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state)
intel_crtc_put_color_blobs(crtc_state);
}
-void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state)
+void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state,
+ const struct intel_crtc_state *from_crtc_state)
{
drm_property_replace_blob(&crtc_state->hw.degamma_lut,
- crtc_state->uapi.degamma_lut);
+ from_crtc_state->uapi.degamma_lut);
drm_property_replace_blob(&crtc_state->hw.gamma_lut,
- crtc_state->uapi.gamma_lut);
+ from_crtc_state->uapi.gamma_lut);
drm_property_replace_blob(&crtc_state->hw.ctm,
- crtc_state->uapi.ctm);
+ from_crtc_state->uapi.ctm);
}
/**
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h b/drivers/gpu/drm/i915/display/intel_atomic.h
index 285de07011dc..62a3365ed5e6 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic.h
@@ -43,7 +43,8 @@ struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
void intel_crtc_destroy_state(struct drm_crtc *crtc,
struct drm_crtc_state *state);
void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state);
-void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state);
+void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state,
+ const struct intel_crtc_state *from_crtc_state);
struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
void intel_atomic_state_free(struct drm_atomic_state *state);
void intel_atomic_state_clear(struct drm_atomic_state *state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index cc540c7b7dcd..37b56f4c2401 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8130,9 +8130,24 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- const struct drm_display_mode *pipe_mode = &pipe_config->hw.pipe_mode;
+ struct drm_display_mode *pipe_mode = &pipe_config->hw.pipe_mode;
int clock_limit = dev_priv->max_dotclk_freq;
+ *pipe_mode = pipe_config->hw.adjusted_mode;
+
+ /* Adjust pipe_mode for bigjoiner, with half the horizontal mode */
+ if (pipe_config->bigjoiner) {
+ pipe_mode->crtc_clock /= 2;
+ pipe_mode->crtc_hdisplay /= 2;
+ pipe_mode->crtc_hblank_start /= 2;
+ pipe_mode->crtc_hblank_end /= 2;
+ pipe_mode->crtc_hsync_start /= 2;
+ pipe_mode->crtc_hsync_end /= 2;
+ pipe_mode->crtc_htotal /= 2;
+ pipe_mode->crtc_hskew /= 2;
+ pipe_config->pipe_src_w /= 2;
+ }
+
if (INTEL_GEN(dev_priv) < 4) {
clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
@@ -8193,7 +8208,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
* WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
*/
if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
- pipe_mode->crtc_hsync_start == pipe_mode->crtc_hdisplay)
+ pipe_mode->crtc_hsync_start == pipe_mode->crtc_hdisplay)
return -EINVAL;
intel_crtc_compute_pixel_rate(pipe_config);
@@ -12559,7 +12574,7 @@ static bool encoders_cloneable(const struct intel_encoder *a,
b->cloneable & (1 << a->type));
}
-static bool check_single_encoder_cloning(struct drm_atomic_state *state,
+static bool check_single_encoder_cloning(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder)
{
@@ -12568,7 +12583,7 @@ static bool check_single_encoder_cloning(struct drm_atomic_state *state,
struct drm_connector_state *connector_state;
int i;
- for_each_new_connector_in_state(state, connector, connector_state, i) {
+ for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
if (connector_state->crtc != &crtc->base)
continue;
@@ -12808,6 +12823,7 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
if (mode_changed && crtc_state->hw.enable &&
dev_priv->display.crtc_compute_clock &&
+ !crtc_state->bigjoiner_slave &&
!drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) {
ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state);
if (ret)
@@ -13341,19 +13357,32 @@ static bool check_digital_port_conflicts(struct intel_atomic_state *state)
}
static void
-intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_crtc_state *crtc_state)
+intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state,
+ struct intel_crtc_state *crtc_state)
{
- intel_crtc_copy_color_blobs(crtc_state);
+ const struct intel_crtc_state *from_crtc_state = crtc_state;
+
+ if (crtc_state->bigjoiner_slave) {
+ from_crtc_state = intel_atomic_get_new_crtc_state(state,
+ crtc_state->bigjoiner_linked_crtc);
+
+ /* No need to copy state if the master state is unchanged */
+ if (!from_crtc_state)
+ return;
+ }
+
+ intel_crtc_copy_color_blobs(crtc_state, from_crtc_state);
}
static void
-intel_crtc_copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state)
+intel_crtc_copy_uapi_to_hw_state(struct intel_atomic_state *state,
+ struct intel_crtc_state *crtc_state)
{
crtc_state->hw.enable = crtc_state->uapi.enable;
crtc_state->hw.active = crtc_state->uapi.active;
crtc_state->hw.mode = crtc_state->uapi.mode;
crtc_state->hw.pipe_mode = crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
- intel_crtc_copy_uapi_to_hw_state_nomodeset(crtc_state);
+ intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc_state);
}
static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
@@ -13375,7 +13404,49 @@ static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state
}
static int
-intel_crtc_prepare_cleared_state(struct intel_crtc_state *crtc_state)
+copy_bigjoiner_crtc_state(struct intel_crtc_state *crtc_state,
+ const struct intel_crtc_state *from_crtc_state)
+{
+ struct intel_crtc_state *saved_state;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
+ saved_state = kmemdup(from_crtc_state, sizeof(*saved_state), GFP_KERNEL);
+ if (!saved_state)
+ return -ENOMEM;
+
+ saved_state->uapi = crtc_state->uapi;
+ saved_state->scaler_state = crtc_state->scaler_state;
+ saved_state->shared_dpll = crtc_state->shared_dpll;
+ saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
+ saved_state->crc_enabled = crtc_state->crc_enabled;
+
+ intel_crtc_free_hw_state(crtc_state);
+ memcpy(crtc_state, saved_state, sizeof(*crtc_state));
+ kfree(saved_state);
+
+ /* Re-init hw state */
+ memset(&crtc_state->hw, 0, sizeof(saved_state->hw));
+ crtc_state->hw.enable = from_crtc_state->hw.enable;
+ crtc_state->hw.active = from_crtc_state->hw.active;
+ crtc_state->hw.pipe_mode = from_crtc_state->hw.pipe_mode;
+ crtc_state->hw.adjusted_mode = from_crtc_state->hw.adjusted_mode;
+
+ /* Some fixups */
+ crtc_state->uapi.mode_changed = from_crtc_state->uapi.mode_changed;
+ crtc_state->uapi.connectors_changed = from_crtc_state->uapi.connectors_changed;
+ crtc_state->uapi.active_changed = from_crtc_state->uapi.active_changed;
+ crtc_state->nv12_planes = crtc_state->c8_planes = crtc_state->update_planes = 0;
+ crtc_state->bigjoiner_linked_crtc = to_intel_crtc(from_crtc_state->uapi.crtc);
+ crtc_state->bigjoiner_slave = true;
+ crtc_state->cpu_transcoder = (enum transcoder)crtc->pipe;
+ crtc_state->has_audio = false;
+
+ return 0;
+}
+
+static int
+intel_crtc_prepare_cleared_state(struct intel_atomic_state *state,
+ struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -13407,16 +13478,16 @@ intel_crtc_prepare_cleared_state(struct intel_crtc_state *crtc_state)
memcpy(crtc_state, saved_state, sizeof(*crtc_state));
kfree(saved_state);
- intel_crtc_copy_uapi_to_hw_state(crtc_state);
+ intel_crtc_copy_uapi_to_hw_state(state, crtc_state);
return 0;
}
static int
-intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
+intel_modeset_pipe_config(struct intel_atomic_state *state,
+ struct intel_crtc_state *pipe_config)
{
struct drm_crtc *crtc = pipe_config->uapi.crtc;
- struct drm_atomic_state *state = pipe_config->uapi.state;
struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
struct drm_connector *connector;
struct drm_connector_state *connector_state;
@@ -13458,7 +13529,7 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
&pipe_config->pipe_src_w,
&pipe_config->pipe_src_h);
- for_each_new_connector_in_state(state, connector, connector_state, i) {
+ for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
struct intel_encoder *encoder =
to_intel_encoder(connector_state->best_encoder);
@@ -13496,7 +13567,7 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
* adjust it according to limitations or connector properties, and also
* a chance to reject the mode entirely.
*/
- for_each_new_connector_in_state(state, connector, connector_state, i) {
+ for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
struct intel_encoder *encoder =
to_intel_encoder(connector_state->best_encoder);
@@ -13548,9 +13619,6 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
"hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
- /* without bigjoiner, pipe_mode == adjusted_mode */
- pipe_config->hw.pipe_mode = pipe_config->hw.adjusted_mode;
-
return 0;
}
@@ -14946,6 +15014,75 @@ static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
return false;
}
+static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_crtc_state *old_crtc_state,
+ struct intel_crtc_state *new_crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_crtc_state *slave_crtc_state, *master_crtc_state;
+ struct intel_crtc *slave, *master;
+
+ /* slave being enabled, is master is still claiming this crtc? */
+ if (old_crtc_state->bigjoiner_slave) {
+ slave = crtc;
+ master = old_crtc_state->bigjoiner_linked_crtc;
+ master_crtc_state = intel_atomic_get_new_crtc_state(state, master);
+ if (!master_crtc_state || !needs_modeset(master_crtc_state))
+ goto claimed;
+ }
+
+ if (!new_crtc_state->bigjoiner)
+ return 0;
+
+ if (1 + crtc->pipe >= INTEL_NUM_PIPES(dev_priv)) {
+ DRM_DEBUG_KMS("[CRTC:%d:%s] Big joiner configuration requires "
+ "CRTC + 1 to be used, doesn't exist\n",
+ crtc->base.base.id, crtc->base.name);
+ return -EINVAL;
+ }
+
+ slave = new_crtc_state->bigjoiner_linked_crtc =
+ intel_get_crtc_for_pipe(dev_priv, crtc->pipe + 1);
+ slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave);
+ master = crtc;
+ if (IS_ERR(slave_crtc_state))
+ return PTR_ERR(slave_crtc_state);
+
+ /* master being enabled, slave was already configured? */
+ if (slave_crtc_state->uapi.enable)
+ goto claimed;
+
+ DRM_DEBUG_KMS("[CRTC:%d:%s] Used as slave for big joiner\n",
+ slave->base.base.id, slave->base.name);
+
+ return copy_bigjoiner_crtc_state(slave_crtc_state, new_crtc_state);
+
+claimed:
+ DRM_DEBUG_KMS("[CRTC:%d:%s] Slave is enabled as normal CRTC, but "
+ "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n",
+ slave->base.base.id, slave->base.name,
+ master->base.base.id, master->base.name);
+ return -EINVAL;
+}
+
+static int kill_bigjoiner_slave(struct intel_atomic_state *state,
+ struct intel_crtc_state *master_crtc_state)
+{
+ struct intel_crtc_state *slave_crtc_state =
+ intel_atomic_get_crtc_state(&state->base,
+ master_crtc_state->bigjoiner_linked_crtc);
+
+ if (IS_ERR(slave_crtc_state))
+ return PTR_ERR(slave_crtc_state);
+
+ slave_crtc_state->bigjoiner = master_crtc_state->bigjoiner = false;
+ slave_crtc_state->bigjoiner_slave = master_crtc_state->bigjoiner_slave = false;
+ slave_crtc_state->bigjoiner_linked_crtc = master_crtc_state->bigjoiner_linked_crtc = NULL;
+ intel_crtc_copy_uapi_to_hw_state(state, slave_crtc_state);
+ return 0;
+}
+
/**
* DOC: asynchronous flip implementation
*
@@ -15108,19 +15245,36 @@ static int intel_atomic_check(struct drm_device *dev,
new_crtc_state, i) {
if (!needs_modeset(new_crtc_state)) {
/* Light copy */
- intel_crtc_copy_uapi_to_hw_state_nomodeset(new_crtc_state);
+ intel_crtc_copy_uapi_to_hw_state_nomodeset(state, new_crtc_state);
+
+ continue;
+ }
+ /* Kill old bigjoiner link, we may re-establish afterwards */
+ if (old_crtc_state->bigjoiner && !old_crtc_state->bigjoiner_slave) {
+ ret = kill_bigjoiner_slave(state, new_crtc_state);
+ if (ret)
+ goto fail;
+ }
+
+ if (!new_crtc_state->uapi.enable) {
+ if (!new_crtc_state->bigjoiner_slave) {
+ intel_crtc_copy_uapi_to_hw_state(state, new_crtc_state);
+ any_ms = true;
+ }
continue;
}
- ret = intel_crtc_prepare_cleared_state(new_crtc_state);
+ ret = intel_crtc_prepare_cleared_state(state, new_crtc_state);
if (ret)
goto fail;
- if (!new_crtc_state->hw.enable)
- continue;
+ ret = intel_modeset_pipe_config(state, new_crtc_state);
+ if (ret)
+ goto fail;
- ret = intel_modeset_pipe_config(new_crtc_state);
+ ret = intel_atomic_check_bigjoiner(state, crtc, old_crtc_state,
+ new_crtc_state);
if (ret)
goto fail;
}
@@ -15458,7 +15612,9 @@ static void intel_update_crtc(struct intel_atomic_state *state,
commit_pipe_config(state, crtc);
- if (INTEL_GEN(dev_priv) >= 9)
+ if (new_crtc_state->bigjoiner) {
+ /* Not supported yet */
+ } else if (INTEL_GEN(dev_priv) >= 9)
skl_update_planes_on_crtc(state, crtc);
else
i9xx_update_planes_on_crtc(state, crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 513576217d14..c159f6a48bf0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1066,6 +1066,15 @@ struct intel_crtc_state {
/* enable pipe csc? */
bool csc_enable;
+ /* enable pipe big joiner? */
+ bool bigjoiner;
+
+ /* big joiner slave crtc? */
+ bool bigjoiner_slave;
+
+ /* linked crtc for bigjoiner, either slave or master */
+ struct intel_crtc *bigjoiner_linked_crtc;
+
/* Display Stream compression state */
struct {
bool compression_enable;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index af2ff425e5d5..a627ad77dd3f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2386,6 +2386,15 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
pipe_config->lane_count = limits->max_lane_count;
+ if (adjusted_mode->crtc_clock > intel_dp_max_dotclock(intel_dp, false)) {
+ if (adjusted_mode->crtc_clock > intel_dp_max_dotclock(intel_dp, true)) {
+ DRM_DEBUG_KMS("Clock rate too high for big joiner\n");
+ return -EINVAL;
+ }
+ pipe_config->bigjoiner = true;
+ DRM_DEBUG_KMS("Using bigjoiner configuration\n");
+ }
+
if (intel_dp_is_edp(intel_dp)) {
pipe_config->dsc.compressed_bpp =
min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
@@ -2403,12 +2412,12 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
pipe_config->lane_count,
adjusted_mode->crtc_clock,
adjusted_mode->crtc_hdisplay,
- false);
+ pipe_config->bigjoiner);
dsc_dp_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
adjusted_mode->crtc_clock,
adjusted_mode->crtc_hdisplay,
- false);
+ pipe_config->bigjoiner);
if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
drm_dbg_kms(&dev_priv->drm,
"Compressed BPP/Slice Count not supported\n");
@@ -2424,14 +2433,15 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
* is greater than the maximum Cdclock and if slice count is even
* then we need to use 2 VDSC instances.
*/
- if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) {
- if (pipe_config->dsc.slice_count > 1) {
- pipe_config->dsc.dsc_split = true;
- } else {
+ if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq ||
+ pipe_config->bigjoiner) {
+ if (pipe_config->dsc.slice_count < 2) {
drm_dbg_kms(&dev_priv->drm,
"Cannot split stream to use 2 VDSC instances\n");
return -EINVAL;
}
+
+ pipe_config->dsc.dsc_split = true;
}
ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config);
--
2.19.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Intel-gfx] [PATCH v10 06/11] drm/i915: Enable big joiner support in enable and disable sequences.
2020-10-08 21:45 [Intel-gfx] [PATCH v10 01/11] HAX to make DSC work on the icelake test system Manasi Navare
` (3 preceding siblings ...)
2020-10-08 21:45 ` [Intel-gfx] [PATCH v10 05/11] drm/i915: Try to make bigjoiner work in atomic check Manasi Navare
@ 2020-10-08 21:45 ` Manasi Navare
2020-10-14 11:07 ` Jani Nikula
2020-10-15 13:07 ` Ville Syrjälä
2020-10-08 21:45 ` [Intel-gfx] [PATCH v10 07/11] drm/i915: Make hardware readout work on i915 Manasi Navare
` (12 subsequent siblings)
17 siblings, 2 replies; 50+ messages in thread
From: Manasi Navare @ 2020-10-08 21:45 UTC (permalink / raw)
To: intel-gfx
From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Make vdsc work when no output is enabled. The big joiner needs VDSC
on the slave, so enable it and set the appropriate bits.
Also update timestamping constants, because slave crtc's are not
updated in drm_atomic_helper_update_legacy_modeset_state().
This should be enough to bring up CRTC's in a big joiner configuration,
without any plane configuration on the second pipe yet.
HOWEVER, we still bring up the crtc's in the wrong order. We need to
make sure that the master crtc is brought up after the slave crtc.
This is done correctly later in this series.
The next steps are to enable planes correctly, and make sure we enable
and update both master and slave in the correct order.
v2:
* Manual rebase (Manasi)
v3:
* Rebase (Manasi)
v4:
* Rebase (Manasi)
v5:
* Get dsc power domain in ddi_init (Manasi)
v6:
* Remove dsc power put from dsc_disable (Maarten)
v7:
* Rebase (Manasi)
v8:
* Rebase (Manasi)
v9:
* Rebase (Manasi)
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 2 -
drivers/gpu/drm/i915/display/intel_ddi.c | 68 ++-
drivers/gpu/drm/i915/display/intel_display.c | 392 ++++++++++++------
.../drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 6 +-
drivers/gpu/drm/i915/display/intel_vdsc.c | 201 ++++-----
drivers/gpu/drm/i915/display/intel_vdsc.h | 7 +-
7 files changed, 421 insertions(+), 256 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 4400e83f783f..be8756816650 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1492,8 +1492,6 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
- intel_dsc_get_config(encoder, pipe_config);
-
/* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
pipe_config->port_clock = intel_dpll_get_freq(i915,
pipe_config->shared_dpll);
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index bbd5f04dc140..6b2c09effbdd 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -28,6 +28,7 @@
#include <drm/drm_scdc_helper.h>
#include "i915_drv.h"
+#include "i915_trace.h"
#include "intel_audio.h"
#include "intel_combo_phy.h"
#include "intel_connector.h"
@@ -2217,12 +2218,6 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
intel_display_power_get(dev_priv,
intel_ddi_main_link_aux_domain(dig_port));
- /*
- * VDSC power is needed when DSC is enabled
- */
- if (crtc_state->dsc.compression_enable)
- intel_display_power_get(dev_priv,
- intel_dsc_power_domain(crtc_state));
}
void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder,
@@ -3507,7 +3502,8 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
/* 7.l Configure and enable FEC if needed */
intel_ddi_enable_fec(encoder, crtc_state);
- intel_dsc_enable(encoder, crtc_state);
+ if (!crtc_state->bigjoiner)
+ intel_dsc_enable(encoder, crtc_state);
}
static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
@@ -3579,7 +3575,8 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
if (!is_mst)
intel_ddi_enable_pipe_clock(encoder, crtc_state);
- intel_dsc_enable(encoder, crtc_state);
+ if (!crtc_state->bigjoiner)
+ intel_dsc_enable(encoder, crtc_state);
}
static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
@@ -3828,6 +3825,21 @@ static void intel_ddi_post_disable(struct intel_atomic_state *state,
ilk_pfit_disable(old_crtc_state);
}
+ if (old_crtc_state->bigjoiner_linked_crtc) {
+ struct intel_atomic_state *state =
+ to_intel_atomic_state(old_crtc_state->uapi.state);
+ struct intel_crtc *slave =
+ old_crtc_state->bigjoiner_linked_crtc;
+ const struct intel_crtc_state *old_slave_crtc_state =
+ intel_atomic_get_old_crtc_state(state, slave);
+
+ intel_crtc_vblank_off(old_slave_crtc_state);
+ trace_intel_pipe_disable(slave);
+
+ intel_dsc_disable(old_slave_crtc_state);
+ skl_scaler_disable(old_slave_crtc_state);
+ }
+
/*
* When called from DP MST code:
* - old_conn_state will be NULL
@@ -4044,7 +4056,8 @@ static void intel_enable_ddi(struct intel_atomic_state *state,
{
drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder);
- intel_ddi_enable_transcoder_func(encoder, crtc_state);
+ if (!crtc_state->bigjoiner_slave)
+ intel_ddi_enable_transcoder_func(encoder, crtc_state);
intel_enable_pipe(crtc_state);
@@ -4397,21 +4410,18 @@ static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state)
crtc_state->sync_mode_slaves_mask);
}
-void intel_ddi_get_config(struct intel_encoder *encoder,
- struct intel_crtc_state *pipe_config)
+static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
+ struct intel_crtc_state *pipe_config)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
u32 temp, flags = 0;
- /* XXX: DSI transcoder paranoia */
- if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)))
+ temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
+ if (!(temp & TRANS_DDI_FUNC_ENABLE))
return;
- intel_dsc_get_config(encoder, pipe_config);
-
- temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
if (temp & TRANS_DDI_PHSYNC)
flags |= DRM_MODE_FLAG_PHSYNC;
else
@@ -4504,6 +4514,29 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
default:
break;
}
+}
+
+void intel_ddi_get_config(struct intel_encoder *encoder,
+ struct intel_crtc_state *pipe_config)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
+
+ /* XXX: DSI transcoder paranoia */
+ if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
+ return;
+
+ intel_ddi_read_func_ctl(encoder, pipe_config);
+ if (pipe_config->bigjoiner_slave) {
+ /* read out pipe settings from master */
+ enum transcoder save = pipe_config->cpu_transcoder;
+
+ /* Our own transcoder needs to be disabled when reading it in intel_ddi_read_func_ctl() */
+ WARN_ON(pipe_config->output_types);
+ pipe_config->cpu_transcoder = (enum transcoder)pipe_config->bigjoiner_linked_crtc->pipe;
+ intel_ddi_read_func_ctl(encoder, pipe_config);
+ pipe_config->cpu_transcoder = save;
+ }
pipe_config->has_audio =
intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
@@ -4529,7 +4562,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
}
- intel_ddi_clock_get(encoder, pipe_config);
+ if (!pipe_config->bigjoiner_slave)
+ intel_ddi_clock_get(encoder, pipe_config);
if (IS_GEN9_LP(dev_priv))
pipe_config->lane_lat_optim_mask =
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 37b56f4c2401..faf8bf757bed 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7125,6 +7125,45 @@ static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
intel_de_write(dev_priv, reg, val);
}
+static void tgl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *master = to_intel_crtc(crtc_state->uapi.crtc);
+ struct intel_crtc_state *master_crtc_state;
+ struct drm_connector_state *conn_state;
+ struct drm_connector *conn;
+ struct intel_encoder *encoder = NULL;
+ int i;
+
+ if (crtc_state->bigjoiner_slave)
+ master = crtc_state->bigjoiner_linked_crtc;
+
+ master_crtc_state = intel_atomic_get_new_crtc_state(state, master);
+
+ for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
+ if (conn_state->crtc != &master->base)
+ continue;
+
+ encoder = to_intel_encoder(conn_state->best_encoder);
+ break;
+ }
+
+ if (!crtc_state->bigjoiner_slave) {
+ /* need to enable VDSC, which we skipped in pre-enable */
+ intel_dsc_enable(encoder, crtc_state);
+ } else {
+ /*
+ * Enable sequence steps 1-7 on bigjoiner master
+ */
+ intel_encoders_pre_pll_enable(state, master);
+ intel_enable_shared_dpll(master_crtc_state);
+ intel_encoders_pre_enable(state, master);
+
+ /* and DSC on slave */
+ intel_dsc_enable(NULL, crtc_state);
+ }
+}
+
static void hsw_crtc_enable(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
@@ -7138,34 +7177,39 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
if (drm_WARN_ON(&dev_priv->drm, crtc->active))
return;
- intel_encoders_pre_pll_enable(state, crtc);
-
- if (new_crtc_state->shared_dpll)
- intel_enable_shared_dpll(new_crtc_state);
+ if (!new_crtc_state->bigjoiner) {
+ intel_encoders_pre_pll_enable(state, crtc);
- intel_encoders_pre_enable(state, crtc);
+ if (new_crtc_state->shared_dpll)
+ intel_enable_shared_dpll(new_crtc_state);
- if (!transcoder_is_dsi(cpu_transcoder))
- intel_set_transcoder_timings(new_crtc_state);
+ intel_encoders_pre_enable(state, crtc);
+ } else {
+ tgl_ddi_bigjoiner_pre_enable(state, new_crtc_state);
+ }
intel_set_pipe_src_size(new_crtc_state);
+ if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
+ bdw_set_pipemisc(new_crtc_state);
- if (cpu_transcoder != TRANSCODER_EDP &&
- !transcoder_is_dsi(cpu_transcoder))
- intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
- new_crtc_state->pixel_multiplier - 1);
+ if (!new_crtc_state->bigjoiner_slave && !transcoder_is_dsi(cpu_transcoder)) {
+ if (!transcoder_is_dsi(cpu_transcoder))
+ intel_set_transcoder_timings(new_crtc_state);
- if (new_crtc_state->has_pch_encoder)
- intel_cpu_transcoder_set_m_n(new_crtc_state,
- &new_crtc_state->fdi_m_n, NULL);
+ if (cpu_transcoder != TRANSCODER_EDP &&
+ !transcoder_is_dsi(cpu_transcoder))
+ intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
+ new_crtc_state->pixel_multiplier - 1);
+
+ if (new_crtc_state->has_pch_encoder)
+ intel_cpu_transcoder_set_m_n(new_crtc_state,
+ &new_crtc_state->fdi_m_n, NULL);
- if (!transcoder_is_dsi(cpu_transcoder)) {
hsw_set_frame_start_delay(new_crtc_state);
- hsw_set_pipeconf(new_crtc_state);
}
- if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
- bdw_set_pipemisc(new_crtc_state);
+ if (!transcoder_is_dsi(cpu_transcoder))
+ hsw_set_pipeconf(new_crtc_state);
crtc->active = true;
@@ -7201,6 +7245,11 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
if (INTEL_GEN(dev_priv) >= 11)
icl_pipe_mbus_enable(crtc);
+ if (new_crtc_state->bigjoiner_slave) {
+ trace_intel_pipe_enable(crtc);
+ intel_crtc_vblank_on(new_crtc_state);
+ }
+
intel_encoders_enable(state, crtc);
if (psl_clkgate_wa) {
@@ -7495,6 +7544,9 @@ static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
if (crtc_state->shared_dpll)
mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);
+ if (crtc_state->dsc.compression_enable)
+ mask |= BIT_ULL(intel_dsc_power_domain(crtc_state));
+
return mask;
}
@@ -8113,6 +8165,30 @@ static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
pfit_w * pfit_h);
}
+static void intel_encoder_get_config(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state)
+{
+ struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
+
+ encoder->get_config(encoder, crtc_state);
+
+ *pipe_mode = crtc_state->hw.adjusted_mode;
+ if (crtc_state->bigjoiner) {
+ /*
+ * transcoder is programmed to the full mode,
+ * but pipe timings are half of the transcoder mode
+ */
+ pipe_mode->crtc_hdisplay /= 2;
+ pipe_mode->crtc_hblank_start /= 2;
+ pipe_mode->crtc_hblank_end /= 2;
+ pipe_mode->crtc_hsync_start /= 2;
+ pipe_mode->crtc_hsync_end /= 2;
+ pipe_mode->crtc_htotal /= 2;
+ pipe_mode->crtc_hskew /= 2;
+ pipe_mode->crtc_clock /= 2;
+ }
+}
+
static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
@@ -9027,20 +9103,22 @@ static void intel_get_pipe_src_size(struct intel_crtc *crtc,
void intel_mode_from_pipe_config(struct drm_display_mode *mode,
struct intel_crtc_state *pipe_config)
{
- mode->hdisplay = pipe_config->hw.adjusted_mode.crtc_hdisplay;
- mode->htotal = pipe_config->hw.adjusted_mode.crtc_htotal;
- mode->hsync_start = pipe_config->hw.adjusted_mode.crtc_hsync_start;
- mode->hsync_end = pipe_config->hw.adjusted_mode.crtc_hsync_end;
+ struct drm_display_mode *hw_mode = &pipe_config->hw.adjusted_mode;
+
+ mode->hdisplay = hw_mode->crtc_hdisplay;
+ mode->htotal = hw_mode->crtc_htotal;
+ mode->hsync_start = hw_mode->crtc_hsync_start;
+ mode->hsync_end = hw_mode->crtc_hsync_end;
- mode->vdisplay = pipe_config->hw.adjusted_mode.crtc_vdisplay;
- mode->vtotal = pipe_config->hw.adjusted_mode.crtc_vtotal;
- mode->vsync_start = pipe_config->hw.adjusted_mode.crtc_vsync_start;
- mode->vsync_end = pipe_config->hw.adjusted_mode.crtc_vsync_end;
+ mode->vdisplay = hw_mode->crtc_vdisplay;
+ mode->vtotal = hw_mode->crtc_vtotal;
+ mode->vsync_start = hw_mode->crtc_vsync_start;
+ mode->vsync_end = hw_mode->crtc_vsync_end;
- mode->flags = pipe_config->hw.adjusted_mode.flags;
+ mode->flags = hw_mode->flags;
mode->type = DRM_MODE_TYPE_DRIVER;
- mode->clock = pipe_config->hw.adjusted_mode.crtc_clock;
+ mode->clock = hw_mode->crtc_clock;
drm_mode_set_name(mode);
}
@@ -11207,6 +11285,9 @@ static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
} else {
tmp = intel_de_read(dev_priv,
TRANS_DDI_FUNC_CTL(cpu_transcoder));
+ if (!(tmp & TRANS_DDI_FUNC_ENABLE))
+ return;
+
if (INTEL_GEN(dev_priv) >= 12)
port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
else
@@ -11279,12 +11360,20 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
drm_WARN_ON(&dev_priv->drm, active);
active = true;
}
+ intel_dsc_get_config(pipe_config);
- if (!active)
- goto out;
+ if (!active) {
+ /* bigjoiner slave doesn't enable transcoder */
+ if (!pipe_config->bigjoiner_slave)
+ goto out;
- if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
- INTEL_GEN(dev_priv) >= 11) {
+ active = true;
+ pipe_config->pixel_multiplier = 1;
+
+ /* we cannot read out most state, so don't bother.. */
+ pipe_config->quirks |= PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE;
+ } else if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
+ INTEL_GEN(dev_priv) >= 11) {
hsw_get_ddi_port_state(crtc, pipe_config);
intel_get_transcoder_timings(crtc, pipe_config);
}
@@ -11370,8 +11459,11 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
}
}
- if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
- !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
+ if (pipe_config->bigjoiner_slave) {
+ /* Cannot be read out as a slave, set to 0. */
+ pipe_config->pixel_multiplier = 0;
+ } else if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
+ !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
pipe_config->pixel_multiplier =
intel_de_read(dev_priv,
PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
@@ -12386,7 +12478,7 @@ intel_encoder_current_mode(struct intel_encoder *encoder)
return NULL;
}
- encoder->get_config(encoder, crtc_state);
+ intel_encoder_get_config(encoder, crtc_state);
intel_mode_from_pipe_config(mode, crtc_state);
@@ -13385,12 +13477,15 @@ intel_crtc_copy_uapi_to_hw_state(struct intel_atomic_state *state,
intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc_state);
}
-static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
+static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state,
+ struct drm_display_mode *user_mode)
{
- crtc_state->uapi.enable = crtc_state->hw.enable;
- crtc_state->uapi.active = crtc_state->hw.active;
- drm_WARN_ON(crtc_state->uapi.crtc->dev,
- drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);
+ if (!crtc_state->bigjoiner_slave) {
+ crtc_state->uapi.enable = crtc_state->hw.enable;
+ crtc_state->uapi.active = crtc_state->hw.active;
+ drm_WARN_ON(crtc_state->uapi.crtc->dev,
+ drm_atomic_set_mode_for_crtc(&crtc_state->uapi, user_mode) < 0);
+ }
crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
@@ -14027,21 +14122,42 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_X(output_types);
- PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
- PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
- PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
- PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
- PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
- PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
-
- PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
- PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
- PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
- PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
- PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
- PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
-
- PIPE_CONF_CHECK_I(pixel_multiplier);
+ if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) {
+ /* bigjoiner mode = transcoder mode / 2, for calculations */
+ PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);
+ PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_htotal);
+ PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vdisplay);
+ PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vtotal);
+
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
+
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
+
+ PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
+ DRM_MODE_FLAG_INTERLACE);
+
+ if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
+ PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
+ DRM_MODE_FLAG_PHSYNC);
+ PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
+ DRM_MODE_FLAG_NHSYNC);
+ PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
+ DRM_MODE_FLAG_PVSYNC);
+ PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
+ DRM_MODE_FLAG_NVSYNC);
+ }
+ PIPE_CONF_CHECK_I(pixel_multiplier);
+ }
PIPE_CONF_CHECK_I(output_format);
PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
@@ -14051,24 +14167,11 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
PIPE_CONF_CHECK_BOOL(has_infoframe);
- PIPE_CONF_CHECK_BOOL(fec_enable);
+ if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE))
+ PIPE_CONF_CHECK_BOOL(fec_enable);
PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
- PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
- DRM_MODE_FLAG_INTERLACE);
-
- if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
- PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
- DRM_MODE_FLAG_PHSYNC);
- PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
- DRM_MODE_FLAG_NHSYNC);
- PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
- DRM_MODE_FLAG_PVSYNC);
- PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
- DRM_MODE_FLAG_NVSYNC);
- }
-
PIPE_CONF_CHECK_X(gmch_pfit.control);
/* pfit ratios are autocomputed by the hw on gen4+ */
if (INTEL_GEN(dev_priv) < 4)
@@ -14094,7 +14197,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
}
PIPE_CONF_CHECK_I(scaler_state.scaler_id);
- PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
+ if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE))
+ PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
PIPE_CONF_CHECK_X(gamma_mode);
if (IS_CHERRYVIEW(dev_priv))
@@ -14115,48 +14219,51 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_BOOL(double_wide);
PIPE_CONF_CHECK_P(shared_dpll);
- PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
- PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
- PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
- PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
- PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
- PIPE_CONF_CHECK_X(dpll_hw_state.spll);
- PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
- PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
- PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
- PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
- PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
- PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
- PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
- PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
- PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
- PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
- PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
- PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
- PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
- PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
- PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
-
- PIPE_CONF_CHECK_X(dsi_pll.ctrl);
- PIPE_CONF_CHECK_X(dsi_pll.div);
-
- if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
- PIPE_CONF_CHECK_I(pipe_bpp);
-
- PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
- PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
-
- PIPE_CONF_CHECK_I(min_voltage_level);
+ if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) {
+ PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
+ PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
+ PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
+ PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
+ PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
+ PIPE_CONF_CHECK_X(dpll_hw_state.spll);
+ PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
+ PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
+ PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
+ PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
+ PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
+ PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
+ PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
+ PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
+ PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
+ PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
+ PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
+ PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
+ PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
+ PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
+ PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
+ PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
+ PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
+ PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
+ PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
+ PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
+ PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
+ PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
+ PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
+ PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
+ PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
+
+ PIPE_CONF_CHECK_X(dsi_pll.ctrl);
+ PIPE_CONF_CHECK_X(dsi_pll.div);
+
+ if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
+ PIPE_CONF_CHECK_I(pipe_bpp);
+
+ PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
+ PIPE_CONF_CHECK_CLOCK_FUZZY(hw.pipe_mode.crtc_clock);
+ PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
+
+ PIPE_CONF_CHECK_I(min_voltage_level);
+ }
PIPE_CONF_CHECK_X(infoframes.enable);
PIPE_CONF_CHECK_X(infoframes.gcp);
@@ -14168,11 +14275,12 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
PIPE_CONF_CHECK_I(master_transcoder);
-
+ PIPE_CONF_CHECK_BOOL(bigjoiner);
+ PIPE_CONF_CHECK_BOOL(bigjoiner_slave);
+ PIPE_CONF_CHECK_P(bigjoiner_linked_crtc);
PIPE_CONF_CHECK_I(dsc.compression_enable);
PIPE_CONF_CHECK_I(dsc.dsc_split);
PIPE_CONF_CHECK_I(dsc.compressed_bpp);
-
PIPE_CONF_CHECK_I(mst_master_transcoder);
#undef PIPE_CONF_CHECK_X
@@ -14439,6 +14547,7 @@ verify_crtc_state(struct intel_crtc *crtc,
struct intel_encoder *encoder;
struct intel_crtc_state *pipe_config = old_crtc_state;
struct drm_atomic_state *state = old_crtc_state->uapi.state;
+ struct intel_crtc *master = crtc;
__drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi);
intel_crtc_free_hw_state(old_crtc_state);
@@ -14467,7 +14576,10 @@ verify_crtc_state(struct intel_crtc *crtc,
"(expected %i, found %i)\n",
new_crtc_state->hw.active, crtc->active);
- for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
+ if (new_crtc_state->bigjoiner_slave)
+ master = new_crtc_state->bigjoiner_linked_crtc;
+
+ for_each_encoder_on_crtc(dev, &master->base, encoder) {
enum pipe pipe;
bool active;
@@ -14477,12 +14589,12 @@ verify_crtc_state(struct intel_crtc *crtc,
encoder->base.base.id, active,
new_crtc_state->hw.active);
- I915_STATE_WARN(active && crtc->pipe != pipe,
+ I915_STATE_WARN(active && master->pipe != pipe,
"Encoder connected to wrong pipe %c\n",
pipe_name(pipe));
if (active)
- encoder->get_config(encoder, pipe_config);
+ intel_encoder_get_config(encoder, pipe_config);
}
intel_crtc_compute_pixel_rate(pipe_config);
@@ -15640,7 +15752,12 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ drm_WARN_ON(&dev_priv->drm, old_crtc_state->bigjoiner_slave);
+
intel_crtc_disable_planes(state, crtc);
+ if (old_crtc_state->bigjoiner)
+ intel_crtc_disable_planes(state,
+ old_crtc_state->bigjoiner_linked_crtc);
/*
* We need to disable pipe CRC before disabling the pipe,
@@ -15670,7 +15787,7 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state)
/* Only disable port sync and MST slaves */
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
- if (!needs_modeset(new_crtc_state))
+ if (!needs_modeset(new_crtc_state) || old_crtc_state->bigjoiner_slave)
continue;
if (!old_crtc_state->hw.active)
@@ -15685,7 +15802,6 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state)
!intel_dp_mst_is_slave_trans(old_crtc_state))
continue;
- intel_pre_plane_update(state, crtc);
intel_old_crtc_state_disables(state, old_crtc_state,
new_crtc_state, crtc);
handled |= BIT(crtc->pipe);
@@ -15695,10 +15811,18 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state)
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
if (!needs_modeset(new_crtc_state) ||
- (handled & BIT(crtc->pipe)))
+ (handled & BIT(crtc->pipe)) ||
+ old_crtc_state->bigjoiner_slave)
continue;
intel_pre_plane_update(state, crtc);
+ if (old_crtc_state->bigjoiner) {
+ struct intel_crtc *slave =
+ old_crtc_state->bigjoiner_linked_crtc;
+
+ intel_pre_plane_update(state, slave);
+ }
+
if (old_crtc_state->hw.active)
intel_old_crtc_state_disables(state, old_crtc_state,
new_crtc_state, crtc);
@@ -18357,7 +18481,7 @@ int intel_modeset_init_nogem(struct drm_i915_private *i915)
for_each_intel_crtc(dev, crtc) {
struct intel_initial_plane_config plane_config = {};
- if (!crtc->active)
+ if (!to_intel_crtc_state(crtc->base.state)->uapi.active)
continue;
/*
@@ -18880,9 +19004,19 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
crtc_state = to_intel_crtc_state(crtc->base.state);
encoder->base.crtc = &crtc->base;
- encoder->get_config(encoder, crtc_state);
+ intel_encoder_get_config(encoder, crtc_state);
if (encoder->sync_state)
encoder->sync_state(encoder, crtc_state);
+
+ /* read out to slave crtc as well for bigjoiner */
+ if (crtc_state->bigjoiner) {
+ /* encoder should read be linked to bigjoiner master */
+ WARN_ON(crtc_state->bigjoiner_slave);
+
+ crtc = crtc_state->bigjoiner_linked_crtc;
+ crtc_state = to_intel_crtc_state(crtc->base.state);
+ intel_encoder_get_config(encoder, crtc_state);
+ }
} else {
encoder->base.crtc = NULL;
}
@@ -18939,15 +19073,11 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
int min_cdclk = 0;
if (crtc_state->hw.active) {
- struct drm_display_mode *mode = &crtc_state->hw.mode;
+ struct drm_display_mode mode;
intel_mode_from_pipe_config(&crtc_state->hw.adjusted_mode,
crtc_state);
- *mode = crtc_state->hw.adjusted_mode;
- mode->hdisplay = crtc_state->pipe_src_w;
- mode->vdisplay = crtc_state->pipe_src_h;
-
/*
* The initial mode needs to be set in order to keep
* the atomic core happy. It wants a valid mode if the
@@ -18962,11 +19092,15 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
/* initialize pipe_mode */
crtc_state->hw.pipe_mode = crtc_state->hw.adjusted_mode;
+ mode = crtc_state->hw.adjusted_mode;
+ mode.hdisplay = crtc_state->pipe_src_w;
+ mode.vdisplay = crtc_state->pipe_src_h;
+
intel_crtc_compute_pixel_rate(crtc_state);
intel_crtc_update_active_timings(crtc_state);
- intel_crtc_copy_hw_to_uapi_state(crtc_state);
+ intel_crtc_copy_hw_to_uapi_state(crtc_state, &mode);
}
for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index c159f6a48bf0..7a62b1d7e727 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -838,6 +838,7 @@ struct intel_crtc_state {
* accordingly.
*/
#define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
+#define PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE (1<<1) /* bigjoiner slave, partial readout */
unsigned long quirks;
unsigned fb_bits; /* framebuffers to flip */
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index a627ad77dd3f..7a7994121274 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2103,12 +2103,10 @@ static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
{
- struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
-
- if (!intel_dp_is_edp(intel_dp) && !crtc_state->fec_enable)
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable)
return false;
- return intel_dsc_source_support(encoder, crtc_state) &&
+ return intel_dsc_source_support(crtc_state) &&
drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
}
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index c5735c365659..e2716a67b281 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -332,11 +332,10 @@ static const struct rc_parameters *get_rc_params(u16 compressed_bpp,
return &rc_parameters[row_index][column_index];
}
-bool intel_dsc_source_support(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state)
+bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
{
const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
enum pipe pipe = crtc->pipe;
@@ -490,11 +489,10 @@ intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
}
-static void intel_dsc_pps_configure(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state)
+static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
enum pipe pipe = crtc->pipe;
u32 pps_val = 0;
@@ -503,6 +501,9 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder,
u8 num_vdsc_instances = (crtc_state->dsc.dsc_split) ? 2 : 1;
int i = 0;
+ if (crtc_state->bigjoiner)
+ num_vdsc_instances *= 2;
+
/* Populate PICTURE_PARAMETER_SET_0 registers */
pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor <<
DSC_VER_MIN_SHIFT |
@@ -973,55 +974,6 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder,
}
}
-void intel_dsc_get_config(struct intel_encoder *encoder,
- struct intel_crtc_state *crtc_state)
-{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- enum pipe pipe = crtc->pipe;
- enum intel_display_power_domain power_domain;
- intel_wakeref_t wakeref;
- u32 dss_ctl1, dss_ctl2, val;
-
- if (!intel_dsc_source_support(encoder, crtc_state))
- return;
-
- power_domain = intel_dsc_power_domain(crtc_state);
-
- wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
- if (!wakeref)
- return;
-
- if (!is_pipe_dsc(crtc_state)) {
- dss_ctl1 = intel_de_read(dev_priv, DSS_CTL1);
- dss_ctl2 = intel_de_read(dev_priv, DSS_CTL2);
- } else {
- dss_ctl1 = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe));
- dss_ctl2 = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL2(pipe));
- }
-
- crtc_state->dsc.compression_enable = dss_ctl2 & LEFT_BRANCH_VDSC_ENABLE;
- if (!crtc_state->dsc.compression_enable)
- goto out;
-
- crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) &&
- (dss_ctl1 & JOINER_ENABLE);
-
- /* FIXME: add more state readout as needed */
-
- /* PPS1 */
- if (!is_pipe_dsc(crtc_state))
- val = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1);
- else
- val = intel_de_read(dev_priv,
- ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
- vdsc_cfg->bits_per_pixel = val;
- crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
-out:
- intel_display_power_put(dev_priv, power_domain, wakeref);
-}
-
static void intel_dsc_dsi_pps_write(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
@@ -1060,77 +1012,126 @@ static void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
sizeof(dp_dsc_pps_sdp));
}
+static i915_reg_t dss_ctl1_reg(const struct intel_crtc_state *crtc_state)
+{
+ enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
+
+ if (crtc_state->cpu_transcoder == TRANSCODER_EDP)
+ return DSS_CTL1;
+
+ return ICL_PIPE_DSS_CTL1(pipe);
+}
+
+static i915_reg_t dss_ctl2_reg(const struct intel_crtc_state *crtc_state)
+{
+ enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
+
+ if (crtc_state->cpu_transcoder == TRANSCODER_EDP)
+ return DSS_CTL2;
+
+ return ICL_PIPE_DSS_CTL2(pipe);
+}
+
void intel_dsc_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- enum pipe pipe = crtc->pipe;
- i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 dss_ctl1_val = 0;
u32 dss_ctl2_val = 0;
if (!crtc_state->dsc.compression_enable)
return;
- /* Enable Power wells for VDSC/joining */
- intel_display_power_get(dev_priv,
- intel_dsc_power_domain(crtc_state));
-
- intel_dsc_pps_configure(encoder, crtc_state);
+ intel_dsc_pps_configure(crtc_state);
- if (encoder->type == INTEL_OUTPUT_DSI)
- intel_dsc_dsi_pps_write(encoder, crtc_state);
- else
- intel_dsc_dp_pps_write(encoder, crtc_state);
-
- if (!is_pipe_dsc(crtc_state)) {
- dss_ctl1_reg = DSS_CTL1;
- dss_ctl2_reg = DSS_CTL2;
- } else {
- dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
- dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
+ if (!crtc_state->bigjoiner_slave) {
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
+ intel_dsc_dsi_pps_write(encoder, crtc_state);
+ else
+ intel_dsc_dp_pps_write(encoder, crtc_state);
}
+
dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE;
if (crtc_state->dsc.dsc_split) {
dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE;
dss_ctl1_val |= JOINER_ENABLE;
}
- intel_de_write(dev_priv, dss_ctl1_reg, dss_ctl1_val);
- intel_de_write(dev_priv, dss_ctl2_reg, dss_ctl2_val);
+ if (crtc_state->bigjoiner) {
+ dss_ctl1_val |= BIG_JOINER_ENABLE;
+ if (!crtc_state->bigjoiner_slave)
+ dss_ctl1_val |= MASTER_BIG_JOINER_ENABLE;
+ }
+ intel_de_write(dev_priv, dss_ctl1_reg(crtc_state), dss_ctl1_val);
+ intel_de_write(dev_priv, dss_ctl2_reg(crtc_state), dss_ctl2_val);
}
void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- enum pipe pipe = crtc->pipe;
- i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
- u32 dss_ctl1_val = 0, dss_ctl2_val = 0;
if (!old_crtc_state->dsc.compression_enable)
return;
- if (!is_pipe_dsc(old_crtc_state)) {
- dss_ctl1_reg = DSS_CTL1;
- dss_ctl2_reg = DSS_CTL2;
- } else {
- dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
- dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
+ intel_de_write(dev_priv, dss_ctl1_reg(old_crtc_state), 0);
+ intel_de_write(dev_priv, dss_ctl2_reg(old_crtc_state), 0);
+}
+
+void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
+{
+ struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+ enum intel_display_power_domain power_domain;
+ intel_wakeref_t wakeref;
+ u32 dss_ctl1, dss_ctl2, val;
+
+ if (!intel_dsc_source_support(crtc_state))
+ return;
+
+ power_domain = intel_dsc_power_domain(crtc_state);
+
+ wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
+ if (!wakeref)
+ return;
+
+ dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc_state));
+ dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg(crtc_state));
+
+ crtc_state->dsc.compression_enable = dss_ctl2 & LEFT_BRANCH_VDSC_ENABLE;
+ if (!crtc_state->dsc.compression_enable)
+ goto out;
+
+ crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) &&
+ (dss_ctl1 & JOINER_ENABLE);
+
+ if (dss_ctl1 & BIG_JOINER_ENABLE) {
+ crtc_state->bigjoiner = true;
+
+ if (!(dss_ctl1 & MASTER_BIG_JOINER_ENABLE)) {
+ crtc_state->bigjoiner_slave = true;
+ if (!WARN_ON(crtc->pipe == PIPE_A))
+ crtc_state->bigjoiner_linked_crtc =
+ intel_get_crtc_for_pipe(dev_priv, crtc->pipe - 1);
+ } else {
+ if (!WARN_ON(INTEL_NUM_PIPES(dev_priv) == crtc->pipe + 1))
+ crtc_state->bigjoiner_linked_crtc =
+ intel_get_crtc_for_pipe(dev_priv, crtc->pipe + 1);
+ }
}
- dss_ctl1_val = intel_de_read(dev_priv, dss_ctl1_reg);
- if (dss_ctl1_val & JOINER_ENABLE)
- dss_ctl1_val &= ~JOINER_ENABLE;
- intel_de_write(dev_priv, dss_ctl1_reg, dss_ctl1_val);
-
- dss_ctl2_val = intel_de_read(dev_priv, dss_ctl2_reg);
- if (dss_ctl2_val & LEFT_BRANCH_VDSC_ENABLE ||
- dss_ctl2_val & RIGHT_BRANCH_VDSC_ENABLE)
- dss_ctl2_val &= ~(LEFT_BRANCH_VDSC_ENABLE |
- RIGHT_BRANCH_VDSC_ENABLE);
- intel_de_write(dev_priv, dss_ctl2_reg, dss_ctl2_val);
-
- /* Disable Power wells for VDSC/joining */
- intel_display_power_put_unchecked(dev_priv,
- intel_dsc_power_domain(old_crtc_state));
+
+ /* FIXME: add more state readout as needed */
+
+ /* PPS1 */
+ if (!is_pipe_dsc(crtc_state))
+ val = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1);
+ else
+ val = intel_de_read(dev_priv,
+ ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
+ vdsc_cfg->bits_per_pixel = val;
+ crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
+out:
+ intel_display_power_put(dev_priv, power_domain, wakeref);
}
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h
index e56a3254c214..5301345ac5e7 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.h
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
@@ -11,15 +11,14 @@
struct intel_encoder;
struct intel_crtc_state;
-bool intel_dsc_source_support(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state);
+bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state);
void intel_dsc_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void intel_dsc_disable(const struct intel_crtc_state *crtc_state);
int intel_dsc_compute_params(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config);
-void intel_dsc_get_config(struct intel_encoder *encoder,
- struct intel_crtc_state *crtc_state);
+void intel_dsc_get_config(struct intel_crtc_state *crtc_state);
+
enum intel_display_power_domain
intel_dsc_power_domain(const struct intel_crtc_state *crtc_state);
--
2.19.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Intel-gfx] [PATCH v10 07/11] drm/i915: Make hardware readout work on i915.
2020-10-08 21:45 [Intel-gfx] [PATCH v10 01/11] HAX to make DSC work on the icelake test system Manasi Navare
` (4 preceding siblings ...)
2020-10-08 21:45 ` [Intel-gfx] [PATCH v10 06/11] drm/i915: Enable big joiner support in enable and disable sequences Manasi Navare
@ 2020-10-08 21:45 ` Manasi Navare
2020-10-11 20:18 ` kernel test robot
2020-10-19 16:36 ` Ville Syrjälä
2020-10-08 21:45 ` [Intel-gfx] [PATCH v10 08/11] drm/i915: Link planes in a bigjoiner configuration, v3 Manasi Navare
` (11 subsequent siblings)
17 siblings, 2 replies; 50+ messages in thread
From: Manasi Navare @ 2020-10-08 21:45 UTC (permalink / raw)
To: intel-gfx
From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Unfortunately I have no way to test this, but it should be correct
if the bios sets up bigjoiner in a sane way.
Skip iterating over bigjoiner slaves, only the master has the state we
care about.
Add the width of the bigjoiner slave to the reconstructed fb.
Hide the bigjoiner slave to userspace, and double the mode on bigjoiner
master.
And last, disable bigjoiner slave from primary if reconstruction fails.
v2:
* Manual Rebase (Manasi)
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 64 +++++++++++++++++++-
1 file changed, 62 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index faf8bf757bed..aa981aa4f6a1 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3619,6 +3619,8 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
struct intel_plane *intel_plane = to_intel_plane(primary);
struct intel_plane_state *intel_state =
to_intel_plane_state(plane_state);
+ struct intel_crtc_state *crtc_state =
+ to_intel_crtc_state(intel_crtc->base.state);
struct drm_framebuffer *fb;
struct i915_vma *vma;
@@ -3641,7 +3643,7 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
if (c == &intel_crtc->base)
continue;
- if (!to_intel_crtc(c)->active)
+ if (!to_intel_crtc_state(c->state)->uapi.active)
continue;
state = to_intel_plane_state(c->primary->state);
@@ -3663,6 +3665,11 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
* pretend the BIOS never had it enabled.
*/
intel_plane_disable_noatomic(intel_crtc, intel_plane);
+ if (crtc_state->bigjoiner) {
+ struct intel_crtc *slave =
+ crtc_state->bigjoiner_linked_crtc;
+ intel_plane_disable_noatomic(slave, to_intel_plane(slave->base.primary));
+ }
return;
@@ -10687,6 +10694,7 @@ static void
skl_get_initial_plane_config(struct intel_crtc *crtc,
struct intel_initial_plane_config *plane_config)
{
+ struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_plane *plane = to_intel_plane(crtc->base.primary);
@@ -10795,6 +10803,18 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
fb->height = ((val >> 16) & 0xffff) + 1;
fb->width = ((val >> 0) & 0xffff) + 1;
+ /* add bigjoiner slave as well, if the fb stretches both */
+ if (crtc_state->bigjoiner) {
+ enum pipe bigjoiner_pipe = crtc_state->bigjoiner_linked_crtc->pipe;
+
+ if (fb->width == crtc_state->pipe_src_w &&
+ (intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & 0xfffff000) == plane_config->base) {
+ val = intel_de_read(dev_priv, PLANE_SIZE(bigjoiner_pipe, plane_id));
+ fb->height += ((val >> 16) & 0xfff) + 1;
+ fb->width += ((val >> 0) & 0x1fff) + 1;
+ }
+ }
+
val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id));
stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
fb->pitches[0] = (val & 0x3ff) * stride_mult;
@@ -18793,7 +18813,8 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc,
/* Adjust the state of the output pipe according to whether we
* have active connectors/encoders. */
- if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc))
+ if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc) &&
+ !crtc_state->bigjoiner_slave)
intel_crtc_disable_noatomic(crtc, ctx);
if (crtc_state->hw.active || HAS_GMCH(dev_priv)) {
@@ -19072,6 +19093,9 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
struct intel_plane *plane;
int min_cdclk = 0;
+ if (crtc_state->bigjoiner_slave)
+ continue;
+
if (crtc_state->hw.active) {
struct drm_display_mode mode;
@@ -19096,6 +19120,9 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
mode.hdisplay = crtc_state->pipe_src_w;
mode.vdisplay = crtc_state->pipe_src_h;
+ if (crtc_state->bigjoiner)
+ mode.hdisplay *= 2;
+
intel_crtc_compute_pixel_rate(crtc_state);
intel_crtc_update_active_timings(crtc_state);
@@ -19146,6 +19173,39 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
intel_bw_crtc_update(bw_state, crtc_state);
intel_pipe_config_sanity_check(dev_priv, crtc_state);
+
+ /* discard our incomplete slave state, copy it from master */
+ if (crtc_state->bigjoiner && crtc_state->hw.active) {
+ struct intel_crtc *slave = crtc_state->bigjoiner_linked_crtc;
+ struct intel_crtc_state *slave_crtc_state =
+ to_intel_crtc_state(slave->base.state);
+
+ copy_bigjoiner_crtc_state(slave_crtc_state, crtc_state);
+ slave->base.mode = crtc->base.mode;
+
+ cdclk_state->min_cdclk[slave->pipe] = min_cdclk;
+ cdclk_state->min_voltage_level[slave->pipe] =
+ crtc_state->min_voltage_level;
+
+ for_each_intel_plane_on_crtc(&dev_priv->drm, slave, plane) {
+ const struct intel_plane_state *plane_state =
+ to_intel_plane_state(plane->base.state);
+
+ /*
+ * FIXME don't have the fb yet, so can't
+ * use intel_plane_data_rate() :(
+ */
+ if (plane_state->uapi.visible)
+ crtc_state->data_rate[plane->id] =
+ 4 * crtc_state->pixel_rate;
+ else
+ crtc_state->data_rate[plane->id] = 0;
+ }
+
+ intel_bw_crtc_update(bw_state, slave_crtc_state);
+ drm_calc_timestamping_constants(&slave->base,
+ &slave_crtc_state->hw.adjusted_mode);
+ }
}
}
--
2.19.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Intel-gfx] [PATCH v10 08/11] drm/i915: Link planes in a bigjoiner configuration, v3.
2020-10-08 21:45 [Intel-gfx] [PATCH v10 01/11] HAX to make DSC work on the icelake test system Manasi Navare
` (5 preceding siblings ...)
2020-10-08 21:45 ` [Intel-gfx] [PATCH v10 07/11] drm/i915: Make hardware readout work on i915 Manasi Navare
@ 2020-10-08 21:45 ` Manasi Navare
2020-10-08 21:45 ` [Intel-gfx] [PATCH v10 09/11] drm/i915: Add bigjoiner aware plane clipping checks Manasi Navare
` (10 subsequent siblings)
17 siblings, 0 replies; 50+ messages in thread
From: Manasi Navare @ 2020-10-08 21:45 UTC (permalink / raw)
To: intel-gfx
From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Make sure that when a plane is set in a bigjoiner mode, we will add
their counterpart to the atomic state as well. This will allow us to
make sure all state is available when planes are checked.
Because of the funny interactions with bigjoiner and planar YUV
formats, we may end up adding a lot of planes, so we have to keep
iterating until we no longer add any planes.
Also fix the atomic intel plane iterator, so things watermarks start
working automagically.
v6:
* Fix from_plane_state assignments (Manasi)
v5:
* Rebase after adding sagv support (Manasi)
v4:
* Manual rebase (Manasi)
Changes since v1:
- Rebase on top of plane_state split, cleaning up the code a lot.
- Make intel_atomic_crtc_state_for_each_plane_state() bigjoiner capable.
- Add iter macro to intel_atomic_crtc_state_for_each_plane_state() to
keep iteration working.
Changes since v2:
- Add icl_(un)set_bigjoiner_plane_links, to make it more clear where
links are made and broken.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 53 ++++-
.../gpu/drm/i915/display/intel_atomic_plane.h | 3 +-
drivers/gpu/drm/i915/display/intel_display.c | 207 ++++++++++++++++--
drivers/gpu/drm/i915/display/intel_display.h | 20 +-
.../drm/i915/display/intel_display_types.h | 11 +
drivers/gpu/drm/i915/intel_pm.c | 20 +-
6 files changed, 274 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 6bd8e6cdd477..a8f1fd85a6c0 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -246,12 +246,17 @@ static void intel_plane_clear_hw_state(struct intel_plane_state *plane_state)
memset(&plane_state->hw, 0, sizeof(plane_state->hw));
}
-void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
+void intel_plane_copy_uapi_to_hw_state(const struct intel_crtc_state *crtc_state,
+ struct intel_plane_state *plane_state,
const struct intel_plane_state *from_plane_state)
{
intel_plane_clear_hw_state(plane_state);
- plane_state->hw.crtc = from_plane_state->uapi.crtc;
+ if (from_plane_state->uapi.crtc)
+ plane_state->hw.crtc = crtc_state->uapi.crtc;
+ else
+ plane_state->hw.crtc = NULL;
+
plane_state->hw.fb = from_plane_state->uapi.fb;
if (plane_state->hw.fb)
drm_framebuffer_get(plane_state->hw.fb);
@@ -319,15 +324,36 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
}
static struct intel_crtc *
-get_crtc_from_states(const struct intel_plane_state *old_plane_state,
+get_crtc_from_states(struct intel_atomic_state *state,
+ const struct intel_plane_state *old_plane_state,
const struct intel_plane_state *new_plane_state)
{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
+
if (new_plane_state->uapi.crtc)
return to_intel_crtc(new_plane_state->uapi.crtc);
if (old_plane_state->uapi.crtc)
return to_intel_crtc(old_plane_state->uapi.crtc);
+ if (new_plane_state->bigjoiner_slave) {
+ const struct intel_plane_state *new_master_plane_state =
+ intel_atomic_get_new_plane_state(state, new_plane_state->bigjoiner_plane);
+
+ /* need to use uapi here, new_master_plane_state might not be copied to hw yet */
+ if (new_master_plane_state->uapi.crtc)
+ return intel_get_crtc_for_pipe(dev_priv, plane->pipe);
+ }
+
+ if (old_plane_state->bigjoiner_slave) {
+ const struct intel_plane_state *old_master_plane_state =
+ intel_atomic_get_old_plane_state(state, old_plane_state->bigjoiner_plane);
+
+ if (old_master_plane_state->uapi.crtc)
+ return intel_get_crtc_for_pipe(dev_priv, plane->pipe);
+ }
+
return NULL;
}
@@ -338,18 +364,33 @@ int intel_plane_atomic_check(struct intel_atomic_state *state,
intel_atomic_get_new_plane_state(state, plane);
const struct intel_plane_state *old_plane_state =
intel_atomic_get_old_plane_state(state, plane);
+ const struct intel_plane_state *new_master_plane_state;
struct intel_crtc *crtc =
- get_crtc_from_states(old_plane_state, new_plane_state);
+ get_crtc_from_states(state, old_plane_state,
+ new_plane_state);
const struct intel_crtc_state *old_crtc_state;
struct intel_crtc_state *new_crtc_state;
- intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state);
+ if (crtc)
+ new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
+ else
+ new_crtc_state = NULL;
+
+ new_master_plane_state = new_plane_state;
+ if (new_plane_state->bigjoiner_slave)
+ new_master_plane_state =
+ intel_atomic_get_new_plane_state(state,
+ new_plane_state->bigjoiner_plane);
+
+ intel_plane_copy_uapi_to_hw_state(new_crtc_state,
+ new_plane_state,
+ new_master_plane_state);
+
new_plane_state->uapi.visible = false;
if (!crtc)
return 0;
old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
- new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
return intel_plane_atomic_check_with_state(old_crtc_state,
new_crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index 59dd1fbb02ea..c2a1e7c86e6c 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -23,7 +23,8 @@ unsigned int intel_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state);
-void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
+void intel_plane_copy_uapi_to_hw_state(const struct intel_crtc_state *crtc_state,
+ struct intel_plane_state *plane_state,
const struct intel_plane_state *from_plane_state);
void intel_update_plane(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index aa981aa4f6a1..d5a6f07bb674 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3706,7 +3706,7 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
drm_framebuffer_get(fb);
plane_state->crtc = &intel_crtc->base;
- intel_plane_copy_uapi_to_hw_state(intel_state, intel_state);
+ intel_plane_copy_uapi_to_hw_state(crtc_state, intel_state, intel_state);
intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
@@ -12708,26 +12708,180 @@ static bool check_single_encoder_cloning(struct intel_atomic_state *state,
return true;
}
+static int icl_unset_bigjoiner_plane_links(struct intel_atomic_state *state,
+ struct intel_crtc_state *new_crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
+ struct intel_plane *plane;
+
+ /*
+ * Teardown the old bigjoiner plane mappings.
+ */
+ for_each_intel_plane_on_crtc(crtc->base.dev, crtc, plane) {
+ struct intel_plane_state *plane_state, *other_plane_state;
+ struct intel_plane *other_plane;
+
+ plane_state = intel_atomic_get_plane_state(state, plane);
+ if (IS_ERR(plane_state))
+ return PTR_ERR(plane_state);
+
+ other_plane = plane_state->bigjoiner_plane;
+ if (!other_plane)
+ continue;
+
+ plane_state->bigjoiner_plane = NULL;
+ plane_state->bigjoiner_slave = false;
+
+ other_plane_state = intel_atomic_get_plane_state(state, other_plane);
+ if (IS_ERR(other_plane_state))
+ return PTR_ERR(other_plane_state);
+ other_plane_state->bigjoiner_plane = NULL;
+ other_plane_state->bigjoiner_slave = false;
+ }
+ return 0;
+}
+
+static int icl_set_bigjoiner_plane_links(struct intel_atomic_state *state,
+ struct intel_crtc_state *new_crtc_state)
+{
+ struct intel_plane *plane;
+ struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
+ struct intel_crtc *other_crtc = new_crtc_state->bigjoiner_linked_crtc;
+
+ /*
+ * Setup and teardown the new bigjoiner plane mappings.
+ */
+ for_each_intel_plane_on_crtc(crtc->base.dev, crtc, plane) {
+ struct intel_plane_state *plane_state;
+ struct intel_plane *other_plane = NULL;
+ bool found_plane = false;
+
+ plane_state = intel_atomic_get_plane_state(state, plane);
+ if (IS_ERR(plane_state))
+ return PTR_ERR(plane_state);
+
+ for_each_intel_plane_on_crtc(crtc->base.dev, other_crtc, other_plane) {
+ if (other_plane->id != plane->id)
+ continue;
+
+ plane_state->bigjoiner_plane = other_plane;
+ plane_state->bigjoiner_slave = new_crtc_state->bigjoiner_slave;
+
+ plane_state = intel_atomic_get_plane_state(state, other_plane);
+ if (IS_ERR(plane_state))
+ return PTR_ERR(plane_state);
+
+ plane_state->bigjoiner_plane = plane;
+ plane_state->bigjoiner_slave = !new_crtc_state->bigjoiner_slave;
+
+ found_plane = true;
+ break;
+ }
+
+ if (!found_plane) {
+ /* All pipes should have identical planes. */
+ WARN_ON(!found_plane);
+ return -EINVAL;
+ }
+ }
+ return 0;
+}
+
+static int icl_add_dependent_planes(struct intel_atomic_state *state,
+ struct intel_plane_state *plane_state)
+{
+ struct intel_plane_state *new_plane_state;
+ struct intel_plane *plane;
+ int ret = 0;
+
+ plane = plane_state->bigjoiner_plane;
+ if (plane && !intel_atomic_get_new_plane_state(state, plane)) {
+ new_plane_state = intel_atomic_get_plane_state(state, plane);
+ if (IS_ERR(new_plane_state))
+ return PTR_ERR(new_plane_state);
+
+ ret = 1;
+ }
+
+ plane = plane_state->planar_linked_plane;
+ if (plane && !intel_atomic_get_new_plane_state(state, plane)) {
+ new_plane_state = intel_atomic_get_plane_state(state, plane);
+ if (IS_ERR(new_plane_state))
+ return PTR_ERR(new_plane_state);
+
+ ret = 1;
+ }
+
+ return ret;
+}
+
static int icl_add_linked_planes(struct intel_atomic_state *state)
{
- struct intel_plane *plane, *linked;
- struct intel_plane_state *plane_state, *linked_plane_state;
+ struct intel_plane *plane;
+ struct intel_plane_state *old_plane_state, *new_plane_state;
+ struct intel_crtc *crtc, *linked_crtc;
+ struct intel_crtc_state *old_crtc_state, *new_crtc_state, *linked_crtc_state;
+ bool added;
int i;
- for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
- linked = plane_state->planar_linked_plane;
+ /*
+ * Iteratively add plane_state->linked_plane and plane_state->bigjoiner_plane
+ *
+ * This needs to be done repeatedly, because of is a funny interaction;
+ * the Y-plane may be assigned differently on the other bigjoiner crtc,
+ * and we could end up with the following evil recursion, when only adding a
+ * single plane to state:
+ *
+ * XRGB8888 master plane 6 adds NV12 slave Y-plane 6, which adds slave UV plane 0,
+ * which adds master UV plane 0, which adds master Y-plane 7, which adds XRGB8888
+ *slave plane 7.
+ *
+ * We could pull in even more because of old_plane_state vs new_plane_state.
+ *
+ * Max depth = 5 (or 7 for evil case) in this case.
+ * Number of passes will be less, because newly added planes show up in the
+ * same iteration round when added_plane->index > plane->index.
+ */
+ do {
+ added = false;
- if (!linked)
- continue;
+ for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
+ int ret, ret2;
+
+ ret = icl_add_dependent_planes(state, old_plane_state);
+ if (ret < 0)
+ return ret;
+
+ ret2 = icl_add_dependent_planes(state, new_plane_state);
+ if (ret2 < 0)
+ return ret2;
+
+ added |= ret || ret2;
+ }
+ } while (added);
+
+ /*
+ * Make sure bigjoiner slave crtc's are also pulled in. This is not done automatically
+ * when adding slave planes, because plane_state->crtc is null.
+ */
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
+ linked_crtc = old_crtc_state->bigjoiner_linked_crtc;
+ if (linked_crtc) {
+ linked_crtc_state =
+ intel_atomic_get_crtc_state(&state->base, linked_crtc);
+
+ if (IS_ERR(linked_crtc_state))
+ return PTR_ERR(linked_crtc_state);
+ }
- linked_plane_state = intel_atomic_get_plane_state(state, linked);
- if (IS_ERR(linked_plane_state))
- return PTR_ERR(linked_plane_state);
+ linked_crtc = new_crtc_state->bigjoiner_linked_crtc;
+ if (linked_crtc && linked_crtc != old_crtc_state->bigjoiner_linked_crtc) {
+ linked_crtc_state =
+ intel_atomic_get_crtc_state(&state->base, linked_crtc);
- drm_WARN_ON(state->base.dev,
- linked_plane_state->planar_linked_plane != plane);
- drm_WARN_ON(state->base.dev,
- linked_plane_state->planar_slave == plane_state->planar_slave);
+ if (IS_ERR(linked_crtc_state))
+ return PTR_ERR(linked_crtc_state);
+ }
}
return 0;
@@ -12767,6 +12921,7 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
struct intel_plane_state *linked_state = NULL;
+ struct intel_plane_state *master_plane_state;
if (plane->pipe != crtc->pipe ||
!(crtc_state->nv12_planes & BIT(plane->id)))
@@ -12810,7 +12965,14 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
memcpy(linked_state->color_plane, plane_state->color_plane,
sizeof(linked_state->color_plane));
- intel_plane_copy_uapi_to_hw_state(linked_state, plane_state);
+ master_plane_state = plane_state;
+ if (plane_state->bigjoiner_slave)
+ master_plane_state =
+ intel_atomic_get_new_plane_state(state,
+ plane_state->bigjoiner_plane);
+
+ intel_plane_copy_uapi_to_hw_state(crtc_state, linked_state,
+ master_plane_state);
linked_state->uapi.src = plane_state->uapi.src;
linked_state->uapi.dst = plane_state->uapi.dst;
@@ -15154,6 +15316,7 @@ static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state,
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc_state *slave_crtc_state, *master_crtc_state;
struct intel_crtc *slave, *master;
+ int ret;
/* slave being enabled, is master is still claiming this crtc? */
if (old_crtc_state->bigjoiner_slave) {
@@ -15164,6 +15327,12 @@ static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state,
goto claimed;
}
+ if (old_crtc_state->bigjoiner) {
+ ret = icl_unset_bigjoiner_plane_links(state, new_crtc_state);
+ if (ret)
+ return ret;
+ }
+
if (!new_crtc_state->bigjoiner)
return 0;
@@ -15188,7 +15357,11 @@ static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state,
DRM_DEBUG_KMS("[CRTC:%d:%s] Used as slave for big joiner\n",
slave->base.base.id, slave->base.name);
- return copy_bigjoiner_crtc_state(slave_crtc_state, new_crtc_state);
+ ret = copy_bigjoiner_crtc_state(slave_crtc_state, new_crtc_state);
+ if (ret)
+ return ret;
+
+ return icl_set_bigjoiner_plane_links(state, new_crtc_state);
claimed:
DRM_DEBUG_KMS("[CRTC:%d:%s] Slave is enabled as normal CRTC, but "
@@ -16790,7 +16963,7 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
new_plane_state->uapi.crtc_w = crtc_w;
new_plane_state->uapi.crtc_h = crtc_h;
- intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state);
+ intel_plane_copy_uapi_to_hw_state(new_crtc_state, new_plane_state, new_plane_state);
ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state,
old_plane_state, new_plane_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 3d860a9da8fe..0887ef783116 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -467,12 +467,20 @@ enum phy_fia {
for_each_if(crtc)
#define intel_atomic_crtc_state_for_each_plane_state( \
- plane, plane_state, \
- crtc_state) \
- for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \
- ((crtc_state)->uapi.plane_mask)) \
- for_each_if ((plane_state = \
- to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base))))
+ plane, iter, plane_state, \
+ crtc_state) \
+ for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (iter), \
+ (((crtc_state)->bigjoiner_slave ? \
+ intel_atomic_get_new_crtc_state( \
+ to_intel_atomic_state((crtc_state)->uapi.state), \
+ (crtc_state)->bigjoiner_linked_crtc) : \
+ (crtc_state))->uapi.plane_mask)) \
+ for_each_if ((((plane_state) = \
+ to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &iter->base))), \
+ ((plane) = (plane_state)->bigjoiner_slave ? (plane_state)->bigjoiner_plane : (iter)), \
+ ((plane_state) = (plane_state)->bigjoiner_slave ? \
+ to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base)) : \
+ (plane_state))))
#define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
for ((__i) = 0; \
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 7a62b1d7e727..19c6d117f353 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -587,6 +587,17 @@ struct intel_plane_state {
*/
struct intel_plane *planar_linked_plane;
+ /*
+ * bigjoiner_plane:
+ *
+ * When 2 pipes are joined in a bigjoiner configuration,
+ * points to the same plane on the other pipe.
+ *
+ * bigjoiner_slave is set on the slave pipe.
+ */
+ struct intel_plane *bigjoiner_plane;
+ u32 bigjoiner_slave;
+
/*
* planar_slave:
* If set don't update use the linked plane's state for updating
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1b9fd02f49b4..387e80e1e590 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3144,7 +3144,7 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct intel_pipe_wm *pipe_wm;
- struct intel_plane *plane;
+ struct intel_plane *plane, *iter;
const struct intel_plane_state *plane_state;
const struct intel_plane_state *pristate = NULL;
const struct intel_plane_state *sprstate = NULL;
@@ -3154,7 +3154,7 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
pipe_wm = &crtc_state->wm.ilk.optimal;
- intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
+ intel_atomic_crtc_state_for_each_plane_state(plane, iter, plane_state, crtc_state) {
if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
pristate = plane_state;
else if (plane->base.type == DRM_PLANE_TYPE_OVERLAY)
@@ -3873,7 +3873,7 @@ static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- struct intel_plane *plane;
+ struct intel_plane *plane, *iter;
const struct intel_plane_state *plane_state;
int level, latency;
@@ -3886,7 +3886,7 @@ static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
if (crtc_state->hw.pipe_mode.flags & DRM_MODE_FLAG_INTERLACE)
return false;
- intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
+ intel_atomic_crtc_state_for_each_plane_state(plane, iter, plane_state, crtc_state) {
const struct skl_plane_wm *wm =
&crtc_state->wm.skl.optimal.planes[plane->id];
@@ -4708,12 +4708,12 @@ skl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
u64 *plane_data_rate,
u64 *uv_plane_data_rate)
{
- struct intel_plane *plane;
+ struct intel_plane *plane, *iter;
const struct intel_plane_state *plane_state;
u64 total_data_rate = 0;
/* Calculate and cache data rate for each plane */
- intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
+ intel_atomic_crtc_state_for_each_plane_state(plane, iter, plane_state, crtc_state) {
enum plane_id plane_id = plane->id;
u64 rate;
@@ -4735,12 +4735,12 @@ static u64
icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
u64 *plane_data_rate)
{
- struct intel_plane *plane;
+ struct intel_plane *plane, *iter;
const struct intel_plane_state *plane_state;
u64 total_data_rate = 0;
/* Calculate and cache data rate for each plane */
- intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
+ intel_atomic_crtc_state_for_each_plane_state(plane, iter, plane_state, crtc_state) {
enum plane_id plane_id = plane->id;
u64 rate;
@@ -5587,7 +5587,7 @@ static int skl_build_pipe_wm(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
- struct intel_plane *plane;
+ struct intel_plane *plane, *iter;
const struct intel_plane_state *plane_state;
int ret;
@@ -5597,7 +5597,7 @@ static int skl_build_pipe_wm(struct intel_crtc_state *crtc_state)
*/
memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes));
- intel_atomic_crtc_state_for_each_plane_state(plane, plane_state,
+ intel_atomic_crtc_state_for_each_plane_state(plane, iter, plane_state,
crtc_state) {
if (INTEL_GEN(dev_priv) >= 11)
--
2.19.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Intel-gfx] [PATCH v10 09/11] drm/i915: Add bigjoiner aware plane clipping checks
2020-10-08 21:45 [Intel-gfx] [PATCH v10 01/11] HAX to make DSC work on the icelake test system Manasi Navare
` (6 preceding siblings ...)
2020-10-08 21:45 ` [Intel-gfx] [PATCH v10 08/11] drm/i915: Link planes in a bigjoiner configuration, v3 Manasi Navare
@ 2020-10-08 21:45 ` Manasi Navare
2020-10-19 16:20 ` Ville Syrjälä
2020-10-08 21:45 ` [Intel-gfx] [PATCH v10 10/11] drm/i915: Ensure correct master/slave enable/disable sequence Manasi Navare
` (9 subsequent siblings)
17 siblings, 1 reply; 50+ messages in thread
From: Manasi Navare @ 2020-10-08 21:45 UTC (permalink / raw)
To: intel-gfx
From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
We need to look at hw.fb for the framebuffer, and add the translation
for the slave_plane_state. With these changes we set the correct
rectangle on the bigjoiner slave, and don't set incorrect
src/dst/visibility on the slave plane.
v2:
* Manual rebase (Manasi)
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 60 +++++++++++++++++++
.../gpu/drm/i915/display/intel_atomic_plane.h | 4 ++
drivers/gpu/drm/i915/display/intel_display.c | 19 +++---
drivers/gpu/drm/i915/display/intel_sprite.c | 21 +++----
4 files changed, 80 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index a8f1fd85a6c0..09cb3adc36da 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -267,6 +267,9 @@ void intel_plane_copy_uapi_to_hw_state(const struct intel_crtc_state *crtc_state
plane_state->hw.rotation = from_plane_state->uapi.rotation;
plane_state->hw.color_encoding = from_plane_state->uapi.color_encoding;
plane_state->hw.color_range = from_plane_state->uapi.color_range;
+
+ plane_state->uapi.src = drm_plane_state_src(&from_plane_state->uapi);
+ plane_state->uapi.dst = drm_plane_state_dest(&from_plane_state->uapi);
}
void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
@@ -519,6 +522,63 @@ void i9xx_update_planes_on_crtc(struct intel_atomic_state *state,
}
}
+int intel_atomic_plane_check_clipping(struct intel_plane_state *plane_state,
+ struct intel_crtc_state *crtc_state,
+ int min_scale, int max_scale,
+ bool can_position)
+{
+ struct drm_framebuffer *fb = plane_state->hw.fb;
+ struct drm_rect *src = &plane_state->uapi.src;
+ struct drm_rect *dst = &plane_state->uapi.dst;
+ unsigned int rotation = plane_state->uapi.rotation;
+ struct drm_rect clip = {};
+ int hscale, vscale;
+
+ if (!fb) {
+ plane_state->uapi.visible = false;
+ return 0;
+ }
+
+ drm_rect_rotate(src, fb->width << 16, fb->height << 16, rotation);
+
+ /* Check scaling */
+ hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
+ vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
+ if (hscale < 0 || vscale < 0) {
+ DRM_DEBUG_KMS("Invalid scaling of plane\n");
+ drm_rect_debug_print("src: ", src, true);
+ drm_rect_debug_print("dst: ", dst, false);
+ return -ERANGE;
+ }
+
+ if (crtc_state->hw.enable) {
+ clip.x2 = crtc_state->pipe_src_w;
+ clip.y2 = crtc_state->pipe_src_h;
+ }
+
+ /* right side of the image is on the slave crtc, adjust dst to match */
+ if (crtc_state->bigjoiner_slave)
+ drm_rect_translate(dst, -crtc_state->pipe_src_w, 0);
+
+ /*
+ * FIXME: This might need further adjustment for seamless scaling
+ * with phase information, for the 2p2 and 2p1 scenarios.
+ */
+ plane_state->uapi.visible = drm_rect_clip_scaled(src, dst, &clip);
+
+ drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16, rotation);
+
+ if (!can_position && plane_state->uapi.visible &&
+ !drm_rect_equals(dst, &clip)) {
+ DRM_DEBUG_KMS("Plane must cover entire CRTC\n");
+ drm_rect_debug_print("dst: ", dst, false);
+ drm_rect_debug_print("clip: ", &clip, false);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
const struct drm_plane_helper_funcs intel_plane_helper_funcs = {
.prepare_fb = intel_prepare_plane_fb,
.cleanup_fb = intel_cleanup_plane_fb,
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index c2a1e7c86e6c..d0a599d00ecd 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -53,6 +53,10 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
struct intel_plane *plane,
bool *need_cdclk_calc);
+int intel_atomic_plane_check_clipping(struct intel_plane_state *plane_state,
+ struct intel_crtc_state *crtc_state,
+ int min_scale, int max_scale,
+ bool can_position);
void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
struct intel_plane_state *plane_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index d5a6f07bb674..357cc2bce300 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4409,12 +4409,10 @@ i9xx_plane_check(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
- &crtc_state->uapi,
- DRM_PLANE_HELPER_NO_SCALING,
- DRM_PLANE_HELPER_NO_SCALING,
- i9xx_plane_has_windowing(plane),
- true);
+ ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,
+ DRM_PLANE_HELPER_NO_SCALING,
+ DRM_PLANE_HELPER_NO_SCALING,
+ i9xx_plane_has_windowing(plane));
if (ret)
return ret;
@@ -11611,11 +11609,10 @@ static int intel_check_cursor(struct intel_crtc_state *crtc_state,
return -EINVAL;
}
- ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
- &crtc_state->uapi,
- DRM_PLANE_HELPER_NO_SCALING,
- DRM_PLANE_HELPER_NO_SCALING,
- true, true);
+ ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,
+ DRM_PLANE_HELPER_NO_SCALING,
+ DRM_PLANE_HELPER_NO_SCALING,
+ true);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 2da11ab6343c..9e235210adc7 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2047,10 +2047,8 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state,
}
}
- ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
- &crtc_state->uapi,
- min_scale, max_scale,
- true, true);
+ ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,
+ min_scale, max_scale, true);
if (ret)
return ret;
@@ -2105,11 +2103,10 @@ vlv_sprite_check(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
- &crtc_state->uapi,
- DRM_PLANE_HELPER_NO_SCALING,
- DRM_PLANE_HELPER_NO_SCALING,
- true, true);
+ ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,
+ DRM_PLANE_HELPER_NO_SCALING,
+ DRM_PLANE_HELPER_NO_SCALING,
+ true);
if (ret)
return ret;
@@ -2316,10 +2313,8 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
max_scale = skl_plane_max_scale(dev_priv, fb);
}
- ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
- &crtc_state->uapi,
- min_scale, max_scale,
- true, true);
+ ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,
+ min_scale, max_scale, true);
if (ret)
return ret;
--
2.19.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Intel-gfx] [PATCH v10 10/11] drm/i915: Ensure correct master/slave enable/disable sequence
2020-10-08 21:45 [Intel-gfx] [PATCH v10 01/11] HAX to make DSC work on the icelake test system Manasi Navare
` (7 preceding siblings ...)
2020-10-08 21:45 ` [Intel-gfx] [PATCH v10 09/11] drm/i915: Add bigjoiner aware plane clipping checks Manasi Navare
@ 2020-10-08 21:45 ` Manasi Navare
2020-10-19 16:26 ` Ville Syrjälä
2020-10-08 21:45 ` [Intel-gfx] [PATCH v10 11/11] drm/i915: Add debugfs dumping for bigjoiner, v3 Manasi Navare
` (8 subsequent siblings)
17 siblings, 1 reply; 50+ messages in thread
From: Manasi Navare @ 2020-10-08 21:45 UTC (permalink / raw)
To: intel-gfx
From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Enabling is done in a special sequence and so should plane updates
be. Ideally the end user never notices the second pipe is used.
This way ideally everything will be tear free, and updates are
really atomic as userspace expects it.
This uses generic modeset_enables() calls like trans port sync
but still has special handling for disable since for slave we
should not disable things like encoder, plls that are not enabled
for slave.
v3:
* Fixes in enable and disable sequence from testing (Manasi)
v2:
* Manual Rebase (Manasi)
* Refactoring on intel_update_crtc and enable_crtc and removing
special trans_port_sync_update (Manasi)
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 55 ++++++++++++++------
drivers/gpu/drm/i915/display/intel_sprite.c | 5 +-
2 files changed, 43 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 357cc2bce300..101ddd0b48ab 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15878,6 +15878,9 @@ static void intel_enable_crtc(struct intel_atomic_state *state,
dev_priv->display.crtc_enable(state, crtc);
+ if (new_crtc_state->bigjoiner_slave)
+ return;
+
/* vblanks work again, re-enable pipe CRC. */
intel_crtc_enable_pipe_crc(crtc);
}
@@ -15914,9 +15917,7 @@ static void intel_update_crtc(struct intel_atomic_state *state,
commit_pipe_config(state, crtc);
- if (new_crtc_state->bigjoiner) {
- /* Not supported yet */
- } else if (INTEL_GEN(dev_priv) >= 9)
+ if (INTEL_GEN(dev_priv) >= 9)
skl_update_planes_on_crtc(state, crtc);
else
i9xx_update_planes_on_crtc(state, crtc);
@@ -15945,9 +15946,17 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
drm_WARN_ON(&dev_priv->drm, old_crtc_state->bigjoiner_slave);
intel_crtc_disable_planes(state, crtc);
- if (old_crtc_state->bigjoiner)
+
+ /*
+ * We still need special handling for disabling bigjoiner master
+ * and slaves since for slave we do not have encoder or plls
+ * so we dont need to disable those.
+ */
+ if (old_crtc_state->bigjoiner) {
intel_crtc_disable_planes(state,
old_crtc_state->bigjoiner_linked_crtc);
+ old_crtc_state->bigjoiner_linked_crtc->active = false;
+ }
/*
* We need to disable pipe CRC before disabling the pipe,
@@ -15977,7 +15986,7 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state)
/* Only disable port sync and MST slaves */
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
- if (!needs_modeset(new_crtc_state) || old_crtc_state->bigjoiner_slave)
+ if (!needs_modeset(new_crtc_state) || old_crtc_state->bigjoiner)
continue;
if (!old_crtc_state->hw.active)
@@ -16040,6 +16049,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
struct intel_crtc *crtc;
struct intel_crtc_state *old_crtc_state, *new_crtc_state;
struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
+ struct skl_ddb_entry new_entries[I915_MAX_PIPES] = {};
u8 update_pipes = 0, modeset_pipes = 0;
int i;
@@ -16056,6 +16066,14 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
} else {
modeset_pipes |= BIT(pipe);
}
+
+ new_entries[i] = new_crtc_state->wm.skl.ddb;
+
+ /* ignore allocations for crtc's that have been turned off during modeset. */
+ if (needs_modeset(new_crtc_state))
+ continue;
+
+ entries[i] = old_crtc_state->wm.skl.ddb;
}
/*
@@ -16071,28 +16089,28 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
enum pipe pipe = crtc->pipe;
+ bool ddb_changed;
if ((update_pipes & BIT(pipe)) == 0)
continue;
- if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
+ if (skl_ddb_allocation_overlaps(&new_entries[pipe],
entries, I915_MAX_PIPES, pipe))
continue;
- entries[pipe] = new_crtc_state->wm.skl.ddb;
+ ddb_changed = !skl_ddb_entry_equal(&new_entries[pipe], &entries[pipe]);
+ entries[pipe] = new_entries[pipe];
update_pipes &= ~BIT(pipe);
- intel_update_crtc(state, crtc);
-
/*
* If this is an already active pipe, it's DDB changed,
* and this isn't the last pipe that needs updating
* then we need to wait for a vblank to pass for the
* new ddb allocation to take effect.
*/
- if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
- &old_crtc_state->wm.skl.ddb) &&
- (update_pipes | modeset_pipes))
+ intel_update_crtc(state, crtc);
+
+ if (ddb_changed && (update_pipes | modeset_pipes))
intel_wait_for_vblank(dev_priv, pipe);
}
}
@@ -16110,7 +16128,8 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
continue;
if (intel_dp_mst_is_slave_trans(new_crtc_state) ||
- is_trans_port_sync_master(new_crtc_state))
+ is_trans_port_sync_master(new_crtc_state) ||
+ (new_crtc_state->bigjoiner && !new_crtc_state->bigjoiner_slave))
continue;
modeset_pipes &= ~BIT(pipe);
@@ -16120,7 +16139,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
/*
* Then we enable all remaining pipes that depend on other
- * pipes: MST slaves and port sync masters.
+ * pipes: MST slaves and port sync masters, big joiner master
*/
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
enum pipe pipe = crtc->pipe;
@@ -16128,6 +16147,10 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
if ((modeset_pipes & BIT(pipe)) == 0)
continue;
+ WARN_ON(skl_ddb_allocation_overlaps(&new_entries[pipe],
+ entries, I915_MAX_PIPES, pipe));
+
+ entries[pipe] = new_entries[pipe];
modeset_pipes &= ~BIT(pipe);
intel_enable_crtc(state, crtc);
@@ -16142,10 +16165,10 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
if ((update_pipes & BIT(pipe)) == 0)
continue;
- drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
+ drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_entries[pipe],
entries, I915_MAX_PIPES, pipe));
- entries[pipe] = new_crtc_state->wm.skl.ddb;
+ entries[pipe] = new_entries[pipe];
update_pipes &= ~BIT(pipe);
intel_update_crtc(state, crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 9e235210adc7..1c740a22a8d7 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -103,6 +103,8 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
/* FIXME needs to be calibrated sensibly */
min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
+ new_crtc_state->bigjoiner ?
+ 2 * VBLANK_EVASION_TIME_US :
VBLANK_EVASION_TIME_US);
max = vblank_start - 1;
@@ -227,7 +229,8 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
spin_lock(&crtc->base.dev->event_lock);
drm_crtc_arm_vblank_event(&crtc->base,
- new_crtc_state->uapi.event);
+ new_crtc_state->uapi.event);
+
spin_unlock(&crtc->base.dev->event_lock);
new_crtc_state->uapi.event = NULL;
--
2.19.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Intel-gfx] [PATCH v10 11/11] drm/i915: Add debugfs dumping for bigjoiner, v3.
2020-10-08 21:45 [Intel-gfx] [PATCH v10 01/11] HAX to make DSC work on the icelake test system Manasi Navare
` (8 preceding siblings ...)
2020-10-08 21:45 ` [Intel-gfx] [PATCH v10 10/11] drm/i915: Ensure correct master/slave enable/disable sequence Manasi Navare
@ 2020-10-08 21:45 ` Manasi Navare
2020-10-08 22:15 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v10,01/11] HAX to make DSC work on the icelake test system Patchwork
` (7 subsequent siblings)
17 siblings, 0 replies; 50+ messages in thread
From: Manasi Navare @ 2020-10-08 21:45 UTC (permalink / raw)
To: intel-gfx
From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Dump debugfs and planar links as well, this will make it easier to debug
when things go wrong.
v4:
* Rebase
Changes since v1:
- Report planar slaves as such, now that we have the plane_state switch.
Changes since v2:
- Rebase on top of the new plane format dumping
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
.../drm/i915/display/intel_display_debugfs.c | 29 ++++++++++++++++++-
1 file changed, 28 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 0bf31f9a8af5..2760e132582d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -750,6 +750,17 @@ static void plane_rotation(char *buf, size_t bufsize, unsigned int rotation)
rotation);
}
+static const char *plane_visibility(const struct intel_plane_state *plane_state)
+{
+ if (plane_state->uapi.visible)
+ return "visible";
+
+ if (plane_state->planar_slave)
+ return "planar-slave";
+
+ return "hidden";
+}
+
static void intel_plane_uapi_info(struct seq_file *m, struct intel_plane *plane)
{
const struct intel_plane_state *plane_state =
@@ -768,12 +779,22 @@ static void intel_plane_uapi_info(struct seq_file *m, struct intel_plane *plane)
plane_rotation(rot_str, sizeof(rot_str),
plane_state->uapi.rotation);
- seq_printf(m, "\t\tuapi: fb=%d,%s,%dx%d, src=" DRM_RECT_FP_FMT ", dst=" DRM_RECT_FMT ", rotation=%s\n",
+ seq_printf(m, "\t\tuapi: fb=%d,%s,%dx%d, visible=%s, src=" DRM_RECT_FP_FMT ", dst=" DRM_RECT_FMT ", rotation=%s\n",
fb ? fb->base.id : 0, fb ? format_name.str : "n/a",
fb ? fb->width : 0, fb ? fb->height : 0,
+ plane_visibility(plane_state),
DRM_RECT_FP_ARG(&src),
DRM_RECT_ARG(&dst),
rot_str);
+
+ if (plane_state->planar_linked_plane)
+ seq_printf(m, "\t\tplanar: Linked to [PLANE:%d:%s] as a %s\n",
+ plane_state->planar_linked_plane->base.base.id, plane_state->planar_linked_plane->base.name,
+ plane_state->planar_slave ? "slave" : "master");
+ if (plane_state->bigjoiner_plane)
+ seq_printf(m, "\t\tbigjoiner: Linked to [PLANE:%d:%s] as a %s\n",
+ plane_state->bigjoiner_plane->base.base.id, plane_state->bigjoiner_plane->base.name,
+ plane_state->bigjoiner_slave ? "slave" : "master");
}
static void intel_plane_hw_info(struct seq_file *m, struct intel_plane *plane)
@@ -869,6 +890,12 @@ static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc)
intel_scaler_info(m, crtc);
}
+ if (crtc_state->bigjoiner)
+ seq_printf(m, "\tLinked to [CRTC:%d:%s] as a %s\n",
+ crtc_state->bigjoiner_linked_crtc->base.base.id,
+ crtc_state->bigjoiner_linked_crtc->base.name,
+ crtc_state->bigjoiner_slave ? "slave" : "master");
+
for_each_intel_encoder_mask(&dev_priv->drm, encoder,
crtc_state->uapi.encoder_mask)
intel_encoder_info(m, crtc, encoder);
--
2.19.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v10,01/11] HAX to make DSC work on the icelake test system
2020-10-08 21:45 [Intel-gfx] [PATCH v10 01/11] HAX to make DSC work on the icelake test system Manasi Navare
` (9 preceding siblings ...)
2020-10-08 21:45 ` [Intel-gfx] [PATCH v10 11/11] drm/i915: Add debugfs dumping for bigjoiner, v3 Manasi Navare
@ 2020-10-08 22:15 ` Patchwork
2020-10-08 22:17 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (6 subsequent siblings)
17 siblings, 0 replies; 50+ messages in thread
From: Patchwork @ 2020-10-08 22:15 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v10,01/11] HAX to make DSC work on the icelake test system
URL : https://patchwork.freedesktop.org/series/82483/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
999aa92a11f0 HAX to make DSC work on the icelake test system
870138d57034 drm/i915/display: Rename pipe_timings to transcoder_timings
-:11: WARNING:TYPO_SPELLING: 'halfs' may be misspelled - perhaps 'halves'?
#11:
With Bigjoiner, there are 2 pipes driving 2 halfs of 1
total: 0 errors, 1 warnings, 0 checks, 82 lines checked
d7eab67d7a38 drm/i915: Add hw.pipe_mode to allow bigjoiner pipe/transcoder split
-:7: WARNING:TYPO_SPELLING: 'halfs' may be misspelled - perhaps 'halves'?
#7:
With bigjoiner, there will be 2 pipes driving 2 halfs of 1 transcoder,
-:134: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#134: FILE: drivers/gpu/drm/i915/display/intel_display.c:13355:
+ crtc_state->hw.pipe_mode = crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
total: 0 errors, 1 warnings, 1 checks, 364 lines checked
03231e226425 drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.
0f128ffd6e7b drm/i915: Try to make bigjoiner work in atomic check
-:145: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#145: FILE: drivers/gpu/drm/i915/display/intel_display.c:13367:
+ crtc_state->bigjoiner_linked_crtc);
-:205: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#205: FILE: drivers/gpu/drm/i915/display/intel_display.c:13438:
+ crtc_state->nv12_planes = crtc_state->c8_planes = crtc_state->update_planes = 0;
-:300: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#300: FILE: drivers/gpu/drm/i915/display/intel_display.c:15045:
+ slave = new_crtc_state->bigjoiner_linked_crtc =
-:334: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#334: FILE: drivers/gpu/drm/i915/display/intel_display.c:15079:
+ slave_crtc_state->bigjoiner = master_crtc_state->bigjoiner = false;
-:335: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#335: FILE: drivers/gpu/drm/i915/display/intel_display.c:15080:
+ slave_crtc_state->bigjoiner_slave = master_crtc_state->bigjoiner_slave = false;
-:336: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#336: FILE: drivers/gpu/drm/i915/display/intel_display.c:15081:
+ slave_crtc_state->bigjoiner_linked_crtc = master_crtc_state->bigjoiner_linked_crtc = NULL;
-:336: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#336: FILE: drivers/gpu/drm/i915/display/intel_display.c:15081:
+ slave_crtc_state->bigjoiner_linked_crtc = master_crtc_state->bigjoiner_linked_crtc = NULL;
-:391: WARNING:BRACES: braces {} are not necessary for any arm of this statement
#391: FILE: drivers/gpu/drm/i915/display/intel_display.c:15615:
+ if (new_crtc_state->bigjoiner) {
[...]
+ } else if (INTEL_GEN(dev_priv) >= 9)
[...]
else
[...]
total: 0 errors, 3 warnings, 5 checks, 403 lines checked
8b2c9eaf5fbf drm/i915: Enable big joiner support in enable and disable sequences.
-:186: WARNING:LONG_LINE_COMMENT: line length of 106 exceeds 100 columns
#186: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:4534:
+ /* Our own transcoder needs to be disabled when reading it in intel_ddi_read_func_ctl() */
-:188: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#188: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:4536:
+ pipe_config->cpu_transcoder = (enum transcoder)pipe_config->bigjoiner_linked_crtc->pipe;
-:839: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#839: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:841:
+#define PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE (1<<1) /* bigjoiner slave, partial readout */
^
total: 0 errors, 2 warnings, 1 checks, 1033 lines checked
9bf5d4cad324 drm/i915: Make hardware readout work on i915.
-:33: WARNING:TABSTOP: Statements should start on a tabstop
#33: FILE: drivers/gpu/drm/i915/display/intel_display.c:3622:
+ struct intel_crtc_state *crtc_state =
-:76: WARNING:LONG_LINE: line length of 111 exceeds 100 columns
#76: FILE: drivers/gpu/drm/i915/display/intel_display.c:10811:
+ (intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & 0xfffff000) == plane_config->base) {
total: 0 errors, 2 warnings, 0 checks, 118 lines checked
6f55653a6e1f drm/i915: Link planes in a bigjoiner configuration, v3.
-:206: ERROR:CODE_INDENT: code indent should use tabs where possible
#206: FILE: drivers/gpu/drm/i915/display/intel_display.c:12752:
+ * Setup and teardown the new bigjoiner plane mappings.$
-:207: ERROR:CODE_INDENT: code indent should use tabs where possible
#207: FILE: drivers/gpu/drm/i915/display/intel_display.c:12753:
+ */$
-:292: ERROR:CODE_INDENT: code indent should use tabs where possible
#292: FILE: drivers/gpu/drm/i915/display/intel_display.c:12834:
+ *$
-:308: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#308: FILE: drivers/gpu/drm/i915/display/intel_display.c:12848:
+ for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
-:324: ERROR:CODE_INDENT: code indent should use tabs where possible
#324: FILE: drivers/gpu/drm/i915/display/intel_display.c:12864:
+ * Make sure bigjoiner slave crtc's are also pulled in. This is not done automatically$
-:325: ERROR:CODE_INDENT: code indent should use tabs where possible
#325: FILE: drivers/gpu/drm/i915/display/intel_display.c:12865:
+ * when adding slave planes, because plane_state->crtc is null.$
-:326: ERROR:CODE_INDENT: code indent should use tabs where possible
#326: FILE: drivers/gpu/drm/i915/display/intel_display.c:12866:
+ */$
-:438: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional statements (8, 8)
#438: FILE: drivers/gpu/drm/i915/display/intel_display.h:472:
+ for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (iter), \
[...]
+ for_each_if ((((plane_state) = \
-:444: WARNING:SPACING: space prohibited between function name and open parenthesis '('
#444: FILE: drivers/gpu/drm/i915/display/intel_display.h:478:
+ for_each_if ((((plane_state) = \
-:445: WARNING:LONG_LINE: line length of 124 exceeds 100 columns
#445: FILE: drivers/gpu/drm/i915/display/intel_display.h:479:
+ to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &iter->base))), \
-:446: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#446: FILE: drivers/gpu/drm/i915/display/intel_display.h:480:
+ ((plane) = (plane_state)->bigjoiner_slave ? (plane_state)->bigjoiner_plane : (iter)), \
-:448: WARNING:LONG_LINE: line length of 125 exceeds 100 columns
#448: FILE: drivers/gpu/drm/i915/display/intel_display.h:482:
+ to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base)) : \
total: 6 errors, 6 warnings, 0 checks, 482 lines checked
aea49fc97daa drm/i915: Add bigjoiner aware plane clipping checks
225f41e9605a drm/i915: Ensure correct master/slave enable/disable sequence
5595d86a59e6 drm/i915: Add debugfs dumping for bigjoiner, v3.
-:46: WARNING:LONG_LINE: line length of 123 exceeds 100 columns
#46: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs.c:782:
+ seq_printf(m, "\t\tuapi: fb=%d,%s,%dx%d, visible=%s, src=" DRM_RECT_FP_FMT ", dst=" DRM_RECT_FMT ", rotation=%s\n",
-:56: WARNING:LONG_LINE: line length of 119 exceeds 100 columns
#56: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs.c:792:
+ plane_state->planar_linked_plane->base.base.id, plane_state->planar_linked_plane->base.name,
-:60: WARNING:LONG_LINE: line length of 111 exceeds 100 columns
#60: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs.c:796:
+ plane_state->bigjoiner_plane->base.base.id, plane_state->bigjoiner_plane->base.name,
total: 0 errors, 3 warnings, 0 checks, 52 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v10,01/11] HAX to make DSC work on the icelake test system
2020-10-08 21:45 [Intel-gfx] [PATCH v10 01/11] HAX to make DSC work on the icelake test system Manasi Navare
` (10 preceding siblings ...)
2020-10-08 22:15 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v10,01/11] HAX to make DSC work on the icelake test system Patchwork
@ 2020-10-08 22:17 ` Patchwork
2020-10-08 22:33 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (5 subsequent siblings)
17 siblings, 0 replies; 50+ messages in thread
From: Patchwork @ 2020-10-08 22:17 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v10,01/11] HAX to make DSC work on the icelake test system
URL : https://patchwork.freedesktop.org/series/82483/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1019:47: expected unsigned int [addressable] [usertype] ulClockParams
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1019:47: got restricted __le32 [usertype]
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1019:47: warning: incorrect type in assignment (different base types)
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1028:50: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1029:49: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1037:47: warning: too many warnings
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:184:44: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:283:14: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:320:14: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:323:14: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:326:14: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:329:18: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:330:26: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:338:30: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:340:38: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:342:30: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:346:30: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:348:30: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:353:33: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:367:43: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:369:38: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:374:67: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:375:53: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:378:66: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:389:80: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:395:57: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:402:69: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:403:53: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:406:66: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:414:66: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:423:69: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:424:69: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:473:30: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:476:45: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:477:45: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:484:54: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:52:28: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:531:35: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:53:29: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:533:25: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:54:26: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:55:27: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:56:25: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:57:26: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:577:21: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:581:25: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:58:25: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:583:21: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:586:25: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:590:25: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:59:26: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:598:21: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:600:21: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:617:25: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:621:21: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:623:21: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:630:21: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:632:21: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:644:25: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:648:21: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:650:21: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:657:21: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:659:21: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:662:21: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:664:21: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:676:25: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:688:25: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:691:47: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:697:25: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:796:46: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:797:40: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:800:46: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:801:40: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:804:46: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:805:40: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:812:46: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:813:40: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:816:46: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:817:40: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:820:46: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:821:40: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:828:46: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:829:40: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:832:46: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:833:40: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:836:46: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:837:40: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:844:46: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:845:40: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:848:46: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:849:40: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:852:46: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:853:40: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:916:47: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:918:49: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:920:52: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:934:47: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:936:49: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:938:52: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:956:47: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:958:49: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:960:52: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:328:34: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:365:34: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:395:25: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:397:25: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:404:25: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:418:40: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:441:40: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:44:21: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:482:53: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:486:33: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:489:61: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:490:64: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:492:54: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:518:17: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:521:21: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:64:25: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:80:17: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:80:17: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:80:17: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:85:30: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:86:24: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:98:39: warning: cast to restricted __le16
+drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:222:29: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:226:37: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:226:37: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:226:37: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:227:37: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:233:43: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:236:44: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:239:51: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:458:41: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:458:41: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:458:41: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:464:39: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:465:30: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:466:39: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:468:24: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:140:26: expected unsigned long long [usertype] *chunk_array_user
+drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:140:26: got void [noderef] __user *
+drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:140:26: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:141:41: expected void const [noderef] __user *from
+drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:141:41: got unsigned long long [usertype] *chunk_array_user
+drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:141:41: warning: incorrect type in argument 2 (different address spaces)
+drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:160:27: expected struct drm_amdgpu_cs_chunk [noderef] __user **chunk_ptr
+drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:160:27: got void [noderef] __user *
+drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:160:27: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:161:49: expected void const [noderef] __user *from
+drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:161:49: got struct drm_amdgpu_cs_chunk [noderef] __user **chunk_ptr
+drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:161:49: warning: incorrect type in argument 2 (different address spaces)
+drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1624:21: expected struct drm_amdgpu_fence *fences_user
+drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1624:21: got void [noderef] __user *
+drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1624:21: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1625:36: expected void const [noderef] __user *from
+drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1625:36: got struct drm_amdgpu_fence *fences_user
+drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1625:36: warning: incorrect type in argument 2 (different address spaces)
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1367:25: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1367:25: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1367:25: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1368:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1368:17: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1368:17: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1427:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1427:17: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1427:17: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:143:17: expected restricted __poll_t ( *poll )( ... )
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:143:17: got unsigned int ( * )( ... )
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:143:17: warning: incorrect type in initializer (different base types)
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:266:29: expected void const volatile [noderef] __user *ptr
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:266:29: got unsigned int [usertype] *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:266:29: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:266:29: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:266:29: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:266:29: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:266:29: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:266:29: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:266:29: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:266:29: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:266:29: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:266:29: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:266:29: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:266:29: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:266:29: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:266:29: warning: incorrect type in argument 1 (different address spaces)
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:268:29: expected void const volatile [noderef] __user *ptr
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:268:29: got unsigned int [usertype] *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:268:29: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:268:29: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:268:29: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:268:29: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:268:29: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:268:29: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:268:29: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:268:29: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:268:29: warning: incorrect type in argument 1 (different address spaces)
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:359:21: expected void const volatile [noderef] __user *ptr
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:359:21: got unsigned int [usertype] *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:359:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:359:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:359:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:359:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:359:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:359:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:359:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:359:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:359:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:359:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:359:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:359:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:359:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:359:21: warning: incorrect type in argument 1 (different address spaces)
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:417:21: expected void const volatile [noderef] __user *ptr
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:417:21: got unsigned int [usertype] *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:417:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:417:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:417:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:417:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:417:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:417:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:417:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:417:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:417:21: warning: incorrect type in argument 1 (different address spaces)
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:478:21: expected void const volatile [noderef] __user *ptr
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:478:21: got unsigned int [usertype] *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:478:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:478:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:478:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:478:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:478:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:478:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:478:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:478:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:478:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:478:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:478:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:478:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:478:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:478:21: warning: incorrect type in argument 1 (different address spaces)
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:536:21: expected void const volatile [noderef] __user *ptr
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:536:21: got unsigned int [usertype] *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:536:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:536:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:536:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:536:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:536:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:536:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:536:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:536:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:536:21: warning: incorrect type in argument 1 (different address spaces)
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:597:21: expected void const volatile [noderef] __user *ptr
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:597:21: got unsigned int [usertype] *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:597:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:597:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:597:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:597:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:597:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:597:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:597:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:597:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:597:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:597:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:597:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:597:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:597:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:597:21: warning: incorrect type in argument 1 (different address spaces)
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:655:21: expected void const volatile [noderef] __user *ptr
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:655:21: got unsigned int [usertype] *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:655:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:655:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:655:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:655:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:655:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:655:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:655:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:655:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:655:21: warning: incorrect type in argument 1 (different address spaces)
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:752:21: expected void const volatile [noderef] __user *ptr
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:752:21: got unsigned int [usertype] *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:752:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:752:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:752:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:752:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:752:21: warning: cast removes address space '__user' of expression
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:752:21: warning: incorrect type in argument 1 (different address spaces)
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:752:21: warning: too many warnings
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1729:65: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1737:55: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1738:50: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1739:50: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1740:56: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1742:25: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1743:45: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1744:51: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1745:55: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1746:57: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1748:25: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1749:53: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1751:25: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1753:25: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1754:46: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1758:73: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1760:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1762:33: warning: cast to restricted _
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v10,01/11] HAX to make DSC work on the icelake test system
2020-10-08 21:45 [Intel-gfx] [PATCH v10 01/11] HAX to make DSC work on the icelake test system Manasi Navare
` (11 preceding siblings ...)
2020-10-08 22:17 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2020-10-08 22:33 ` Patchwork
2020-10-09 1:32 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
` (4 subsequent siblings)
17 siblings, 0 replies; 50+ messages in thread
From: Patchwork @ 2020-10-08 22:33 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 7341 bytes --]
== Series Details ==
Series: series starting with [v10,01/11] HAX to make DSC work on the icelake test system
URL : https://patchwork.freedesktop.org/series/82483/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9113 -> Patchwork_18662
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/index.html
Known issues
------------
Here are the changes found in Patchwork_18662 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_rpm@module-reload:
- fi-bsw-n3050: [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/fi-bsw-n3050/igt@i915_pm_rpm@module-reload.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/fi-bsw-n3050/igt@i915_pm_rpm@module-reload.html
- fi-bxt-dsi: [PASS][3] -> [DMESG-WARN][4] ([i915#1635] / [i915#1982])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/fi-bxt-dsi/igt@i915_pm_rpm@module-reload.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/fi-bxt-dsi/igt@i915_pm_rpm@module-reload.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
#### Possible fixes ####
* {igt@core_hotunplug@unbind-rebind}:
- fi-icl-y: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/fi-icl-y/igt@core_hotunplug@unbind-rebind.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/fi-icl-y/igt@core_hotunplug@unbind-rebind.html
* igt@gem_exec_suspend@basic-s3:
- fi-skl-lmem: [INCOMPLETE][9] ([i915#198]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/fi-skl-lmem/igt@gem_exec_suspend@basic-s3.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/fi-skl-lmem/igt@gem_exec_suspend@basic-s3.html
* igt@kms_busy@basic@flip:
- fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/fi-kbl-x1275/igt@kms_busy@basic@flip.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/fi-kbl-x1275/igt@kms_busy@basic@flip.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-bsw-n3050: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@vgem_basic@unload:
- fi-skl-guc: [DMESG-WARN][15] ([i915#2203]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/fi-skl-guc/igt@vgem_basic@unload.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/fi-skl-guc/igt@vgem_basic@unload.html
#### Warnings ####
* igt@gem_exec_suspend@basic-s0:
- fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92]) -> [DMESG-WARN][18] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html
* igt@i915_pm_rpm@module-reload:
- fi-kbl-x1275: [DMESG-FAIL][19] ([i915#62]) -> [SKIP][20] ([fdo#109271])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html
* igt@kms_force_connector_basic@prune-stale-modes:
- fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][22] ([i915#62] / [i915#92]) +6 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/fi-kbl-x1275/igt@kms_force_connector_basic@prune-stale-modes.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/fi-kbl-x1275/igt@kms_force_connector_basic@prune-stale-modes.html
* igt@vgem_basic@unload:
- fi-kbl-x1275: [DMESG-WARN][23] ([i915#62] / [i915#92]) -> [DMESG-WARN][24] ([i915#95])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/fi-kbl-x1275/igt@vgem_basic@unload.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/fi-kbl-x1275/igt@vgem_basic@unload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (45 -> 39)
------------------------------
Additional (1): fi-cfl-8109u
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_9113 -> Patchwork_18662
CI-20190529: 20190529
CI_DRM_9113: 412ff15f2b9a97bd0ab32f562ecb7efc84837881 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5805: 9ce50ffed89a46fa1bc98ee2cfe2271c49801079 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18662: 5595d86a59e6cf2f942094def63adcf70d5334ba @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
5595d86a59e6 drm/i915: Add debugfs dumping for bigjoiner, v3.
225f41e9605a drm/i915: Ensure correct master/slave enable/disable sequence
aea49fc97daa drm/i915: Add bigjoiner aware plane clipping checks
6f55653a6e1f drm/i915: Link planes in a bigjoiner configuration, v3.
9bf5d4cad324 drm/i915: Make hardware readout work on i915.
8b2c9eaf5fbf drm/i915: Enable big joiner support in enable and disable sequences.
0f128ffd6e7b drm/i915: Try to make bigjoiner work in atomic check
03231e226425 drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.
d7eab67d7a38 drm/i915: Add hw.pipe_mode to allow bigjoiner pipe/transcoder split
870138d57034 drm/i915/display: Rename pipe_timings to transcoder_timings
999aa92a11f0 HAX to make DSC work on the icelake test system
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/index.html
[-- Attachment #1.2: Type: text/html, Size: 9271 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v10,01/11] HAX to make DSC work on the icelake test system
2020-10-08 21:45 [Intel-gfx] [PATCH v10 01/11] HAX to make DSC work on the icelake test system Manasi Navare
` (12 preceding siblings ...)
2020-10-08 22:33 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-10-09 1:32 ` Patchwork
2020-10-13 19:19 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v10,01/11] HAX to make DSC work on the icelake test system (rev2) Patchwork
` (3 subsequent siblings)
17 siblings, 0 replies; 50+ messages in thread
From: Patchwork @ 2020-10-09 1:32 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 15743 bytes --]
== Series Details ==
Series: series starting with [v10,01/11] HAX to make DSC work on the icelake test system
URL : https://patchwork.freedesktop.org/series/82483/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9113_full -> Patchwork_18662_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_18662_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][1] -> [SKIP][2] ([i915#2190])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-tglb7/igt@gem_huc_copy@huc-copy.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/shard-tglb6/igt@gem_huc_copy@huc-copy.html
* igt@gem_tiled_pread_pwrite:
- shard-iclb: [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-iclb8/igt@gem_tiled_pread_pwrite.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/shard-iclb2/igt@gem_tiled_pread_pwrite.html
* igt@gen9_exec_parse@allowed-all:
- shard-skl: [PASS][5] -> [DMESG-WARN][6] ([i915#1436] / [i915#716])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-skl5/igt@gen9_exec_parse@allowed-all.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/shard-skl2/igt@gen9_exec_parse@allowed-all.html
* igt@i915_pm_dc@dc6-psr:
- shard-skl: [PASS][7] -> [FAIL][8] ([i915#454])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-skl7/igt@i915_pm_dc@dc6-psr.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/shard-skl10/igt@i915_pm_dc@dc6-psr.html
* igt@kms_cursor_edge_walk@pipe-b-128x128-bottom-edge:
- shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-kbl1/igt@kms_cursor_edge_walk@pipe-b-128x128-bottom-edge.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/shard-kbl6/igt@kms_cursor_edge_walk@pipe-b-128x128-bottom-edge.html
* igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic:
- shard-glk: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) +2 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html
* igt@kms_cursor_legacy@pipe-c-torture-bo:
- shard-tglb: [PASS][13] -> [DMESG-WARN][14] ([i915#128])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-tglb8/igt@kms_cursor_legacy@pipe-c-torture-bo.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/shard-tglb8/igt@kms_cursor_legacy@pipe-c-torture-bo.html
* igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1:
- shard-skl: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) +3 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-skl7/igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/shard-skl4/igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1.html
* igt@kms_flip@flip-vs-expired-vblank@b-edp1:
- shard-skl: [PASS][17] -> [FAIL][18] ([i915#79])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-skl3/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/shard-skl5/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
* igt@kms_flip@flip-vs-suspend@a-dp1:
- shard-kbl: [PASS][19] -> [INCOMPLETE][20] ([i915#155])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-kbl7/igt@kms_flip@flip-vs-suspend@a-dp1.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/shard-kbl1/igt@kms_flip@flip-vs-suspend@a-dp1.html
* igt@kms_flip@flip-vs-suspend@b-edp1:
- shard-skl: [PASS][21] -> [INCOMPLETE][22] ([i915#198])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-skl1/igt@kms_flip@flip-vs-suspend@b-edp1.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/shard-skl7/igt@kms_flip@flip-vs-suspend@b-edp1.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-wc:
- shard-tglb: [PASS][23] -> [DMESG-WARN][24] ([i915#1982]) +2 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-wc.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-wc.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [PASS][25] -> [FAIL][26] ([i915#1188]) +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-skl3/igt@kms_hdr@bpc-switch-suspend.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/shard-skl5/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][27] -> [FAIL][28] ([fdo#108145] / [i915#265]) +2 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_cursor_plane_move:
- shard-iclb: [PASS][29] -> [SKIP][30] ([fdo#109441]) +2 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/shard-iclb4/igt@kms_psr@psr2_cursor_plane_move.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][31] -> [FAIL][32] ([i915#1635] / [i915#31])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-apl6/igt@kms_setmode@basic.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/shard-apl1/igt@kms_setmode@basic.html
- shard-glk: [PASS][33] -> [FAIL][34] ([i915#31])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-glk4/igt@kms_setmode@basic.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/shard-glk2/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: [PASS][35] -> [DMESG-WARN][36] ([i915#180]) +2 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-kbl2/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/shard-kbl4/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
#### Possible fixes ####
* {igt@gem_exec_capture@pi@rcs0}:
- shard-skl: [INCOMPLETE][37] -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-skl2/igt@gem_exec_capture@pi@rcs0.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/shard-skl8/igt@gem_exec_capture@pi@rcs0.html
* igt@i915_pm_rpm@system-suspend:
- shard-skl: [INCOMPLETE][39] ([i915#151]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-skl1/igt@i915_pm_rpm@system-suspend.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/shard-skl9/igt@i915_pm_rpm@system-suspend.html
* igt@i915_selftest@live@gt_heartbeat:
- shard-skl: [DMESG-FAIL][41] ([i915#541]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-skl3/igt@i915_selftest@live@gt_heartbeat.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/shard-skl4/igt@i915_selftest@live@gt_heartbeat.html
* {igt@kms_async_flips@alternate-sync-async-flip}:
- shard-kbl: [FAIL][43] ([i915#2521]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-kbl2/igt@kms_async_flips@alternate-sync-async-flip.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/shard-kbl4/igt@kms_async_flips@alternate-sync-async-flip.html
* {igt@kms_async_flips@async-flip-with-page-flip-events}:
- shard-glk: [FAIL][45] ([i915#2521]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-glk3/igt@kms_async_flips@async-flip-with-page-flip-events.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/shard-glk4/igt@kms_async_flips@async-flip-with-page-flip-events.html
* igt@kms_cursor_edge_walk@pipe-b-128x128-bottom-edge:
- shard-glk: [DMESG-WARN][47] ([i915#1982]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-glk1/igt@kms_cursor_edge_walk@pipe-b-128x128-bottom-edge.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/shard-glk3/igt@kms_cursor_edge_walk@pipe-b-128x128-bottom-edge.html
* igt@kms_frontbuffer_tracking@fbc-farfromfence:
- shard-glk: [FAIL][49] ([i915#49]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-glk8/igt@kms_frontbuffer_tracking@fbc-farfromfence.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/shard-glk9/igt@kms_frontbuffer_tracking@fbc-farfromfence.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite:
- shard-tglb: [DMESG-WARN][51] ([i915#1982]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite.html
* igt@kms_plane@plane-position-covered-pipe-b-planes:
- shard-skl: [DMESG-WARN][53] ([i915#1982]) -> [PASS][54] +4 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-skl8/igt@kms_plane@plane-position-covered-pipe-b-planes.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/shard-skl5/igt@kms_plane@plane-position-covered-pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [FAIL][55] ([fdo#108145] / [i915#265]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-iclb: [SKIP][57] ([fdo#109441]) -> [PASS][58] +1 similar issue
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-iclb3/igt@kms_psr@psr2_sprite_mmap_gtt.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
* igt@kms_setmode@basic:
- shard-skl: [FAIL][59] ([i915#31]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-skl5/igt@kms_setmode@basic.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/shard-skl2/igt@kms_setmode@basic.html
* igt@prime_vgem@sync@rcs0:
- shard-iclb: [INCOMPLETE][61] ([i915#409]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-iclb3/igt@prime_vgem@sync@rcs0.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/shard-iclb2/igt@prime_vgem@sync@rcs0.html
#### Warnings ####
* igt@i915_pm_dc@dc5-psr:
- shard-tglb: [DMESG-WARN][63] ([i915#2411]) -> [FAIL][64] ([i915#1899])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-tglb6/igt@i915_pm_dc@dc5-psr.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/shard-tglb1/igt@i915_pm_dc@dc5-psr.html
* igt@kms_content_protection@legacy:
- shard-apl: [FAIL][65] ([fdo#110321] / [fdo#110336] / [i915#1635]) -> [TIMEOUT][66] ([i915#1319] / [i915#1635])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-apl4/igt@kms_content_protection@legacy.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/shard-apl3/igt@kms_content_protection@legacy.html
* igt@kms_content_protection@lic:
- shard-apl: [TIMEOUT][67] ([i915#1319] / [i915#1635]) -> [FAIL][68] ([fdo#110321] / [i915#1635])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-apl1/igt@kms_content_protection@lic.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/shard-apl3/igt@kms_content_protection@lic.html
* igt@runner@aborted:
- shard-skl: [FAIL][69] ([i915#2439]) -> [FAIL][70] ([i915#1436])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-skl2/igt@runner@aborted.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/shard-skl2/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321
[fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151
[i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1899]: https://gitlab.freedesktop.org/drm/intel/issues/1899
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2439]: https://gitlab.freedesktop.org/drm/intel/issues/2439
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#409]: https://gitlab.freedesktop.org/drm/intel/issues/409
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_9113 -> Patchwork_18662
CI-20190529: 20190529
CI_DRM_9113: 412ff15f2b9a97bd0ab32f562ecb7efc84837881 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5805: 9ce50ffed89a46fa1bc98ee2cfe2271c49801079 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18662: 5595d86a59e6cf2f942094def63adcf70d5334ba @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18662/index.html
[-- Attachment #1.2: Type: text/html, Size: 18539 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v10 05/11] drm/i915: Try to make bigjoiner work in atomic check
2020-10-08 21:45 ` [Intel-gfx] [PATCH v10 05/11] drm/i915: Try to make bigjoiner work in atomic check Manasi Navare
@ 2020-10-11 11:18 ` kernel test robot
2020-10-14 11:33 ` Ville Syrjälä
1 sibling, 0 replies; 50+ messages in thread
From: kernel test robot @ 2020-10-11 11:18 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 2334 bytes --]
Hi Manasi,
I love your patch! Perhaps something to improve:
[auto build test WARNING on drm-tip/drm-tip]
[also build test WARNING on next-20201009]
[cannot apply to drm-intel/for-linux-next linus/master v5.9-rc8]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Manasi-Navare/HAX-to-make-DSC-work-on-the-icelake-test-system/20201009-054559
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: i386-randconfig-m031-20201011 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
New smatch warnings:
drivers/gpu/drm/i915/display/intel_display.c:15076 kill_bigjoiner_slave() warn: inconsistent indenting
Old smatch warnings:
drivers/gpu/drm/i915/gem/i915_gem_object.h:127 __i915_gem_object_lock() error: we previously assumed 'ww' could be null (see line 119)
drivers/gpu/drm/i915/display/intel_display.c:6236 skl_update_scaler_plane() error: we previously assumed 'fb' could be null (see line 6220)
drivers/gpu/drm/i915/display/intel_display.c:17053 intel_crtc_init() warn: passing a valid pointer to 'PTR_ERR'
vim +15076 drivers/gpu/drm/i915/display/intel_display.c
15068
15069 static int kill_bigjoiner_slave(struct intel_atomic_state *state,
15070 struct intel_crtc_state *master_crtc_state)
15071 {
15072 struct intel_crtc_state *slave_crtc_state =
15073 intel_atomic_get_crtc_state(&state->base,
15074 master_crtc_state->bigjoiner_linked_crtc);
15075
15076 if (IS_ERR(slave_crtc_state))
15077 return PTR_ERR(slave_crtc_state);
15078
15079 slave_crtc_state->bigjoiner = master_crtc_state->bigjoiner = false;
15080 slave_crtc_state->bigjoiner_slave = master_crtc_state->bigjoiner_slave = false;
15081 slave_crtc_state->bigjoiner_linked_crtc = master_crtc_state->bigjoiner_linked_crtc = NULL;
15082 intel_crtc_copy_uapi_to_hw_state(state, slave_crtc_state);
15083 return 0;
15084 }
15085
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 42528 bytes --]
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v10 07/11] drm/i915: Make hardware readout work on i915.
2020-10-08 21:45 ` [Intel-gfx] [PATCH v10 07/11] drm/i915: Make hardware readout work on i915 Manasi Navare
@ 2020-10-11 20:18 ` kernel test robot
2020-10-19 16:36 ` Ville Syrjälä
1 sibling, 0 replies; 50+ messages in thread
From: kernel test robot @ 2020-10-11 20:18 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 5543 bytes --]
Hi Manasi,
I love your patch! Perhaps something to improve:
[auto build test WARNING on drm-tip/drm-tip]
[cannot apply to drm-intel/for-linux-next linus/master v5.9-rc8 next-20201009]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Manasi-Navare/HAX-to-make-DSC-work-on-the-icelake-test-system/20201009-054559
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: i386-randconfig-m031-20201011 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
New smatch warnings:
drivers/gpu/drm/i915/display/intel_display.c:3622 intel_find_initial_plane_obj() warn: inconsistent indenting
Old smatch warnings:
drivers/gpu/drm/i915/gem/i915_gem_object.h:127 __i915_gem_object_lock() error: we previously assumed 'ww' could be null (see line 119)
drivers/gpu/drm/i915/display/intel_display.c:6243 skl_update_scaler_plane() error: we previously assumed 'fb' could be null (see line 6227)
drivers/gpu/drm/i915/display/intel_display.c:15208 kill_bigjoiner_slave() warn: inconsistent indenting
drivers/gpu/drm/i915/display/intel_display.c:17197 intel_crtc_init() warn: passing a valid pointer to 'PTR_ERR'
vim +3622 drivers/gpu/drm/i915/display/intel_display.c
3609
3610 static void
3611 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
3612 struct intel_initial_plane_config *plane_config)
3613 {
3614 struct drm_device *dev = intel_crtc->base.dev;
3615 struct drm_i915_private *dev_priv = to_i915(dev);
3616 struct drm_crtc *c;
3617 struct drm_plane *primary = intel_crtc->base.primary;
3618 struct drm_plane_state *plane_state = primary->state;
3619 struct intel_plane *intel_plane = to_intel_plane(primary);
3620 struct intel_plane_state *intel_state =
3621 to_intel_plane_state(plane_state);
> 3622 struct intel_crtc_state *crtc_state =
3623 to_intel_crtc_state(intel_crtc->base.state);
3624 struct drm_framebuffer *fb;
3625 struct i915_vma *vma;
3626
3627 if (!plane_config->fb)
3628 return;
3629
3630 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
3631 fb = &plane_config->fb->base;
3632 vma = plane_config->vma;
3633 goto valid_fb;
3634 }
3635
3636 /*
3637 * Failed to alloc the obj, check to see if we should share
3638 * an fb with another CRTC instead
3639 */
3640 for_each_crtc(dev, c) {
3641 struct intel_plane_state *state;
3642
3643 if (c == &intel_crtc->base)
3644 continue;
3645
3646 if (!to_intel_crtc_state(c->state)->uapi.active)
3647 continue;
3648
3649 state = to_intel_plane_state(c->primary->state);
3650 if (!state->vma)
3651 continue;
3652
3653 if (intel_plane_ggtt_offset(state) == plane_config->base) {
3654 fb = state->hw.fb;
3655 vma = state->vma;
3656 goto valid_fb;
3657 }
3658 }
3659
3660 /*
3661 * We've failed to reconstruct the BIOS FB. Current display state
3662 * indicates that the primary plane is visible, but has a NULL FB,
3663 * which will lead to problems later if we don't fix it up. The
3664 * simplest solution is to just disable the primary plane now and
3665 * pretend the BIOS never had it enabled.
3666 */
3667 intel_plane_disable_noatomic(intel_crtc, intel_plane);
3668 if (crtc_state->bigjoiner) {
3669 struct intel_crtc *slave =
3670 crtc_state->bigjoiner_linked_crtc;
3671 intel_plane_disable_noatomic(slave, to_intel_plane(slave->base.primary));
3672 }
3673
3674 return;
3675
3676 valid_fb:
3677 intel_state->hw.rotation = plane_config->rotation;
3678 intel_fill_fb_ggtt_view(&intel_state->view, fb,
3679 intel_state->hw.rotation);
3680 intel_state->color_plane[0].stride =
3681 intel_fb_pitch(fb, 0, intel_state->hw.rotation);
3682
3683 __i915_vma_pin(vma);
3684 intel_state->vma = i915_vma_get(vma);
3685 if (intel_plane_uses_fence(intel_state) && i915_vma_pin_fence(vma) == 0)
3686 if (vma->fence)
3687 intel_state->flags |= PLANE_HAS_FENCE;
3688
3689 plane_state->src_x = 0;
3690 plane_state->src_y = 0;
3691 plane_state->src_w = fb->width << 16;
3692 plane_state->src_h = fb->height << 16;
3693
3694 plane_state->crtc_x = 0;
3695 plane_state->crtc_y = 0;
3696 plane_state->crtc_w = fb->width;
3697 plane_state->crtc_h = fb->height;
3698
3699 intel_state->uapi.src = drm_plane_state_src(plane_state);
3700 intel_state->uapi.dst = drm_plane_state_dest(plane_state);
3701
3702 if (plane_config->tiling)
3703 dev_priv->preserve_bios_swizzle = true;
3704
3705 plane_state->fb = fb;
3706 drm_framebuffer_get(fb);
3707
3708 plane_state->crtc = &intel_crtc->base;
3709 intel_plane_copy_uapi_to_hw_state(intel_state, intel_state);
3710
3711 intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
3712
3713 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
3714 &to_intel_frontbuffer(fb)->bits);
3715 }
3716
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 42528 bytes --]
^ permalink raw reply [flat|nested] 50+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v10,01/11] HAX to make DSC work on the icelake test system (rev2)
2020-10-08 21:45 [Intel-gfx] [PATCH v10 01/11] HAX to make DSC work on the icelake test system Manasi Navare
` (13 preceding siblings ...)
2020-10-09 1:32 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2020-10-13 19:19 ` Patchwork
2020-10-13 19:21 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
17 siblings, 0 replies; 50+ messages in thread
From: Patchwork @ 2020-10-13 19:19 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v10,01/11] HAX to make DSC work on the icelake test system (rev2)
URL : https://patchwork.freedesktop.org/series/82483/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
98c263260e2e HAX to make DSC work on the icelake test system
3f5a6ad31ee9 drm/i915/display: Rename pipe_timings to transcoder_timings
-:11: WARNING:TYPO_SPELLING: 'halfs' may be misspelled - perhaps 'halves'?
#11:
With Bigjoiner, there are 2 pipes driving 2 halfs of 1
total: 0 errors, 1 warnings, 0 checks, 82 lines checked
8d72cc42bc4a drm/i915: Add hw.pipe_mode to allow bigjoiner pipe/transcoder split
-:7: WARNING:TYPO_SPELLING: 'halfs' may be misspelled - perhaps 'halves'?
#7:
With bigjoiner, there will be 2 pipes driving 2 halfs of 1 transcoder,
-:134: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#134: FILE: drivers/gpu/drm/i915/display/intel_display.c:13358:
+ crtc_state->hw.pipe_mode = crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
total: 0 errors, 1 warnings, 1 checks, 364 lines checked
4bc6201920b4 drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.
eacf263eb780 drm/i915: Try to make bigjoiner work in atomic check
-:145: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#145: FILE: drivers/gpu/drm/i915/display/intel_display.c:13370:
+ crtc_state->bigjoiner_linked_crtc);
-:205: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#205: FILE: drivers/gpu/drm/i915/display/intel_display.c:13441:
+ crtc_state->nv12_planes = crtc_state->c8_planes = crtc_state->update_planes = 0;
-:300: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#300: FILE: drivers/gpu/drm/i915/display/intel_display.c:15048:
+ slave = new_crtc_state->bigjoiner_linked_crtc =
-:334: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#334: FILE: drivers/gpu/drm/i915/display/intel_display.c:15082:
+ slave_crtc_state->bigjoiner = master_crtc_state->bigjoiner = false;
-:335: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#335: FILE: drivers/gpu/drm/i915/display/intel_display.c:15083:
+ slave_crtc_state->bigjoiner_slave = master_crtc_state->bigjoiner_slave = false;
-:336: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#336: FILE: drivers/gpu/drm/i915/display/intel_display.c:15084:
+ slave_crtc_state->bigjoiner_linked_crtc = master_crtc_state->bigjoiner_linked_crtc = NULL;
-:336: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#336: FILE: drivers/gpu/drm/i915/display/intel_display.c:15084:
+ slave_crtc_state->bigjoiner_linked_crtc = master_crtc_state->bigjoiner_linked_crtc = NULL;
-:391: WARNING:BRACES: braces {} are not necessary for any arm of this statement
#391: FILE: drivers/gpu/drm/i915/display/intel_display.c:15618:
+ if (new_crtc_state->bigjoiner) {
[...]
+ } else if (INTEL_GEN(dev_priv) >= 9)
[...]
else
[...]
total: 0 errors, 3 warnings, 5 checks, 403 lines checked
ef32759023ff drm/i915: Enable big joiner support in enable and disable sequences.
-:186: WARNING:LONG_LINE_COMMENT: line length of 106 exceeds 100 columns
#186: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:4533:
+ /* Our own transcoder needs to be disabled when reading it in intel_ddi_read_func_ctl() */
-:188: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#188: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:4535:
+ pipe_config->cpu_transcoder = (enum transcoder)pipe_config->bigjoiner_linked_crtc->pipe;
-:839: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#839: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:846:
+#define PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE (1<<1) /* bigjoiner slave, partial readout */
^
total: 0 errors, 2 warnings, 1 checks, 1033 lines checked
7843fc926a4a drm/i915: Make hardware readout work on i915.
-:33: WARNING:TABSTOP: Statements should start on a tabstop
#33: FILE: drivers/gpu/drm/i915/display/intel_display.c:3626:
+ struct intel_crtc_state *crtc_state =
-:76: WARNING:LONG_LINE: line length of 111 exceeds 100 columns
#76: FILE: drivers/gpu/drm/i915/display/intel_display.c:10808:
+ (intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & 0xfffff000) == plane_config->base) {
total: 0 errors, 2 warnings, 0 checks, 118 lines checked
f5fa5a71b2b1 drm/i915: Link planes in a bigjoiner configuration, v3.
-:206: ERROR:CODE_INDENT: code indent should use tabs where possible
#206: FILE: drivers/gpu/drm/i915/display/intel_display.c:12752:
+ * Setup and teardown the new bigjoiner plane mappings.$
-:207: ERROR:CODE_INDENT: code indent should use tabs where possible
#207: FILE: drivers/gpu/drm/i915/display/intel_display.c:12753:
+ */$
-:292: ERROR:CODE_INDENT: code indent should use tabs where possible
#292: FILE: drivers/gpu/drm/i915/display/intel_display.c:12834:
+ *$
-:308: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#308: FILE: drivers/gpu/drm/i915/display/intel_display.c:12848:
+ for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
-:324: ERROR:CODE_INDENT: code indent should use tabs where possible
#324: FILE: drivers/gpu/drm/i915/display/intel_display.c:12864:
+ * Make sure bigjoiner slave crtc's are also pulled in. This is not done automatically$
-:325: ERROR:CODE_INDENT: code indent should use tabs where possible
#325: FILE: drivers/gpu/drm/i915/display/intel_display.c:12865:
+ * when adding slave planes, because plane_state->crtc is null.$
-:326: ERROR:CODE_INDENT: code indent should use tabs where possible
#326: FILE: drivers/gpu/drm/i915/display/intel_display.c:12866:
+ */$
-:438: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional statements (8, 8)
#438: FILE: drivers/gpu/drm/i915/display/intel_display.h:472:
+ for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (iter), \
[...]
+ for_each_if ((((plane_state) = \
-:444: WARNING:SPACING: space prohibited between function name and open parenthesis '('
#444: FILE: drivers/gpu/drm/i915/display/intel_display.h:478:
+ for_each_if ((((plane_state) = \
-:445: WARNING:LONG_LINE: line length of 124 exceeds 100 columns
#445: FILE: drivers/gpu/drm/i915/display/intel_display.h:479:
+ to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &iter->base))), \
-:446: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#446: FILE: drivers/gpu/drm/i915/display/intel_display.h:480:
+ ((plane) = (plane_state)->bigjoiner_slave ? (plane_state)->bigjoiner_plane : (iter)), \
-:448: WARNING:LONG_LINE: line length of 125 exceeds 100 columns
#448: FILE: drivers/gpu/drm/i915/display/intel_display.h:482:
+ to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base)) : \
total: 6 errors, 6 warnings, 0 checks, 482 lines checked
02e2f03e5e81 drm/i915: Add bigjoiner aware plane clipping checks
3a4c35512ae7 drm/i915: Ensure correct master/slave enable/disable sequence
1f504d7510c7 drm/i915: Add debugfs dumping for bigjoiner, v3.
-:46: WARNING:LONG_LINE: line length of 123 exceeds 100 columns
#46: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs.c:782:
+ seq_printf(m, "\t\tuapi: fb=%d,%s,%dx%d, visible=%s, src=" DRM_RECT_FP_FMT ", dst=" DRM_RECT_FMT ", rotation=%s\n",
-:56: WARNING:LONG_LINE: line length of 119 exceeds 100 columns
#56: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs.c:792:
+ plane_state->planar_linked_plane->base.base.id, plane_state->planar_linked_plane->base.name,
-:60: WARNING:LONG_LINE: line length of 111 exceeds 100 columns
#60: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs.c:796:
+ plane_state->bigjoiner_plane->base.base.id, plane_state->bigjoiner_plane->base.name,
total: 0 errors, 3 warnings, 0 checks, 52 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v10,01/11] HAX to make DSC work on the icelake test system (rev2)
2020-10-08 21:45 [Intel-gfx] [PATCH v10 01/11] HAX to make DSC work on the icelake test system Manasi Navare
` (14 preceding siblings ...)
2020-10-13 19:19 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v10,01/11] HAX to make DSC work on the icelake test system (rev2) Patchwork
@ 2020-10-13 19:21 ` Patchwork
2020-10-13 19:45 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-14 14:32 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
17 siblings, 0 replies; 50+ messages in thread
From: Patchwork @ 2020-10-13 19:21 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v10,01/11] HAX to make DSC work on the icelake test system (rev2)
URL : https://patchwork.freedesktop.org/series/82483/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1367:25: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1367:25: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1367:25: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1368:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1368:17: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1368:17: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1427:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1427:17: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1427:17: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:262:16: error: incompatible types in comparison expression (different type sizes):
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:262:16: unsigned long *
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:262:16: unsigned long long *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:274:25: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:274:25: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:274:25: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:275:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:275:17: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:275:17: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:330:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:330:17: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:330:17: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h:92:56: error: marked inline, but without a definition
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49:
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v10,01/11] HAX to make DSC work on the icelake test system (rev2)
2020-10-08 21:45 [Intel-gfx] [PATCH v10 01/11] HAX to make DSC work on the icelake test system Manasi Navare
` (15 preceding siblings ...)
2020-10-13 19:21 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2020-10-13 19:45 ` Patchwork
2020-10-14 14:32 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
17 siblings, 0 replies; 50+ messages in thread
From: Patchwork @ 2020-10-13 19:45 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 7402 bytes --]
== Series Details ==
Series: series starting with [v10,01/11] HAX to make DSC work on the icelake test system (rev2)
URL : https://patchwork.freedesktop.org/series/82483/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9136 -> Patchwork_18692
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18692/index.html
Known issues
------------
Here are the changes found in Patchwork_18692 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_create@basic:
- fi-byt-j1900: [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9136/fi-byt-j1900/igt@gem_ctx_create@basic.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18692/fi-byt-j1900/igt@gem_ctx_create@basic.html
* igt@i915_module_load@reload:
- fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#1982] / [k.org#205379])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9136/fi-tgl-y/igt@i915_module_load@reload.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18692/fi-tgl-y/igt@i915_module_load@reload.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-tgl-u2: [PASS][5] -> [INCOMPLETE][6] ([i915#2557])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9136/fi-tgl-u2/igt@i915_selftest@live@gt_heartbeat.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18692/fi-tgl-u2/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-bsw-n3050: [PASS][7] -> [DMESG-WARN][8] ([i915#1982])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9136/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18692/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
- fi-icl-u2: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) +2 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9136/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18692/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- fi-tgl-y: [PASS][11] -> [DMESG-WARN][12] ([i915#1982])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9136/fi-tgl-y/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18692/fi-tgl-y/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
* igt@vgem_basic@sysfs:
- fi-tgl-y: [PASS][13] -> [DMESG-WARN][14] ([i915#402]) +1 similar issue
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9136/fi-tgl-y/igt@vgem_basic@sysfs.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18692/fi-tgl-y/igt@vgem_basic@sysfs.html
#### Possible fixes ####
* igt@gem_flink_basic@flink-lifetime:
- fi-tgl-y: [DMESG-WARN][15] ([i915#402]) -> [PASS][16] +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9136/fi-tgl-y/igt@gem_flink_basic@flink-lifetime.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18692/fi-tgl-y/igt@gem_flink_basic@flink-lifetime.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-n3050: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9136/fi-bsw-n3050/igt@i915_pm_rpm@basic-pci-d3-state.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18692/fi-bsw-n3050/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@kms_busy@basic@flip:
- {fi-kbl-7560u}: [DMESG-WARN][19] ([i915#1982]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9136/fi-kbl-7560u/igt@kms_busy@basic@flip.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18692/fi-kbl-7560u/igt@kms_busy@basic@flip.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-legacy:
- fi-icl-u2: [DMESG-WARN][21] ([i915#1982]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9136/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cursor-legacy.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18692/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cursor-legacy.html
* igt@kms_pipe_crc_basic@read-crc-pipe-b:
- fi-tgl-y: [DMESG-WARN][23] ([i915#1982]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9136/fi-tgl-y/igt@kms_pipe_crc_basic@read-crc-pipe-b.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18692/fi-tgl-y/igt@kms_pipe_crc_basic@read-crc-pipe-b.html
#### Warnings ####
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-y: [DMESG-WARN][25] ([i915#2411] / [i915#402]) -> [DMESG-WARN][26] ([i915#2411])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9136/fi-tgl-y/igt@gem_exec_suspend@basic-s3.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18692/fi-tgl-y/igt@gem_exec_suspend@basic-s3.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2557]: https://gitlab.freedesktop.org/drm/intel/issues/2557
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456
[k.org#205379]: https://bugzilla.kernel.org/show_bug.cgi?id=205379
Participating hosts (47 -> 40)
------------------------------
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-blb-e6850 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_9136 -> Patchwork_18692
CI-20190529: 20190529
CI_DRM_9136: 29eb1a8ba2cc0d14d3cae7213f9cdaaa13f3dd99 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5813: d4e6dd955a1dad02271aa41c9389f5097ee17765 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18692: 1f504d7510c72ba8fadb0948e84cd415b0642c23 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
1f504d7510c7 drm/i915: Add debugfs dumping for bigjoiner, v3.
3a4c35512ae7 drm/i915: Ensure correct master/slave enable/disable sequence
02e2f03e5e81 drm/i915: Add bigjoiner aware plane clipping checks
f5fa5a71b2b1 drm/i915: Link planes in a bigjoiner configuration, v3.
7843fc926a4a drm/i915: Make hardware readout work on i915.
ef32759023ff drm/i915: Enable big joiner support in enable and disable sequences.
eacf263eb780 drm/i915: Try to make bigjoiner work in atomic check
4bc6201920b4 drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.
8d72cc42bc4a drm/i915: Add hw.pipe_mode to allow bigjoiner pipe/transcoder split
3f5a6ad31ee9 drm/i915/display: Rename pipe_timings to transcoder_timings
98c263260e2e HAX to make DSC work on the icelake test system
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18692/index.html
[-- Attachment #1.2: Type: text/html, Size: 8991 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v10 06/11] drm/i915: Enable big joiner support in enable and disable sequences.
2020-10-08 21:45 ` [Intel-gfx] [PATCH v10 06/11] drm/i915: Enable big joiner support in enable and disable sequences Manasi Navare
@ 2020-10-14 11:07 ` Jani Nikula
2020-10-15 13:07 ` Ville Syrjälä
1 sibling, 0 replies; 50+ messages in thread
From: Jani Nikula @ 2020-10-14 11:07 UTC (permalink / raw)
To: Manasi Navare, intel-gfx
On Thu, 08 Oct 2020, Manasi Navare <manasi.d.navare@intel.com> wrote:
> From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
>
> Make vdsc work when no output is enabled. The big joiner needs VDSC
> on the slave, so enable it and set the appropriate bits.
> Also update timestamping constants, because slave crtc's are not
> updated in drm_atomic_helper_update_legacy_modeset_state().
>
> This should be enough to bring up CRTC's in a big joiner configuration,
> without any plane configuration on the second pipe yet.
>
> HOWEVER, we still bring up the crtc's in the wrong order. We need to
> make sure that the master crtc is brought up after the slave crtc.
> This is done correctly later in this series.
>
> The next steps are to enable planes correctly, and make sure we enable
> and update both master and slave in the correct order.
Yikes this is a big patch. Is there any way to make it smaller?
I've heard reports that this series breaks DSI VDSC (*), and if the
bisect points were to point at this, I'd be clueless.
BR,
Jani.
(*) Which means we really need to be careful to get test results on DSI
VDSC before merging the series!
>
> v2:
> * Manual rebase (Manasi)
>
> v3:
> * Rebase (Manasi)
>
> v4:
> * Rebase (Manasi)
>
> v5:
> * Get dsc power domain in ddi_init (Manasi)
>
> v6:
> * Remove dsc power put from dsc_disable (Maarten)
>
> v7:
> * Rebase (Manasi)
>
> v8:
> * Rebase (Manasi)
>
> v9:
> * Rebase (Manasi)
>
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 2 -
> drivers/gpu/drm/i915/display/intel_ddi.c | 68 ++-
> drivers/gpu/drm/i915/display/intel_display.c | 392 ++++++++++++------
> .../drm/i915/display/intel_display_types.h | 1 +
> drivers/gpu/drm/i915/display/intel_dp.c | 6 +-
> drivers/gpu/drm/i915/display/intel_vdsc.c | 201 ++++-----
> drivers/gpu/drm/i915/display/intel_vdsc.h | 7 +-
> 7 files changed, 421 insertions(+), 256 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 4400e83f783f..be8756816650 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -1492,8 +1492,6 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
> struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
>
> - intel_dsc_get_config(encoder, pipe_config);
> -
> /* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
> pipe_config->port_clock = intel_dpll_get_freq(i915,
> pipe_config->shared_dpll);
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index bbd5f04dc140..6b2c09effbdd 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -28,6 +28,7 @@
> #include <drm/drm_scdc_helper.h>
>
> #include "i915_drv.h"
> +#include "i915_trace.h"
> #include "intel_audio.h"
> #include "intel_combo_phy.h"
> #include "intel_connector.h"
> @@ -2217,12 +2218,6 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
> intel_display_power_get(dev_priv,
> intel_ddi_main_link_aux_domain(dig_port));
>
> - /*
> - * VDSC power is needed when DSC is enabled
> - */
> - if (crtc_state->dsc.compression_enable)
> - intel_display_power_get(dev_priv,
> - intel_dsc_power_domain(crtc_state));
> }
>
> void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder,
> @@ -3507,7 +3502,8 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
>
> /* 7.l Configure and enable FEC if needed */
> intel_ddi_enable_fec(encoder, crtc_state);
> - intel_dsc_enable(encoder, crtc_state);
> + if (!crtc_state->bigjoiner)
> + intel_dsc_enable(encoder, crtc_state);
> }
>
> static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
> @@ -3579,7 +3575,8 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
> if (!is_mst)
> intel_ddi_enable_pipe_clock(encoder, crtc_state);
>
> - intel_dsc_enable(encoder, crtc_state);
> + if (!crtc_state->bigjoiner)
> + intel_dsc_enable(encoder, crtc_state);
> }
>
> static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
> @@ -3828,6 +3825,21 @@ static void intel_ddi_post_disable(struct intel_atomic_state *state,
> ilk_pfit_disable(old_crtc_state);
> }
>
> + if (old_crtc_state->bigjoiner_linked_crtc) {
> + struct intel_atomic_state *state =
> + to_intel_atomic_state(old_crtc_state->uapi.state);
> + struct intel_crtc *slave =
> + old_crtc_state->bigjoiner_linked_crtc;
> + const struct intel_crtc_state *old_slave_crtc_state =
> + intel_atomic_get_old_crtc_state(state, slave);
> +
> + intel_crtc_vblank_off(old_slave_crtc_state);
> + trace_intel_pipe_disable(slave);
> +
> + intel_dsc_disable(old_slave_crtc_state);
> + skl_scaler_disable(old_slave_crtc_state);
> + }
> +
> /*
> * When called from DP MST code:
> * - old_conn_state will be NULL
> @@ -4044,7 +4056,8 @@ static void intel_enable_ddi(struct intel_atomic_state *state,
> {
> drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder);
>
> - intel_ddi_enable_transcoder_func(encoder, crtc_state);
> + if (!crtc_state->bigjoiner_slave)
> + intel_ddi_enable_transcoder_func(encoder, crtc_state);
>
> intel_enable_pipe(crtc_state);
>
> @@ -4397,21 +4410,18 @@ static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state)
> crtc_state->sync_mode_slaves_mask);
> }
>
> -void intel_ddi_get_config(struct intel_encoder *encoder,
> - struct intel_crtc_state *pipe_config)
> +static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
> + struct intel_crtc_state *pipe_config)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
> enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
> u32 temp, flags = 0;
>
> - /* XXX: DSI transcoder paranoia */
> - if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)))
> + temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
> + if (!(temp & TRANS_DDI_FUNC_ENABLE))
> return;
>
> - intel_dsc_get_config(encoder, pipe_config);
> -
> - temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
> if (temp & TRANS_DDI_PHSYNC)
> flags |= DRM_MODE_FLAG_PHSYNC;
> else
> @@ -4504,6 +4514,29 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
> default:
> break;
> }
> +}
> +
> +void intel_ddi_get_config(struct intel_encoder *encoder,
> + struct intel_crtc_state *pipe_config)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
> +
> + /* XXX: DSI transcoder paranoia */
> + if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
> + return;
> +
> + intel_ddi_read_func_ctl(encoder, pipe_config);
> + if (pipe_config->bigjoiner_slave) {
> + /* read out pipe settings from master */
> + enum transcoder save = pipe_config->cpu_transcoder;
> +
> + /* Our own transcoder needs to be disabled when reading it in intel_ddi_read_func_ctl() */
> + WARN_ON(pipe_config->output_types);
> + pipe_config->cpu_transcoder = (enum transcoder)pipe_config->bigjoiner_linked_crtc->pipe;
> + intel_ddi_read_func_ctl(encoder, pipe_config);
> + pipe_config->cpu_transcoder = save;
> + }
>
> pipe_config->has_audio =
> intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
> @@ -4529,7 +4562,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
> dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
> }
>
> - intel_ddi_clock_get(encoder, pipe_config);
> + if (!pipe_config->bigjoiner_slave)
> + intel_ddi_clock_get(encoder, pipe_config);
>
> if (IS_GEN9_LP(dev_priv))
> pipe_config->lane_lat_optim_mask =
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 37b56f4c2401..faf8bf757bed 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7125,6 +7125,45 @@ static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
> intel_de_write(dev_priv, reg, val);
> }
>
> +static void tgl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
> + const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *master = to_intel_crtc(crtc_state->uapi.crtc);
> + struct intel_crtc_state *master_crtc_state;
> + struct drm_connector_state *conn_state;
> + struct drm_connector *conn;
> + struct intel_encoder *encoder = NULL;
> + int i;
> +
> + if (crtc_state->bigjoiner_slave)
> + master = crtc_state->bigjoiner_linked_crtc;
> +
> + master_crtc_state = intel_atomic_get_new_crtc_state(state, master);
> +
> + for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
> + if (conn_state->crtc != &master->base)
> + continue;
> +
> + encoder = to_intel_encoder(conn_state->best_encoder);
> + break;
> + }
> +
> + if (!crtc_state->bigjoiner_slave) {
> + /* need to enable VDSC, which we skipped in pre-enable */
> + intel_dsc_enable(encoder, crtc_state);
> + } else {
> + /*
> + * Enable sequence steps 1-7 on bigjoiner master
> + */
> + intel_encoders_pre_pll_enable(state, master);
> + intel_enable_shared_dpll(master_crtc_state);
> + intel_encoders_pre_enable(state, master);
> +
> + /* and DSC on slave */
> + intel_dsc_enable(NULL, crtc_state);
> + }
> +}
> +
> static void hsw_crtc_enable(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> @@ -7138,34 +7177,39 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
> if (drm_WARN_ON(&dev_priv->drm, crtc->active))
> return;
>
> - intel_encoders_pre_pll_enable(state, crtc);
> -
> - if (new_crtc_state->shared_dpll)
> - intel_enable_shared_dpll(new_crtc_state);
> + if (!new_crtc_state->bigjoiner) {
> + intel_encoders_pre_pll_enable(state, crtc);
>
> - intel_encoders_pre_enable(state, crtc);
> + if (new_crtc_state->shared_dpll)
> + intel_enable_shared_dpll(new_crtc_state);
>
> - if (!transcoder_is_dsi(cpu_transcoder))
> - intel_set_transcoder_timings(new_crtc_state);
> + intel_encoders_pre_enable(state, crtc);
> + } else {
> + tgl_ddi_bigjoiner_pre_enable(state, new_crtc_state);
> + }
>
> intel_set_pipe_src_size(new_crtc_state);
> + if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
> + bdw_set_pipemisc(new_crtc_state);
>
> - if (cpu_transcoder != TRANSCODER_EDP &&
> - !transcoder_is_dsi(cpu_transcoder))
> - intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
> - new_crtc_state->pixel_multiplier - 1);
> + if (!new_crtc_state->bigjoiner_slave && !transcoder_is_dsi(cpu_transcoder)) {
> + if (!transcoder_is_dsi(cpu_transcoder))
> + intel_set_transcoder_timings(new_crtc_state);
>
> - if (new_crtc_state->has_pch_encoder)
> - intel_cpu_transcoder_set_m_n(new_crtc_state,
> - &new_crtc_state->fdi_m_n, NULL);
> + if (cpu_transcoder != TRANSCODER_EDP &&
> + !transcoder_is_dsi(cpu_transcoder))
> + intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
> + new_crtc_state->pixel_multiplier - 1);
> +
> + if (new_crtc_state->has_pch_encoder)
> + intel_cpu_transcoder_set_m_n(new_crtc_state,
> + &new_crtc_state->fdi_m_n, NULL);
>
> - if (!transcoder_is_dsi(cpu_transcoder)) {
> hsw_set_frame_start_delay(new_crtc_state);
> - hsw_set_pipeconf(new_crtc_state);
> }
>
> - if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
> - bdw_set_pipemisc(new_crtc_state);
> + if (!transcoder_is_dsi(cpu_transcoder))
> + hsw_set_pipeconf(new_crtc_state);
>
> crtc->active = true;
>
> @@ -7201,6 +7245,11 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
> if (INTEL_GEN(dev_priv) >= 11)
> icl_pipe_mbus_enable(crtc);
>
> + if (new_crtc_state->bigjoiner_slave) {
> + trace_intel_pipe_enable(crtc);
> + intel_crtc_vblank_on(new_crtc_state);
> + }
> +
> intel_encoders_enable(state, crtc);
>
> if (psl_clkgate_wa) {
> @@ -7495,6 +7544,9 @@ static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
> if (crtc_state->shared_dpll)
> mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);
>
> + if (crtc_state->dsc.compression_enable)
> + mask |= BIT_ULL(intel_dsc_power_domain(crtc_state));
> +
> return mask;
> }
>
> @@ -8113,6 +8165,30 @@ static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
> pfit_w * pfit_h);
> }
>
> +static void intel_encoder_get_config(struct intel_encoder *encoder,
> + struct intel_crtc_state *crtc_state)
> +{
> + struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
> +
> + encoder->get_config(encoder, crtc_state);
> +
> + *pipe_mode = crtc_state->hw.adjusted_mode;
> + if (crtc_state->bigjoiner) {
> + /*
> + * transcoder is programmed to the full mode,
> + * but pipe timings are half of the transcoder mode
> + */
> + pipe_mode->crtc_hdisplay /= 2;
> + pipe_mode->crtc_hblank_start /= 2;
> + pipe_mode->crtc_hblank_end /= 2;
> + pipe_mode->crtc_hsync_start /= 2;
> + pipe_mode->crtc_hsync_end /= 2;
> + pipe_mode->crtc_htotal /= 2;
> + pipe_mode->crtc_hskew /= 2;
> + pipe_mode->crtc_clock /= 2;
> + }
> +}
> +
> static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> @@ -9027,20 +9103,22 @@ static void intel_get_pipe_src_size(struct intel_crtc *crtc,
> void intel_mode_from_pipe_config(struct drm_display_mode *mode,
> struct intel_crtc_state *pipe_config)
> {
> - mode->hdisplay = pipe_config->hw.adjusted_mode.crtc_hdisplay;
> - mode->htotal = pipe_config->hw.adjusted_mode.crtc_htotal;
> - mode->hsync_start = pipe_config->hw.adjusted_mode.crtc_hsync_start;
> - mode->hsync_end = pipe_config->hw.adjusted_mode.crtc_hsync_end;
> + struct drm_display_mode *hw_mode = &pipe_config->hw.adjusted_mode;
> +
> + mode->hdisplay = hw_mode->crtc_hdisplay;
> + mode->htotal = hw_mode->crtc_htotal;
> + mode->hsync_start = hw_mode->crtc_hsync_start;
> + mode->hsync_end = hw_mode->crtc_hsync_end;
>
> - mode->vdisplay = pipe_config->hw.adjusted_mode.crtc_vdisplay;
> - mode->vtotal = pipe_config->hw.adjusted_mode.crtc_vtotal;
> - mode->vsync_start = pipe_config->hw.adjusted_mode.crtc_vsync_start;
> - mode->vsync_end = pipe_config->hw.adjusted_mode.crtc_vsync_end;
> + mode->vdisplay = hw_mode->crtc_vdisplay;
> + mode->vtotal = hw_mode->crtc_vtotal;
> + mode->vsync_start = hw_mode->crtc_vsync_start;
> + mode->vsync_end = hw_mode->crtc_vsync_end;
>
> - mode->flags = pipe_config->hw.adjusted_mode.flags;
> + mode->flags = hw_mode->flags;
> mode->type = DRM_MODE_TYPE_DRIVER;
>
> - mode->clock = pipe_config->hw.adjusted_mode.crtc_clock;
> + mode->clock = hw_mode->crtc_clock;
>
> drm_mode_set_name(mode);
> }
> @@ -11207,6 +11285,9 @@ static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
> } else {
> tmp = intel_de_read(dev_priv,
> TRANS_DDI_FUNC_CTL(cpu_transcoder));
> + if (!(tmp & TRANS_DDI_FUNC_ENABLE))
> + return;
> +
> if (INTEL_GEN(dev_priv) >= 12)
> port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
> else
> @@ -11279,12 +11360,20 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
> drm_WARN_ON(&dev_priv->drm, active);
> active = true;
> }
> + intel_dsc_get_config(pipe_config);
>
> - if (!active)
> - goto out;
> + if (!active) {
> + /* bigjoiner slave doesn't enable transcoder */
> + if (!pipe_config->bigjoiner_slave)
> + goto out;
>
> - if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
> - INTEL_GEN(dev_priv) >= 11) {
> + active = true;
> + pipe_config->pixel_multiplier = 1;
> +
> + /* we cannot read out most state, so don't bother.. */
> + pipe_config->quirks |= PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE;
> + } else if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
> + INTEL_GEN(dev_priv) >= 11) {
> hsw_get_ddi_port_state(crtc, pipe_config);
> intel_get_transcoder_timings(crtc, pipe_config);
> }
> @@ -11370,8 +11459,11 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
> }
> }
>
> - if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
> - !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
> + if (pipe_config->bigjoiner_slave) {
> + /* Cannot be read out as a slave, set to 0. */
> + pipe_config->pixel_multiplier = 0;
> + } else if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
> + !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
> pipe_config->pixel_multiplier =
> intel_de_read(dev_priv,
> PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
> @@ -12386,7 +12478,7 @@ intel_encoder_current_mode(struct intel_encoder *encoder)
> return NULL;
> }
>
> - encoder->get_config(encoder, crtc_state);
> + intel_encoder_get_config(encoder, crtc_state);
>
> intel_mode_from_pipe_config(mode, crtc_state);
>
> @@ -13385,12 +13477,15 @@ intel_crtc_copy_uapi_to_hw_state(struct intel_atomic_state *state,
> intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc_state);
> }
>
> -static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
> +static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state,
> + struct drm_display_mode *user_mode)
> {
> - crtc_state->uapi.enable = crtc_state->hw.enable;
> - crtc_state->uapi.active = crtc_state->hw.active;
> - drm_WARN_ON(crtc_state->uapi.crtc->dev,
> - drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);
> + if (!crtc_state->bigjoiner_slave) {
> + crtc_state->uapi.enable = crtc_state->hw.enable;
> + crtc_state->uapi.active = crtc_state->hw.active;
> + drm_WARN_ON(crtc_state->uapi.crtc->dev,
> + drm_atomic_set_mode_for_crtc(&crtc_state->uapi, user_mode) < 0);
> + }
>
> crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
>
> @@ -14027,21 +14122,42 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>
> PIPE_CONF_CHECK_X(output_types);
>
> - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
> - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
> - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
> - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
> - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
> - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
> -
> - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
> - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
> - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
> - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
> - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
> - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
> -
> - PIPE_CONF_CHECK_I(pixel_multiplier);
> + if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) {
> + /* bigjoiner mode = transcoder mode / 2, for calculations */
> + PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);
> + PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_htotal);
> + PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vdisplay);
> + PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vtotal);
> +
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
> +
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
> +
> + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> + DRM_MODE_FLAG_INTERLACE);
> +
> + if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
> + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> + DRM_MODE_FLAG_PHSYNC);
> + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> + DRM_MODE_FLAG_NHSYNC);
> + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> + DRM_MODE_FLAG_PVSYNC);
> + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> + DRM_MODE_FLAG_NVSYNC);
> + }
> + PIPE_CONF_CHECK_I(pixel_multiplier);
> + }
> PIPE_CONF_CHECK_I(output_format);
> PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
> if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
> @@ -14051,24 +14167,11 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
> PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
> PIPE_CONF_CHECK_BOOL(has_infoframe);
> - PIPE_CONF_CHECK_BOOL(fec_enable);
> + if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE))
> + PIPE_CONF_CHECK_BOOL(fec_enable);
>
> PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
>
> - PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> - DRM_MODE_FLAG_INTERLACE);
> -
> - if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
> - PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> - DRM_MODE_FLAG_PHSYNC);
> - PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> - DRM_MODE_FLAG_NHSYNC);
> - PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> - DRM_MODE_FLAG_PVSYNC);
> - PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> - DRM_MODE_FLAG_NVSYNC);
> - }
> -
> PIPE_CONF_CHECK_X(gmch_pfit.control);
> /* pfit ratios are autocomputed by the hw on gen4+ */
> if (INTEL_GEN(dev_priv) < 4)
> @@ -14094,7 +14197,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> }
>
> PIPE_CONF_CHECK_I(scaler_state.scaler_id);
> - PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
> + if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE))
> + PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
>
> PIPE_CONF_CHECK_X(gamma_mode);
> if (IS_CHERRYVIEW(dev_priv))
> @@ -14115,48 +14219,51 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> PIPE_CONF_CHECK_BOOL(double_wide);
>
> PIPE_CONF_CHECK_P(shared_dpll);
> - PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
> - PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
> - PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
> - PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
> - PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
> - PIPE_CONF_CHECK_X(dpll_hw_state.spll);
> - PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
> - PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
> - PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
> - PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
> - PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
> - PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
> - PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
> - PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
> - PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
> - PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
> - PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
> - PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
> - PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
> - PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
> - PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
> - PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
> - PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
> - PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
> - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
> - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
> - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
> - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
> - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
> - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
> - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
> -
> - PIPE_CONF_CHECK_X(dsi_pll.ctrl);
> - PIPE_CONF_CHECK_X(dsi_pll.div);
> -
> - if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
> - PIPE_CONF_CHECK_I(pipe_bpp);
> -
> - PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
> - PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
> -
> - PIPE_CONF_CHECK_I(min_voltage_level);
> + if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) {
> + PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
> + PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
> + PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
> + PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
> + PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
> + PIPE_CONF_CHECK_X(dpll_hw_state.spll);
> + PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
> + PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
> + PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
> + PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
> + PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
> + PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
> + PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
> + PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
> + PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
> + PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
> + PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
> + PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
> + PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
> + PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
> + PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
> + PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
> + PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
> + PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
> + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
> + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
> + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
> + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
> + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
> + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
> + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
> +
> + PIPE_CONF_CHECK_X(dsi_pll.ctrl);
> + PIPE_CONF_CHECK_X(dsi_pll.div);
> +
> + if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
> + PIPE_CONF_CHECK_I(pipe_bpp);
> +
> + PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
> + PIPE_CONF_CHECK_CLOCK_FUZZY(hw.pipe_mode.crtc_clock);
> + PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
> +
> + PIPE_CONF_CHECK_I(min_voltage_level);
> + }
>
> PIPE_CONF_CHECK_X(infoframes.enable);
> PIPE_CONF_CHECK_X(infoframes.gcp);
> @@ -14168,11 +14275,12 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>
> PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
> PIPE_CONF_CHECK_I(master_transcoder);
> -
> + PIPE_CONF_CHECK_BOOL(bigjoiner);
> + PIPE_CONF_CHECK_BOOL(bigjoiner_slave);
> + PIPE_CONF_CHECK_P(bigjoiner_linked_crtc);
> PIPE_CONF_CHECK_I(dsc.compression_enable);
> PIPE_CONF_CHECK_I(dsc.dsc_split);
> PIPE_CONF_CHECK_I(dsc.compressed_bpp);
> -
> PIPE_CONF_CHECK_I(mst_master_transcoder);
>
> #undef PIPE_CONF_CHECK_X
> @@ -14439,6 +14547,7 @@ verify_crtc_state(struct intel_crtc *crtc,
> struct intel_encoder *encoder;
> struct intel_crtc_state *pipe_config = old_crtc_state;
> struct drm_atomic_state *state = old_crtc_state->uapi.state;
> + struct intel_crtc *master = crtc;
>
> __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi);
> intel_crtc_free_hw_state(old_crtc_state);
> @@ -14467,7 +14576,10 @@ verify_crtc_state(struct intel_crtc *crtc,
> "(expected %i, found %i)\n",
> new_crtc_state->hw.active, crtc->active);
>
> - for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
> + if (new_crtc_state->bigjoiner_slave)
> + master = new_crtc_state->bigjoiner_linked_crtc;
> +
> + for_each_encoder_on_crtc(dev, &master->base, encoder) {
> enum pipe pipe;
> bool active;
>
> @@ -14477,12 +14589,12 @@ verify_crtc_state(struct intel_crtc *crtc,
> encoder->base.base.id, active,
> new_crtc_state->hw.active);
>
> - I915_STATE_WARN(active && crtc->pipe != pipe,
> + I915_STATE_WARN(active && master->pipe != pipe,
> "Encoder connected to wrong pipe %c\n",
> pipe_name(pipe));
>
> if (active)
> - encoder->get_config(encoder, pipe_config);
> + intel_encoder_get_config(encoder, pipe_config);
> }
>
> intel_crtc_compute_pixel_rate(pipe_config);
> @@ -15640,7 +15752,12 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
>
> + drm_WARN_ON(&dev_priv->drm, old_crtc_state->bigjoiner_slave);
> +
> intel_crtc_disable_planes(state, crtc);
> + if (old_crtc_state->bigjoiner)
> + intel_crtc_disable_planes(state,
> + old_crtc_state->bigjoiner_linked_crtc);
>
> /*
> * We need to disable pipe CRC before disabling the pipe,
> @@ -15670,7 +15787,7 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state)
> /* Only disable port sync and MST slaves */
> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> new_crtc_state, i) {
> - if (!needs_modeset(new_crtc_state))
> + if (!needs_modeset(new_crtc_state) || old_crtc_state->bigjoiner_slave)
> continue;
>
> if (!old_crtc_state->hw.active)
> @@ -15685,7 +15802,6 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state)
> !intel_dp_mst_is_slave_trans(old_crtc_state))
> continue;
>
> - intel_pre_plane_update(state, crtc);
> intel_old_crtc_state_disables(state, old_crtc_state,
> new_crtc_state, crtc);
> handled |= BIT(crtc->pipe);
> @@ -15695,10 +15811,18 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state)
> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> new_crtc_state, i) {
> if (!needs_modeset(new_crtc_state) ||
> - (handled & BIT(crtc->pipe)))
> + (handled & BIT(crtc->pipe)) ||
> + old_crtc_state->bigjoiner_slave)
> continue;
>
> intel_pre_plane_update(state, crtc);
> + if (old_crtc_state->bigjoiner) {
> + struct intel_crtc *slave =
> + old_crtc_state->bigjoiner_linked_crtc;
> +
> + intel_pre_plane_update(state, slave);
> + }
> +
> if (old_crtc_state->hw.active)
> intel_old_crtc_state_disables(state, old_crtc_state,
> new_crtc_state, crtc);
> @@ -18357,7 +18481,7 @@ int intel_modeset_init_nogem(struct drm_i915_private *i915)
> for_each_intel_crtc(dev, crtc) {
> struct intel_initial_plane_config plane_config = {};
>
> - if (!crtc->active)
> + if (!to_intel_crtc_state(crtc->base.state)->uapi.active)
> continue;
>
> /*
> @@ -18880,9 +19004,19 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> crtc_state = to_intel_crtc_state(crtc->base.state);
>
> encoder->base.crtc = &crtc->base;
> - encoder->get_config(encoder, crtc_state);
> + intel_encoder_get_config(encoder, crtc_state);
> if (encoder->sync_state)
> encoder->sync_state(encoder, crtc_state);
> +
> + /* read out to slave crtc as well for bigjoiner */
> + if (crtc_state->bigjoiner) {
> + /* encoder should read be linked to bigjoiner master */
> + WARN_ON(crtc_state->bigjoiner_slave);
> +
> + crtc = crtc_state->bigjoiner_linked_crtc;
> + crtc_state = to_intel_crtc_state(crtc->base.state);
> + intel_encoder_get_config(encoder, crtc_state);
> + }
> } else {
> encoder->base.crtc = NULL;
> }
> @@ -18939,15 +19073,11 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> int min_cdclk = 0;
>
> if (crtc_state->hw.active) {
> - struct drm_display_mode *mode = &crtc_state->hw.mode;
> + struct drm_display_mode mode;
>
> intel_mode_from_pipe_config(&crtc_state->hw.adjusted_mode,
> crtc_state);
>
> - *mode = crtc_state->hw.adjusted_mode;
> - mode->hdisplay = crtc_state->pipe_src_w;
> - mode->vdisplay = crtc_state->pipe_src_h;
> -
> /*
> * The initial mode needs to be set in order to keep
> * the atomic core happy. It wants a valid mode if the
> @@ -18962,11 +19092,15 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> /* initialize pipe_mode */
> crtc_state->hw.pipe_mode = crtc_state->hw.adjusted_mode;
>
> + mode = crtc_state->hw.adjusted_mode;
> + mode.hdisplay = crtc_state->pipe_src_w;
> + mode.vdisplay = crtc_state->pipe_src_h;
> +
> intel_crtc_compute_pixel_rate(crtc_state);
>
> intel_crtc_update_active_timings(crtc_state);
>
> - intel_crtc_copy_hw_to_uapi_state(crtc_state);
> + intel_crtc_copy_hw_to_uapi_state(crtc_state, &mode);
> }
>
> for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index c159f6a48bf0..7a62b1d7e727 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -838,6 +838,7 @@ struct intel_crtc_state {
> * accordingly.
> */
> #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
> +#define PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE (1<<1) /* bigjoiner slave, partial readout */
> unsigned long quirks;
>
> unsigned fb_bits; /* framebuffers to flip */
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index a627ad77dd3f..7a7994121274 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2103,12 +2103,10 @@ static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
> static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state)
> {
> - struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> -
> - if (!intel_dp_is_edp(intel_dp) && !crtc_state->fec_enable)
> + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable)
> return false;
>
> - return intel_dsc_source_support(encoder, crtc_state) &&
> + return intel_dsc_source_support(crtc_state) &&
> drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index c5735c365659..e2716a67b281 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -332,11 +332,10 @@ static const struct rc_parameters *get_rc_params(u16 compressed_bpp,
> return &rc_parameters[row_index][column_index];
> }
>
> -bool intel_dsc_source_support(struct intel_encoder *encoder,
> - const struct intel_crtc_state *crtc_state)
> +bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
> {
> const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> enum pipe pipe = crtc->pipe;
>
> @@ -490,11 +489,10 @@ intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
> return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
> }
>
> -static void intel_dsc_pps_configure(struct intel_encoder *encoder,
> - const struct intel_crtc_state *crtc_state)
> +static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
> enum pipe pipe = crtc->pipe;
> u32 pps_val = 0;
> @@ -503,6 +501,9 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder,
> u8 num_vdsc_instances = (crtc_state->dsc.dsc_split) ? 2 : 1;
> int i = 0;
>
> + if (crtc_state->bigjoiner)
> + num_vdsc_instances *= 2;
> +
> /* Populate PICTURE_PARAMETER_SET_0 registers */
> pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor <<
> DSC_VER_MIN_SHIFT |
> @@ -973,55 +974,6 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder,
> }
> }
>
> -void intel_dsc_get_config(struct intel_encoder *encoder,
> - struct intel_crtc_state *crtc_state)
> -{
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - enum pipe pipe = crtc->pipe;
> - enum intel_display_power_domain power_domain;
> - intel_wakeref_t wakeref;
> - u32 dss_ctl1, dss_ctl2, val;
> -
> - if (!intel_dsc_source_support(encoder, crtc_state))
> - return;
> -
> - power_domain = intel_dsc_power_domain(crtc_state);
> -
> - wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
> - if (!wakeref)
> - return;
> -
> - if (!is_pipe_dsc(crtc_state)) {
> - dss_ctl1 = intel_de_read(dev_priv, DSS_CTL1);
> - dss_ctl2 = intel_de_read(dev_priv, DSS_CTL2);
> - } else {
> - dss_ctl1 = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe));
> - dss_ctl2 = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL2(pipe));
> - }
> -
> - crtc_state->dsc.compression_enable = dss_ctl2 & LEFT_BRANCH_VDSC_ENABLE;
> - if (!crtc_state->dsc.compression_enable)
> - goto out;
> -
> - crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) &&
> - (dss_ctl1 & JOINER_ENABLE);
> -
> - /* FIXME: add more state readout as needed */
> -
> - /* PPS1 */
> - if (!is_pipe_dsc(crtc_state))
> - val = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1);
> - else
> - val = intel_de_read(dev_priv,
> - ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
> - vdsc_cfg->bits_per_pixel = val;
> - crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
> -out:
> - intel_display_power_put(dev_priv, power_domain, wakeref);
> -}
> -
> static void intel_dsc_dsi_pps_write(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> @@ -1060,77 +1012,126 @@ static void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
> sizeof(dp_dsc_pps_sdp));
> }
>
> +static i915_reg_t dss_ctl1_reg(const struct intel_crtc_state *crtc_state)
> +{
> + enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
> +
> + if (crtc_state->cpu_transcoder == TRANSCODER_EDP)
> + return DSS_CTL1;
> +
> + return ICL_PIPE_DSS_CTL1(pipe);
> +}
> +
> +static i915_reg_t dss_ctl2_reg(const struct intel_crtc_state *crtc_state)
> +{
> + enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
> +
> + if (crtc_state->cpu_transcoder == TRANSCODER_EDP)
> + return DSS_CTL2;
> +
> + return ICL_PIPE_DSS_CTL2(pipe);
> +}
> +
> void intel_dsc_enable(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - enum pipe pipe = crtc->pipe;
> - i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> u32 dss_ctl1_val = 0;
> u32 dss_ctl2_val = 0;
>
> if (!crtc_state->dsc.compression_enable)
> return;
>
> - /* Enable Power wells for VDSC/joining */
> - intel_display_power_get(dev_priv,
> - intel_dsc_power_domain(crtc_state));
> -
> - intel_dsc_pps_configure(encoder, crtc_state);
> + intel_dsc_pps_configure(crtc_state);
>
> - if (encoder->type == INTEL_OUTPUT_DSI)
> - intel_dsc_dsi_pps_write(encoder, crtc_state);
> - else
> - intel_dsc_dp_pps_write(encoder, crtc_state);
> -
> - if (!is_pipe_dsc(crtc_state)) {
> - dss_ctl1_reg = DSS_CTL1;
> - dss_ctl2_reg = DSS_CTL2;
> - } else {
> - dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
> - dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
> + if (!crtc_state->bigjoiner_slave) {
> + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
> + intel_dsc_dsi_pps_write(encoder, crtc_state);
> + else
> + intel_dsc_dp_pps_write(encoder, crtc_state);
> }
> +
> dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE;
> if (crtc_state->dsc.dsc_split) {
> dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE;
> dss_ctl1_val |= JOINER_ENABLE;
> }
> - intel_de_write(dev_priv, dss_ctl1_reg, dss_ctl1_val);
> - intel_de_write(dev_priv, dss_ctl2_reg, dss_ctl2_val);
> + if (crtc_state->bigjoiner) {
> + dss_ctl1_val |= BIG_JOINER_ENABLE;
> + if (!crtc_state->bigjoiner_slave)
> + dss_ctl1_val |= MASTER_BIG_JOINER_ENABLE;
> + }
> + intel_de_write(dev_priv, dss_ctl1_reg(crtc_state), dss_ctl1_val);
> + intel_de_write(dev_priv, dss_ctl2_reg(crtc_state), dss_ctl2_val);
> }
>
> void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - enum pipe pipe = crtc->pipe;
> - i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
> - u32 dss_ctl1_val = 0, dss_ctl2_val = 0;
>
> if (!old_crtc_state->dsc.compression_enable)
> return;
>
> - if (!is_pipe_dsc(old_crtc_state)) {
> - dss_ctl1_reg = DSS_CTL1;
> - dss_ctl2_reg = DSS_CTL2;
> - } else {
> - dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
> - dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
> + intel_de_write(dev_priv, dss_ctl1_reg(old_crtc_state), 0);
> + intel_de_write(dev_priv, dss_ctl2_reg(old_crtc_state), 0);
> +}
> +
> +void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
> +{
> + struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + enum pipe pipe = crtc->pipe;
> + enum intel_display_power_domain power_domain;
> + intel_wakeref_t wakeref;
> + u32 dss_ctl1, dss_ctl2, val;
> +
> + if (!intel_dsc_source_support(crtc_state))
> + return;
> +
> + power_domain = intel_dsc_power_domain(crtc_state);
> +
> + wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
> + if (!wakeref)
> + return;
> +
> + dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc_state));
> + dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg(crtc_state));
> +
> + crtc_state->dsc.compression_enable = dss_ctl2 & LEFT_BRANCH_VDSC_ENABLE;
> + if (!crtc_state->dsc.compression_enable)
> + goto out;
> +
> + crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) &&
> + (dss_ctl1 & JOINER_ENABLE);
> +
> + if (dss_ctl1 & BIG_JOINER_ENABLE) {
> + crtc_state->bigjoiner = true;
> +
> + if (!(dss_ctl1 & MASTER_BIG_JOINER_ENABLE)) {
> + crtc_state->bigjoiner_slave = true;
> + if (!WARN_ON(crtc->pipe == PIPE_A))
> + crtc_state->bigjoiner_linked_crtc =
> + intel_get_crtc_for_pipe(dev_priv, crtc->pipe - 1);
> + } else {
> + if (!WARN_ON(INTEL_NUM_PIPES(dev_priv) == crtc->pipe + 1))
> + crtc_state->bigjoiner_linked_crtc =
> + intel_get_crtc_for_pipe(dev_priv, crtc->pipe + 1);
> + }
> }
> - dss_ctl1_val = intel_de_read(dev_priv, dss_ctl1_reg);
> - if (dss_ctl1_val & JOINER_ENABLE)
> - dss_ctl1_val &= ~JOINER_ENABLE;
> - intel_de_write(dev_priv, dss_ctl1_reg, dss_ctl1_val);
> -
> - dss_ctl2_val = intel_de_read(dev_priv, dss_ctl2_reg);
> - if (dss_ctl2_val & LEFT_BRANCH_VDSC_ENABLE ||
> - dss_ctl2_val & RIGHT_BRANCH_VDSC_ENABLE)
> - dss_ctl2_val &= ~(LEFT_BRANCH_VDSC_ENABLE |
> - RIGHT_BRANCH_VDSC_ENABLE);
> - intel_de_write(dev_priv, dss_ctl2_reg, dss_ctl2_val);
> -
> - /* Disable Power wells for VDSC/joining */
> - intel_display_power_put_unchecked(dev_priv,
> - intel_dsc_power_domain(old_crtc_state));
> +
> + /* FIXME: add more state readout as needed */
> +
> + /* PPS1 */
> + if (!is_pipe_dsc(crtc_state))
> + val = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1);
> + else
> + val = intel_de_read(dev_priv,
> + ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
> + vdsc_cfg->bits_per_pixel = val;
> + crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
> +out:
> + intel_display_power_put(dev_priv, power_domain, wakeref);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h
> index e56a3254c214..5301345ac5e7 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.h
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
> @@ -11,15 +11,14 @@
> struct intel_encoder;
> struct intel_crtc_state;
>
> -bool intel_dsc_source_support(struct intel_encoder *encoder,
> - const struct intel_crtc_state *crtc_state);
> +bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state);
> void intel_dsc_enable(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state);
> void intel_dsc_disable(const struct intel_crtc_state *crtc_state);
> int intel_dsc_compute_params(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config);
> -void intel_dsc_get_config(struct intel_encoder *encoder,
> - struct intel_crtc_state *crtc_state);
> +void intel_dsc_get_config(struct intel_crtc_state *crtc_state);
> +
> enum intel_display_power_domain
> intel_dsc_power_domain(const struct intel_crtc_state *crtc_state);
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v10 04/11] drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.
2020-10-08 21:45 ` [Intel-gfx] [PATCH v10 04/11] drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3 Manasi Navare
@ 2020-10-14 11:26 ` Ville Syrjälä
2020-10-14 19:04 ` Navare, Manasi
2020-10-20 18:39 ` Ville Syrjälä
1 sibling, 1 reply; 50+ messages in thread
From: Ville Syrjälä @ 2020-10-14 11:26 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
On Thu, Oct 08, 2020 at 02:45:28PM -0700, Manasi Navare wrote:
> From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
>
> Small changes to intel_dp_mode_valid(), allow listing modes that
> can only be supported in the bigjoiner configuration, which is
> not supported yet.
>
> eDP does not support bigjoiner, so do not expose bigjoiner only
> modes on the eDP port.
>
> v7:
> * Add can_bigjoiner() helper (Ville)
> * Pass bigjoiner to plane_size validation (Ville)
> v6:
> * Rebase after dp_downstream mode valid changes (Manasi)
> v5:
> * Increase max plane width to support 8K with bigjoiner (Maarten)
> v4:
> * Rebase (Manasi)
>
> Changes since v1:
> - Disallow bigjoiner on eDP.
> Changes since v2:
> - Rename intel_dp_downstream_max_dotclock to intel_dp_max_dotclock,
> and split off the downstream and source checking to its own function.
> (Ville)
> v3:
> * Rebase (Manasi)
>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 5 +-
> drivers/gpu/drm/i915/display/intel_display.h | 3 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 126 +++++++++++++++----
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
> drivers/gpu/drm/i915/display/intel_dsi.c | 2 +-
> drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
> 6 files changed, 111 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 723766b1eae3..cc540c7b7dcd 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -17642,7 +17642,8 @@ intel_mode_valid(struct drm_device *dev,
>
> enum drm_mode_status
> intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
> - const struct drm_display_mode *mode)
> + const struct drm_display_mode *mode,
> + bool bigjoiner)
> {
> int plane_width_max, plane_height_max;
>
> @@ -17659,7 +17660,7 @@ intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
> * too big for that.
> */
> if (INTEL_GEN(dev_priv) >= 11) {
> - plane_width_max = 5120;
> + plane_width_max = 5120 << bigjoiner;
> plane_height_max = 4320;
> } else {
> plane_width_max = 5120;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index d10b7c8cde3f..3d860a9da8fe 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -496,7 +496,8 @@ u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
> bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
> enum drm_mode_status
> intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
> - const struct drm_display_mode *mode);
> + const struct drm_display_mode *mode,
> + bool bigjoiner);
> enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
> bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 8a522edd7386..af2ff425e5d5 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -247,6 +247,29 @@ intel_dp_max_data_rate(int max_link_clock, int max_lanes)
> return max_link_clock * max_lanes;
> }
>
> +static int source_max_dotclock(struct intel_dp *intel_dp, bool allow_bigjoiner)
> +{
> + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> + struct intel_encoder *encoder = &intel_dig_port->base;
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +
> + if (allow_bigjoiner && INTEL_GEN(dev_priv) >= 11 && !intel_dp_is_edp(intel_dp))
> + return 2 * dev_priv->max_dotclk_freq;
> +
> + return dev_priv->max_dotclk_freq;
> +}
> +
> +static int
> +intel_dp_max_dotclock(struct intel_dp *intel_dp, bool allow_bigjoiner)
> +{
> + int max_dotclk = source_max_dotclock(intel_dp, allow_bigjoiner);
> +
> + if (intel_dp->dfp.max_dotclock)
No. dfp checks should stay where they are.
> + return min(max_dotclk, intel_dp->dfp.max_dotclock);
> +
> + return max_dotclk;
> +}
> +
> static int cnl_max_source_rate(struct intel_dp *intel_dp)
> {
> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> @@ -512,7 +535,8 @@ small_joiner_ram_size_bits(struct drm_i915_private *i915)
>
> static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
> u32 link_clock, u32 lane_count,
> - u32 mode_clock, u32 mode_hdisplay)
> + u32 mode_clock, u32 mode_hdisplay,
> + bool bigjoiner)
> {
> u32 bits_per_pixel, max_bpp_small_joiner_ram;
> int i;
> @@ -530,6 +554,10 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
> /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
> max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
> mode_hdisplay;
> +
> + if (bigjoiner)
> + max_bpp_small_joiner_ram *= 2;
> +
> drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n",
> max_bpp_small_joiner_ram);
>
> @@ -539,6 +567,15 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
> */
> bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
>
> + if (bigjoiner) {
> + u32 max_bpp_bigjoiner =
> + i915->max_cdclk_freq * 48 /
> + intel_dp_mode_to_fec_clock(mode_clock);
> +
> + DRM_DEBUG_KMS("Max big joiner bpp: %u\n", max_bpp_bigjoiner);
> + bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
> + }
> +
> /* Error out if the max bpp is less than smallest allowed valid bpp */
> if (bits_per_pixel < valid_dsc_bpp[0]) {
> drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
> @@ -561,7 +598,8 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
> }
>
> static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
> - int mode_clock, int mode_hdisplay)
> + int mode_clock, int mode_hdisplay,
> + bool bigjoiner)
> {
> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> u8 min_slice_count, i;
> @@ -588,12 +626,20 @@ static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
>
> /* Find the closest match to the valid slice count values */
> for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
> - if (valid_dsc_slicecount[i] >
> - drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
> - false))
> + u8 test_slice_count = bigjoiner ?
> + 2 * valid_dsc_slicecount[i] :
> + valid_dsc_slicecount[i];
> +
> + if (test_slice_count >
> + drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, false))
> break;
> - if (min_slice_count <= valid_dsc_slicecount[i])
> - return valid_dsc_slicecount[i];
> +
> + /* big joiner needs small joiner to be enabled */
> + if (bigjoiner && test_slice_count < 4)
> + continue;
> +
> + if (min_slice_count <= test_slice_count)
> + return test_slice_count;
> }
>
> drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
> @@ -676,10 +722,6 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector,
> const struct drm_display_info *info = &connector->base.display_info;
> int tmds_clock;
>
> - if (intel_dp->dfp.max_dotclock &&
> - target_clock > intel_dp->dfp.max_dotclock)
> - return MODE_CLOCK_HIGH;
> -
> /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
> tmds_clock = target_clock;
> if (drm_mode_is_420_only(info, mode))
> @@ -695,6 +737,16 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector,
> return MODE_OK;
> }
>
> +static bool intel_dp_can_bigjoiner(struct drm_connector *connector)
> +{
> + struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
> + struct drm_i915_private *dev_priv = to_i915(connector->dev);
> +
> + return INTEL_GEN(dev_priv) >= 12 ||
> + (INTEL_GEN(dev_priv) == 11 &&
> + encoder->port != PORT_A);
> +}
> +
> static enum drm_mode_status
> intel_dp_mode_valid(struct drm_connector *connector,
> struct drm_display_mode *mode)
> @@ -709,10 +761,16 @@ intel_dp_mode_valid(struct drm_connector *connector,
> u16 dsc_max_output_bpp = 0;
> u8 dsc_slice_count = 0;
> enum drm_mode_status status;
> + bool dsc = false, bigjoiner = false;
>
> if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
> return MODE_NO_DBLESCAN;
>
> + if (mode->flags & DRM_MODE_FLAG_DBLCLK)
> + return MODE_H_ILLEGAL;
This random shuffling of things makes for a messy diff.
> +
> + max_dotclk = intel_dp_max_dotclock(intel_dp, false);
> +
> if (intel_dp_is_edp(intel_dp) && fixed_mode) {
> if (mode->hdisplay > fixed_mode->hdisplay)
> return MODE_PANEL;
> @@ -723,6 +781,21 @@ intel_dp_mode_valid(struct drm_connector *connector,
> target_clock = fixed_mode->clock;
> }
>
> + if (mode->clock < 10000)
> + return MODE_CLOCK_LOW;
Another random shuffling. Hmm. What on earth is this even and why is it
checking mode->clock and not target_clock?
Anywyas, plese split out the unrelated stuff so we at least have a
chance of getting a legible diff.
> +
> + if (target_clock > max_dotclk) {
> + if (intel_dp_is_edp(intel_dp))
> + return MODE_CLOCK_HIGH;
> +
> + max_dotclk = intel_dp_max_dotclock(intel_dp, true);
> +
> + if (target_clock > max_dotclk)
> + return MODE_CLOCK_HIGH;
> +
> + bigjoiner = intel_dp_can_bigjoiner(connector);
> + }
> +
> max_link_clock = intel_dp_max_link_rate(intel_dp);
> max_lanes = intel_dp_max_lane_count(intel_dp);
>
> @@ -751,30 +824,35 @@ intel_dp_mode_valid(struct drm_connector *connector,
> max_link_clock,
> max_lanes,
> target_clock,
> - mode->hdisplay) >> 4;
> + mode->hdisplay,
> + bigjoiner) >> 4;
> dsc_slice_count =
> intel_dp_dsc_get_slice_count(intel_dp,
> target_clock,
> - mode->hdisplay);
> + mode->hdisplay,
> + bigjoiner);
> }
> +
> + dsc = dsc_max_output_bpp && dsc_slice_count;
> }
>
> - if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) ||
> - target_clock > max_dotclk)
> + /* big joiner configuration needs DSC */
> + if (bigjoiner && !dsc) {
> + DRM_DEBUG_KMS("Link clock needs bigjoiner, but DSC or FEC not available\n");
> return MODE_CLOCK_HIGH;
> + }
>
> - if (mode->clock < 10000)
> - return MODE_CLOCK_LOW;
> -
> - if (mode->flags & DRM_MODE_FLAG_DBLCLK)
> - return MODE_H_ILLEGAL;
> + if (mode_rate > max_rate && !dsc) {
> + DRM_DEBUG_KMS("Cannot drive without DSC\n");
> + return MODE_CLOCK_HIGH;
> + }
>
> status = intel_dp_mode_valid_downstream(intel_connector,
> mode, target_clock);
> if (status != MODE_OK)
> return status;
>
> - return intel_mode_valid_max_plane_size(dev_priv, mode);
> + return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
> }
>
> u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
> @@ -2324,11 +2402,13 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> pipe_config->port_clock,
> pipe_config->lane_count,
> adjusted_mode->crtc_clock,
> - adjusted_mode->crtc_hdisplay);
> + adjusted_mode->crtc_hdisplay,
> + false);
> dsc_dp_slice_count =
> intel_dp_dsc_get_slice_count(intel_dp,
> adjusted_mode->crtc_clock,
> - adjusted_mode->crtc_hdisplay);
> + adjusted_mode->crtc_hdisplay,
> + false);
> if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
> drm_dbg_kms(&dev_priv->drm,
> "Compressed BPP/Slice Count not supported\n");
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index e948aacbd4ab..0fe2a3929ce6 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -714,7 +714,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
> return 0;
> }
>
> - *status = intel_mode_valid_max_plane_size(dev_priv, mode);
> + *status = intel_mode_valid_max_plane_size(dev_priv, mode, true);
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dsi.c b/drivers/gpu/drm/i915/display/intel_dsi.c
> index afa4e6817e8c..f453ceb8d149 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsi.c
> @@ -75,7 +75,7 @@ enum drm_mode_status intel_dsi_mode_valid(struct drm_connector *connector,
> return MODE_CLOCK_HIGH;
> }
>
> - return intel_mode_valid_max_plane_size(dev_priv, mode);
> + return intel_mode_valid_max_plane_size(dev_priv, mode, false);
> }
>
> struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index f90838bc74fb..82674a8853c6 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -2274,7 +2274,7 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
> if (status != MODE_OK)
> return status;
>
> - return intel_mode_valid_max_plane_size(dev_priv, mode);
> + return intel_mode_valid_max_plane_size(dev_priv, mode, false);
> }
>
> bool intel_hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
> --
> 2.19.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v10 05/11] drm/i915: Try to make bigjoiner work in atomic check
2020-10-08 21:45 ` [Intel-gfx] [PATCH v10 05/11] drm/i915: Try to make bigjoiner work in atomic check Manasi Navare
2020-10-11 11:18 ` kernel test robot
@ 2020-10-14 11:33 ` Ville Syrjälä
2020-10-14 19:09 ` Navare, Manasi
1 sibling, 1 reply; 50+ messages in thread
From: Ville Syrjälä @ 2020-10-14 11:33 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
On Thu, Oct 08, 2020 at 02:45:29PM -0700, Manasi Navare wrote:
> From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
>
> When the clock is higher than the dotclock, try with 2 pipes enabled.
> If we can enable 2, then we will go into big joiner mode, and steal
> the adjacent crtc.
>
> This only links the crtc's in software, no hardware or plane
> programming is done yet. Blobs are also copied from the master's
> crtc_state, so it doesn't depend at commit time on the other
> crtc_state.
>
> v4:
> * Fixes in intel_crtc_compute_config (Ville)
> v3:
> * Manual Rebase (Manasi)
> Changes since v1:
> - Rename pipe timings to transcoder timings, as they are now different.
> Changes since v2:
> - Rework bigjoiner checks; always disable slave when recalculating
> master. No need to have a separate bigjoiner pass any more.
> - Use pipe_mode instead of transcoder_mode, to clean up the code.
>
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_atomic.c | 9 +-
> drivers/gpu/drm/i915/display/intel_atomic.h | 3 +-
> drivers/gpu/drm/i915/display/intel_display.c | 202 ++++++++++++++++--
> .../drm/i915/display/intel_display_types.h | 9 +
> drivers/gpu/drm/i915/display/intel_dp.c | 22 +-
> 5 files changed, 211 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
> index 86be032bcf96..e243ce97b534 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> @@ -270,14 +270,15 @@ void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state)
> intel_crtc_put_color_blobs(crtc_state);
> }
>
> -void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state)
> +void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state,
> + const struct intel_crtc_state *from_crtc_state)
> {
> drm_property_replace_blob(&crtc_state->hw.degamma_lut,
> - crtc_state->uapi.degamma_lut);
> + from_crtc_state->uapi.degamma_lut);
> drm_property_replace_blob(&crtc_state->hw.gamma_lut,
> - crtc_state->uapi.gamma_lut);
> + from_crtc_state->uapi.gamma_lut);
> drm_property_replace_blob(&crtc_state->hw.ctm,
> - crtc_state->uapi.ctm);
> + from_crtc_state->uapi.ctm);
> }
This thing could easily be its own patch.
>
> /**
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h b/drivers/gpu/drm/i915/display/intel_atomic.h
> index 285de07011dc..62a3365ed5e6 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.h
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.h
> @@ -43,7 +43,8 @@ struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
> void intel_crtc_destroy_state(struct drm_crtc *crtc,
> struct drm_crtc_state *state);
> void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state);
> -void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state);
> +void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state,
> + const struct intel_crtc_state *from_crtc_state);
> struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
> void intel_atomic_state_free(struct drm_atomic_state *state);
> void intel_atomic_state_clear(struct drm_atomic_state *state);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index cc540c7b7dcd..37b56f4c2401 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -8130,9 +8130,24 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
> struct intel_crtc_state *pipe_config)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - const struct drm_display_mode *pipe_mode = &pipe_config->hw.pipe_mode;
> + struct drm_display_mode *pipe_mode = &pipe_config->hw.pipe_mode;
> int clock_limit = dev_priv->max_dotclk_freq;
>
> + *pipe_mode = pipe_config->hw.adjusted_mode;
> +
> + /* Adjust pipe_mode for bigjoiner, with half the horizontal mode */
> + if (pipe_config->bigjoiner) {
> + pipe_mode->crtc_clock /= 2;
> + pipe_mode->crtc_hdisplay /= 2;
> + pipe_mode->crtc_hblank_start /= 2;
> + pipe_mode->crtc_hblank_end /= 2;
> + pipe_mode->crtc_hsync_start /= 2;
> + pipe_mode->crtc_hsync_end /= 2;
> + pipe_mode->crtc_htotal /= 2;
> + pipe_mode->crtc_hskew /= 2;
> + pipe_config->pipe_src_w /= 2;
> + }
> +
> if (INTEL_GEN(dev_priv) < 4) {
> clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
>
> @@ -8193,7 +8208,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
> * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
> */
> if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
> - pipe_mode->crtc_hsync_start == pipe_mode->crtc_hdisplay)
> + pipe_mode->crtc_hsync_start == pipe_mode->crtc_hdisplay)
> return -EINVAL;
>
> intel_crtc_compute_pixel_rate(pipe_config);
> @@ -12559,7 +12574,7 @@ static bool encoders_cloneable(const struct intel_encoder *a,
> b->cloneable & (1 << a->type));
> }
>
> -static bool check_single_encoder_cloning(struct drm_atomic_state *state,
> +static bool check_single_encoder_cloning(struct intel_atomic_state *state,
> struct intel_crtc *crtc,
> struct intel_encoder *encoder)
> {
These things should be split out.
> @@ -12568,7 +12583,7 @@ static bool check_single_encoder_cloning(struct drm_atomic_state *state,
> struct drm_connector_state *connector_state;
> int i;
>
> - for_each_new_connector_in_state(state, connector, connector_state, i) {
> + for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
> if (connector_state->crtc != &crtc->base)
> continue;
>
> @@ -12808,6 +12823,7 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
>
> if (mode_changed && crtc_state->hw.enable &&
> dev_priv->display.crtc_compute_clock &&
> + !crtc_state->bigjoiner_slave &&
> !drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) {
> ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state);
> if (ret)
> @@ -13341,19 +13357,32 @@ static bool check_digital_port_conflicts(struct intel_atomic_state *state)
> }
>
> static void
> -intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_crtc_state *crtc_state)
> +intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state,
> + struct intel_crtc_state *crtc_state)
> {
> - intel_crtc_copy_color_blobs(crtc_state);
> + const struct intel_crtc_state *from_crtc_state = crtc_state;
> +
> + if (crtc_state->bigjoiner_slave) {
> + from_crtc_state = intel_atomic_get_new_crtc_state(state,
> + crtc_state->bigjoiner_linked_crtc);
> +
> + /* No need to copy state if the master state is unchanged */
> + if (!from_crtc_state)
> + return;
> + }
> +
> + intel_crtc_copy_color_blobs(crtc_state, from_crtc_state);
> }
>
> static void
> -intel_crtc_copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state)
> +intel_crtc_copy_uapi_to_hw_state(struct intel_atomic_state *state,
> + struct intel_crtc_state *crtc_state)
> {
> crtc_state->hw.enable = crtc_state->uapi.enable;
> crtc_state->hw.active = crtc_state->uapi.active;
> crtc_state->hw.mode = crtc_state->uapi.mode;
> crtc_state->hw.pipe_mode = crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
> - intel_crtc_copy_uapi_to_hw_state_nomodeset(crtc_state);
> + intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc_state);
> }
>
> static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
> @@ -13375,7 +13404,49 @@ static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state
> }
>
> static int
> -intel_crtc_prepare_cleared_state(struct intel_crtc_state *crtc_state)
> +copy_bigjoiner_crtc_state(struct intel_crtc_state *crtc_state,
> + const struct intel_crtc_state *from_crtc_state)
> +{
> + struct intel_crtc_state *saved_state;
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +
> + saved_state = kmemdup(from_crtc_state, sizeof(*saved_state), GFP_KERNEL);
> + if (!saved_state)
> + return -ENOMEM;
> +
> + saved_state->uapi = crtc_state->uapi;
> + saved_state->scaler_state = crtc_state->scaler_state;
> + saved_state->shared_dpll = crtc_state->shared_dpll;
> + saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
> + saved_state->crc_enabled = crtc_state->crc_enabled;
> +
> + intel_crtc_free_hw_state(crtc_state);
> + memcpy(crtc_state, saved_state, sizeof(*crtc_state));
> + kfree(saved_state);
> +
> + /* Re-init hw state */
> + memset(&crtc_state->hw, 0, sizeof(saved_state->hw));
> + crtc_state->hw.enable = from_crtc_state->hw.enable;
> + crtc_state->hw.active = from_crtc_state->hw.active;
> + crtc_state->hw.pipe_mode = from_crtc_state->hw.pipe_mode;
> + crtc_state->hw.adjusted_mode = from_crtc_state->hw.adjusted_mode;
> +
> + /* Some fixups */
> + crtc_state->uapi.mode_changed = from_crtc_state->uapi.mode_changed;
> + crtc_state->uapi.connectors_changed = from_crtc_state->uapi.connectors_changed;
> + crtc_state->uapi.active_changed = from_crtc_state->uapi.active_changed;
> + crtc_state->nv12_planes = crtc_state->c8_planes = crtc_state->update_planes = 0;
> + crtc_state->bigjoiner_linked_crtc = to_intel_crtc(from_crtc_state->uapi.crtc);
> + crtc_state->bigjoiner_slave = true;
> + crtc_state->cpu_transcoder = (enum transcoder)crtc->pipe;
> + crtc_state->has_audio = false;
> +
> + return 0;
> +}
> +
> +static int
> +intel_crtc_prepare_cleared_state(struct intel_atomic_state *state,
> + struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> @@ -13407,16 +13478,16 @@ intel_crtc_prepare_cleared_state(struct intel_crtc_state *crtc_state)
> memcpy(crtc_state, saved_state, sizeof(*crtc_state));
> kfree(saved_state);
>
> - intel_crtc_copy_uapi_to_hw_state(crtc_state);
> + intel_crtc_copy_uapi_to_hw_state(state, crtc_state);
>
> return 0;
> }
>
> static int
> -intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
> +intel_modeset_pipe_config(struct intel_atomic_state *state,
> + struct intel_crtc_state *pipe_config)
> {
> struct drm_crtc *crtc = pipe_config->uapi.crtc;
> - struct drm_atomic_state *state = pipe_config->uapi.state;
> struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
> struct drm_connector *connector;
> struct drm_connector_state *connector_state;
> @@ -13458,7 +13529,7 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
> &pipe_config->pipe_src_w,
> &pipe_config->pipe_src_h);
>
> - for_each_new_connector_in_state(state, connector, connector_state, i) {
> + for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
> struct intel_encoder *encoder =
> to_intel_encoder(connector_state->best_encoder);
>
> @@ -13496,7 +13567,7 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
> * adjust it according to limitations or connector properties, and also
> * a chance to reject the mode entirely.
> */
> - for_each_new_connector_in_state(state, connector, connector_state, i) {
> + for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
> struct intel_encoder *encoder =
> to_intel_encoder(connector_state->best_encoder);
>
> @@ -13548,9 +13619,6 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
> "hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
> base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
>
> - /* without bigjoiner, pipe_mode == adjusted_mode */
> - pipe_config->hw.pipe_mode = pipe_config->hw.adjusted_mode;
> -
> return 0;
> }
>
> @@ -14946,6 +15014,75 @@ static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
> return false;
> }
>
> +static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state,
> + struct intel_crtc *crtc,
> + struct intel_crtc_state *old_crtc_state,
> + struct intel_crtc_state *new_crtc_state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_crtc_state *slave_crtc_state, *master_crtc_state;
> + struct intel_crtc *slave, *master;
> +
> + /* slave being enabled, is master is still claiming this crtc? */
> + if (old_crtc_state->bigjoiner_slave) {
> + slave = crtc;
> + master = old_crtc_state->bigjoiner_linked_crtc;
> + master_crtc_state = intel_atomic_get_new_crtc_state(state, master);
> + if (!master_crtc_state || !needs_modeset(master_crtc_state))
> + goto claimed;
> + }
> +
> + if (!new_crtc_state->bigjoiner)
> + return 0;
> +
> + if (1 + crtc->pipe >= INTEL_NUM_PIPES(dev_priv)) {
> + DRM_DEBUG_KMS("[CRTC:%d:%s] Big joiner configuration requires "
> + "CRTC + 1 to be used, doesn't exist\n",
> + crtc->base.base.id, crtc->base.name);
> + return -EINVAL;
> + }
> +
> + slave = new_crtc_state->bigjoiner_linked_crtc =
> + intel_get_crtc_for_pipe(dev_priv, crtc->pipe + 1);
> + slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave);
> + master = crtc;
> + if (IS_ERR(slave_crtc_state))
> + return PTR_ERR(slave_crtc_state);
> +
> + /* master being enabled, slave was already configured? */
> + if (slave_crtc_state->uapi.enable)
> + goto claimed;
> +
> + DRM_DEBUG_KMS("[CRTC:%d:%s] Used as slave for big joiner\n",
> + slave->base.base.id, slave->base.name);
> +
> + return copy_bigjoiner_crtc_state(slave_crtc_state, new_crtc_state);
> +
> +claimed:
> + DRM_DEBUG_KMS("[CRTC:%d:%s] Slave is enabled as normal CRTC, but "
> + "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n",
> + slave->base.base.id, slave->base.name,
> + master->base.base.id, master->base.name);
> + return -EINVAL;
> +}
> +
> +static int kill_bigjoiner_slave(struct intel_atomic_state *state,
> + struct intel_crtc_state *master_crtc_state)
> +{
> + struct intel_crtc_state *slave_crtc_state =
> + intel_atomic_get_crtc_state(&state->base,
> + master_crtc_state->bigjoiner_linked_crtc);
> +
> + if (IS_ERR(slave_crtc_state))
> + return PTR_ERR(slave_crtc_state);
> +
> + slave_crtc_state->bigjoiner = master_crtc_state->bigjoiner = false;
> + slave_crtc_state->bigjoiner_slave = master_crtc_state->bigjoiner_slave = false;
> + slave_crtc_state->bigjoiner_linked_crtc = master_crtc_state->bigjoiner_linked_crtc = NULL;
> + intel_crtc_copy_uapi_to_hw_state(state, slave_crtc_state);
> + return 0;
> +}
> +
> /**
> * DOC: asynchronous flip implementation
> *
> @@ -15108,19 +15245,36 @@ static int intel_atomic_check(struct drm_device *dev,
> new_crtc_state, i) {
> if (!needs_modeset(new_crtc_state)) {
> /* Light copy */
> - intel_crtc_copy_uapi_to_hw_state_nomodeset(new_crtc_state);
> + intel_crtc_copy_uapi_to_hw_state_nomodeset(state, new_crtc_state);
> +
> + continue;
> + }
>
> + /* Kill old bigjoiner link, we may re-establish afterwards */
> + if (old_crtc_state->bigjoiner && !old_crtc_state->bigjoiner_slave) {
> + ret = kill_bigjoiner_slave(state, new_crtc_state);
> + if (ret)
> + goto fail;
> + }
> +
> + if (!new_crtc_state->uapi.enable) {
> + if (!new_crtc_state->bigjoiner_slave) {
> + intel_crtc_copy_uapi_to_hw_state(state, new_crtc_state);
> + any_ms = true;
> + }
> continue;
> }
>
> - ret = intel_crtc_prepare_cleared_state(new_crtc_state);
> + ret = intel_crtc_prepare_cleared_state(state, new_crtc_state);
> if (ret)
> goto fail;
>
> - if (!new_crtc_state->hw.enable)
> - continue;
> + ret = intel_modeset_pipe_config(state, new_crtc_state);
> + if (ret)
> + goto fail;
>
> - ret = intel_modeset_pipe_config(new_crtc_state);
> + ret = intel_atomic_check_bigjoiner(state, crtc, old_crtc_state,
> + new_crtc_state);
> if (ret)
> goto fail;
> }
> @@ -15458,7 +15612,9 @@ static void intel_update_crtc(struct intel_atomic_state *state,
>
> commit_pipe_config(state, crtc);
>
> - if (INTEL_GEN(dev_priv) >= 9)
> + if (new_crtc_state->bigjoiner) {
> + /* Not supported yet */
> + } else if (INTEL_GEN(dev_priv) >= 9)
> skl_update_planes_on_crtc(state, crtc);
> else
> i9xx_update_planes_on_crtc(state, crtc);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 513576217d14..c159f6a48bf0 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1066,6 +1066,15 @@ struct intel_crtc_state {
> /* enable pipe csc? */
> bool csc_enable;
>
> + /* enable pipe big joiner? */
> + bool bigjoiner;
> +
> + /* big joiner slave crtc? */
> + bool bigjoiner_slave;
> +
> + /* linked crtc for bigjoiner, either slave or master */
> + struct intel_crtc *bigjoiner_linked_crtc;
> +
> /* Display Stream compression state */
> struct {
> bool compression_enable;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index af2ff425e5d5..a627ad77dd3f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2386,6 +2386,15 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
> pipe_config->lane_count = limits->max_lane_count;
>
> + if (adjusted_mode->crtc_clock > intel_dp_max_dotclock(intel_dp, false)) {
> + if (adjusted_mode->crtc_clock > intel_dp_max_dotclock(intel_dp, true)) {
> + DRM_DEBUG_KMS("Clock rate too high for big joiner\n");
> + return -EINVAL;
> + }
> + pipe_config->bigjoiner = true;
> + DRM_DEBUG_KMS("Using bigjoiner configuration\n");
> + }
> +
> if (intel_dp_is_edp(intel_dp)) {
> pipe_config->dsc.compressed_bpp =
> min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
> @@ -2403,12 +2412,12 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> pipe_config->lane_count,
> adjusted_mode->crtc_clock,
> adjusted_mode->crtc_hdisplay,
> - false);
> + pipe_config->bigjoiner);
> dsc_dp_slice_count =
> intel_dp_dsc_get_slice_count(intel_dp,
> adjusted_mode->crtc_clock,
> adjusted_mode->crtc_hdisplay,
> - false);
> + pipe_config->bigjoiner);
> if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
> drm_dbg_kms(&dev_priv->drm,
> "Compressed BPP/Slice Count not supported\n");
> @@ -2424,14 +2433,15 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> * is greater than the maximum Cdclock and if slice count is even
> * then we need to use 2 VDSC instances.
> */
> - if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) {
> - if (pipe_config->dsc.slice_count > 1) {
> - pipe_config->dsc.dsc_split = true;
> - } else {
> + if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq ||
> + pipe_config->bigjoiner) {
> + if (pipe_config->dsc.slice_count < 2) {
> drm_dbg_kms(&dev_priv->drm,
> "Cannot split stream to use 2 VDSC instances\n");
> return -EINVAL;
> }
> +
> + pipe_config->dsc.dsc_split = true;
> }
>
> ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config);
> --
> 2.19.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v10,01/11] HAX to make DSC work on the icelake test system (rev2)
2020-10-08 21:45 [Intel-gfx] [PATCH v10 01/11] HAX to make DSC work on the icelake test system Manasi Navare
` (16 preceding siblings ...)
2020-10-13 19:45 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-10-14 14:32 ` Patchwork
17 siblings, 0 replies; 50+ messages in thread
From: Patchwork @ 2020-10-14 14:32 UTC (permalink / raw)
To: Navare, Manasi; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 14350 bytes --]
== Series Details ==
Series: series starting with [v10,01/11] HAX to make DSC work on the icelake test system (rev2)
URL : https://patchwork.freedesktop.org/series/82483/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9136_full -> Patchwork_18692_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_18692_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_gttfill@all:
- shard-glk: [PASS][1] -> [DMESG-WARN][2] ([i915#118] / [i915#95])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9136/shard-glk1/igt@gem_exec_gttfill@all.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18692/shard-glk4/igt@gem_exec_gttfill@all.html
* igt@gem_userptr_blits@unsync-unmap-cycles:
- shard-skl: [PASS][3] -> [TIMEOUT][4] ([i915#2424]) +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9136/shard-skl1/igt@gem_userptr_blits@unsync-unmap-cycles.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18692/shard-skl3/igt@gem_userptr_blits@unsync-unmap-cycles.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [PASS][5] -> [DMESG-WARN][6] ([i915#1436] / [i915#716])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9136/shard-skl2/igt@gen9_exec_parse@allowed-single.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18692/shard-skl3/igt@gen9_exec_parse@allowed-single.html
* igt@kms_cursor_edge_walk@pipe-b-256x256-left-edge:
- shard-skl: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) +11 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9136/shard-skl5/igt@kms_cursor_edge_walk@pipe-b-256x256-left-edge.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18692/shard-skl2/igt@kms_cursor_edge_walk@pipe-b-256x256-left-edge.html
* igt@kms_draw_crc@draw-method-rgb565-pwrite-ytiled:
- shard-skl: [PASS][9] -> [FAIL][10] ([i915#52] / [i915#54])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9136/shard-skl8/igt@kms_draw_crc@draw-method-rgb565-pwrite-ytiled.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18692/shard-skl1/igt@kms_draw_crc@draw-method-rgb565-pwrite-ytiled.html
* igt@kms_flip@2x-flip-vs-wf_vblank-interruptible@ab-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][11] -> [DMESG-WARN][12] ([i915#1982])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9136/shard-glk3/igt@kms_flip@2x-flip-vs-wf_vblank-interruptible@ab-hdmi-a1-hdmi-a2.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18692/shard-glk1/igt@kms_flip@2x-flip-vs-wf_vblank-interruptible@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-absolute-wf_vblank@b-edp1:
- shard-skl: [PASS][13] -> [FAIL][14] ([i915#2122])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9136/shard-skl2/igt@kms_flip@flip-vs-absolute-wf_vblank@b-edp1.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18692/shard-skl3/igt@kms_flip@flip-vs-absolute-wf_vblank@b-edp1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1:
- shard-apl: [PASS][15] -> [FAIL][16] ([i915#1635] / [i915#79])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9136/shard-apl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18692/shard-apl3/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-wc:
- shard-tglb: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) +2 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9136/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-wc.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18692/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-wc.html
* igt@kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence:
- shard-skl: [PASS][19] -> [FAIL][20] ([i915#53])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9136/shard-skl4/igt@kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18692/shard-skl7/igt@kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
- shard-skl: [PASS][21] -> [INCOMPLETE][22] ([i915#198])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9136/shard-skl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18692/shard-skl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [PASS][23] -> [FAIL][24] ([fdo#108145] / [i915#265]) +1 similar issue
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9136/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18692/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_psr@psr2_suspend:
- shard-iclb: [PASS][25] -> [SKIP][26] ([fdo#109441]) +2 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9136/shard-iclb2/igt@kms_psr@psr2_suspend.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18692/shard-iclb7/igt@kms_psr@psr2_suspend.html
* igt@kms_setmode@basic:
- shard-skl: [PASS][27] -> [FAIL][28] ([i915#31])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9136/shard-skl7/igt@kms_setmode@basic.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18692/shard-skl8/igt@kms_setmode@basic.html
#### Possible fixes ####
* igt@gem_exec_fence@parallel@rcs0:
- shard-tglb: [FAIL][29] ([i915#1893]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9136/shard-tglb6/igt@gem_exec_fence@parallel@rcs0.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18692/shard-tglb3/igt@gem_exec_fence@parallel@rcs0.html
* igt@gem_exec_reloc@basic-many-active@bcs0:
- shard-glk: [FAIL][31] ([i915#2389]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9136/shard-glk7/igt@gem_exec_reloc@basic-many-active@bcs0.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18692/shard-glk7/igt@gem_exec_reloc@basic-many-active@bcs0.html
* igt@gem_exec_whisper@basic-queues-all:
- shard-glk: [DMESG-WARN][33] ([i915#118] / [i915#95]) -> [PASS][34] +1 similar issue
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9136/shard-glk1/igt@gem_exec_whisper@basic-queues-all.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18692/shard-glk6/igt@gem_exec_whisper@basic-queues-all.html
* igt@kms_big_fb@linear-32bpp-rotate-180:
- shard-skl: [DMESG-WARN][35] ([i915#1982]) -> [PASS][36] +12 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9136/shard-skl5/igt@kms_big_fb@linear-32bpp-rotate-180.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18692/shard-skl2/igt@kms_big_fb@linear-32bpp-rotate-180.html
* igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1:
- shard-skl: [FAIL][37] ([i915#2122]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9136/shard-skl9/igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18692/shard-skl10/igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt:
- shard-kbl: [DMESG-WARN][39] ([i915#1982]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9136/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18692/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt:
- shard-tglb: [FAIL][41] -> [PASS][42] +2 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9136/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18692/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [FAIL][43] ([i915#1188]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9136/shard-skl3/igt@kms_hdr@bpc-switch.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18692/shard-skl3/igt@kms_hdr@bpc-switch.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-kbl: [DMESG-WARN][45] ([i915#165] / [i915#78]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9136/shard-kbl2/igt@kms_hdr@bpc-switch-dpms.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18692/shard-kbl1/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_pipe_crc_basic@read-crc-pipe-a:
- shard-skl: [FAIL][47] ([i915#53]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9136/shard-skl2/igt@kms_pipe_crc_basic@read-crc-pipe-a.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18692/shard-skl3/igt@kms_pipe_crc_basic@read-crc-pipe-a.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [FAIL][49] ([fdo#108145] / [i915#265]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9136/shard-skl2/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18692/shard-skl3/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_psr@psr2_cursor_plane_move:
- shard-iclb: [SKIP][51] ([fdo#109441]) -> [PASS][52] +1 similar issue
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9136/shard-iclb6/igt@kms_psr@psr2_cursor_plane_move.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18692/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html
* igt@kms_setmode@basic:
- shard-apl: [FAIL][53] ([i915#1635] / [i915#31]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9136/shard-apl8/igt@kms_setmode@basic.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18692/shard-apl1/igt@kms_setmode@basic.html
* igt@sysfs_heartbeat_interval@mixed@vcs1:
- shard-kbl: [INCOMPLETE][55] ([i915#1731]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9136/shard-kbl4/igt@sysfs_heartbeat_interval@mixed@vcs1.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18692/shard-kbl2/igt@sysfs_heartbeat_interval@mixed@vcs1.html
#### Warnings ####
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [FAIL][57] ([i915#1515]) -> [WARN][58] ([i915#1515])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9136/shard-iclb5/igt@i915_pm_rc6_residency@rc6-idle.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18692/shard-iclb8/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@kms_cursor_legacy@flip-vs-cursor-crc-legacy:
- shard-skl: [DMESG-FAIL][59] ([i915#1982]) -> [DMESG-WARN][60] ([i915#1982])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9136/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-crc-legacy.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18692/shard-skl9/igt@kms_cursor_legacy@flip-vs-cursor-crc-legacy.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1515]: https://gitlab.freedesktop.org/drm/intel/issues/1515
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
[i915#1731]: https://gitlab.freedesktop.org/drm/intel/issues/1731
[i915#1893]: https://gitlab.freedesktop.org/drm/intel/issues/1893
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389
[i915#2424]: https://gitlab.freedesktop.org/drm/intel/issues/2424
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2559]: https://gitlab.freedesktop.org/drm/intel/issues/2559
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52
[i915#53]: https://gitlab.freedesktop.org/drm/intel/issues/53
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#78]: https://gitlab.freedesktop.org/drm/intel/issues/78
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (12 -> 11)
------------------------------
Missing (1): pig-snb-2600
Build changes
-------------
* Linux: CI_DRM_9136 -> Patchwork_18692
CI-20190529: 20190529
CI_DRM_9136: 29eb1a8ba2cc0d14d3cae7213f9cdaaa13f3dd99 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5813: d4e6dd955a1dad02271aa41c9389f5097ee17765 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18692: 1f504d7510c72ba8fadb0948e84cd415b0642c23 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18692/index.html
[-- Attachment #1.2: Type: text/html, Size: 16628 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v10 04/11] drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.
2020-10-14 11:26 ` Ville Syrjälä
@ 2020-10-14 19:04 ` Navare, Manasi
2020-10-15 11:52 ` Ville Syrjälä
0 siblings, 1 reply; 50+ messages in thread
From: Navare, Manasi @ 2020-10-14 19:04 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Wed, Oct 14, 2020 at 02:26:34PM +0300, Ville Syrjälä wrote:
> On Thu, Oct 08, 2020 at 02:45:28PM -0700, Manasi Navare wrote:
> > From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> >
> > Small changes to intel_dp_mode_valid(), allow listing modes that
> > can only be supported in the bigjoiner configuration, which is
> > not supported yet.
> >
> > eDP does not support bigjoiner, so do not expose bigjoiner only
> > modes on the eDP port.
> >
> > v7:
> > * Add can_bigjoiner() helper (Ville)
> > * Pass bigjoiner to plane_size validation (Ville)
> > v6:
> > * Rebase after dp_downstream mode valid changes (Manasi)
> > v5:
> > * Increase max plane width to support 8K with bigjoiner (Maarten)
> > v4:
> > * Rebase (Manasi)
> >
> > Changes since v1:
> > - Disallow bigjoiner on eDP.
> > Changes since v2:
> > - Rename intel_dp_downstream_max_dotclock to intel_dp_max_dotclock,
> > and split off the downstream and source checking to its own function.
> > (Ville)
> > v3:
> > * Rebase (Manasi)
> >
> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 5 +-
> > drivers/gpu/drm/i915/display/intel_display.h | 3 +-
> > drivers/gpu/drm/i915/display/intel_dp.c | 126 +++++++++++++++----
> > drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_dsi.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
> > 6 files changed, 111 insertions(+), 29 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index 723766b1eae3..cc540c7b7dcd 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -17642,7 +17642,8 @@ intel_mode_valid(struct drm_device *dev,
> >
> > enum drm_mode_status
> > intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
> > - const struct drm_display_mode *mode)
> > + const struct drm_display_mode *mode,
> > + bool bigjoiner)
> > {
> > int plane_width_max, plane_height_max;
> >
> > @@ -17659,7 +17660,7 @@ intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
> > * too big for that.
> > */
> > if (INTEL_GEN(dev_priv) >= 11) {
> > - plane_width_max = 5120;
> > + plane_width_max = 5120 << bigjoiner;
> > plane_height_max = 4320;
> > } else {
> > plane_width_max = 5120;
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> > index d10b7c8cde3f..3d860a9da8fe 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display.h
> > @@ -496,7 +496,8 @@ u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
> > bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
> > enum drm_mode_status
> > intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
> > - const struct drm_display_mode *mode);
> > + const struct drm_display_mode *mode,
> > + bool bigjoiner);
> > enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
> > bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 8a522edd7386..af2ff425e5d5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -247,6 +247,29 @@ intel_dp_max_data_rate(int max_link_clock, int max_lanes)
> > return max_link_clock * max_lanes;
> > }
> >
> > +static int source_max_dotclock(struct intel_dp *intel_dp, bool allow_bigjoiner)
> > +{
> > + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> > + struct intel_encoder *encoder = &intel_dig_port->base;
> > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > +
> > + if (allow_bigjoiner && INTEL_GEN(dev_priv) >= 11 && !intel_dp_is_edp(intel_dp))
> > + return 2 * dev_priv->max_dotclk_freq;
> > +
> > + return dev_priv->max_dotclk_freq;
> > +}
> > +
> > +static int
> > +intel_dp_max_dotclock(struct intel_dp *intel_dp, bool allow_bigjoiner)
> > +{
> > + int max_dotclk = source_max_dotclock(intel_dp, allow_bigjoiner);
> > +
> > + if (intel_dp->dfp.max_dotclock)
>
> No. dfp checks should stay where they are.
I am using dfp.max_dotclock because we populate that with drm_dp_downstream_max_dotclock()
should that be used here directly from drm_dp_downstream_max_dotclock instead of using dfp.maxdotclock ?
>
> > + return min(max_dotclk, intel_dp->dfp.max_dotclock);
> > +
> > + return max_dotclk;
> > +}
> > +
> > static int cnl_max_source_rate(struct intel_dp *intel_dp)
> > {
> > struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> > @@ -512,7 +535,8 @@ small_joiner_ram_size_bits(struct drm_i915_private *i915)
> >
> > static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
> > u32 link_clock, u32 lane_count,
> > - u32 mode_clock, u32 mode_hdisplay)
> > + u32 mode_clock, u32 mode_hdisplay,
> > + bool bigjoiner)
> > {
> > u32 bits_per_pixel, max_bpp_small_joiner_ram;
> > int i;
> > @@ -530,6 +554,10 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
> > /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
> > max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
> > mode_hdisplay;
> > +
> > + if (bigjoiner)
> > + max_bpp_small_joiner_ram *= 2;
> > +
> > drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n",
> > max_bpp_small_joiner_ram);
> >
> > @@ -539,6 +567,15 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
> > */
> > bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
> >
> > + if (bigjoiner) {
> > + u32 max_bpp_bigjoiner =
> > + i915->max_cdclk_freq * 48 /
> > + intel_dp_mode_to_fec_clock(mode_clock);
> > +
> > + DRM_DEBUG_KMS("Max big joiner bpp: %u\n", max_bpp_bigjoiner);
> > + bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
> > + }
> > +
> > /* Error out if the max bpp is less than smallest allowed valid bpp */
> > if (bits_per_pixel < valid_dsc_bpp[0]) {
> > drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
> > @@ -561,7 +598,8 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
> > }
> >
> > static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
> > - int mode_clock, int mode_hdisplay)
> > + int mode_clock, int mode_hdisplay,
> > + bool bigjoiner)
> > {
> > struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> > u8 min_slice_count, i;
> > @@ -588,12 +626,20 @@ static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
> >
> > /* Find the closest match to the valid slice count values */
> > for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
> > - if (valid_dsc_slicecount[i] >
> > - drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
> > - false))
> > + u8 test_slice_count = bigjoiner ?
> > + 2 * valid_dsc_slicecount[i] :
> > + valid_dsc_slicecount[i];
> > +
> > + if (test_slice_count >
> > + drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, false))
> > break;
> > - if (min_slice_count <= valid_dsc_slicecount[i])
> > - return valid_dsc_slicecount[i];
> > +
> > + /* big joiner needs small joiner to be enabled */
> > + if (bigjoiner && test_slice_count < 4)
> > + continue;
> > +
> > + if (min_slice_count <= test_slice_count)
> > + return test_slice_count;
> > }
> >
> > drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
> > @@ -676,10 +722,6 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector,
> > const struct drm_display_info *info = &connector->base.display_info;
> > int tmds_clock;
> >
> > - if (intel_dp->dfp.max_dotclock &&
> > - target_clock > intel_dp->dfp.max_dotclock)
> > - return MODE_CLOCK_HIGH;
> > -
> > /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
> > tmds_clock = target_clock;
> > if (drm_mode_is_420_only(info, mode))
> > @@ -695,6 +737,16 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector,
> > return MODE_OK;
> > }
> >
> > +static bool intel_dp_can_bigjoiner(struct drm_connector *connector)
> > +{
> > + struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
> > + struct drm_i915_private *dev_priv = to_i915(connector->dev);
> > +
> > + return INTEL_GEN(dev_priv) >= 12 ||
> > + (INTEL_GEN(dev_priv) == 11 &&
> > + encoder->port != PORT_A);
> > +}
> > +
> > static enum drm_mode_status
> > intel_dp_mode_valid(struct drm_connector *connector,
> > struct drm_display_mode *mode)
> > @@ -709,10 +761,16 @@ intel_dp_mode_valid(struct drm_connector *connector,
> > u16 dsc_max_output_bpp = 0;
> > u8 dsc_slice_count = 0;
> > enum drm_mode_status status;
> > + bool dsc = false, bigjoiner = false;
> >
> > if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
> > return MODE_NO_DBLESCAN;
> >
> > + if (mode->flags & DRM_MODE_FLAG_DBLCLK)
> > + return MODE_H_ILLEGAL;
>
> This random shuffling of things makes for a messy diff.
Yea this is just a shuffle of this condition from bottom of this function to above
but will try to add this in a separate patch.
>
> > +
> > + max_dotclk = intel_dp_max_dotclock(intel_dp, false);
> > +
> > if (intel_dp_is_edp(intel_dp) && fixed_mode) {
> > if (mode->hdisplay > fixed_mode->hdisplay)
> > return MODE_PANEL;
> > @@ -723,6 +781,21 @@ intel_dp_mode_valid(struct drm_connector *connector,
> > target_clock = fixed_mode->clock;
> > }
> >
> > + if (mode->clock < 10000)
> > + return MODE_CLOCK_LOW;
>
> Another random shuffling. Hmm. What on earth is this even and why is it
> checking mode->clock and not target_clock?
This was always there in intel_dp_mode_valid() just been moved up at the top
will try to add this shuffling in a separate patch.
everything else looks good?
Manasi
>
> Anywyas, plese split out the unrelated stuff so we at least have a
> chance of getting a legible diff.
>
> > +
> > + if (target_clock > max_dotclk) {
> > + if (intel_dp_is_edp(intel_dp))
> > + return MODE_CLOCK_HIGH;
> > +
> > + max_dotclk = intel_dp_max_dotclock(intel_dp, true);
> > +
> > + if (target_clock > max_dotclk)
> > + return MODE_CLOCK_HIGH;
> > +
> > + bigjoiner = intel_dp_can_bigjoiner(connector);
> > + }
> > +
> > max_link_clock = intel_dp_max_link_rate(intel_dp);
> > max_lanes = intel_dp_max_lane_count(intel_dp);
> >
> > @@ -751,30 +824,35 @@ intel_dp_mode_valid(struct drm_connector *connector,
> > max_link_clock,
> > max_lanes,
> > target_clock,
> > - mode->hdisplay) >> 4;
> > + mode->hdisplay,
> > + bigjoiner) >> 4;
> > dsc_slice_count =
> > intel_dp_dsc_get_slice_count(intel_dp,
> > target_clock,
> > - mode->hdisplay);
> > + mode->hdisplay,
> > + bigjoiner);
> > }
> > +
> > + dsc = dsc_max_output_bpp && dsc_slice_count;
> > }
> >
> > - if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) ||
> > - target_clock > max_dotclk)
> > + /* big joiner configuration needs DSC */
> > + if (bigjoiner && !dsc) {
> > + DRM_DEBUG_KMS("Link clock needs bigjoiner, but DSC or FEC not available\n");
> > return MODE_CLOCK_HIGH;
> > + }
> >
> > - if (mode->clock < 10000)
> > - return MODE_CLOCK_LOW;
> > -
> > - if (mode->flags & DRM_MODE_FLAG_DBLCLK)
> > - return MODE_H_ILLEGAL;
> > + if (mode_rate > max_rate && !dsc) {
> > + DRM_DEBUG_KMS("Cannot drive without DSC\n");
> > + return MODE_CLOCK_HIGH;
> > + }
> >
> > status = intel_dp_mode_valid_downstream(intel_connector,
> > mode, target_clock);
> > if (status != MODE_OK)
> > return status;
> >
> > - return intel_mode_valid_max_plane_size(dev_priv, mode);
> > + return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
> > }
> >
> > u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
> > @@ -2324,11 +2402,13 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> > pipe_config->port_clock,
> > pipe_config->lane_count,
> > adjusted_mode->crtc_clock,
> > - adjusted_mode->crtc_hdisplay);
> > + adjusted_mode->crtc_hdisplay,
> > + false);
> > dsc_dp_slice_count =
> > intel_dp_dsc_get_slice_count(intel_dp,
> > adjusted_mode->crtc_clock,
> > - adjusted_mode->crtc_hdisplay);
> > + adjusted_mode->crtc_hdisplay,
> > + false);
> > if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
> > drm_dbg_kms(&dev_priv->drm,
> > "Compressed BPP/Slice Count not supported\n");
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > index e948aacbd4ab..0fe2a3929ce6 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > @@ -714,7 +714,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
> > return 0;
> > }
> >
> > - *status = intel_mode_valid_max_plane_size(dev_priv, mode);
> > + *status = intel_mode_valid_max_plane_size(dev_priv, mode, true);
> > return 0;
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dsi.c b/drivers/gpu/drm/i915/display/intel_dsi.c
> > index afa4e6817e8c..f453ceb8d149 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dsi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dsi.c
> > @@ -75,7 +75,7 @@ enum drm_mode_status intel_dsi_mode_valid(struct drm_connector *connector,
> > return MODE_CLOCK_HIGH;
> > }
> >
> > - return intel_mode_valid_max_plane_size(dev_priv, mode);
> > + return intel_mode_valid_max_plane_size(dev_priv, mode, false);
> > }
> >
> > struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > index f90838bc74fb..82674a8853c6 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > @@ -2274,7 +2274,7 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
> > if (status != MODE_OK)
> > return status;
> >
> > - return intel_mode_valid_max_plane_size(dev_priv, mode);
> > + return intel_mode_valid_max_plane_size(dev_priv, mode, false);
> > }
> >
> > bool intel_hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
> > --
> > 2.19.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v10 05/11] drm/i915: Try to make bigjoiner work in atomic check
2020-10-14 11:33 ` Ville Syrjälä
@ 2020-10-14 19:09 ` Navare, Manasi
0 siblings, 0 replies; 50+ messages in thread
From: Navare, Manasi @ 2020-10-14 19:09 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Wed, Oct 14, 2020 at 02:33:15PM +0300, Ville Syrjälä wrote:
> On Thu, Oct 08, 2020 at 02:45:29PM -0700, Manasi Navare wrote:
> > From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> >
> > When the clock is higher than the dotclock, try with 2 pipes enabled.
> > If we can enable 2, then we will go into big joiner mode, and steal
> > the adjacent crtc.
> >
> > This only links the crtc's in software, no hardware or plane
> > programming is done yet. Blobs are also copied from the master's
> > crtc_state, so it doesn't depend at commit time on the other
> > crtc_state.
> >
> > v4:
> > * Fixes in intel_crtc_compute_config (Ville)
> > v3:
> > * Manual Rebase (Manasi)
> > Changes since v1:
> > - Rename pipe timings to transcoder timings, as they are now different.
> > Changes since v2:
> > - Rework bigjoiner checks; always disable slave when recalculating
> > master. No need to have a separate bigjoiner pass any more.
> > - Use pipe_mode instead of transcoder_mode, to clean up the code.
> >
> > Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_atomic.c | 9 +-
> > drivers/gpu/drm/i915/display/intel_atomic.h | 3 +-
> > drivers/gpu/drm/i915/display/intel_display.c | 202 ++++++++++++++++--
> > .../drm/i915/display/intel_display_types.h | 9 +
> > drivers/gpu/drm/i915/display/intel_dp.c | 22 +-
> > 5 files changed, 211 insertions(+), 34 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
> > index 86be032bcf96..e243ce97b534 100644
> > --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> > +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> > @@ -270,14 +270,15 @@ void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state)
> > intel_crtc_put_color_blobs(crtc_state);
> > }
> >
> > -void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state)
> > +void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state,
> > + const struct intel_crtc_state *from_crtc_state)
> > {
> > drm_property_replace_blob(&crtc_state->hw.degamma_lut,
> > - crtc_state->uapi.degamma_lut);
> > + from_crtc_state->uapi.degamma_lut);
> > drm_property_replace_blob(&crtc_state->hw.gamma_lut,
> > - crtc_state->uapi.gamma_lut);
> > + from_crtc_state->uapi.gamma_lut);
> > drm_property_replace_blob(&crtc_state->hw.ctm,
> > - crtc_state->uapi.ctm);
> > + from_crtc_state->uapi.ctm);
> > }
>
> This thing could easily be its own patch.
Yes probably have a separate patch that adds from_crtc_state, will do that
>
> >
> > /**
> > diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h b/drivers/gpu/drm/i915/display/intel_atomic.h
> > index 285de07011dc..62a3365ed5e6 100644
> > --- a/drivers/gpu/drm/i915/display/intel_atomic.h
> > +++ b/drivers/gpu/drm/i915/display/intel_atomic.h
> > @@ -43,7 +43,8 @@ struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
> > void intel_crtc_destroy_state(struct drm_crtc *crtc,
> > struct drm_crtc_state *state);
> > void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state);
> > -void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state);
> > +void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state,
> > + const struct intel_crtc_state *from_crtc_state);
> > struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
> > void intel_atomic_state_free(struct drm_atomic_state *state);
> > void intel_atomic_state_clear(struct drm_atomic_state *state);
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index cc540c7b7dcd..37b56f4c2401 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -8130,9 +8130,24 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
> > struct intel_crtc_state *pipe_config)
> > {
> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > - const struct drm_display_mode *pipe_mode = &pipe_config->hw.pipe_mode;
> > + struct drm_display_mode *pipe_mode = &pipe_config->hw.pipe_mode;
> > int clock_limit = dev_priv->max_dotclk_freq;
> >
> > + *pipe_mode = pipe_config->hw.adjusted_mode;
> > +
> > + /* Adjust pipe_mode for bigjoiner, with half the horizontal mode */
> > + if (pipe_config->bigjoiner) {
> > + pipe_mode->crtc_clock /= 2;
> > + pipe_mode->crtc_hdisplay /= 2;
> > + pipe_mode->crtc_hblank_start /= 2;
> > + pipe_mode->crtc_hblank_end /= 2;
> > + pipe_mode->crtc_hsync_start /= 2;
> > + pipe_mode->crtc_hsync_end /= 2;
> > + pipe_mode->crtc_htotal /= 2;
> > + pipe_mode->crtc_hskew /= 2;
> > + pipe_config->pipe_src_w /= 2;
> > + }
> > +
> > if (INTEL_GEN(dev_priv) < 4) {
> > clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
> >
> > @@ -8193,7 +8208,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
> > * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
> > */
> > if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
> > - pipe_mode->crtc_hsync_start == pipe_mode->crtc_hdisplay)
> > + pipe_mode->crtc_hsync_start == pipe_mode->crtc_hdisplay)
> > return -EINVAL;
> >
> > intel_crtc_compute_pixel_rate(pipe_config);
> > @@ -12559,7 +12574,7 @@ static bool encoders_cloneable(const struct intel_encoder *a,
> > b->cloneable & (1 << a->type));
> > }
> >
> > -static bool check_single_encoder_cloning(struct drm_atomic_state *state,
> > +static bool check_single_encoder_cloning(struct intel_atomic_state *state,
> > struct intel_crtc *crtc,
> > struct intel_encoder *encoder)
> > {
>
> These things should be split out.
So split out changing drm_atomic_state to intel_atomic_state in a separate patch?
Okay will do.. and everything else in this patch?
Manasi
>
> > @@ -12568,7 +12583,7 @@ static bool check_single_encoder_cloning(struct drm_atomic_state *state,
> > struct drm_connector_state *connector_state;
> > int i;
> >
> > - for_each_new_connector_in_state(state, connector, connector_state, i) {
> > + for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
> > if (connector_state->crtc != &crtc->base)
> > continue;
> >
> > @@ -12808,6 +12823,7 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
> >
> > if (mode_changed && crtc_state->hw.enable &&
> > dev_priv->display.crtc_compute_clock &&
> > + !crtc_state->bigjoiner_slave &&
> > !drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) {
> > ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state);
> > if (ret)
> > @@ -13341,19 +13357,32 @@ static bool check_digital_port_conflicts(struct intel_atomic_state *state)
> > }
> >
> > static void
> > -intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_crtc_state *crtc_state)
> > +intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state,
> > + struct intel_crtc_state *crtc_state)
> > {
> > - intel_crtc_copy_color_blobs(crtc_state);
> > + const struct intel_crtc_state *from_crtc_state = crtc_state;
> > +
> > + if (crtc_state->bigjoiner_slave) {
> > + from_crtc_state = intel_atomic_get_new_crtc_state(state,
> > + crtc_state->bigjoiner_linked_crtc);
> > +
> > + /* No need to copy state if the master state is unchanged */
> > + if (!from_crtc_state)
> > + return;
> > + }
> > +
> > + intel_crtc_copy_color_blobs(crtc_state, from_crtc_state);
> > }
> >
> > static void
> > -intel_crtc_copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state)
> > +intel_crtc_copy_uapi_to_hw_state(struct intel_atomic_state *state,
> > + struct intel_crtc_state *crtc_state)
> > {
> > crtc_state->hw.enable = crtc_state->uapi.enable;
> > crtc_state->hw.active = crtc_state->uapi.active;
> > crtc_state->hw.mode = crtc_state->uapi.mode;
> > crtc_state->hw.pipe_mode = crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
> > - intel_crtc_copy_uapi_to_hw_state_nomodeset(crtc_state);
> > + intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc_state);
> > }
> >
> > static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
> > @@ -13375,7 +13404,49 @@ static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state
> > }
> >
> > static int
> > -intel_crtc_prepare_cleared_state(struct intel_crtc_state *crtc_state)
> > +copy_bigjoiner_crtc_state(struct intel_crtc_state *crtc_state,
> > + const struct intel_crtc_state *from_crtc_state)
> > +{
> > + struct intel_crtc_state *saved_state;
> > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > +
> > + saved_state = kmemdup(from_crtc_state, sizeof(*saved_state), GFP_KERNEL);
> > + if (!saved_state)
> > + return -ENOMEM;
> > +
> > + saved_state->uapi = crtc_state->uapi;
> > + saved_state->scaler_state = crtc_state->scaler_state;
> > + saved_state->shared_dpll = crtc_state->shared_dpll;
> > + saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
> > + saved_state->crc_enabled = crtc_state->crc_enabled;
> > +
> > + intel_crtc_free_hw_state(crtc_state);
> > + memcpy(crtc_state, saved_state, sizeof(*crtc_state));
> > + kfree(saved_state);
> > +
> > + /* Re-init hw state */
> > + memset(&crtc_state->hw, 0, sizeof(saved_state->hw));
> > + crtc_state->hw.enable = from_crtc_state->hw.enable;
> > + crtc_state->hw.active = from_crtc_state->hw.active;
> > + crtc_state->hw.pipe_mode = from_crtc_state->hw.pipe_mode;
> > + crtc_state->hw.adjusted_mode = from_crtc_state->hw.adjusted_mode;
> > +
> > + /* Some fixups */
> > + crtc_state->uapi.mode_changed = from_crtc_state->uapi.mode_changed;
> > + crtc_state->uapi.connectors_changed = from_crtc_state->uapi.connectors_changed;
> > + crtc_state->uapi.active_changed = from_crtc_state->uapi.active_changed;
> > + crtc_state->nv12_planes = crtc_state->c8_planes = crtc_state->update_planes = 0;
> > + crtc_state->bigjoiner_linked_crtc = to_intel_crtc(from_crtc_state->uapi.crtc);
> > + crtc_state->bigjoiner_slave = true;
> > + crtc_state->cpu_transcoder = (enum transcoder)crtc->pipe;
> > + crtc_state->has_audio = false;
> > +
> > + return 0;
> > +}
> > +
> > +static int
> > +intel_crtc_prepare_cleared_state(struct intel_atomic_state *state,
> > + struct intel_crtc_state *crtc_state)
> > {
> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > @@ -13407,16 +13478,16 @@ intel_crtc_prepare_cleared_state(struct intel_crtc_state *crtc_state)
> > memcpy(crtc_state, saved_state, sizeof(*crtc_state));
> > kfree(saved_state);
> >
> > - intel_crtc_copy_uapi_to_hw_state(crtc_state);
> > + intel_crtc_copy_uapi_to_hw_state(state, crtc_state);
> >
> > return 0;
> > }
> >
> > static int
> > -intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
> > +intel_modeset_pipe_config(struct intel_atomic_state *state,
> > + struct intel_crtc_state *pipe_config)
> > {
> > struct drm_crtc *crtc = pipe_config->uapi.crtc;
> > - struct drm_atomic_state *state = pipe_config->uapi.state;
> > struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
> > struct drm_connector *connector;
> > struct drm_connector_state *connector_state;
> > @@ -13458,7 +13529,7 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
> > &pipe_config->pipe_src_w,
> > &pipe_config->pipe_src_h);
> >
> > - for_each_new_connector_in_state(state, connector, connector_state, i) {
> > + for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
> > struct intel_encoder *encoder =
> > to_intel_encoder(connector_state->best_encoder);
> >
> > @@ -13496,7 +13567,7 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
> > * adjust it according to limitations or connector properties, and also
> > * a chance to reject the mode entirely.
> > */
> > - for_each_new_connector_in_state(state, connector, connector_state, i) {
> > + for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
> > struct intel_encoder *encoder =
> > to_intel_encoder(connector_state->best_encoder);
> >
> > @@ -13548,9 +13619,6 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
> > "hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
> > base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
> >
> > - /* without bigjoiner, pipe_mode == adjusted_mode */
> > - pipe_config->hw.pipe_mode = pipe_config->hw.adjusted_mode;
> > -
> > return 0;
> > }
> >
> > @@ -14946,6 +15014,75 @@ static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
> > return false;
> > }
> >
> > +static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state,
> > + struct intel_crtc *crtc,
> > + struct intel_crtc_state *old_crtc_state,
> > + struct intel_crtc_state *new_crtc_state)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > + struct intel_crtc_state *slave_crtc_state, *master_crtc_state;
> > + struct intel_crtc *slave, *master;
> > +
> > + /* slave being enabled, is master is still claiming this crtc? */
> > + if (old_crtc_state->bigjoiner_slave) {
> > + slave = crtc;
> > + master = old_crtc_state->bigjoiner_linked_crtc;
> > + master_crtc_state = intel_atomic_get_new_crtc_state(state, master);
> > + if (!master_crtc_state || !needs_modeset(master_crtc_state))
> > + goto claimed;
> > + }
> > +
> > + if (!new_crtc_state->bigjoiner)
> > + return 0;
> > +
> > + if (1 + crtc->pipe >= INTEL_NUM_PIPES(dev_priv)) {
> > + DRM_DEBUG_KMS("[CRTC:%d:%s] Big joiner configuration requires "
> > + "CRTC + 1 to be used, doesn't exist\n",
> > + crtc->base.base.id, crtc->base.name);
> > + return -EINVAL;
> > + }
> > +
> > + slave = new_crtc_state->bigjoiner_linked_crtc =
> > + intel_get_crtc_for_pipe(dev_priv, crtc->pipe + 1);
> > + slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave);
> > + master = crtc;
> > + if (IS_ERR(slave_crtc_state))
> > + return PTR_ERR(slave_crtc_state);
> > +
> > + /* master being enabled, slave was already configured? */
> > + if (slave_crtc_state->uapi.enable)
> > + goto claimed;
> > +
> > + DRM_DEBUG_KMS("[CRTC:%d:%s] Used as slave for big joiner\n",
> > + slave->base.base.id, slave->base.name);
> > +
> > + return copy_bigjoiner_crtc_state(slave_crtc_state, new_crtc_state);
> > +
> > +claimed:
> > + DRM_DEBUG_KMS("[CRTC:%d:%s] Slave is enabled as normal CRTC, but "
> > + "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n",
> > + slave->base.base.id, slave->base.name,
> > + master->base.base.id, master->base.name);
> > + return -EINVAL;
> > +}
> > +
> > +static int kill_bigjoiner_slave(struct intel_atomic_state *state,
> > + struct intel_crtc_state *master_crtc_state)
> > +{
> > + struct intel_crtc_state *slave_crtc_state =
> > + intel_atomic_get_crtc_state(&state->base,
> > + master_crtc_state->bigjoiner_linked_crtc);
> > +
> > + if (IS_ERR(slave_crtc_state))
> > + return PTR_ERR(slave_crtc_state);
> > +
> > + slave_crtc_state->bigjoiner = master_crtc_state->bigjoiner = false;
> > + slave_crtc_state->bigjoiner_slave = master_crtc_state->bigjoiner_slave = false;
> > + slave_crtc_state->bigjoiner_linked_crtc = master_crtc_state->bigjoiner_linked_crtc = NULL;
> > + intel_crtc_copy_uapi_to_hw_state(state, slave_crtc_state);
> > + return 0;
> > +}
> > +
> > /**
> > * DOC: asynchronous flip implementation
> > *
> > @@ -15108,19 +15245,36 @@ static int intel_atomic_check(struct drm_device *dev,
> > new_crtc_state, i) {
> > if (!needs_modeset(new_crtc_state)) {
> > /* Light copy */
> > - intel_crtc_copy_uapi_to_hw_state_nomodeset(new_crtc_state);
> > + intel_crtc_copy_uapi_to_hw_state_nomodeset(state, new_crtc_state);
> > +
> > + continue;
> > + }
> >
> > + /* Kill old bigjoiner link, we may re-establish afterwards */
> > + if (old_crtc_state->bigjoiner && !old_crtc_state->bigjoiner_slave) {
> > + ret = kill_bigjoiner_slave(state, new_crtc_state);
> > + if (ret)
> > + goto fail;
> > + }
> > +
> > + if (!new_crtc_state->uapi.enable) {
> > + if (!new_crtc_state->bigjoiner_slave) {
> > + intel_crtc_copy_uapi_to_hw_state(state, new_crtc_state);
> > + any_ms = true;
> > + }
> > continue;
> > }
> >
> > - ret = intel_crtc_prepare_cleared_state(new_crtc_state);
> > + ret = intel_crtc_prepare_cleared_state(state, new_crtc_state);
> > if (ret)
> > goto fail;
> >
> > - if (!new_crtc_state->hw.enable)
> > - continue;
> > + ret = intel_modeset_pipe_config(state, new_crtc_state);
> > + if (ret)
> > + goto fail;
> >
> > - ret = intel_modeset_pipe_config(new_crtc_state);
> > + ret = intel_atomic_check_bigjoiner(state, crtc, old_crtc_state,
> > + new_crtc_state);
> > if (ret)
> > goto fail;
> > }
> > @@ -15458,7 +15612,9 @@ static void intel_update_crtc(struct intel_atomic_state *state,
> >
> > commit_pipe_config(state, crtc);
> >
> > - if (INTEL_GEN(dev_priv) >= 9)
> > + if (new_crtc_state->bigjoiner) {
> > + /* Not supported yet */
> > + } else if (INTEL_GEN(dev_priv) >= 9)
> > skl_update_planes_on_crtc(state, crtc);
> > else
> > i9xx_update_planes_on_crtc(state, crtc);
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 513576217d14..c159f6a48bf0 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1066,6 +1066,15 @@ struct intel_crtc_state {
> > /* enable pipe csc? */
> > bool csc_enable;
> >
> > + /* enable pipe big joiner? */
> > + bool bigjoiner;
> > +
> > + /* big joiner slave crtc? */
> > + bool bigjoiner_slave;
> > +
> > + /* linked crtc for bigjoiner, either slave or master */
> > + struct intel_crtc *bigjoiner_linked_crtc;
> > +
> > /* Display Stream compression state */
> > struct {
> > bool compression_enable;
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > index af2ff425e5d5..a627ad77dd3f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -2386,6 +2386,15 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> > pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
> > pipe_config->lane_count = limits->max_lane_count;
> >
> > + if (adjusted_mode->crtc_clock > intel_dp_max_dotclock(intel_dp, false)) {
> > + if (adjusted_mode->crtc_clock > intel_dp_max_dotclock(intel_dp, true)) {
> > + DRM_DEBUG_KMS("Clock rate too high for big joiner\n");
> > + return -EINVAL;
> > + }
> > + pipe_config->bigjoiner = true;
> > + DRM_DEBUG_KMS("Using bigjoiner configuration\n");
> > + }
> > +
> > if (intel_dp_is_edp(intel_dp)) {
> > pipe_config->dsc.compressed_bpp =
> > min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
> > @@ -2403,12 +2412,12 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> > pipe_config->lane_count,
> > adjusted_mode->crtc_clock,
> > adjusted_mode->crtc_hdisplay,
> > - false);
> > + pipe_config->bigjoiner);
> > dsc_dp_slice_count =
> > intel_dp_dsc_get_slice_count(intel_dp,
> > adjusted_mode->crtc_clock,
> > adjusted_mode->crtc_hdisplay,
> > - false);
> > + pipe_config->bigjoiner);
> > if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
> > drm_dbg_kms(&dev_priv->drm,
> > "Compressed BPP/Slice Count not supported\n");
> > @@ -2424,14 +2433,15 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> > * is greater than the maximum Cdclock and if slice count is even
> > * then we need to use 2 VDSC instances.
> > */
> > - if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) {
> > - if (pipe_config->dsc.slice_count > 1) {
> > - pipe_config->dsc.dsc_split = true;
> > - } else {
> > + if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq ||
> > + pipe_config->bigjoiner) {
> > + if (pipe_config->dsc.slice_count < 2) {
> > drm_dbg_kms(&dev_priv->drm,
> > "Cannot split stream to use 2 VDSC instances\n");
> > return -EINVAL;
> > }
> > +
> > + pipe_config->dsc.dsc_split = true;
> > }
> >
> > ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config);
> > --
> > 2.19.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v10 04/11] drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.
2020-10-14 19:04 ` Navare, Manasi
@ 2020-10-15 11:52 ` Ville Syrjälä
2020-10-15 16:26 ` Navare, Manasi
0 siblings, 1 reply; 50+ messages in thread
From: Ville Syrjälä @ 2020-10-15 11:52 UTC (permalink / raw)
To: Navare, Manasi; +Cc: intel-gfx
On Wed, Oct 14, 2020 at 12:04:10PM -0700, Navare, Manasi wrote:
> On Wed, Oct 14, 2020 at 02:26:34PM +0300, Ville Syrjälä wrote:
> > On Thu, Oct 08, 2020 at 02:45:28PM -0700, Manasi Navare wrote:
> > > From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > >
> > > Small changes to intel_dp_mode_valid(), allow listing modes that
> > > can only be supported in the bigjoiner configuration, which is
> > > not supported yet.
> > >
> > > eDP does not support bigjoiner, so do not expose bigjoiner only
> > > modes on the eDP port.
> > >
> > > v7:
> > > * Add can_bigjoiner() helper (Ville)
> > > * Pass bigjoiner to plane_size validation (Ville)
> > > v6:
> > > * Rebase after dp_downstream mode valid changes (Manasi)
> > > v5:
> > > * Increase max plane width to support 8K with bigjoiner (Maarten)
> > > v4:
> > > * Rebase (Manasi)
> > >
> > > Changes since v1:
> > > - Disallow bigjoiner on eDP.
> > > Changes since v2:
> > > - Rename intel_dp_downstream_max_dotclock to intel_dp_max_dotclock,
> > > and split off the downstream and source checking to its own function.
> > > (Ville)
> > > v3:
> > > * Rebase (Manasi)
> > >
> > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > > Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_display.c | 5 +-
> > > drivers/gpu/drm/i915/display/intel_display.h | 3 +-
> > > drivers/gpu/drm/i915/display/intel_dp.c | 126 +++++++++++++++----
> > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
> > > drivers/gpu/drm/i915/display/intel_dsi.c | 2 +-
> > > drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
> > > 6 files changed, 111 insertions(+), 29 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > index 723766b1eae3..cc540c7b7dcd 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -17642,7 +17642,8 @@ intel_mode_valid(struct drm_device *dev,
> > >
> > > enum drm_mode_status
> > > intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
> > > - const struct drm_display_mode *mode)
> > > + const struct drm_display_mode *mode,
> > > + bool bigjoiner)
> > > {
> > > int plane_width_max, plane_height_max;
> > >
> > > @@ -17659,7 +17660,7 @@ intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
> > > * too big for that.
> > > */
> > > if (INTEL_GEN(dev_priv) >= 11) {
> > > - plane_width_max = 5120;
> > > + plane_width_max = 5120 << bigjoiner;
> > > plane_height_max = 4320;
> > > } else {
> > > plane_width_max = 5120;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> > > index d10b7c8cde3f..3d860a9da8fe 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.h
> > > @@ -496,7 +496,8 @@ u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
> > > bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
> > > enum drm_mode_status
> > > intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
> > > - const struct drm_display_mode *mode);
> > > + const struct drm_display_mode *mode,
> > > + bool bigjoiner);
> > > enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
> > > bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > > index 8a522edd7386..af2ff425e5d5 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > @@ -247,6 +247,29 @@ intel_dp_max_data_rate(int max_link_clock, int max_lanes)
> > > return max_link_clock * max_lanes;
> > > }
> > >
> > > +static int source_max_dotclock(struct intel_dp *intel_dp, bool allow_bigjoiner)
> > > +{
> > > + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> > > + struct intel_encoder *encoder = &intel_dig_port->base;
> > > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > > +
> > > + if (allow_bigjoiner && INTEL_GEN(dev_priv) >= 11 && !intel_dp_is_edp(intel_dp))
> > > + return 2 * dev_priv->max_dotclk_freq;
> > > +
> > > + return dev_priv->max_dotclk_freq;
> > > +}
> > > +
> > > +static int
> > > +intel_dp_max_dotclock(struct intel_dp *intel_dp, bool allow_bigjoiner)
> > > +{
> > > + int max_dotclk = source_max_dotclock(intel_dp, allow_bigjoiner);
> > > +
> > > + if (intel_dp->dfp.max_dotclock)
> >
> > No. dfp checks should stay where they are.
>
> I am using dfp.max_dotclock because we populate that with drm_dp_downstream_max_dotclock()
> should that be used here directly from drm_dp_downstream_max_dotclock instead of using dfp.maxdotclock ?
Can you explain how bigjoiner and DFP dotclock limits relate to each
other?
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v10 06/11] drm/i915: Enable big joiner support in enable and disable sequences.
2020-10-08 21:45 ` [Intel-gfx] [PATCH v10 06/11] drm/i915: Enable big joiner support in enable and disable sequences Manasi Navare
2020-10-14 11:07 ` Jani Nikula
@ 2020-10-15 13:07 ` Ville Syrjälä
2020-10-15 16:37 ` Navare, Manasi
1 sibling, 1 reply; 50+ messages in thread
From: Ville Syrjälä @ 2020-10-15 13:07 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
On Thu, Oct 08, 2020 at 02:45:30PM -0700, Manasi Navare wrote:
> @@ -4504,6 +4514,29 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
> default:
> break;
> }
> +}
> +
> +void intel_ddi_get_config(struct intel_encoder *encoder,
> + struct intel_crtc_state *pipe_config)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
> +
> + /* XXX: DSI transcoder paranoia */
> + if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
> + return;
> +
> + intel_ddi_read_func_ctl(encoder, pipe_config);
> + if (pipe_config->bigjoiner_slave) {
> + /* read out pipe settings from master */
> + enum transcoder save = pipe_config->cpu_transcoder;
> +
> + /* Our own transcoder needs to be disabled when reading it in intel_ddi_read_func_ctl() */
> + WARN_ON(pipe_config->output_types);
> + pipe_config->cpu_transcoder = (enum transcoder)pipe_config->bigjoiner_linked_crtc->pipe;
> + intel_ddi_read_func_ctl(encoder, pipe_config);
> + pipe_config->cpu_transcoder = save;
> + }
This stuff is rather horrible. Shouldn't both pipes be using the
same transcoder anyway? If so, is this stuff here just because
we've miscalculated cpu_transcoder for the slave?
>
> pipe_config->has_audio =
> intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
> @@ -4529,7 +4562,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
> dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
> }
>
> - intel_ddi_clock_get(encoder, pipe_config);
> + if (!pipe_config->bigjoiner_slave)
> + intel_ddi_clock_get(encoder, pipe_config);
>
> if (IS_GEN9_LP(dev_priv))
> pipe_config->lane_lat_optim_mask =
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 37b56f4c2401..faf8bf757bed 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7125,6 +7125,45 @@ static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
> intel_de_write(dev_priv, reg, val);
> }
>
> +static void tgl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
> + const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *master = to_intel_crtc(crtc_state->uapi.crtc);
> + struct intel_crtc_state *master_crtc_state;
> + struct drm_connector_state *conn_state;
> + struct drm_connector *conn;
> + struct intel_encoder *encoder = NULL;
> + int i;
> +
> + if (crtc_state->bigjoiner_slave)
> + master = crtc_state->bigjoiner_linked_crtc;
> +
> + master_crtc_state = intel_atomic_get_new_crtc_state(state, master);
> +
> + for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
> + if (conn_state->crtc != &master->base)
> + continue;
> +
> + encoder = to_intel_encoder(conn_state->best_encoder);
> + break;
> + }
> +
> + if (!crtc_state->bigjoiner_slave) {
> + /* need to enable VDSC, which we skipped in pre-enable */
> + intel_dsc_enable(encoder, crtc_state);
> + } else {
> + /*
> + * Enable sequence steps 1-7 on bigjoiner master
> + */
> + intel_encoders_pre_pll_enable(state, master);
> + intel_enable_shared_dpll(master_crtc_state);
> + intel_encoders_pre_enable(state, master);
> +
> + /* and DSC on slave */
> + intel_dsc_enable(NULL, crtc_state);
> + }
> +}
> +
> static void hsw_crtc_enable(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> @@ -7138,34 +7177,39 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
> if (drm_WARN_ON(&dev_priv->drm, crtc->active))
> return;
>
> - intel_encoders_pre_pll_enable(state, crtc);
> -
> - if (new_crtc_state->shared_dpll)
> - intel_enable_shared_dpll(new_crtc_state);
> + if (!new_crtc_state->bigjoiner) {
> + intel_encoders_pre_pll_enable(state, crtc);
>
> - intel_encoders_pre_enable(state, crtc);
> + if (new_crtc_state->shared_dpll)
> + intel_enable_shared_dpll(new_crtc_state);
>
> - if (!transcoder_is_dsi(cpu_transcoder))
> - intel_set_transcoder_timings(new_crtc_state);
> + intel_encoders_pre_enable(state, crtc);
> + } else {
> + tgl_ddi_bigjoiner_pre_enable(state, new_crtc_state);
> + }
>
> intel_set_pipe_src_size(new_crtc_state);
> + if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
> + bdw_set_pipemisc(new_crtc_state);
>
> - if (cpu_transcoder != TRANSCODER_EDP &&
> - !transcoder_is_dsi(cpu_transcoder))
> - intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
> - new_crtc_state->pixel_multiplier - 1);
> + if (!new_crtc_state->bigjoiner_slave && !transcoder_is_dsi(cpu_transcoder)) {
> + if (!transcoder_is_dsi(cpu_transcoder))
> + intel_set_transcoder_timings(new_crtc_state);
>
> - if (new_crtc_state->has_pch_encoder)
> - intel_cpu_transcoder_set_m_n(new_crtc_state,
> - &new_crtc_state->fdi_m_n, NULL);
> + if (cpu_transcoder != TRANSCODER_EDP &&
> + !transcoder_is_dsi(cpu_transcoder))
> + intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
> + new_crtc_state->pixel_multiplier - 1);
> +
> + if (new_crtc_state->has_pch_encoder)
> + intel_cpu_transcoder_set_m_n(new_crtc_state,
> + &new_crtc_state->fdi_m_n, NULL);
>
> - if (!transcoder_is_dsi(cpu_transcoder)) {
> hsw_set_frame_start_delay(new_crtc_state);
> - hsw_set_pipeconf(new_crtc_state);
> }
>
> - if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
> - bdw_set_pipemisc(new_crtc_state);
> + if (!transcoder_is_dsi(cpu_transcoder))
> + hsw_set_pipeconf(new_crtc_state);
>
> crtc->active = true;
>
> @@ -7201,6 +7245,11 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
> if (INTEL_GEN(dev_priv) >= 11)
> icl_pipe_mbus_enable(crtc);
>
> + if (new_crtc_state->bigjoiner_slave) {
> + trace_intel_pipe_enable(crtc);
> + intel_crtc_vblank_on(new_crtc_state);
> + }
> +
> intel_encoders_enable(state, crtc);
>
> if (psl_clkgate_wa) {
> @@ -7495,6 +7544,9 @@ static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
> if (crtc_state->shared_dpll)
> mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);
>
> + if (crtc_state->dsc.compression_enable)
> + mask |= BIT_ULL(intel_dsc_power_domain(crtc_state));
> +
> return mask;
> }
>
> @@ -8113,6 +8165,30 @@ static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
> pfit_w * pfit_h);
> }
>
> +static void intel_encoder_get_config(struct intel_encoder *encoder,
> + struct intel_crtc_state *crtc_state)
> +{
> + struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
> +
> + encoder->get_config(encoder, crtc_state);
> +
> + *pipe_mode = crtc_state->hw.adjusted_mode;
> + if (crtc_state->bigjoiner) {
> + /*
> + * transcoder is programmed to the full mode,
> + * but pipe timings are half of the transcoder mode
> + */
> + pipe_mode->crtc_hdisplay /= 2;
> + pipe_mode->crtc_hblank_start /= 2;
> + pipe_mode->crtc_hblank_end /= 2;
> + pipe_mode->crtc_hsync_start /= 2;
> + pipe_mode->crtc_hsync_end /= 2;
> + pipe_mode->crtc_htotal /= 2;
> + pipe_mode->crtc_hskew /= 2;
> + pipe_mode->crtc_clock /= 2;
> + }
> +}
> +
> static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> @@ -9027,20 +9103,22 @@ static void intel_get_pipe_src_size(struct intel_crtc *crtc,
> void intel_mode_from_pipe_config(struct drm_display_mode *mode,
> struct intel_crtc_state *pipe_config)
> {
> - mode->hdisplay = pipe_config->hw.adjusted_mode.crtc_hdisplay;
> - mode->htotal = pipe_config->hw.adjusted_mode.crtc_htotal;
> - mode->hsync_start = pipe_config->hw.adjusted_mode.crtc_hsync_start;
> - mode->hsync_end = pipe_config->hw.adjusted_mode.crtc_hsync_end;
> + struct drm_display_mode *hw_mode = &pipe_config->hw.adjusted_mode;
> +
> + mode->hdisplay = hw_mode->crtc_hdisplay;
> + mode->htotal = hw_mode->crtc_htotal;
> + mode->hsync_start = hw_mode->crtc_hsync_start;
> + mode->hsync_end = hw_mode->crtc_hsync_end;
>
> - mode->vdisplay = pipe_config->hw.adjusted_mode.crtc_vdisplay;
> - mode->vtotal = pipe_config->hw.adjusted_mode.crtc_vtotal;
> - mode->vsync_start = pipe_config->hw.adjusted_mode.crtc_vsync_start;
> - mode->vsync_end = pipe_config->hw.adjusted_mode.crtc_vsync_end;
> + mode->vdisplay = hw_mode->crtc_vdisplay;
> + mode->vtotal = hw_mode->crtc_vtotal;
> + mode->vsync_start = hw_mode->crtc_vsync_start;
> + mode->vsync_end = hw_mode->crtc_vsync_end;
>
> - mode->flags = pipe_config->hw.adjusted_mode.flags;
> + mode->flags = hw_mode->flags;
> mode->type = DRM_MODE_TYPE_DRIVER;
>
> - mode->clock = pipe_config->hw.adjusted_mode.crtc_clock;
> + mode->clock = hw_mode->crtc_clock;
>
> drm_mode_set_name(mode);
> }
> @@ -11207,6 +11285,9 @@ static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
> } else {
> tmp = intel_de_read(dev_priv,
> TRANS_DDI_FUNC_CTL(cpu_transcoder));
> + if (!(tmp & TRANS_DDI_FUNC_ENABLE))
> + return;
> +
> if (INTEL_GEN(dev_priv) >= 12)
> port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
> else
> @@ -11279,12 +11360,20 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
> drm_WARN_ON(&dev_priv->drm, active);
> active = true;
> }
> + intel_dsc_get_config(pipe_config);
>
> - if (!active)
> - goto out;
> + if (!active) {
> + /* bigjoiner slave doesn't enable transcoder */
> + if (!pipe_config->bigjoiner_slave)
> + goto out;
>
> - if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
> - INTEL_GEN(dev_priv) >= 11) {
> + active = true;
> + pipe_config->pixel_multiplier = 1;
> +
> + /* we cannot read out most state, so don't bother.. */
> + pipe_config->quirks |= PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE;
> + } else if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
> + INTEL_GEN(dev_priv) >= 11) {
> hsw_get_ddi_port_state(crtc, pipe_config);
> intel_get_transcoder_timings(crtc, pipe_config);
> }
> @@ -11370,8 +11459,11 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
> }
> }
>
> - if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
> - !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
> + if (pipe_config->bigjoiner_slave) {
> + /* Cannot be read out as a slave, set to 0. */
> + pipe_config->pixel_multiplier = 0;
> + } else if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
> + !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
> pipe_config->pixel_multiplier =
> intel_de_read(dev_priv,
> PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
> @@ -12386,7 +12478,7 @@ intel_encoder_current_mode(struct intel_encoder *encoder)
> return NULL;
> }
>
> - encoder->get_config(encoder, crtc_state);
> + intel_encoder_get_config(encoder, crtc_state);
>
> intel_mode_from_pipe_config(mode, crtc_state);
>
> @@ -13385,12 +13477,15 @@ intel_crtc_copy_uapi_to_hw_state(struct intel_atomic_state *state,
> intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc_state);
> }
>
> -static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
> +static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state,
> + struct drm_display_mode *user_mode)
> {
> - crtc_state->uapi.enable = crtc_state->hw.enable;
> - crtc_state->uapi.active = crtc_state->hw.active;
> - drm_WARN_ON(crtc_state->uapi.crtc->dev,
> - drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);
> + if (!crtc_state->bigjoiner_slave) {
> + crtc_state->uapi.enable = crtc_state->hw.enable;
> + crtc_state->uapi.active = crtc_state->hw.active;
> + drm_WARN_ON(crtc_state->uapi.crtc->dev,
> + drm_atomic_set_mode_for_crtc(&crtc_state->uapi, user_mode) < 0);
> + }
>
> crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
>
> @@ -14027,21 +14122,42 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>
> PIPE_CONF_CHECK_X(output_types);
>
> - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
> - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
> - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
> - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
> - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
> - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
> -
> - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
> - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
> - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
> - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
> - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
> - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
> -
> - PIPE_CONF_CHECK_I(pixel_multiplier);
> + if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) {
> + /* bigjoiner mode = transcoder mode / 2, for calculations */
> + PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);
> + PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_htotal);
> + PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vdisplay);
> + PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vtotal);
> +
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
> +
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
> +
> + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> + DRM_MODE_FLAG_INTERLACE);
> +
> + if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
> + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> + DRM_MODE_FLAG_PHSYNC);
> + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> + DRM_MODE_FLAG_NHSYNC);
> + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> + DRM_MODE_FLAG_PVSYNC);
> + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> + DRM_MODE_FLAG_NVSYNC);
> + }
> + PIPE_CONF_CHECK_I(pixel_multiplier);
> + }
> PIPE_CONF_CHECK_I(output_format);
> PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
> if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
> @@ -14051,24 +14167,11 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
> PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
> PIPE_CONF_CHECK_BOOL(has_infoframe);
> - PIPE_CONF_CHECK_BOOL(fec_enable);
> + if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE))
> + PIPE_CONF_CHECK_BOOL(fec_enable);
>
> PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
>
> - PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> - DRM_MODE_FLAG_INTERLACE);
> -
> - if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
> - PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> - DRM_MODE_FLAG_PHSYNC);
> - PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> - DRM_MODE_FLAG_NHSYNC);
> - PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> - DRM_MODE_FLAG_PVSYNC);
> - PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> - DRM_MODE_FLAG_NVSYNC);
> - }
> -
> PIPE_CONF_CHECK_X(gmch_pfit.control);
> /* pfit ratios are autocomputed by the hw on gen4+ */
> if (INTEL_GEN(dev_priv) < 4)
> @@ -14094,7 +14197,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> }
>
> PIPE_CONF_CHECK_I(scaler_state.scaler_id);
> - PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
> + if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE))
> + PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
>
> PIPE_CONF_CHECK_X(gamma_mode);
> if (IS_CHERRYVIEW(dev_priv))
> @@ -14115,48 +14219,51 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> PIPE_CONF_CHECK_BOOL(double_wide);
>
> PIPE_CONF_CHECK_P(shared_dpll);
> - PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
> - PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
> - PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
> - PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
> - PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
> - PIPE_CONF_CHECK_X(dpll_hw_state.spll);
> - PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
> - PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
> - PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
> - PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
> - PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
> - PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
> - PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
> - PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
> - PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
> - PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
> - PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
> - PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
> - PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
> - PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
> - PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
> - PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
> - PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
> - PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
> - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
> - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
> - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
> - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
> - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
> - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
> - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
> -
> - PIPE_CONF_CHECK_X(dsi_pll.ctrl);
> - PIPE_CONF_CHECK_X(dsi_pll.div);
> -
> - if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
> - PIPE_CONF_CHECK_I(pipe_bpp);
> -
> - PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
> - PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
> -
> - PIPE_CONF_CHECK_I(min_voltage_level);
> + if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) {
This looks super sketchy. I don't see why we'd want to skip all this
state checking for bigjoiner.
> + PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
> + PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
> + PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
> + PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
> + PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
> + PIPE_CONF_CHECK_X(dpll_hw_state.spll);
> + PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
> + PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
> + PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
> + PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
> + PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
> + PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
> + PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
> + PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
> + PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
> + PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
> + PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
> + PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
> + PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
> + PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
> + PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
> + PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
> + PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
> + PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
> + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
> + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
> + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
> + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
> + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
> + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
> + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
> +
> + PIPE_CONF_CHECK_X(dsi_pll.ctrl);
> + PIPE_CONF_CHECK_X(dsi_pll.div);
> +
> + if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
> + PIPE_CONF_CHECK_I(pipe_bpp);
> +
> + PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
> + PIPE_CONF_CHECK_CLOCK_FUZZY(hw.pipe_mode.crtc_clock);
> + PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
> +
> + PIPE_CONF_CHECK_I(min_voltage_level);
> + }
>
> PIPE_CONF_CHECK_X(infoframes.enable);
> PIPE_CONF_CHECK_X(infoframes.gcp);
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v10 04/11] drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.
2020-10-15 11:52 ` Ville Syrjälä
@ 2020-10-15 16:26 ` Navare, Manasi
2020-10-19 16:30 ` Ville Syrjälä
0 siblings, 1 reply; 50+ messages in thread
From: Navare, Manasi @ 2020-10-15 16:26 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Thu, Oct 15, 2020 at 02:52:47PM +0300, Ville Syrjälä wrote:
> On Wed, Oct 14, 2020 at 12:04:10PM -0700, Navare, Manasi wrote:
> > On Wed, Oct 14, 2020 at 02:26:34PM +0300, Ville Syrjälä wrote:
> > > On Thu, Oct 08, 2020 at 02:45:28PM -0700, Manasi Navare wrote:
> > > > From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > > >
> > > > Small changes to intel_dp_mode_valid(), allow listing modes that
> > > > can only be supported in the bigjoiner configuration, which is
> > > > not supported yet.
> > > >
> > > > eDP does not support bigjoiner, so do not expose bigjoiner only
> > > > modes on the eDP port.
> > > >
> > > > v7:
> > > > * Add can_bigjoiner() helper (Ville)
> > > > * Pass bigjoiner to plane_size validation (Ville)
> > > > v6:
> > > > * Rebase after dp_downstream mode valid changes (Manasi)
> > > > v5:
> > > > * Increase max plane width to support 8K with bigjoiner (Maarten)
> > > > v4:
> > > > * Rebase (Manasi)
> > > >
> > > > Changes since v1:
> > > > - Disallow bigjoiner on eDP.
> > > > Changes since v2:
> > > > - Rename intel_dp_downstream_max_dotclock to intel_dp_max_dotclock,
> > > > and split off the downstream and source checking to its own function.
> > > > (Ville)
> > > > v3:
> > > > * Rebase (Manasi)
> > > >
> > > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > > > Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_display.c | 5 +-
> > > > drivers/gpu/drm/i915/display/intel_display.h | 3 +-
> > > > drivers/gpu/drm/i915/display/intel_dp.c | 126 +++++++++++++++----
> > > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
> > > > drivers/gpu/drm/i915/display/intel_dsi.c | 2 +-
> > > > drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
> > > > 6 files changed, 111 insertions(+), 29 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > > index 723766b1eae3..cc540c7b7dcd 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > @@ -17642,7 +17642,8 @@ intel_mode_valid(struct drm_device *dev,
> > > >
> > > > enum drm_mode_status
> > > > intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
> > > > - const struct drm_display_mode *mode)
> > > > + const struct drm_display_mode *mode,
> > > > + bool bigjoiner)
> > > > {
> > > > int plane_width_max, plane_height_max;
> > > >
> > > > @@ -17659,7 +17660,7 @@ intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
> > > > * too big for that.
> > > > */
> > > > if (INTEL_GEN(dev_priv) >= 11) {
> > > > - plane_width_max = 5120;
> > > > + plane_width_max = 5120 << bigjoiner;
> > > > plane_height_max = 4320;
> > > > } else {
> > > > plane_width_max = 5120;
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> > > > index d10b7c8cde3f..3d860a9da8fe 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display.h
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display.h
> > > > @@ -496,7 +496,8 @@ u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
> > > > bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
> > > > enum drm_mode_status
> > > > intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
> > > > - const struct drm_display_mode *mode);
> > > > + const struct drm_display_mode *mode,
> > > > + bool bigjoiner);
> > > > enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
> > > > bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > index 8a522edd7386..af2ff425e5d5 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > @@ -247,6 +247,29 @@ intel_dp_max_data_rate(int max_link_clock, int max_lanes)
> > > > return max_link_clock * max_lanes;
> > > > }
> > > >
> > > > +static int source_max_dotclock(struct intel_dp *intel_dp, bool allow_bigjoiner)
> > > > +{
> > > > + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> > > > + struct intel_encoder *encoder = &intel_dig_port->base;
> > > > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > > > +
> > > > + if (allow_bigjoiner && INTEL_GEN(dev_priv) >= 11 && !intel_dp_is_edp(intel_dp))
> > > > + return 2 * dev_priv->max_dotclk_freq;
> > > > +
> > > > + return dev_priv->max_dotclk_freq;
> > > > +}
> > > > +
> > > > +static int
> > > > +intel_dp_max_dotclock(struct intel_dp *intel_dp, bool allow_bigjoiner)
> > > > +{
> > > > + int max_dotclk = source_max_dotclock(intel_dp, allow_bigjoiner);
> > > > +
> > > > + if (intel_dp->dfp.max_dotclock)
> > >
> > > No. dfp checks should stay where they are.
> >
> > I am using dfp.max_dotclock because we populate that with drm_dp_downstream_max_dotclock()
> > should that be used here directly from drm_dp_downstream_max_dotclock instead of using dfp.maxdotclock ?
>
> Can you explain how bigjoiner and DFP dotclock limits relate to each
> other?
Before the dfp dotclock checks were added, we were obtaining the max dotclock as min (source_max_dotclock, downstream max dotclock from dpcd)
And thats why I was using the dfp.max_dotclock
But while addressing your feedback , I have now max_dotclock = source max dotclock
and the downstream max dotclock checks happen in intel_dp_mode_valid_downstream(), so I think we dont need to consider
this here in max dotclock computation.
Is this correct?
Manasi
>
> --
> Ville Syrjälä
> Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v10 06/11] drm/i915: Enable big joiner support in enable and disable sequences.
2020-10-15 13:07 ` Ville Syrjälä
@ 2020-10-15 16:37 ` Navare, Manasi
2020-10-16 16:06 ` Ville Syrjälä
0 siblings, 1 reply; 50+ messages in thread
From: Navare, Manasi @ 2020-10-15 16:37 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Thu, Oct 15, 2020 at 04:07:05PM +0300, Ville Syrjälä wrote:
> On Thu, Oct 08, 2020 at 02:45:30PM -0700, Manasi Navare wrote:
> > @@ -4504,6 +4514,29 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
> > default:
> > break;
> > }
> > +}
> > +
> > +void intel_ddi_get_config(struct intel_encoder *encoder,
> > + struct intel_crtc_state *pipe_config)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > + enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
> > +
> > + /* XXX: DSI transcoder paranoia */
> > + if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
> > + return;
> > +
> > + intel_ddi_read_func_ctl(encoder, pipe_config);
> > + if (pipe_config->bigjoiner_slave) {
> > + /* read out pipe settings from master */
> > + enum transcoder save = pipe_config->cpu_transcoder;
> > +
> > + /* Our own transcoder needs to be disabled when reading it in intel_ddi_read_func_ctl() */
> > + WARN_ON(pipe_config->output_types);
> > + pipe_config->cpu_transcoder = (enum transcoder)pipe_config->bigjoiner_linked_crtc->pipe;
> > + intel_ddi_read_func_ctl(encoder, pipe_config);
> > + pipe_config->cpu_transcoder = save;
> > + }
>
> This stuff is rather horrible. Shouldn't both pipes be using the
> same transcoder anyway? If so, is this stuff here just because
> we've miscalculated cpu_transcoder for the slave?
Well honestly @Maarten wrote this and I believe had several iterations of reviews with you.
So he can explain better.
My understanding so far was that there is no encoder /transcoder for slave and thats
why for bigjoiner_slave we actually read stuff from master
So why is this wrong?
>
> >
> > pipe_config->has_audio =
> > intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
> > @@ -4529,7 +4562,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
> > dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
> > }
> >
> > - intel_ddi_clock_get(encoder, pipe_config);
> > + if (!pipe_config->bigjoiner_slave)
> > + intel_ddi_clock_get(encoder, pipe_config);
> >
> > if (IS_GEN9_LP(dev_priv))
> > pipe_config->lane_lat_optim_mask =
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index 37b56f4c2401..faf8bf757bed 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -7125,6 +7125,45 @@ static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
> > intel_de_write(dev_priv, reg, val);
> > }
> >
> > +static void tgl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
> > + const struct intel_crtc_state *crtc_state)
> > +{
> > + struct intel_crtc *master = to_intel_crtc(crtc_state->uapi.crtc);
> > + struct intel_crtc_state *master_crtc_state;
> > + struct drm_connector_state *conn_state;
> > + struct drm_connector *conn;
> > + struct intel_encoder *encoder = NULL;
> > + int i;
> > +
> > + if (crtc_state->bigjoiner_slave)
> > + master = crtc_state->bigjoiner_linked_crtc;
> > +
> > + master_crtc_state = intel_atomic_get_new_crtc_state(state, master);
> > +
> > + for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
> > + if (conn_state->crtc != &master->base)
> > + continue;
> > +
> > + encoder = to_intel_encoder(conn_state->best_encoder);
> > + break;
> > + }
> > +
> > + if (!crtc_state->bigjoiner_slave) {
> > + /* need to enable VDSC, which we skipped in pre-enable */
> > + intel_dsc_enable(encoder, crtc_state);
> > + } else {
> > + /*
> > + * Enable sequence steps 1-7 on bigjoiner master
> > + */
> > + intel_encoders_pre_pll_enable(state, master);
> > + intel_enable_shared_dpll(master_crtc_state);
> > + intel_encoders_pre_enable(state, master);
> > +
> > + /* and DSC on slave */
> > + intel_dsc_enable(NULL, crtc_state);
> > + }
> > +}
> > +
> > static void hsw_crtc_enable(struct intel_atomic_state *state,
> > struct intel_crtc *crtc)
> > {
> > @@ -7138,34 +7177,39 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
> > if (drm_WARN_ON(&dev_priv->drm, crtc->active))
> > return;
> >
> > - intel_encoders_pre_pll_enable(state, crtc);
> > -
> > - if (new_crtc_state->shared_dpll)
> > - intel_enable_shared_dpll(new_crtc_state);
> > + if (!new_crtc_state->bigjoiner) {
> > + intel_encoders_pre_pll_enable(state, crtc);
> >
> > - intel_encoders_pre_enable(state, crtc);
> > + if (new_crtc_state->shared_dpll)
> > + intel_enable_shared_dpll(new_crtc_state);
> >
> > - if (!transcoder_is_dsi(cpu_transcoder))
> > - intel_set_transcoder_timings(new_crtc_state);
> > + intel_encoders_pre_enable(state, crtc);
> > + } else {
> > + tgl_ddi_bigjoiner_pre_enable(state, new_crtc_state);
> > + }
> >
> > intel_set_pipe_src_size(new_crtc_state);
> > + if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
> > + bdw_set_pipemisc(new_crtc_state);
> >
> > - if (cpu_transcoder != TRANSCODER_EDP &&
> > - !transcoder_is_dsi(cpu_transcoder))
> > - intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
> > - new_crtc_state->pixel_multiplier - 1);
> > + if (!new_crtc_state->bigjoiner_slave && !transcoder_is_dsi(cpu_transcoder)) {
> > + if (!transcoder_is_dsi(cpu_transcoder))
> > + intel_set_transcoder_timings(new_crtc_state);
> >
> > - if (new_crtc_state->has_pch_encoder)
> > - intel_cpu_transcoder_set_m_n(new_crtc_state,
> > - &new_crtc_state->fdi_m_n, NULL);
> > + if (cpu_transcoder != TRANSCODER_EDP &&
> > + !transcoder_is_dsi(cpu_transcoder))
> > + intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
> > + new_crtc_state->pixel_multiplier - 1);
> > +
> > + if (new_crtc_state->has_pch_encoder)
> > + intel_cpu_transcoder_set_m_n(new_crtc_state,
> > + &new_crtc_state->fdi_m_n, NULL);
> >
> > - if (!transcoder_is_dsi(cpu_transcoder)) {
> > hsw_set_frame_start_delay(new_crtc_state);
> > - hsw_set_pipeconf(new_crtc_state);
> > }
> >
> > - if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
> > - bdw_set_pipemisc(new_crtc_state);
> > + if (!transcoder_is_dsi(cpu_transcoder))
> > + hsw_set_pipeconf(new_crtc_state);
> >
> > crtc->active = true;
> >
> > @@ -7201,6 +7245,11 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
> > if (INTEL_GEN(dev_priv) >= 11)
> > icl_pipe_mbus_enable(crtc);
> >
> > + if (new_crtc_state->bigjoiner_slave) {
> > + trace_intel_pipe_enable(crtc);
> > + intel_crtc_vblank_on(new_crtc_state);
> > + }
> > +
> > intel_encoders_enable(state, crtc);
> >
> > if (psl_clkgate_wa) {
> > @@ -7495,6 +7544,9 @@ static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
> > if (crtc_state->shared_dpll)
> > mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);
> >
> > + if (crtc_state->dsc.compression_enable)
> > + mask |= BIT_ULL(intel_dsc_power_domain(crtc_state));
> > +
> > return mask;
> > }
> >
> > @@ -8113,6 +8165,30 @@ static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
> > pfit_w * pfit_h);
> > }
> >
> > +static void intel_encoder_get_config(struct intel_encoder *encoder,
> > + struct intel_crtc_state *crtc_state)
> > +{
> > + struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
> > +
> > + encoder->get_config(encoder, crtc_state);
> > +
> > + *pipe_mode = crtc_state->hw.adjusted_mode;
> > + if (crtc_state->bigjoiner) {
> > + /*
> > + * transcoder is programmed to the full mode,
> > + * but pipe timings are half of the transcoder mode
> > + */
> > + pipe_mode->crtc_hdisplay /= 2;
> > + pipe_mode->crtc_hblank_start /= 2;
> > + pipe_mode->crtc_hblank_end /= 2;
> > + pipe_mode->crtc_hsync_start /= 2;
> > + pipe_mode->crtc_hsync_end /= 2;
> > + pipe_mode->crtc_htotal /= 2;
> > + pipe_mode->crtc_hskew /= 2;
> > + pipe_mode->crtc_clock /= 2;
> > + }
> > +}
> > +
> > static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
> > {
> > struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> > @@ -9027,20 +9103,22 @@ static void intel_get_pipe_src_size(struct intel_crtc *crtc,
> > void intel_mode_from_pipe_config(struct drm_display_mode *mode,
> > struct intel_crtc_state *pipe_config)
> > {
> > - mode->hdisplay = pipe_config->hw.adjusted_mode.crtc_hdisplay;
> > - mode->htotal = pipe_config->hw.adjusted_mode.crtc_htotal;
> > - mode->hsync_start = pipe_config->hw.adjusted_mode.crtc_hsync_start;
> > - mode->hsync_end = pipe_config->hw.adjusted_mode.crtc_hsync_end;
> > + struct drm_display_mode *hw_mode = &pipe_config->hw.adjusted_mode;
> > +
> > + mode->hdisplay = hw_mode->crtc_hdisplay;
> > + mode->htotal = hw_mode->crtc_htotal;
> > + mode->hsync_start = hw_mode->crtc_hsync_start;
> > + mode->hsync_end = hw_mode->crtc_hsync_end;
> >
> > - mode->vdisplay = pipe_config->hw.adjusted_mode.crtc_vdisplay;
> > - mode->vtotal = pipe_config->hw.adjusted_mode.crtc_vtotal;
> > - mode->vsync_start = pipe_config->hw.adjusted_mode.crtc_vsync_start;
> > - mode->vsync_end = pipe_config->hw.adjusted_mode.crtc_vsync_end;
> > + mode->vdisplay = hw_mode->crtc_vdisplay;
> > + mode->vtotal = hw_mode->crtc_vtotal;
> > + mode->vsync_start = hw_mode->crtc_vsync_start;
> > + mode->vsync_end = hw_mode->crtc_vsync_end;
> >
> > - mode->flags = pipe_config->hw.adjusted_mode.flags;
> > + mode->flags = hw_mode->flags;
> > mode->type = DRM_MODE_TYPE_DRIVER;
> >
> > - mode->clock = pipe_config->hw.adjusted_mode.crtc_clock;
> > + mode->clock = hw_mode->crtc_clock;
> >
> > drm_mode_set_name(mode);
> > }
> > @@ -11207,6 +11285,9 @@ static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
> > } else {
> > tmp = intel_de_read(dev_priv,
> > TRANS_DDI_FUNC_CTL(cpu_transcoder));
> > + if (!(tmp & TRANS_DDI_FUNC_ENABLE))
> > + return;
> > +
> > if (INTEL_GEN(dev_priv) >= 12)
> > port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
> > else
> > @@ -11279,12 +11360,20 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
> > drm_WARN_ON(&dev_priv->drm, active);
> > active = true;
> > }
> > + intel_dsc_get_config(pipe_config);
> >
> > - if (!active)
> > - goto out;
> > + if (!active) {
> > + /* bigjoiner slave doesn't enable transcoder */
> > + if (!pipe_config->bigjoiner_slave)
> > + goto out;
> >
> > - if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
> > - INTEL_GEN(dev_priv) >= 11) {
> > + active = true;
> > + pipe_config->pixel_multiplier = 1;
> > +
> > + /* we cannot read out most state, so don't bother.. */
> > + pipe_config->quirks |= PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE;
> > + } else if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
> > + INTEL_GEN(dev_priv) >= 11) {
> > hsw_get_ddi_port_state(crtc, pipe_config);
> > intel_get_transcoder_timings(crtc, pipe_config);
> > }
> > @@ -11370,8 +11459,11 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
> > }
> > }
> >
> > - if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
> > - !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
> > + if (pipe_config->bigjoiner_slave) {
> > + /* Cannot be read out as a slave, set to 0. */
> > + pipe_config->pixel_multiplier = 0;
> > + } else if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
> > + !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
> > pipe_config->pixel_multiplier =
> > intel_de_read(dev_priv,
> > PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
> > @@ -12386,7 +12478,7 @@ intel_encoder_current_mode(struct intel_encoder *encoder)
> > return NULL;
> > }
> >
> > - encoder->get_config(encoder, crtc_state);
> > + intel_encoder_get_config(encoder, crtc_state);
> >
> > intel_mode_from_pipe_config(mode, crtc_state);
> >
> > @@ -13385,12 +13477,15 @@ intel_crtc_copy_uapi_to_hw_state(struct intel_atomic_state *state,
> > intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc_state);
> > }
> >
> > -static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
> > +static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state,
> > + struct drm_display_mode *user_mode)
> > {
> > - crtc_state->uapi.enable = crtc_state->hw.enable;
> > - crtc_state->uapi.active = crtc_state->hw.active;
> > - drm_WARN_ON(crtc_state->uapi.crtc->dev,
> > - drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);
> > + if (!crtc_state->bigjoiner_slave) {
> > + crtc_state->uapi.enable = crtc_state->hw.enable;
> > + crtc_state->uapi.active = crtc_state->hw.active;
> > + drm_WARN_ON(crtc_state->uapi.crtc->dev,
> > + drm_atomic_set_mode_for_crtc(&crtc_state->uapi, user_mode) < 0);
> > + }
> >
> > crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
> >
> > @@ -14027,21 +14122,42 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> >
> > PIPE_CONF_CHECK_X(output_types);
> >
> > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
> > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
> > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
> > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
> > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
> > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
> > -
> > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
> > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
> > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
> > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
> > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
> > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
> > -
> > - PIPE_CONF_CHECK_I(pixel_multiplier);
> > + if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) {
> > + /* bigjoiner mode = transcoder mode / 2, for calculations */
> > + PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);
> > + PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_htotal);
> > + PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vdisplay);
> > + PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vtotal);
> > +
> > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
> > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
> > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
> > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
> > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
> > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
> > +
> > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
> > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
> > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
> > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
> > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
> > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
> > +
> > + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > + DRM_MODE_FLAG_INTERLACE);
> > +
> > + if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
> > + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > + DRM_MODE_FLAG_PHSYNC);
> > + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > + DRM_MODE_FLAG_NHSYNC);
> > + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > + DRM_MODE_FLAG_PVSYNC);
> > + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > + DRM_MODE_FLAG_NVSYNC);
> > + }
> > + PIPE_CONF_CHECK_I(pixel_multiplier);
> > + }
> > PIPE_CONF_CHECK_I(output_format);
> > PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
> > if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
> > @@ -14051,24 +14167,11 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> > PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
> > PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
> > PIPE_CONF_CHECK_BOOL(has_infoframe);
> > - PIPE_CONF_CHECK_BOOL(fec_enable);
> > + if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE))
> > + PIPE_CONF_CHECK_BOOL(fec_enable);
> >
> > PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
> >
> > - PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > - DRM_MODE_FLAG_INTERLACE);
> > -
> > - if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
> > - PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > - DRM_MODE_FLAG_PHSYNC);
> > - PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > - DRM_MODE_FLAG_NHSYNC);
> > - PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > - DRM_MODE_FLAG_PVSYNC);
> > - PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > - DRM_MODE_FLAG_NVSYNC);
> > - }
> > -
> > PIPE_CONF_CHECK_X(gmch_pfit.control);
> > /* pfit ratios are autocomputed by the hw on gen4+ */
> > if (INTEL_GEN(dev_priv) < 4)
> > @@ -14094,7 +14197,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> > }
> >
> > PIPE_CONF_CHECK_I(scaler_state.scaler_id);
> > - PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
> > + if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE))
> > + PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
> >
> > PIPE_CONF_CHECK_X(gamma_mode);
> > if (IS_CHERRYVIEW(dev_priv))
> > @@ -14115,48 +14219,51 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> > PIPE_CONF_CHECK_BOOL(double_wide);
> >
> > PIPE_CONF_CHECK_P(shared_dpll);
> > - PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
> > - PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
> > - PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
> > - PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
> > - PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
> > - PIPE_CONF_CHECK_X(dpll_hw_state.spll);
> > - PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
> > - PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
> > - PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
> > - PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
> > - PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
> > - PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
> > - PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
> > - PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
> > - PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
> > - PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
> > - PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
> > - PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
> > - PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
> > - PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
> > - PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
> > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
> > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
> > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
> > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
> > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
> > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
> > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
> > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
> > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
> > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
> > -
> > - PIPE_CONF_CHECK_X(dsi_pll.ctrl);
> > - PIPE_CONF_CHECK_X(dsi_pll.div);
> > -
> > - if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
> > - PIPE_CONF_CHECK_I(pipe_bpp);
> > -
> > - PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
> > - PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
> > -
> > - PIPE_CONF_CHECK_I(min_voltage_level);
> > + if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) {
>
> This looks super sketchy. I don't see why we'd want to skip all this
> state checking for bigjoiner.
For big joiner slave we do not enable plls and hence it doesnt make sense
to compare the hw state of plls for big joiner slave
Manasi
>
> > + PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
> > + PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
> > + PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
> > + PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
> > + PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
> > + PIPE_CONF_CHECK_X(dpll_hw_state.spll);
> > + PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
> > + PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
> > + PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
> > + PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
> > + PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
> > + PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
> > + PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
> > + PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
> > + PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
> > + PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
> > + PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
> > + PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
> > + PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
> > + PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
> > + PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
> > + PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
> > + PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
> > + PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
> > + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
> > + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
> > + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
> > + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
> > + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
> > + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
> > + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
> > +
> > + PIPE_CONF_CHECK_X(dsi_pll.ctrl);
> > + PIPE_CONF_CHECK_X(dsi_pll.div);
> > +
> > + if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
> > + PIPE_CONF_CHECK_I(pipe_bpp);
> > +
> > + PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
> > + PIPE_CONF_CHECK_CLOCK_FUZZY(hw.pipe_mode.crtc_clock);
> > + PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
> > +
> > + PIPE_CONF_CHECK_I(min_voltage_level);
> > + }
> >
> > PIPE_CONF_CHECK_X(infoframes.enable);
> > PIPE_CONF_CHECK_X(infoframes.gcp);
> --
> Ville Syrjälä
> Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v10 06/11] drm/i915: Enable big joiner support in enable and disable sequences.
2020-10-15 16:37 ` Navare, Manasi
@ 2020-10-16 16:06 ` Ville Syrjälä
2020-10-16 18:17 ` Navare, Manasi
0 siblings, 1 reply; 50+ messages in thread
From: Ville Syrjälä @ 2020-10-16 16:06 UTC (permalink / raw)
To: Navare, Manasi; +Cc: intel-gfx
On Thu, Oct 15, 2020 at 09:37:47AM -0700, Navare, Manasi wrote:
> On Thu, Oct 15, 2020 at 04:07:05PM +0300, Ville Syrjälä wrote:
> > On Thu, Oct 08, 2020 at 02:45:30PM -0700, Manasi Navare wrote:
> > > @@ -4504,6 +4514,29 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
> > > default:
> > > break;
> > > }
> > > +}
> > > +
> > > +void intel_ddi_get_config(struct intel_encoder *encoder,
> > > + struct intel_crtc_state *pipe_config)
> > > +{
> > > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > > + enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
> > > +
> > > + /* XXX: DSI transcoder paranoia */
> > > + if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
> > > + return;
> > > +
> > > + intel_ddi_read_func_ctl(encoder, pipe_config);
> > > + if (pipe_config->bigjoiner_slave) {
> > > + /* read out pipe settings from master */
> > > + enum transcoder save = pipe_config->cpu_transcoder;
> > > +
> > > + /* Our own transcoder needs to be disabled when reading it in intel_ddi_read_func_ctl() */
> > > + WARN_ON(pipe_config->output_types);
> > > + pipe_config->cpu_transcoder = (enum transcoder)pipe_config->bigjoiner_linked_crtc->pipe;
> > > + intel_ddi_read_func_ctl(encoder, pipe_config);
> > > + pipe_config->cpu_transcoder = save;
> > > + }
> >
> > This stuff is rather horrible. Shouldn't both pipes be using the
> > same transcoder anyway? If so, is this stuff here just because
> > we've miscalculated cpu_transcoder for the slave?
>
> Well honestly @Maarten wrote this and I believe had several iterations of reviews with you.
> So he can explain better.
> My understanding so far was that there is no encoder /transcoder for slave and thats
> why for bigjoiner_slave we actually read stuff from master
> So why is this wrong?
>
> >
> > >
> > > pipe_config->has_audio =
> > > intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
> > > @@ -4529,7 +4562,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
> > > dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
> > > }
> > >
> > > - intel_ddi_clock_get(encoder, pipe_config);
> > > + if (!pipe_config->bigjoiner_slave)
> > > + intel_ddi_clock_get(encoder, pipe_config);
> > >
> > > if (IS_GEN9_LP(dev_priv))
> > > pipe_config->lane_lat_optim_mask =
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > index 37b56f4c2401..faf8bf757bed 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -7125,6 +7125,45 @@ static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
> > > intel_de_write(dev_priv, reg, val);
> > > }
> > >
> > > +static void tgl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
> > > + const struct intel_crtc_state *crtc_state)
> > > +{
> > > + struct intel_crtc *master = to_intel_crtc(crtc_state->uapi.crtc);
> > > + struct intel_crtc_state *master_crtc_state;
> > > + struct drm_connector_state *conn_state;
> > > + struct drm_connector *conn;
> > > + struct intel_encoder *encoder = NULL;
> > > + int i;
> > > +
> > > + if (crtc_state->bigjoiner_slave)
> > > + master = crtc_state->bigjoiner_linked_crtc;
> > > +
> > > + master_crtc_state = intel_atomic_get_new_crtc_state(state, master);
> > > +
> > > + for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
> > > + if (conn_state->crtc != &master->base)
> > > + continue;
> > > +
> > > + encoder = to_intel_encoder(conn_state->best_encoder);
> > > + break;
> > > + }
> > > +
> > > + if (!crtc_state->bigjoiner_slave) {
> > > + /* need to enable VDSC, which we skipped in pre-enable */
> > > + intel_dsc_enable(encoder, crtc_state);
> > > + } else {
> > > + /*
> > > + * Enable sequence steps 1-7 on bigjoiner master
> > > + */
> > > + intel_encoders_pre_pll_enable(state, master);
> > > + intel_enable_shared_dpll(master_crtc_state);
> > > + intel_encoders_pre_enable(state, master);
> > > +
> > > + /* and DSC on slave */
> > > + intel_dsc_enable(NULL, crtc_state);
> > > + }
> > > +}
> > > +
> > > static void hsw_crtc_enable(struct intel_atomic_state *state,
> > > struct intel_crtc *crtc)
> > > {
> > > @@ -7138,34 +7177,39 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
> > > if (drm_WARN_ON(&dev_priv->drm, crtc->active))
> > > return;
> > >
> > > - intel_encoders_pre_pll_enable(state, crtc);
> > > -
> > > - if (new_crtc_state->shared_dpll)
> > > - intel_enable_shared_dpll(new_crtc_state);
> > > + if (!new_crtc_state->bigjoiner) {
> > > + intel_encoders_pre_pll_enable(state, crtc);
> > >
> > > - intel_encoders_pre_enable(state, crtc);
> > > + if (new_crtc_state->shared_dpll)
> > > + intel_enable_shared_dpll(new_crtc_state);
> > >
> > > - if (!transcoder_is_dsi(cpu_transcoder))
> > > - intel_set_transcoder_timings(new_crtc_state);
> > > + intel_encoders_pre_enable(state, crtc);
> > > + } else {
> > > + tgl_ddi_bigjoiner_pre_enable(state, new_crtc_state);
> > > + }
> > >
> > > intel_set_pipe_src_size(new_crtc_state);
> > > + if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
> > > + bdw_set_pipemisc(new_crtc_state);
> > >
> > > - if (cpu_transcoder != TRANSCODER_EDP &&
> > > - !transcoder_is_dsi(cpu_transcoder))
> > > - intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
> > > - new_crtc_state->pixel_multiplier - 1);
> > > + if (!new_crtc_state->bigjoiner_slave && !transcoder_is_dsi(cpu_transcoder)) {
> > > + if (!transcoder_is_dsi(cpu_transcoder))
> > > + intel_set_transcoder_timings(new_crtc_state);
> > >
> > > - if (new_crtc_state->has_pch_encoder)
> > > - intel_cpu_transcoder_set_m_n(new_crtc_state,
> > > - &new_crtc_state->fdi_m_n, NULL);
> > > + if (cpu_transcoder != TRANSCODER_EDP &&
> > > + !transcoder_is_dsi(cpu_transcoder))
> > > + intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
> > > + new_crtc_state->pixel_multiplier - 1);
> > > +
> > > + if (new_crtc_state->has_pch_encoder)
> > > + intel_cpu_transcoder_set_m_n(new_crtc_state,
> > > + &new_crtc_state->fdi_m_n, NULL);
> > >
> > > - if (!transcoder_is_dsi(cpu_transcoder)) {
> > > hsw_set_frame_start_delay(new_crtc_state);
> > > - hsw_set_pipeconf(new_crtc_state);
> > > }
> > >
> > > - if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
> > > - bdw_set_pipemisc(new_crtc_state);
> > > + if (!transcoder_is_dsi(cpu_transcoder))
> > > + hsw_set_pipeconf(new_crtc_state);
> > >
> > > crtc->active = true;
> > >
> > > @@ -7201,6 +7245,11 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
> > > if (INTEL_GEN(dev_priv) >= 11)
> > > icl_pipe_mbus_enable(crtc);
> > >
> > > + if (new_crtc_state->bigjoiner_slave) {
> > > + trace_intel_pipe_enable(crtc);
> > > + intel_crtc_vblank_on(new_crtc_state);
> > > + }
> > > +
> > > intel_encoders_enable(state, crtc);
> > >
> > > if (psl_clkgate_wa) {
> > > @@ -7495,6 +7544,9 @@ static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
> > > if (crtc_state->shared_dpll)
> > > mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);
> > >
> > > + if (crtc_state->dsc.compression_enable)
> > > + mask |= BIT_ULL(intel_dsc_power_domain(crtc_state));
> > > +
> > > return mask;
> > > }
> > >
> > > @@ -8113,6 +8165,30 @@ static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
> > > pfit_w * pfit_h);
> > > }
> > >
> > > +static void intel_encoder_get_config(struct intel_encoder *encoder,
> > > + struct intel_crtc_state *crtc_state)
> > > +{
> > > + struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
> > > +
> > > + encoder->get_config(encoder, crtc_state);
> > > +
> > > + *pipe_mode = crtc_state->hw.adjusted_mode;
> > > + if (crtc_state->bigjoiner) {
> > > + /*
> > > + * transcoder is programmed to the full mode,
> > > + * but pipe timings are half of the transcoder mode
> > > + */
> > > + pipe_mode->crtc_hdisplay /= 2;
> > > + pipe_mode->crtc_hblank_start /= 2;
> > > + pipe_mode->crtc_hblank_end /= 2;
> > > + pipe_mode->crtc_hsync_start /= 2;
> > > + pipe_mode->crtc_hsync_end /= 2;
> > > + pipe_mode->crtc_htotal /= 2;
> > > + pipe_mode->crtc_hskew /= 2;
> > > + pipe_mode->crtc_clock /= 2;
> > > + }
> > > +}
> > > +
> > > static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
> > > {
> > > struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> > > @@ -9027,20 +9103,22 @@ static void intel_get_pipe_src_size(struct intel_crtc *crtc,
> > > void intel_mode_from_pipe_config(struct drm_display_mode *mode,
> > > struct intel_crtc_state *pipe_config)
> > > {
> > > - mode->hdisplay = pipe_config->hw.adjusted_mode.crtc_hdisplay;
> > > - mode->htotal = pipe_config->hw.adjusted_mode.crtc_htotal;
> > > - mode->hsync_start = pipe_config->hw.adjusted_mode.crtc_hsync_start;
> > > - mode->hsync_end = pipe_config->hw.adjusted_mode.crtc_hsync_end;
> > > + struct drm_display_mode *hw_mode = &pipe_config->hw.adjusted_mode;
> > > +
> > > + mode->hdisplay = hw_mode->crtc_hdisplay;
> > > + mode->htotal = hw_mode->crtc_htotal;
> > > + mode->hsync_start = hw_mode->crtc_hsync_start;
> > > + mode->hsync_end = hw_mode->crtc_hsync_end;
> > >
> > > - mode->vdisplay = pipe_config->hw.adjusted_mode.crtc_vdisplay;
> > > - mode->vtotal = pipe_config->hw.adjusted_mode.crtc_vtotal;
> > > - mode->vsync_start = pipe_config->hw.adjusted_mode.crtc_vsync_start;
> > > - mode->vsync_end = pipe_config->hw.adjusted_mode.crtc_vsync_end;
> > > + mode->vdisplay = hw_mode->crtc_vdisplay;
> > > + mode->vtotal = hw_mode->crtc_vtotal;
> > > + mode->vsync_start = hw_mode->crtc_vsync_start;
> > > + mode->vsync_end = hw_mode->crtc_vsync_end;
> > >
> > > - mode->flags = pipe_config->hw.adjusted_mode.flags;
> > > + mode->flags = hw_mode->flags;
> > > mode->type = DRM_MODE_TYPE_DRIVER;
> > >
> > > - mode->clock = pipe_config->hw.adjusted_mode.crtc_clock;
> > > + mode->clock = hw_mode->crtc_clock;
> > >
> > > drm_mode_set_name(mode);
> > > }
> > > @@ -11207,6 +11285,9 @@ static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
> > > } else {
> > > tmp = intel_de_read(dev_priv,
> > > TRANS_DDI_FUNC_CTL(cpu_transcoder));
> > > + if (!(tmp & TRANS_DDI_FUNC_ENABLE))
> > > + return;
> > > +
> > > if (INTEL_GEN(dev_priv) >= 12)
> > > port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
> > > else
> > > @@ -11279,12 +11360,20 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
> > > drm_WARN_ON(&dev_priv->drm, active);
> > > active = true;
> > > }
> > > + intel_dsc_get_config(pipe_config);
> > >
> > > - if (!active)
> > > - goto out;
> > > + if (!active) {
> > > + /* bigjoiner slave doesn't enable transcoder */
> > > + if (!pipe_config->bigjoiner_slave)
> > > + goto out;
> > >
> > > - if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
> > > - INTEL_GEN(dev_priv) >= 11) {
> > > + active = true;
> > > + pipe_config->pixel_multiplier = 1;
> > > +
> > > + /* we cannot read out most state, so don't bother.. */
> > > + pipe_config->quirks |= PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE;
> > > + } else if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
> > > + INTEL_GEN(dev_priv) >= 11) {
> > > hsw_get_ddi_port_state(crtc, pipe_config);
> > > intel_get_transcoder_timings(crtc, pipe_config);
> > > }
> > > @@ -11370,8 +11459,11 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
> > > }
> > > }
> > >
> > > - if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
> > > - !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
> > > + if (pipe_config->bigjoiner_slave) {
> > > + /* Cannot be read out as a slave, set to 0. */
> > > + pipe_config->pixel_multiplier = 0;
> > > + } else if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
> > > + !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
> > > pipe_config->pixel_multiplier =
> > > intel_de_read(dev_priv,
> > > PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
> > > @@ -12386,7 +12478,7 @@ intel_encoder_current_mode(struct intel_encoder *encoder)
> > > return NULL;
> > > }
> > >
> > > - encoder->get_config(encoder, crtc_state);
> > > + intel_encoder_get_config(encoder, crtc_state);
> > >
> > > intel_mode_from_pipe_config(mode, crtc_state);
> > >
> > > @@ -13385,12 +13477,15 @@ intel_crtc_copy_uapi_to_hw_state(struct intel_atomic_state *state,
> > > intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc_state);
> > > }
> > >
> > > -static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
> > > +static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state,
> > > + struct drm_display_mode *user_mode)
> > > {
> > > - crtc_state->uapi.enable = crtc_state->hw.enable;
> > > - crtc_state->uapi.active = crtc_state->hw.active;
> > > - drm_WARN_ON(crtc_state->uapi.crtc->dev,
> > > - drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);
> > > + if (!crtc_state->bigjoiner_slave) {
> > > + crtc_state->uapi.enable = crtc_state->hw.enable;
> > > + crtc_state->uapi.active = crtc_state->hw.active;
> > > + drm_WARN_ON(crtc_state->uapi.crtc->dev,
> > > + drm_atomic_set_mode_for_crtc(&crtc_state->uapi, user_mode) < 0);
> > > + }
> > >
> > > crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
> > >
> > > @@ -14027,21 +14122,42 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> > >
> > > PIPE_CONF_CHECK_X(output_types);
> > >
> > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
> > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
> > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
> > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
> > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
> > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
> > > -
> > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
> > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
> > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
> > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
> > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
> > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
> > > -
> > > - PIPE_CONF_CHECK_I(pixel_multiplier);
> > > + if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) {
> > > + /* bigjoiner mode = transcoder mode / 2, for calculations */
> > > + PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);
> > > + PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_htotal);
> > > + PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vdisplay);
> > > + PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vtotal);
> > > +
> > > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
> > > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
> > > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
> > > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
> > > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
> > > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
> > > +
> > > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
> > > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
> > > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
> > > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
> > > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
> > > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
> > > +
> > > + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > > + DRM_MODE_FLAG_INTERLACE);
> > > +
> > > + if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
> > > + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > > + DRM_MODE_FLAG_PHSYNC);
> > > + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > > + DRM_MODE_FLAG_NHSYNC);
> > > + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > > + DRM_MODE_FLAG_PVSYNC);
> > > + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > > + DRM_MODE_FLAG_NVSYNC);
> > > + }
> > > + PIPE_CONF_CHECK_I(pixel_multiplier);
> > > + }
> > > PIPE_CONF_CHECK_I(output_format);
> > > PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
> > > if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
> > > @@ -14051,24 +14167,11 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> > > PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
> > > PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
> > > PIPE_CONF_CHECK_BOOL(has_infoframe);
> > > - PIPE_CONF_CHECK_BOOL(fec_enable);
> > > + if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE))
> > > + PIPE_CONF_CHECK_BOOL(fec_enable);
> > >
> > > PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
> > >
> > > - PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > > - DRM_MODE_FLAG_INTERLACE);
> > > -
> > > - if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
> > > - PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > > - DRM_MODE_FLAG_PHSYNC);
> > > - PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > > - DRM_MODE_FLAG_NHSYNC);
> > > - PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > > - DRM_MODE_FLAG_PVSYNC);
> > > - PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > > - DRM_MODE_FLAG_NVSYNC);
> > > - }
> > > -
> > > PIPE_CONF_CHECK_X(gmch_pfit.control);
> > > /* pfit ratios are autocomputed by the hw on gen4+ */
> > > if (INTEL_GEN(dev_priv) < 4)
> > > @@ -14094,7 +14197,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> > > }
> > >
> > > PIPE_CONF_CHECK_I(scaler_state.scaler_id);
> > > - PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
> > > + if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE))
> > > + PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
> > >
> > > PIPE_CONF_CHECK_X(gamma_mode);
> > > if (IS_CHERRYVIEW(dev_priv))
> > > @@ -14115,48 +14219,51 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> > > PIPE_CONF_CHECK_BOOL(double_wide);
> > >
> > > PIPE_CONF_CHECK_P(shared_dpll);
> > > - PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
> > > - PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
> > > - PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
> > > - PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
> > > - PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
> > > - PIPE_CONF_CHECK_X(dpll_hw_state.spll);
> > > - PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
> > > - PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
> > > - PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
> > > - PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
> > > - PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
> > > - PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
> > > - PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
> > > - PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
> > > - PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
> > > - PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
> > > - PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
> > > - PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
> > > - PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
> > > - PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
> > > - PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
> > > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
> > > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
> > > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
> > > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
> > > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
> > > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
> > > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
> > > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
> > > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
> > > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
> > > -
> > > - PIPE_CONF_CHECK_X(dsi_pll.ctrl);
> > > - PIPE_CONF_CHECK_X(dsi_pll.div);
> > > -
> > > - if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
> > > - PIPE_CONF_CHECK_I(pipe_bpp);
> > > -
> > > - PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
> > > - PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
> > > -
> > > - PIPE_CONF_CHECK_I(min_voltage_level);
> > > + if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) {
> >
> > This looks super sketchy. I don't see why we'd want to skip all this
> > state checking for bigjoiner.
>
> For big joiner slave we do not enable plls and hence it doesnt make sense
> to compare the hw state of plls for big joiner slave
This is skipping far more than just plls. Also I think the state should
still match whether it has its own pll or not. I kinda think we should
have a pll for both pipes actually since that would avoid all this
special case code that will just end up breaking all the time.
>
> Manasi
>
> >
> > > + PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
> > > + PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
> > > + PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
> > > + PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
> > > + PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
> > > + PIPE_CONF_CHECK_X(dpll_hw_state.spll);
> > > + PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
> > > + PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
> > > + PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
> > > + PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
> > > + PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
> > > + PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
> > > + PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
> > > + PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
> > > + PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
> > > + PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
> > > + PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
> > > + PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
> > > + PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
> > > + PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
> > > + PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
> > > + PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
> > > + PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
> > > + PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
> > > + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
> > > + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
> > > + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
> > > + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
> > > + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
> > > + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
> > > + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
> > > +
> > > + PIPE_CONF_CHECK_X(dsi_pll.ctrl);
> > > + PIPE_CONF_CHECK_X(dsi_pll.div);
> > > +
> > > + if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
> > > + PIPE_CONF_CHECK_I(pipe_bpp);
> > > +
> > > + PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
> > > + PIPE_CONF_CHECK_CLOCK_FUZZY(hw.pipe_mode.crtc_clock);
> > > + PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
> > > +
> > > + PIPE_CONF_CHECK_I(min_voltage_level);
> > > + }
> > >
> > > PIPE_CONF_CHECK_X(infoframes.enable);
> > > PIPE_CONF_CHECK_X(infoframes.gcp);
> > --
> > Ville Syrjälä
> > Intel
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v10 06/11] drm/i915: Enable big joiner support in enable and disable sequences.
2020-10-16 16:06 ` Ville Syrjälä
@ 2020-10-16 18:17 ` Navare, Manasi
2020-10-16 18:50 ` Ville Syrjälä
0 siblings, 1 reply; 50+ messages in thread
From: Navare, Manasi @ 2020-10-16 18:17 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Fri, Oct 16, 2020 at 07:06:20PM +0300, Ville Syrjälä wrote:
> On Thu, Oct 15, 2020 at 09:37:47AM -0700, Navare, Manasi wrote:
> > On Thu, Oct 15, 2020 at 04:07:05PM +0300, Ville Syrjälä wrote:
> > > On Thu, Oct 08, 2020 at 02:45:30PM -0700, Manasi Navare wrote:
> > > > @@ -4504,6 +4514,29 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
> > > > default:
> > > > break;
> > > > }
> > > > +}
> > > > +
> > > > +void intel_ddi_get_config(struct intel_encoder *encoder,
> > > > + struct intel_crtc_state *pipe_config)
> > > > +{
> > > > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > > > + enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
> > > > +
> > > > + /* XXX: DSI transcoder paranoia */
> > > > + if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
> > > > + return;
> > > > +
> > > > + intel_ddi_read_func_ctl(encoder, pipe_config);
> > > > + if (pipe_config->bigjoiner_slave) {
> > > > + /* read out pipe settings from master */
> > > > + enum transcoder save = pipe_config->cpu_transcoder;
> > > > +
> > > > + /* Our own transcoder needs to be disabled when reading it in intel_ddi_read_func_ctl() */
> > > > + WARN_ON(pipe_config->output_types);
> > > > + pipe_config->cpu_transcoder = (enum transcoder)pipe_config->bigjoiner_linked_crtc->pipe;
> > > > + intel_ddi_read_func_ctl(encoder, pipe_config);
> > > > + pipe_config->cpu_transcoder = save;
> > > > + }
> > >
> > > This stuff is rather horrible. Shouldn't both pipes be using the
> > > same transcoder anyway? If so, is this stuff here just because
> > > we've miscalculated cpu_transcoder for the slave?
> >
> > Well honestly @Maarten wrote this and I believe had several iterations of reviews with you.
> > So he can explain better.
> > My understanding so far was that there is no encoder /transcoder for slave and thats
> > why for bigjoiner_slave we actually read stuff from master
> > So why is this wrong?
> >
> > >
> > > >
> > > > pipe_config->has_audio =
> > > > intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
> > > > @@ -4529,7 +4562,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
> > > > dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
> > > > }
> > > >
> > > > - intel_ddi_clock_get(encoder, pipe_config);
> > > > + if (!pipe_config->bigjoiner_slave)
> > > > + intel_ddi_clock_get(encoder, pipe_config);
> > > >
> > > > if (IS_GEN9_LP(dev_priv))
> > > > pipe_config->lane_lat_optim_mask =
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > > index 37b56f4c2401..faf8bf757bed 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > @@ -7125,6 +7125,45 @@ static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
> > > > intel_de_write(dev_priv, reg, val);
> > > > }
> > > >
> > > > +static void tgl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
> > > > + const struct intel_crtc_state *crtc_state)
> > > > +{
> > > > + struct intel_crtc *master = to_intel_crtc(crtc_state->uapi.crtc);
> > > > + struct intel_crtc_state *master_crtc_state;
> > > > + struct drm_connector_state *conn_state;
> > > > + struct drm_connector *conn;
> > > > + struct intel_encoder *encoder = NULL;
> > > > + int i;
> > > > +
> > > > + if (crtc_state->bigjoiner_slave)
> > > > + master = crtc_state->bigjoiner_linked_crtc;
> > > > +
> > > > + master_crtc_state = intel_atomic_get_new_crtc_state(state, master);
> > > > +
> > > > + for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
> > > > + if (conn_state->crtc != &master->base)
> > > > + continue;
> > > > +
> > > > + encoder = to_intel_encoder(conn_state->best_encoder);
> > > > + break;
> > > > + }
> > > > +
> > > > + if (!crtc_state->bigjoiner_slave) {
> > > > + /* need to enable VDSC, which we skipped in pre-enable */
> > > > + intel_dsc_enable(encoder, crtc_state);
> > > > + } else {
> > > > + /*
> > > > + * Enable sequence steps 1-7 on bigjoiner master
> > > > + */
> > > > + intel_encoders_pre_pll_enable(state, master);
> > > > + intel_enable_shared_dpll(master_crtc_state);
> > > > + intel_encoders_pre_enable(state, master);
> > > > +
> > > > + /* and DSC on slave */
> > > > + intel_dsc_enable(NULL, crtc_state);
> > > > + }
> > > > +}
> > > > +
> > > > static void hsw_crtc_enable(struct intel_atomic_state *state,
> > > > struct intel_crtc *crtc)
> > > > {
> > > > @@ -7138,34 +7177,39 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
> > > > if (drm_WARN_ON(&dev_priv->drm, crtc->active))
> > > > return;
> > > >
> > > > - intel_encoders_pre_pll_enable(state, crtc);
> > > > -
> > > > - if (new_crtc_state->shared_dpll)
> > > > - intel_enable_shared_dpll(new_crtc_state);
> > > > + if (!new_crtc_state->bigjoiner) {
> > > > + intel_encoders_pre_pll_enable(state, crtc);
> > > >
> > > > - intel_encoders_pre_enable(state, crtc);
> > > > + if (new_crtc_state->shared_dpll)
> > > > + intel_enable_shared_dpll(new_crtc_state);
> > > >
> > > > - if (!transcoder_is_dsi(cpu_transcoder))
> > > > - intel_set_transcoder_timings(new_crtc_state);
> > > > + intel_encoders_pre_enable(state, crtc);
> > > > + } else {
> > > > + tgl_ddi_bigjoiner_pre_enable(state, new_crtc_state);
> > > > + }
> > > >
> > > > intel_set_pipe_src_size(new_crtc_state);
> > > > + if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
> > > > + bdw_set_pipemisc(new_crtc_state);
> > > >
> > > > - if (cpu_transcoder != TRANSCODER_EDP &&
> > > > - !transcoder_is_dsi(cpu_transcoder))
> > > > - intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
> > > > - new_crtc_state->pixel_multiplier - 1);
> > > > + if (!new_crtc_state->bigjoiner_slave && !transcoder_is_dsi(cpu_transcoder)) {
> > > > + if (!transcoder_is_dsi(cpu_transcoder))
> > > > + intel_set_transcoder_timings(new_crtc_state);
> > > >
> > > > - if (new_crtc_state->has_pch_encoder)
> > > > - intel_cpu_transcoder_set_m_n(new_crtc_state,
> > > > - &new_crtc_state->fdi_m_n, NULL);
> > > > + if (cpu_transcoder != TRANSCODER_EDP &&
> > > > + !transcoder_is_dsi(cpu_transcoder))
> > > > + intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
> > > > + new_crtc_state->pixel_multiplier - 1);
> > > > +
> > > > + if (new_crtc_state->has_pch_encoder)
> > > > + intel_cpu_transcoder_set_m_n(new_crtc_state,
> > > > + &new_crtc_state->fdi_m_n, NULL);
> > > >
> > > > - if (!transcoder_is_dsi(cpu_transcoder)) {
> > > > hsw_set_frame_start_delay(new_crtc_state);
> > > > - hsw_set_pipeconf(new_crtc_state);
> > > > }
> > > >
> > > > - if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
> > > > - bdw_set_pipemisc(new_crtc_state);
> > > > + if (!transcoder_is_dsi(cpu_transcoder))
> > > > + hsw_set_pipeconf(new_crtc_state);
> > > >
> > > > crtc->active = true;
> > > >
> > > > @@ -7201,6 +7245,11 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
> > > > if (INTEL_GEN(dev_priv) >= 11)
> > > > icl_pipe_mbus_enable(crtc);
> > > >
> > > > + if (new_crtc_state->bigjoiner_slave) {
> > > > + trace_intel_pipe_enable(crtc);
> > > > + intel_crtc_vblank_on(new_crtc_state);
> > > > + }
> > > > +
> > > > intel_encoders_enable(state, crtc);
> > > >
> > > > if (psl_clkgate_wa) {
> > > > @@ -7495,6 +7544,9 @@ static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
> > > > if (crtc_state->shared_dpll)
> > > > mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);
> > > >
> > > > + if (crtc_state->dsc.compression_enable)
> > > > + mask |= BIT_ULL(intel_dsc_power_domain(crtc_state));
> > > > +
> > > > return mask;
> > > > }
> > > >
> > > > @@ -8113,6 +8165,30 @@ static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
> > > > pfit_w * pfit_h);
> > > > }
> > > >
> > > > +static void intel_encoder_get_config(struct intel_encoder *encoder,
> > > > + struct intel_crtc_state *crtc_state)
> > > > +{
> > > > + struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
> > > > +
> > > > + encoder->get_config(encoder, crtc_state);
> > > > +
> > > > + *pipe_mode = crtc_state->hw.adjusted_mode;
> > > > + if (crtc_state->bigjoiner) {
> > > > + /*
> > > > + * transcoder is programmed to the full mode,
> > > > + * but pipe timings are half of the transcoder mode
> > > > + */
> > > > + pipe_mode->crtc_hdisplay /= 2;
> > > > + pipe_mode->crtc_hblank_start /= 2;
> > > > + pipe_mode->crtc_hblank_end /= 2;
> > > > + pipe_mode->crtc_hsync_start /= 2;
> > > > + pipe_mode->crtc_hsync_end /= 2;
> > > > + pipe_mode->crtc_htotal /= 2;
> > > > + pipe_mode->crtc_hskew /= 2;
> > > > + pipe_mode->crtc_clock /= 2;
> > > > + }
> > > > +}
> > > > +
> > > > static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
> > > > {
> > > > struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> > > > @@ -9027,20 +9103,22 @@ static void intel_get_pipe_src_size(struct intel_crtc *crtc,
> > > > void intel_mode_from_pipe_config(struct drm_display_mode *mode,
> > > > struct intel_crtc_state *pipe_config)
> > > > {
> > > > - mode->hdisplay = pipe_config->hw.adjusted_mode.crtc_hdisplay;
> > > > - mode->htotal = pipe_config->hw.adjusted_mode.crtc_htotal;
> > > > - mode->hsync_start = pipe_config->hw.adjusted_mode.crtc_hsync_start;
> > > > - mode->hsync_end = pipe_config->hw.adjusted_mode.crtc_hsync_end;
> > > > + struct drm_display_mode *hw_mode = &pipe_config->hw.adjusted_mode;
> > > > +
> > > > + mode->hdisplay = hw_mode->crtc_hdisplay;
> > > > + mode->htotal = hw_mode->crtc_htotal;
> > > > + mode->hsync_start = hw_mode->crtc_hsync_start;
> > > > + mode->hsync_end = hw_mode->crtc_hsync_end;
> > > >
> > > > - mode->vdisplay = pipe_config->hw.adjusted_mode.crtc_vdisplay;
> > > > - mode->vtotal = pipe_config->hw.adjusted_mode.crtc_vtotal;
> > > > - mode->vsync_start = pipe_config->hw.adjusted_mode.crtc_vsync_start;
> > > > - mode->vsync_end = pipe_config->hw.adjusted_mode.crtc_vsync_end;
> > > > + mode->vdisplay = hw_mode->crtc_vdisplay;
> > > > + mode->vtotal = hw_mode->crtc_vtotal;
> > > > + mode->vsync_start = hw_mode->crtc_vsync_start;
> > > > + mode->vsync_end = hw_mode->crtc_vsync_end;
> > > >
> > > > - mode->flags = pipe_config->hw.adjusted_mode.flags;
> > > > + mode->flags = hw_mode->flags;
> > > > mode->type = DRM_MODE_TYPE_DRIVER;
> > > >
> > > > - mode->clock = pipe_config->hw.adjusted_mode.crtc_clock;
> > > > + mode->clock = hw_mode->crtc_clock;
> > > >
> > > > drm_mode_set_name(mode);
> > > > }
> > > > @@ -11207,6 +11285,9 @@ static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
> > > > } else {
> > > > tmp = intel_de_read(dev_priv,
> > > > TRANS_DDI_FUNC_CTL(cpu_transcoder));
> > > > + if (!(tmp & TRANS_DDI_FUNC_ENABLE))
> > > > + return;
> > > > +
> > > > if (INTEL_GEN(dev_priv) >= 12)
> > > > port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
> > > > else
> > > > @@ -11279,12 +11360,20 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
> > > > drm_WARN_ON(&dev_priv->drm, active);
> > > > active = true;
> > > > }
> > > > + intel_dsc_get_config(pipe_config);
> > > >
> > > > - if (!active)
> > > > - goto out;
> > > > + if (!active) {
> > > > + /* bigjoiner slave doesn't enable transcoder */
> > > > + if (!pipe_config->bigjoiner_slave)
> > > > + goto out;
> > > >
> > > > - if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
> > > > - INTEL_GEN(dev_priv) >= 11) {
> > > > + active = true;
> > > > + pipe_config->pixel_multiplier = 1;
> > > > +
> > > > + /* we cannot read out most state, so don't bother.. */
> > > > + pipe_config->quirks |= PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE;
> > > > + } else if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
> > > > + INTEL_GEN(dev_priv) >= 11) {
> > > > hsw_get_ddi_port_state(crtc, pipe_config);
> > > > intel_get_transcoder_timings(crtc, pipe_config);
> > > > }
> > > > @@ -11370,8 +11459,11 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
> > > > }
> > > > }
> > > >
> > > > - if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
> > > > - !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
> > > > + if (pipe_config->bigjoiner_slave) {
> > > > + /* Cannot be read out as a slave, set to 0. */
> > > > + pipe_config->pixel_multiplier = 0;
> > > > + } else if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
> > > > + !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
> > > > pipe_config->pixel_multiplier =
> > > > intel_de_read(dev_priv,
> > > > PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
> > > > @@ -12386,7 +12478,7 @@ intel_encoder_current_mode(struct intel_encoder *encoder)
> > > > return NULL;
> > > > }
> > > >
> > > > - encoder->get_config(encoder, crtc_state);
> > > > + intel_encoder_get_config(encoder, crtc_state);
> > > >
> > > > intel_mode_from_pipe_config(mode, crtc_state);
> > > >
> > > > @@ -13385,12 +13477,15 @@ intel_crtc_copy_uapi_to_hw_state(struct intel_atomic_state *state,
> > > > intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc_state);
> > > > }
> > > >
> > > > -static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
> > > > +static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state,
> > > > + struct drm_display_mode *user_mode)
> > > > {
> > > > - crtc_state->uapi.enable = crtc_state->hw.enable;
> > > > - crtc_state->uapi.active = crtc_state->hw.active;
> > > > - drm_WARN_ON(crtc_state->uapi.crtc->dev,
> > > > - drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);
> > > > + if (!crtc_state->bigjoiner_slave) {
> > > > + crtc_state->uapi.enable = crtc_state->hw.enable;
> > > > + crtc_state->uapi.active = crtc_state->hw.active;
> > > > + drm_WARN_ON(crtc_state->uapi.crtc->dev,
> > > > + drm_atomic_set_mode_for_crtc(&crtc_state->uapi, user_mode) < 0);
> > > > + }
> > > >
> > > > crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
> > > >
> > > > @@ -14027,21 +14122,42 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> > > >
> > > > PIPE_CONF_CHECK_X(output_types);
> > > >
> > > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
> > > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
> > > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
> > > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
> > > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
> > > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
> > > > -
> > > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
> > > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
> > > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
> > > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
> > > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
> > > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
> > > > -
> > > > - PIPE_CONF_CHECK_I(pixel_multiplier);
> > > > + if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) {
> > > > + /* bigjoiner mode = transcoder mode / 2, for calculations */
> > > > + PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);
> > > > + PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_htotal);
> > > > + PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vdisplay);
> > > > + PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vtotal);
> > > > +
> > > > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
> > > > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
> > > > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
> > > > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
> > > > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
> > > > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
> > > > +
> > > > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
> > > > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
> > > > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
> > > > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
> > > > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
> > > > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
> > > > +
> > > > + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > > > + DRM_MODE_FLAG_INTERLACE);
> > > > +
> > > > + if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
> > > > + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > > > + DRM_MODE_FLAG_PHSYNC);
> > > > + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > > > + DRM_MODE_FLAG_NHSYNC);
> > > > + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > > > + DRM_MODE_FLAG_PVSYNC);
> > > > + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > > > + DRM_MODE_FLAG_NVSYNC);
> > > > + }
> > > > + PIPE_CONF_CHECK_I(pixel_multiplier);
> > > > + }
> > > > PIPE_CONF_CHECK_I(output_format);
> > > > PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
> > > > if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
> > > > @@ -14051,24 +14167,11 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> > > > PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
> > > > PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
> > > > PIPE_CONF_CHECK_BOOL(has_infoframe);
> > > > - PIPE_CONF_CHECK_BOOL(fec_enable);
> > > > + if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE))
> > > > + PIPE_CONF_CHECK_BOOL(fec_enable);
> > > >
> > > > PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
> > > >
> > > > - PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > > > - DRM_MODE_FLAG_INTERLACE);
> > > > -
> > > > - if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
> > > > - PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > > > - DRM_MODE_FLAG_PHSYNC);
> > > > - PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > > > - DRM_MODE_FLAG_NHSYNC);
> > > > - PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > > > - DRM_MODE_FLAG_PVSYNC);
> > > > - PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > > > - DRM_MODE_FLAG_NVSYNC);
> > > > - }
> > > > -
> > > > PIPE_CONF_CHECK_X(gmch_pfit.control);
> > > > /* pfit ratios are autocomputed by the hw on gen4+ */
> > > > if (INTEL_GEN(dev_priv) < 4)
> > > > @@ -14094,7 +14197,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> > > > }
> > > >
> > > > PIPE_CONF_CHECK_I(scaler_state.scaler_id);
> > > > - PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
> > > > + if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE))
> > > > + PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
> > > >
> > > > PIPE_CONF_CHECK_X(gamma_mode);
> > > > if (IS_CHERRYVIEW(dev_priv))
> > > > @@ -14115,48 +14219,51 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> > > > PIPE_CONF_CHECK_BOOL(double_wide);
> > > >
> > > > PIPE_CONF_CHECK_P(shared_dpll);
> > > > - PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
> > > > - PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
> > > > - PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
> > > > - PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
> > > > - PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
> > > > - PIPE_CONF_CHECK_X(dpll_hw_state.spll);
> > > > - PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
> > > > - PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
> > > > - PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
> > > > - PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
> > > > - PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
> > > > - PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
> > > > - PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
> > > > - PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
> > > > - PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
> > > > - PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
> > > > - PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
> > > > - PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
> > > > - PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
> > > > - PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
> > > > - PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
> > > > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
> > > > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
> > > > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
> > > > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
> > > > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
> > > > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
> > > > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
> > > > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
> > > > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
> > > > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
> > > > -
> > > > - PIPE_CONF_CHECK_X(dsi_pll.ctrl);
> > > > - PIPE_CONF_CHECK_X(dsi_pll.div);
> > > > -
> > > > - if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
> > > > - PIPE_CONF_CHECK_I(pipe_bpp);
> > > > -
> > > > - PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
> > > > - PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
> > > > -
> > > > - PIPE_CONF_CHECK_I(min_voltage_level);
> > > > + if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) {
> > >
> > > This looks super sketchy. I don't see why we'd want to skip all this
> > > state checking for bigjoiner.
> >
> > For big joiner slave we do not enable plls and hence it doesnt make sense
> > to compare the hw state of plls for big joiner slave
>
> This is skipping far more than just plls. Also I think the state should
> still match whether it has its own pll or not. I kinda think we should
> have a pll for both pipes actually since that would avoid all this
> special case code that will just end up breaking all the time.
Only the adjusted mode and pipe mode and port clock can be taken out of this condition.
But we cannot have a pll for the slave that contradicts the Bspec modeset enable sequence.
Manasi
>
> >
> > Manasi
> >
> > >
> > > > + PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
> > > > + PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
> > > > + PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
> > > > + PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
> > > > + PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
> > > > + PIPE_CONF_CHECK_X(dpll_hw_state.spll);
> > > > + PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
> > > > + PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
> > > > + PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
> > > > + PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
> > > > + PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
> > > > + PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
> > > > + PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
> > > > + PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
> > > > + PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
> > > > + PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
> > > > + PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
> > > > + PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
> > > > + PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
> > > > + PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
> > > > + PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
> > > > + PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
> > > > + PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
> > > > + PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
> > > > + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
> > > > + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
> > > > + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
> > > > + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
> > > > + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
> > > > + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
> > > > + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
> > > > +
> > > > + PIPE_CONF_CHECK_X(dsi_pll.ctrl);
> > > > + PIPE_CONF_CHECK_X(dsi_pll.div);
> > > > +
> > > > + if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
> > > > + PIPE_CONF_CHECK_I(pipe_bpp);
> > > > +
> > > > + PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
> > > > + PIPE_CONF_CHECK_CLOCK_FUZZY(hw.pipe_mode.crtc_clock);
> > > > + PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
> > > > +
> > > > + PIPE_CONF_CHECK_I(min_voltage_level);
> > > > + }
> > > >
> > > > PIPE_CONF_CHECK_X(infoframes.enable);
> > > > PIPE_CONF_CHECK_X(infoframes.gcp);
> > > --
> > > Ville Syrjälä
> > > Intel
>
> --
> Ville Syrjälä
> Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v10 06/11] drm/i915: Enable big joiner support in enable and disable sequences.
2020-10-16 18:17 ` Navare, Manasi
@ 2020-10-16 18:50 ` Ville Syrjälä
2020-10-16 19:24 ` Navare, Manasi
0 siblings, 1 reply; 50+ messages in thread
From: Ville Syrjälä @ 2020-10-16 18:50 UTC (permalink / raw)
To: Navare, Manasi; +Cc: intel-gfx
On Fri, Oct 16, 2020 at 11:17:33AM -0700, Navare, Manasi wrote:
> On Fri, Oct 16, 2020 at 07:06:20PM +0300, Ville Syrjälä wrote:
> > On Thu, Oct 15, 2020 at 09:37:47AM -0700, Navare, Manasi wrote:
> > > On Thu, Oct 15, 2020 at 04:07:05PM +0300, Ville Syrjälä wrote:
> > > > On Thu, Oct 08, 2020 at 02:45:30PM -0700, Manasi Navare wrote:
> > > > > @@ -4504,6 +4514,29 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
> > > > > default:
> > > > > break;
> > > > > }
> > > > > +}
> > > > > +
> > > > > +void intel_ddi_get_config(struct intel_encoder *encoder,
> > > > > + struct intel_crtc_state *pipe_config)
> > > > > +{
> > > > > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > > > > + enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
> > > > > +
> > > > > + /* XXX: DSI transcoder paranoia */
> > > > > + if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
> > > > > + return;
> > > > > +
> > > > > + intel_ddi_read_func_ctl(encoder, pipe_config);
> > > > > + if (pipe_config->bigjoiner_slave) {
> > > > > + /* read out pipe settings from master */
> > > > > + enum transcoder save = pipe_config->cpu_transcoder;
> > > > > +
> > > > > + /* Our own transcoder needs to be disabled when reading it in intel_ddi_read_func_ctl() */
> > > > > + WARN_ON(pipe_config->output_types);
> > > > > + pipe_config->cpu_transcoder = (enum transcoder)pipe_config->bigjoiner_linked_crtc->pipe;
> > > > > + intel_ddi_read_func_ctl(encoder, pipe_config);
> > > > > + pipe_config->cpu_transcoder = save;
> > > > > + }
> > > >
> > > > This stuff is rather horrible. Shouldn't both pipes be using the
> > > > same transcoder anyway? If so, is this stuff here just because
> > > > we've miscalculated cpu_transcoder for the slave?
> > >
> > > Well honestly @Maarten wrote this and I believe had several iterations of reviews with you.
> > > So he can explain better.
> > > My understanding so far was that there is no encoder /transcoder for slave and thats
> > > why for bigjoiner_slave we actually read stuff from master
> > > So why is this wrong?
> > >
> > > >
> > > > >
> > > > > pipe_config->has_audio =
> > > > > intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
> > > > > @@ -4529,7 +4562,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
> > > > > dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
> > > > > }
> > > > >
> > > > > - intel_ddi_clock_get(encoder, pipe_config);
> > > > > + if (!pipe_config->bigjoiner_slave)
> > > > > + intel_ddi_clock_get(encoder, pipe_config);
> > > > >
> > > > > if (IS_GEN9_LP(dev_priv))
> > > > > pipe_config->lane_lat_optim_mask =
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > index 37b56f4c2401..faf8bf757bed 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > @@ -7125,6 +7125,45 @@ static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
> > > > > intel_de_write(dev_priv, reg, val);
> > > > > }
> > > > >
> > > > > +static void tgl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
> > > > > + const struct intel_crtc_state *crtc_state)
> > > > > +{
> > > > > + struct intel_crtc *master = to_intel_crtc(crtc_state->uapi.crtc);
> > > > > + struct intel_crtc_state *master_crtc_state;
> > > > > + struct drm_connector_state *conn_state;
> > > > > + struct drm_connector *conn;
> > > > > + struct intel_encoder *encoder = NULL;
> > > > > + int i;
> > > > > +
> > > > > + if (crtc_state->bigjoiner_slave)
> > > > > + master = crtc_state->bigjoiner_linked_crtc;
> > > > > +
> > > > > + master_crtc_state = intel_atomic_get_new_crtc_state(state, master);
> > > > > +
> > > > > + for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
> > > > > + if (conn_state->crtc != &master->base)
> > > > > + continue;
> > > > > +
> > > > > + encoder = to_intel_encoder(conn_state->best_encoder);
> > > > > + break;
> > > > > + }
> > > > > +
> > > > > + if (!crtc_state->bigjoiner_slave) {
> > > > > + /* need to enable VDSC, which we skipped in pre-enable */
> > > > > + intel_dsc_enable(encoder, crtc_state);
> > > > > + } else {
> > > > > + /*
> > > > > + * Enable sequence steps 1-7 on bigjoiner master
> > > > > + */
> > > > > + intel_encoders_pre_pll_enable(state, master);
> > > > > + intel_enable_shared_dpll(master_crtc_state);
> > > > > + intel_encoders_pre_enable(state, master);
> > > > > +
> > > > > + /* and DSC on slave */
> > > > > + intel_dsc_enable(NULL, crtc_state);
> > > > > + }
> > > > > +}
> > > > > +
> > > > > static void hsw_crtc_enable(struct intel_atomic_state *state,
> > > > > struct intel_crtc *crtc)
> > > > > {
> > > > > @@ -7138,34 +7177,39 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
> > > > > if (drm_WARN_ON(&dev_priv->drm, crtc->active))
> > > > > return;
> > > > >
> > > > > - intel_encoders_pre_pll_enable(state, crtc);
> > > > > -
> > > > > - if (new_crtc_state->shared_dpll)
> > > > > - intel_enable_shared_dpll(new_crtc_state);
> > > > > + if (!new_crtc_state->bigjoiner) {
> > > > > + intel_encoders_pre_pll_enable(state, crtc);
> > > > >
> > > > > - intel_encoders_pre_enable(state, crtc);
> > > > > + if (new_crtc_state->shared_dpll)
> > > > > + intel_enable_shared_dpll(new_crtc_state);
> > > > >
> > > > > - if (!transcoder_is_dsi(cpu_transcoder))
> > > > > - intel_set_transcoder_timings(new_crtc_state);
> > > > > + intel_encoders_pre_enable(state, crtc);
> > > > > + } else {
> > > > > + tgl_ddi_bigjoiner_pre_enable(state, new_crtc_state);
> > > > > + }
> > > > >
> > > > > intel_set_pipe_src_size(new_crtc_state);
> > > > > + if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
> > > > > + bdw_set_pipemisc(new_crtc_state);
> > > > >
> > > > > - if (cpu_transcoder != TRANSCODER_EDP &&
> > > > > - !transcoder_is_dsi(cpu_transcoder))
> > > > > - intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
> > > > > - new_crtc_state->pixel_multiplier - 1);
> > > > > + if (!new_crtc_state->bigjoiner_slave && !transcoder_is_dsi(cpu_transcoder)) {
> > > > > + if (!transcoder_is_dsi(cpu_transcoder))
> > > > > + intel_set_transcoder_timings(new_crtc_state);
> > > > >
> > > > > - if (new_crtc_state->has_pch_encoder)
> > > > > - intel_cpu_transcoder_set_m_n(new_crtc_state,
> > > > > - &new_crtc_state->fdi_m_n, NULL);
> > > > > + if (cpu_transcoder != TRANSCODER_EDP &&
> > > > > + !transcoder_is_dsi(cpu_transcoder))
> > > > > + intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
> > > > > + new_crtc_state->pixel_multiplier - 1);
> > > > > +
> > > > > + if (new_crtc_state->has_pch_encoder)
> > > > > + intel_cpu_transcoder_set_m_n(new_crtc_state,
> > > > > + &new_crtc_state->fdi_m_n, NULL);
> > > > >
> > > > > - if (!transcoder_is_dsi(cpu_transcoder)) {
> > > > > hsw_set_frame_start_delay(new_crtc_state);
> > > > > - hsw_set_pipeconf(new_crtc_state);
> > > > > }
> > > > >
> > > > > - if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
> > > > > - bdw_set_pipemisc(new_crtc_state);
> > > > > + if (!transcoder_is_dsi(cpu_transcoder))
> > > > > + hsw_set_pipeconf(new_crtc_state);
> > > > >
> > > > > crtc->active = true;
> > > > >
> > > > > @@ -7201,6 +7245,11 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
> > > > > if (INTEL_GEN(dev_priv) >= 11)
> > > > > icl_pipe_mbus_enable(crtc);
> > > > >
> > > > > + if (new_crtc_state->bigjoiner_slave) {
> > > > > + trace_intel_pipe_enable(crtc);
> > > > > + intel_crtc_vblank_on(new_crtc_state);
> > > > > + }
> > > > > +
> > > > > intel_encoders_enable(state, crtc);
> > > > >
> > > > > if (psl_clkgate_wa) {
> > > > > @@ -7495,6 +7544,9 @@ static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
> > > > > if (crtc_state->shared_dpll)
> > > > > mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);
> > > > >
> > > > > + if (crtc_state->dsc.compression_enable)
> > > > > + mask |= BIT_ULL(intel_dsc_power_domain(crtc_state));
> > > > > +
> > > > > return mask;
> > > > > }
> > > > >
> > > > > @@ -8113,6 +8165,30 @@ static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
> > > > > pfit_w * pfit_h);
> > > > > }
> > > > >
> > > > > +static void intel_encoder_get_config(struct intel_encoder *encoder,
> > > > > + struct intel_crtc_state *crtc_state)
> > > > > +{
> > > > > + struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
> > > > > +
> > > > > + encoder->get_config(encoder, crtc_state);
> > > > > +
> > > > > + *pipe_mode = crtc_state->hw.adjusted_mode;
> > > > > + if (crtc_state->bigjoiner) {
> > > > > + /*
> > > > > + * transcoder is programmed to the full mode,
> > > > > + * but pipe timings are half of the transcoder mode
> > > > > + */
> > > > > + pipe_mode->crtc_hdisplay /= 2;
> > > > > + pipe_mode->crtc_hblank_start /= 2;
> > > > > + pipe_mode->crtc_hblank_end /= 2;
> > > > > + pipe_mode->crtc_hsync_start /= 2;
> > > > > + pipe_mode->crtc_hsync_end /= 2;
> > > > > + pipe_mode->crtc_htotal /= 2;
> > > > > + pipe_mode->crtc_hskew /= 2;
> > > > > + pipe_mode->crtc_clock /= 2;
> > > > > + }
> > > > > +}
> > > > > +
> > > > > static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
> > > > > {
> > > > > struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> > > > > @@ -9027,20 +9103,22 @@ static void intel_get_pipe_src_size(struct intel_crtc *crtc,
> > > > > void intel_mode_from_pipe_config(struct drm_display_mode *mode,
> > > > > struct intel_crtc_state *pipe_config)
> > > > > {
> > > > > - mode->hdisplay = pipe_config->hw.adjusted_mode.crtc_hdisplay;
> > > > > - mode->htotal = pipe_config->hw.adjusted_mode.crtc_htotal;
> > > > > - mode->hsync_start = pipe_config->hw.adjusted_mode.crtc_hsync_start;
> > > > > - mode->hsync_end = pipe_config->hw.adjusted_mode.crtc_hsync_end;
> > > > > + struct drm_display_mode *hw_mode = &pipe_config->hw.adjusted_mode;
> > > > > +
> > > > > + mode->hdisplay = hw_mode->crtc_hdisplay;
> > > > > + mode->htotal = hw_mode->crtc_htotal;
> > > > > + mode->hsync_start = hw_mode->crtc_hsync_start;
> > > > > + mode->hsync_end = hw_mode->crtc_hsync_end;
> > > > >
> > > > > - mode->vdisplay = pipe_config->hw.adjusted_mode.crtc_vdisplay;
> > > > > - mode->vtotal = pipe_config->hw.adjusted_mode.crtc_vtotal;
> > > > > - mode->vsync_start = pipe_config->hw.adjusted_mode.crtc_vsync_start;
> > > > > - mode->vsync_end = pipe_config->hw.adjusted_mode.crtc_vsync_end;
> > > > > + mode->vdisplay = hw_mode->crtc_vdisplay;
> > > > > + mode->vtotal = hw_mode->crtc_vtotal;
> > > > > + mode->vsync_start = hw_mode->crtc_vsync_start;
> > > > > + mode->vsync_end = hw_mode->crtc_vsync_end;
> > > > >
> > > > > - mode->flags = pipe_config->hw.adjusted_mode.flags;
> > > > > + mode->flags = hw_mode->flags;
> > > > > mode->type = DRM_MODE_TYPE_DRIVER;
> > > > >
> > > > > - mode->clock = pipe_config->hw.adjusted_mode.crtc_clock;
> > > > > + mode->clock = hw_mode->crtc_clock;
> > > > >
> > > > > drm_mode_set_name(mode);
> > > > > }
> > > > > @@ -11207,6 +11285,9 @@ static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
> > > > > } else {
> > > > > tmp = intel_de_read(dev_priv,
> > > > > TRANS_DDI_FUNC_CTL(cpu_transcoder));
> > > > > + if (!(tmp & TRANS_DDI_FUNC_ENABLE))
> > > > > + return;
> > > > > +
> > > > > if (INTEL_GEN(dev_priv) >= 12)
> > > > > port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
> > > > > else
> > > > > @@ -11279,12 +11360,20 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
> > > > > drm_WARN_ON(&dev_priv->drm, active);
> > > > > active = true;
> > > > > }
> > > > > + intel_dsc_get_config(pipe_config);
> > > > >
> > > > > - if (!active)
> > > > > - goto out;
> > > > > + if (!active) {
> > > > > + /* bigjoiner slave doesn't enable transcoder */
> > > > > + if (!pipe_config->bigjoiner_slave)
> > > > > + goto out;
> > > > >
> > > > > - if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
> > > > > - INTEL_GEN(dev_priv) >= 11) {
> > > > > + active = true;
> > > > > + pipe_config->pixel_multiplier = 1;
> > > > > +
> > > > > + /* we cannot read out most state, so don't bother.. */
> > > > > + pipe_config->quirks |= PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE;
> > > > > + } else if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
> > > > > + INTEL_GEN(dev_priv) >= 11) {
> > > > > hsw_get_ddi_port_state(crtc, pipe_config);
> > > > > intel_get_transcoder_timings(crtc, pipe_config);
> > > > > }
> > > > > @@ -11370,8 +11459,11 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
> > > > > }
> > > > > }
> > > > >
> > > > > - if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
> > > > > - !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
> > > > > + if (pipe_config->bigjoiner_slave) {
> > > > > + /* Cannot be read out as a slave, set to 0. */
> > > > > + pipe_config->pixel_multiplier = 0;
> > > > > + } else if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
> > > > > + !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
> > > > > pipe_config->pixel_multiplier =
> > > > > intel_de_read(dev_priv,
> > > > > PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
> > > > > @@ -12386,7 +12478,7 @@ intel_encoder_current_mode(struct intel_encoder *encoder)
> > > > > return NULL;
> > > > > }
> > > > >
> > > > > - encoder->get_config(encoder, crtc_state);
> > > > > + intel_encoder_get_config(encoder, crtc_state);
> > > > >
> > > > > intel_mode_from_pipe_config(mode, crtc_state);
> > > > >
> > > > > @@ -13385,12 +13477,15 @@ intel_crtc_copy_uapi_to_hw_state(struct intel_atomic_state *state,
> > > > > intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc_state);
> > > > > }
> > > > >
> > > > > -static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
> > > > > +static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state,
> > > > > + struct drm_display_mode *user_mode)
> > > > > {
> > > > > - crtc_state->uapi.enable = crtc_state->hw.enable;
> > > > > - crtc_state->uapi.active = crtc_state->hw.active;
> > > > > - drm_WARN_ON(crtc_state->uapi.crtc->dev,
> > > > > - drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);
> > > > > + if (!crtc_state->bigjoiner_slave) {
> > > > > + crtc_state->uapi.enable = crtc_state->hw.enable;
> > > > > + crtc_state->uapi.active = crtc_state->hw.active;
> > > > > + drm_WARN_ON(crtc_state->uapi.crtc->dev,
> > > > > + drm_atomic_set_mode_for_crtc(&crtc_state->uapi, user_mode) < 0);
> > > > > + }
> > > > >
> > > > > crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
> > > > >
> > > > > @@ -14027,21 +14122,42 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> > > > >
> > > > > PIPE_CONF_CHECK_X(output_types);
> > > > >
> > > > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
> > > > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
> > > > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
> > > > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
> > > > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
> > > > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
> > > > > -
> > > > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
> > > > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
> > > > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
> > > > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
> > > > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
> > > > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
> > > > > -
> > > > > - PIPE_CONF_CHECK_I(pixel_multiplier);
> > > > > + if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) {
> > > > > + /* bigjoiner mode = transcoder mode / 2, for calculations */
> > > > > + PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);
> > > > > + PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_htotal);
> > > > > + PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vdisplay);
> > > > > + PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vtotal);
> > > > > +
> > > > > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
> > > > > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
> > > > > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
> > > > > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
> > > > > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
> > > > > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
> > > > > +
> > > > > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
> > > > > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
> > > > > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
> > > > > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
> > > > > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
> > > > > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
> > > > > +
> > > > > + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > > > > + DRM_MODE_FLAG_INTERLACE);
> > > > > +
> > > > > + if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
> > > > > + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > > > > + DRM_MODE_FLAG_PHSYNC);
> > > > > + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > > > > + DRM_MODE_FLAG_NHSYNC);
> > > > > + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > > > > + DRM_MODE_FLAG_PVSYNC);
> > > > > + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > > > > + DRM_MODE_FLAG_NVSYNC);
> > > > > + }
> > > > > + PIPE_CONF_CHECK_I(pixel_multiplier);
> > > > > + }
> > > > > PIPE_CONF_CHECK_I(output_format);
> > > > > PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
> > > > > if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
> > > > > @@ -14051,24 +14167,11 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> > > > > PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
> > > > > PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
> > > > > PIPE_CONF_CHECK_BOOL(has_infoframe);
> > > > > - PIPE_CONF_CHECK_BOOL(fec_enable);
> > > > > + if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE))
> > > > > + PIPE_CONF_CHECK_BOOL(fec_enable);
> > > > >
> > > > > PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
> > > > >
> > > > > - PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > > > > - DRM_MODE_FLAG_INTERLACE);
> > > > > -
> > > > > - if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
> > > > > - PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > > > > - DRM_MODE_FLAG_PHSYNC);
> > > > > - PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > > > > - DRM_MODE_FLAG_NHSYNC);
> > > > > - PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > > > > - DRM_MODE_FLAG_PVSYNC);
> > > > > - PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > > > > - DRM_MODE_FLAG_NVSYNC);
> > > > > - }
> > > > > -
> > > > > PIPE_CONF_CHECK_X(gmch_pfit.control);
> > > > > /* pfit ratios are autocomputed by the hw on gen4+ */
> > > > > if (INTEL_GEN(dev_priv) < 4)
> > > > > @@ -14094,7 +14197,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> > > > > }
> > > > >
> > > > > PIPE_CONF_CHECK_I(scaler_state.scaler_id);
> > > > > - PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
> > > > > + if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE))
> > > > > + PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
> > > > >
> > > > > PIPE_CONF_CHECK_X(gamma_mode);
> > > > > if (IS_CHERRYVIEW(dev_priv))
> > > > > @@ -14115,48 +14219,51 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> > > > > PIPE_CONF_CHECK_BOOL(double_wide);
> > > > >
> > > > > PIPE_CONF_CHECK_P(shared_dpll);
> > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
> > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
> > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
> > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
> > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
> > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.spll);
> > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
> > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
> > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
> > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
> > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
> > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
> > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
> > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
> > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
> > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
> > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
> > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
> > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
> > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
> > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
> > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
> > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
> > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
> > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
> > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
> > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
> > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
> > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
> > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
> > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
> > > > > -
> > > > > - PIPE_CONF_CHECK_X(dsi_pll.ctrl);
> > > > > - PIPE_CONF_CHECK_X(dsi_pll.div);
> > > > > -
> > > > > - if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
> > > > > - PIPE_CONF_CHECK_I(pipe_bpp);
> > > > > -
> > > > > - PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
> > > > > - PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
> > > > > -
> > > > > - PIPE_CONF_CHECK_I(min_voltage_level);
> > > > > + if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) {
> > > >
> > > > This looks super sketchy. I don't see why we'd want to skip all this
> > > > state checking for bigjoiner.
> > >
> > > For big joiner slave we do not enable plls and hence it doesnt make sense
> > > to compare the hw state of plls for big joiner slave
> >
> > This is skipping far more than just plls. Also I think the state should
> > still match whether it has its own pll or not. I kinda think we should
> > have a pll for both pipes actually since that would avoid all this
> > special case code that will just end up breaking all the time.
>
> Only the adjusted mode and pipe mode and port clock can be taken out of this condition.
> But we cannot have a pll for the slave that contradicts the Bspec modeset enable sequence.
Of course we can have a pll. We won't route that pll's output into the
pipe's unused transcoder though.
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v10 06/11] drm/i915: Enable big joiner support in enable and disable sequences.
2020-10-16 18:50 ` Ville Syrjälä
@ 2020-10-16 19:24 ` Navare, Manasi
2020-10-19 11:34 ` Jani Nikula
0 siblings, 1 reply; 50+ messages in thread
From: Navare, Manasi @ 2020-10-16 19:24 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Fri, Oct 16, 2020 at 09:50:00PM +0300, Ville Syrjälä wrote:
> On Fri, Oct 16, 2020 at 11:17:33AM -0700, Navare, Manasi wrote:
> > On Fri, Oct 16, 2020 at 07:06:20PM +0300, Ville Syrjälä wrote:
> > > On Thu, Oct 15, 2020 at 09:37:47AM -0700, Navare, Manasi wrote:
> > > > On Thu, Oct 15, 2020 at 04:07:05PM +0300, Ville Syrjälä wrote:
> > > > > On Thu, Oct 08, 2020 at 02:45:30PM -0700, Manasi Navare wrote:
> > > > > > @@ -4504,6 +4514,29 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
> > > > > > default:
> > > > > > break;
> > > > > > }
> > > > > > +}
> > > > > > +
> > > > > > +void intel_ddi_get_config(struct intel_encoder *encoder,
> > > > > > + struct intel_crtc_state *pipe_config)
> > > > > > +{
> > > > > > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > > > > > + enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
> > > > > > +
> > > > > > + /* XXX: DSI transcoder paranoia */
> > > > > > + if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
> > > > > > + return;
> > > > > > +
> > > > > > + intel_ddi_read_func_ctl(encoder, pipe_config);
> > > > > > + if (pipe_config->bigjoiner_slave) {
> > > > > > + /* read out pipe settings from master */
> > > > > > + enum transcoder save = pipe_config->cpu_transcoder;
> > > > > > +
> > > > > > + /* Our own transcoder needs to be disabled when reading it in intel_ddi_read_func_ctl() */
> > > > > > + WARN_ON(pipe_config->output_types);
> > > > > > + pipe_config->cpu_transcoder = (enum transcoder)pipe_config->bigjoiner_linked_crtc->pipe;
> > > > > > + intel_ddi_read_func_ctl(encoder, pipe_config);
> > > > > > + pipe_config->cpu_transcoder = save;
> > > > > > + }
> > > > >
> > > > > This stuff is rather horrible. Shouldn't both pipes be using the
> > > > > same transcoder anyway? If so, is this stuff here just because
> > > > > we've miscalculated cpu_transcoder for the slave?
> > > >
> > > > Well honestly @Maarten wrote this and I believe had several iterations of reviews with you.
> > > > So he can explain better.
> > > > My understanding so far was that there is no encoder /transcoder for slave and thats
> > > > why for bigjoiner_slave we actually read stuff from master
> > > > So why is this wrong?
> > > >
> > > > >
> > > > > >
> > > > > > pipe_config->has_audio =
> > > > > > intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
> > > > > > @@ -4529,7 +4562,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
> > > > > > dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
> > > > > > }
> > > > > >
> > > > > > - intel_ddi_clock_get(encoder, pipe_config);
> > > > > > + if (!pipe_config->bigjoiner_slave)
> > > > > > + intel_ddi_clock_get(encoder, pipe_config);
> > > > > >
> > > > > > if (IS_GEN9_LP(dev_priv))
> > > > > > pipe_config->lane_lat_optim_mask =
> > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > index 37b56f4c2401..faf8bf757bed 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > @@ -7125,6 +7125,45 @@ static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
> > > > > > intel_de_write(dev_priv, reg, val);
> > > > > > }
> > > > > >
> > > > > > +static void tgl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
> > > > > > + const struct intel_crtc_state *crtc_state)
> > > > > > +{
> > > > > > + struct intel_crtc *master = to_intel_crtc(crtc_state->uapi.crtc);
> > > > > > + struct intel_crtc_state *master_crtc_state;
> > > > > > + struct drm_connector_state *conn_state;
> > > > > > + struct drm_connector *conn;
> > > > > > + struct intel_encoder *encoder = NULL;
> > > > > > + int i;
> > > > > > +
> > > > > > + if (crtc_state->bigjoiner_slave)
> > > > > > + master = crtc_state->bigjoiner_linked_crtc;
> > > > > > +
> > > > > > + master_crtc_state = intel_atomic_get_new_crtc_state(state, master);
> > > > > > +
> > > > > > + for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
> > > > > > + if (conn_state->crtc != &master->base)
> > > > > > + continue;
> > > > > > +
> > > > > > + encoder = to_intel_encoder(conn_state->best_encoder);
> > > > > > + break;
> > > > > > + }
> > > > > > +
> > > > > > + if (!crtc_state->bigjoiner_slave) {
> > > > > > + /* need to enable VDSC, which we skipped in pre-enable */
> > > > > > + intel_dsc_enable(encoder, crtc_state);
> > > > > > + } else {
> > > > > > + /*
> > > > > > + * Enable sequence steps 1-7 on bigjoiner master
> > > > > > + */
> > > > > > + intel_encoders_pre_pll_enable(state, master);
> > > > > > + intel_enable_shared_dpll(master_crtc_state);
> > > > > > + intel_encoders_pre_enable(state, master);
> > > > > > +
> > > > > > + /* and DSC on slave */
> > > > > > + intel_dsc_enable(NULL, crtc_state);
> > > > > > + }
> > > > > > +}
> > > > > > +
> > > > > > static void hsw_crtc_enable(struct intel_atomic_state *state,
> > > > > > struct intel_crtc *crtc)
> > > > > > {
> > > > > > @@ -7138,34 +7177,39 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
> > > > > > if (drm_WARN_ON(&dev_priv->drm, crtc->active))
> > > > > > return;
> > > > > >
> > > > > > - intel_encoders_pre_pll_enable(state, crtc);
> > > > > > -
> > > > > > - if (new_crtc_state->shared_dpll)
> > > > > > - intel_enable_shared_dpll(new_crtc_state);
> > > > > > + if (!new_crtc_state->bigjoiner) {
> > > > > > + intel_encoders_pre_pll_enable(state, crtc);
> > > > > >
> > > > > > - intel_encoders_pre_enable(state, crtc);
> > > > > > + if (new_crtc_state->shared_dpll)
> > > > > > + intel_enable_shared_dpll(new_crtc_state);
> > > > > >
> > > > > > - if (!transcoder_is_dsi(cpu_transcoder))
> > > > > > - intel_set_transcoder_timings(new_crtc_state);
> > > > > > + intel_encoders_pre_enable(state, crtc);
> > > > > > + } else {
> > > > > > + tgl_ddi_bigjoiner_pre_enable(state, new_crtc_state);
> > > > > > + }
> > > > > >
> > > > > > intel_set_pipe_src_size(new_crtc_state);
> > > > > > + if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
> > > > > > + bdw_set_pipemisc(new_crtc_state);
> > > > > >
> > > > > > - if (cpu_transcoder != TRANSCODER_EDP &&
> > > > > > - !transcoder_is_dsi(cpu_transcoder))
> > > > > > - intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
> > > > > > - new_crtc_state->pixel_multiplier - 1);
> > > > > > + if (!new_crtc_state->bigjoiner_slave && !transcoder_is_dsi(cpu_transcoder)) {
> > > > > > + if (!transcoder_is_dsi(cpu_transcoder))
> > > > > > + intel_set_transcoder_timings(new_crtc_state);
> > > > > >
> > > > > > - if (new_crtc_state->has_pch_encoder)
> > > > > > - intel_cpu_transcoder_set_m_n(new_crtc_state,
> > > > > > - &new_crtc_state->fdi_m_n, NULL);
> > > > > > + if (cpu_transcoder != TRANSCODER_EDP &&
> > > > > > + !transcoder_is_dsi(cpu_transcoder))
> > > > > > + intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
> > > > > > + new_crtc_state->pixel_multiplier - 1);
> > > > > > +
> > > > > > + if (new_crtc_state->has_pch_encoder)
> > > > > > + intel_cpu_transcoder_set_m_n(new_crtc_state,
> > > > > > + &new_crtc_state->fdi_m_n, NULL);
> > > > > >
> > > > > > - if (!transcoder_is_dsi(cpu_transcoder)) {
> > > > > > hsw_set_frame_start_delay(new_crtc_state);
> > > > > > - hsw_set_pipeconf(new_crtc_state);
> > > > > > }
> > > > > >
> > > > > > - if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
> > > > > > - bdw_set_pipemisc(new_crtc_state);
> > > > > > + if (!transcoder_is_dsi(cpu_transcoder))
> > > > > > + hsw_set_pipeconf(new_crtc_state);
> > > > > >
> > > > > > crtc->active = true;
> > > > > >
> > > > > > @@ -7201,6 +7245,11 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
> > > > > > if (INTEL_GEN(dev_priv) >= 11)
> > > > > > icl_pipe_mbus_enable(crtc);
> > > > > >
> > > > > > + if (new_crtc_state->bigjoiner_slave) {
> > > > > > + trace_intel_pipe_enable(crtc);
> > > > > > + intel_crtc_vblank_on(new_crtc_state);
> > > > > > + }
> > > > > > +
> > > > > > intel_encoders_enable(state, crtc);
> > > > > >
> > > > > > if (psl_clkgate_wa) {
> > > > > > @@ -7495,6 +7544,9 @@ static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
> > > > > > if (crtc_state->shared_dpll)
> > > > > > mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);
> > > > > >
> > > > > > + if (crtc_state->dsc.compression_enable)
> > > > > > + mask |= BIT_ULL(intel_dsc_power_domain(crtc_state));
> > > > > > +
> > > > > > return mask;
> > > > > > }
> > > > > >
> > > > > > @@ -8113,6 +8165,30 @@ static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
> > > > > > pfit_w * pfit_h);
> > > > > > }
> > > > > >
> > > > > > +static void intel_encoder_get_config(struct intel_encoder *encoder,
> > > > > > + struct intel_crtc_state *crtc_state)
> > > > > > +{
> > > > > > + struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
> > > > > > +
> > > > > > + encoder->get_config(encoder, crtc_state);
> > > > > > +
> > > > > > + *pipe_mode = crtc_state->hw.adjusted_mode;
> > > > > > + if (crtc_state->bigjoiner) {
> > > > > > + /*
> > > > > > + * transcoder is programmed to the full mode,
> > > > > > + * but pipe timings are half of the transcoder mode
> > > > > > + */
> > > > > > + pipe_mode->crtc_hdisplay /= 2;
> > > > > > + pipe_mode->crtc_hblank_start /= 2;
> > > > > > + pipe_mode->crtc_hblank_end /= 2;
> > > > > > + pipe_mode->crtc_hsync_start /= 2;
> > > > > > + pipe_mode->crtc_hsync_end /= 2;
> > > > > > + pipe_mode->crtc_htotal /= 2;
> > > > > > + pipe_mode->crtc_hskew /= 2;
> > > > > > + pipe_mode->crtc_clock /= 2;
> > > > > > + }
> > > > > > +}
> > > > > > +
> > > > > > static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
> > > > > > {
> > > > > > struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> > > > > > @@ -9027,20 +9103,22 @@ static void intel_get_pipe_src_size(struct intel_crtc *crtc,
> > > > > > void intel_mode_from_pipe_config(struct drm_display_mode *mode,
> > > > > > struct intel_crtc_state *pipe_config)
> > > > > > {
> > > > > > - mode->hdisplay = pipe_config->hw.adjusted_mode.crtc_hdisplay;
> > > > > > - mode->htotal = pipe_config->hw.adjusted_mode.crtc_htotal;
> > > > > > - mode->hsync_start = pipe_config->hw.adjusted_mode.crtc_hsync_start;
> > > > > > - mode->hsync_end = pipe_config->hw.adjusted_mode.crtc_hsync_end;
> > > > > > + struct drm_display_mode *hw_mode = &pipe_config->hw.adjusted_mode;
> > > > > > +
> > > > > > + mode->hdisplay = hw_mode->crtc_hdisplay;
> > > > > > + mode->htotal = hw_mode->crtc_htotal;
> > > > > > + mode->hsync_start = hw_mode->crtc_hsync_start;
> > > > > > + mode->hsync_end = hw_mode->crtc_hsync_end;
> > > > > >
> > > > > > - mode->vdisplay = pipe_config->hw.adjusted_mode.crtc_vdisplay;
> > > > > > - mode->vtotal = pipe_config->hw.adjusted_mode.crtc_vtotal;
> > > > > > - mode->vsync_start = pipe_config->hw.adjusted_mode.crtc_vsync_start;
> > > > > > - mode->vsync_end = pipe_config->hw.adjusted_mode.crtc_vsync_end;
> > > > > > + mode->vdisplay = hw_mode->crtc_vdisplay;
> > > > > > + mode->vtotal = hw_mode->crtc_vtotal;
> > > > > > + mode->vsync_start = hw_mode->crtc_vsync_start;
> > > > > > + mode->vsync_end = hw_mode->crtc_vsync_end;
> > > > > >
> > > > > > - mode->flags = pipe_config->hw.adjusted_mode.flags;
> > > > > > + mode->flags = hw_mode->flags;
> > > > > > mode->type = DRM_MODE_TYPE_DRIVER;
> > > > > >
> > > > > > - mode->clock = pipe_config->hw.adjusted_mode.crtc_clock;
> > > > > > + mode->clock = hw_mode->crtc_clock;
> > > > > >
> > > > > > drm_mode_set_name(mode);
> > > > > > }
> > > > > > @@ -11207,6 +11285,9 @@ static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
> > > > > > } else {
> > > > > > tmp = intel_de_read(dev_priv,
> > > > > > TRANS_DDI_FUNC_CTL(cpu_transcoder));
> > > > > > + if (!(tmp & TRANS_DDI_FUNC_ENABLE))
> > > > > > + return;
> > > > > > +
> > > > > > if (INTEL_GEN(dev_priv) >= 12)
> > > > > > port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
> > > > > > else
> > > > > > @@ -11279,12 +11360,20 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
> > > > > > drm_WARN_ON(&dev_priv->drm, active);
> > > > > > active = true;
> > > > > > }
> > > > > > + intel_dsc_get_config(pipe_config);
> > > > > >
> > > > > > - if (!active)
> > > > > > - goto out;
> > > > > > + if (!active) {
> > > > > > + /* bigjoiner slave doesn't enable transcoder */
> > > > > > + if (!pipe_config->bigjoiner_slave)
> > > > > > + goto out;
> > > > > >
> > > > > > - if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
> > > > > > - INTEL_GEN(dev_priv) >= 11) {
> > > > > > + active = true;
> > > > > > + pipe_config->pixel_multiplier = 1;
> > > > > > +
> > > > > > + /* we cannot read out most state, so don't bother.. */
> > > > > > + pipe_config->quirks |= PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE;
> > > > > > + } else if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
> > > > > > + INTEL_GEN(dev_priv) >= 11) {
> > > > > > hsw_get_ddi_port_state(crtc, pipe_config);
> > > > > > intel_get_transcoder_timings(crtc, pipe_config);
> > > > > > }
> > > > > > @@ -11370,8 +11459,11 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
> > > > > > }
> > > > > > }
> > > > > >
> > > > > > - if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
> > > > > > - !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
> > > > > > + if (pipe_config->bigjoiner_slave) {
> > > > > > + /* Cannot be read out as a slave, set to 0. */
> > > > > > + pipe_config->pixel_multiplier = 0;
> > > > > > + } else if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
> > > > > > + !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
> > > > > > pipe_config->pixel_multiplier =
> > > > > > intel_de_read(dev_priv,
> > > > > > PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
> > > > > > @@ -12386,7 +12478,7 @@ intel_encoder_current_mode(struct intel_encoder *encoder)
> > > > > > return NULL;
> > > > > > }
> > > > > >
> > > > > > - encoder->get_config(encoder, crtc_state);
> > > > > > + intel_encoder_get_config(encoder, crtc_state);
> > > > > >
> > > > > > intel_mode_from_pipe_config(mode, crtc_state);
> > > > > >
> > > > > > @@ -13385,12 +13477,15 @@ intel_crtc_copy_uapi_to_hw_state(struct intel_atomic_state *state,
> > > > > > intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc_state);
> > > > > > }
> > > > > >
> > > > > > -static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
> > > > > > +static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state,
> > > > > > + struct drm_display_mode *user_mode)
> > > > > > {
> > > > > > - crtc_state->uapi.enable = crtc_state->hw.enable;
> > > > > > - crtc_state->uapi.active = crtc_state->hw.active;
> > > > > > - drm_WARN_ON(crtc_state->uapi.crtc->dev,
> > > > > > - drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);
> > > > > > + if (!crtc_state->bigjoiner_slave) {
> > > > > > + crtc_state->uapi.enable = crtc_state->hw.enable;
> > > > > > + crtc_state->uapi.active = crtc_state->hw.active;
> > > > > > + drm_WARN_ON(crtc_state->uapi.crtc->dev,
> > > > > > + drm_atomic_set_mode_for_crtc(&crtc_state->uapi, user_mode) < 0);
> > > > > > + }
> > > > > >
> > > > > > crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
> > > > > >
> > > > > > @@ -14027,21 +14122,42 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> > > > > >
> > > > > > PIPE_CONF_CHECK_X(output_types);
> > > > > >
> > > > > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
> > > > > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
> > > > > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
> > > > > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
> > > > > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
> > > > > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
> > > > > > -
> > > > > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
> > > > > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
> > > > > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
> > > > > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
> > > > > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
> > > > > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
> > > > > > -
> > > > > > - PIPE_CONF_CHECK_I(pixel_multiplier);
> > > > > > + if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) {
> > > > > > + /* bigjoiner mode = transcoder mode / 2, for calculations */
> > > > > > + PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);
> > > > > > + PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_htotal);
> > > > > > + PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vdisplay);
> > > > > > + PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vtotal);
> > > > > > +
> > > > > > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
> > > > > > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
> > > > > > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
> > > > > > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
> > > > > > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
> > > > > > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
> > > > > > +
> > > > > > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
> > > > > > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
> > > > > > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
> > > > > > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
> > > > > > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
> > > > > > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
> > > > > > +
> > > > > > + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > > > > > + DRM_MODE_FLAG_INTERLACE);
> > > > > > +
> > > > > > + if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
> > > > > > + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > > > > > + DRM_MODE_FLAG_PHSYNC);
> > > > > > + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > > > > > + DRM_MODE_FLAG_NHSYNC);
> > > > > > + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > > > > > + DRM_MODE_FLAG_PVSYNC);
> > > > > > + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > > > > > + DRM_MODE_FLAG_NVSYNC);
> > > > > > + }
> > > > > > + PIPE_CONF_CHECK_I(pixel_multiplier);
> > > > > > + }
> > > > > > PIPE_CONF_CHECK_I(output_format);
> > > > > > PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
> > > > > > if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
> > > > > > @@ -14051,24 +14167,11 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> > > > > > PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
> > > > > > PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
> > > > > > PIPE_CONF_CHECK_BOOL(has_infoframe);
> > > > > > - PIPE_CONF_CHECK_BOOL(fec_enable);
> > > > > > + if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE))
> > > > > > + PIPE_CONF_CHECK_BOOL(fec_enable);
> > > > > >
> > > > > > PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
> > > > > >
> > > > > > - PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > > > > > - DRM_MODE_FLAG_INTERLACE);
> > > > > > -
> > > > > > - if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
> > > > > > - PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > > > > > - DRM_MODE_FLAG_PHSYNC);
> > > > > > - PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > > > > > - DRM_MODE_FLAG_NHSYNC);
> > > > > > - PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > > > > > - DRM_MODE_FLAG_PVSYNC);
> > > > > > - PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> > > > > > - DRM_MODE_FLAG_NVSYNC);
> > > > > > - }
> > > > > > -
> > > > > > PIPE_CONF_CHECK_X(gmch_pfit.control);
> > > > > > /* pfit ratios are autocomputed by the hw on gen4+ */
> > > > > > if (INTEL_GEN(dev_priv) < 4)
> > > > > > @@ -14094,7 +14197,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> > > > > > }
> > > > > >
> > > > > > PIPE_CONF_CHECK_I(scaler_state.scaler_id);
> > > > > > - PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
> > > > > > + if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE))
> > > > > > + PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
> > > > > >
> > > > > > PIPE_CONF_CHECK_X(gamma_mode);
> > > > > > if (IS_CHERRYVIEW(dev_priv))
> > > > > > @@ -14115,48 +14219,51 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> > > > > > PIPE_CONF_CHECK_BOOL(double_wide);
> > > > > >
> > > > > > PIPE_CONF_CHECK_P(shared_dpll);
> > > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
> > > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
> > > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
> > > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
> > > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
> > > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.spll);
> > > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
> > > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
> > > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
> > > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
> > > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
> > > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
> > > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
> > > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
> > > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
> > > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
> > > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
> > > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
> > > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
> > > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
> > > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
> > > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
> > > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
> > > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
> > > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
> > > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
> > > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
> > > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
> > > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
> > > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
> > > > > > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
> > > > > > -
> > > > > > - PIPE_CONF_CHECK_X(dsi_pll.ctrl);
> > > > > > - PIPE_CONF_CHECK_X(dsi_pll.div);
> > > > > > -
> > > > > > - if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
> > > > > > - PIPE_CONF_CHECK_I(pipe_bpp);
> > > > > > -
> > > > > > - PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
> > > > > > - PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
> > > > > > -
> > > > > > - PIPE_CONF_CHECK_I(min_voltage_level);
> > > > > > + if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) {
> > > > >
> > > > > This looks super sketchy. I don't see why we'd want to skip all this
> > > > > state checking for bigjoiner.
> > > >
> > > > For big joiner slave we do not enable plls and hence it doesnt make sense
> > > > to compare the hw state of plls for big joiner slave
> > >
> > > This is skipping far more than just plls. Also I think the state should
> > > still match whether it has its own pll or not. I kinda think we should
> > > have a pll for both pipes actually since that would avoid all this
> > > special case code that will just end up breaking all the time.
> >
> > Only the adjusted mode and pipe mode and port clock can be taken out of this condition.
> > But we cannot have a pll for the slave that contradicts the Bspec modeset enable sequence.
>
> Of course we can have a pll. We won't route that pll's output into the
> pipe's unused transcoder though.
I really want to push back on any design changes at this point since we have a working solution
and we currently dont have any special cases. Like I discussed with you all the commit modeset enables
code is now generic and similar to 2p2p.
These kind of changes/ optimizations can be done later. Like you suggested we should get the basic working
solution and support in.
Does this patch look good? Do I have your ack on this?
Manasi
>
> --
> Ville Syrjälä
> Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v10 06/11] drm/i915: Enable big joiner support in enable and disable sequences.
2020-10-16 19:24 ` Navare, Manasi
@ 2020-10-19 11:34 ` Jani Nikula
2020-10-19 22:53 ` Navare, Manasi
0 siblings, 1 reply; 50+ messages in thread
From: Jani Nikula @ 2020-10-19 11:34 UTC (permalink / raw)
To: Navare, Manasi, Ville Syrjälä; +Cc: intel-gfx
On Fri, 16 Oct 2020, "Navare, Manasi" <manasi.d.navare@intel.com> wrote:
> I really want to push back on any design changes at this point since we have a working solution
> and we currently dont have any special cases. Like I discussed with you all the commit modeset enables
> code is now generic and similar to 2p2p.
> These kind of changes/ optimizations can be done later. Like you suggested we should get the basic working
> solution and support in.
Like I said in [1], this is a big scary patch that has been reported to
break DSI VDSC. I tried to skim through it, but it's really impossible
to identify the one thing that could break DSI.
I mean, even if you had the hardware to test, it could take days to
identify the regressing part here.
And this isn't really specific to DSI, but rather to *any* regression
this might cause. Afterwards, would you stand a chance of telling what
goes wrong if you get a bisect result?
BR,
Jani.
[1] http://lore.kernel.org/r/87o8l5awvr.fsf@intel.com
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v10 09/11] drm/i915: Add bigjoiner aware plane clipping checks
2020-10-08 21:45 ` [Intel-gfx] [PATCH v10 09/11] drm/i915: Add bigjoiner aware plane clipping checks Manasi Navare
@ 2020-10-19 16:20 ` Ville Syrjälä
2020-10-19 22:56 ` Navare, Manasi
0 siblings, 1 reply; 50+ messages in thread
From: Ville Syrjälä @ 2020-10-19 16:20 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
On Thu, Oct 08, 2020 at 02:45:33PM -0700, Manasi Navare wrote:
> From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
>
> We need to look at hw.fb for the framebuffer, and add the translation
> for the slave_plane_state. With these changes we set the correct
> rectangle on the bigjoiner slave, and don't set incorrect
> src/dst/visibility on the slave plane.
>
> v2:
> * Manual rebase (Manasi)
>
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
> .../gpu/drm/i915/display/intel_atomic_plane.c | 60 +++++++++++++++++++
> .../gpu/drm/i915/display/intel_atomic_plane.h | 4 ++
> drivers/gpu/drm/i915/display/intel_display.c | 19 +++---
> drivers/gpu/drm/i915/display/intel_sprite.c | 21 +++----
> 4 files changed, 80 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index a8f1fd85a6c0..09cb3adc36da 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -267,6 +267,9 @@ void intel_plane_copy_uapi_to_hw_state(const struct intel_crtc_state *crtc_state
> plane_state->hw.rotation = from_plane_state->uapi.rotation;
> plane_state->hw.color_encoding = from_plane_state->uapi.color_encoding;
> plane_state->hw.color_range = from_plane_state->uapi.color_range;
> +
> + plane_state->uapi.src = drm_plane_state_src(&from_plane_state->uapi);
> + plane_state->uapi.dst = drm_plane_state_dest(&from_plane_state->uapi);
> }
>
> void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
> @@ -519,6 +522,63 @@ void i9xx_update_planes_on_crtc(struct intel_atomic_state *state,
> }
> }
>
> +int intel_atomic_plane_check_clipping(struct intel_plane_state *plane_state,
> + struct intel_crtc_state *crtc_state,
> + int min_scale, int max_scale,
> + bool can_position)
> +{
> + struct drm_framebuffer *fb = plane_state->hw.fb;
> + struct drm_rect *src = &plane_state->uapi.src;
> + struct drm_rect *dst = &plane_state->uapi.dst;
> + unsigned int rotation = plane_state->uapi.rotation;
hw.rotation
The rest seems consistent.
> + struct drm_rect clip = {};
> + int hscale, vscale;
> +
> + if (!fb) {
> + plane_state->uapi.visible = false;
> + return 0;
> + }
> +
> + drm_rect_rotate(src, fb->width << 16, fb->height << 16, rotation);
> +
> + /* Check scaling */
> + hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
> + vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
> + if (hscale < 0 || vscale < 0) {
> + DRM_DEBUG_KMS("Invalid scaling of plane\n");
> + drm_rect_debug_print("src: ", src, true);
> + drm_rect_debug_print("dst: ", dst, false);
> + return -ERANGE;
> + }
> +
> + if (crtc_state->hw.enable) {
> + clip.x2 = crtc_state->pipe_src_w;
> + clip.y2 = crtc_state->pipe_src_h;
> + }
> +
> + /* right side of the image is on the slave crtc, adjust dst to match */
> + if (crtc_state->bigjoiner_slave)
> + drm_rect_translate(dst, -crtc_state->pipe_src_w, 0);
> +
> + /*
> + * FIXME: This might need further adjustment for seamless scaling
> + * with phase information, for the 2p2 and 2p1 scenarios.
> + */
> + plane_state->uapi.visible = drm_rect_clip_scaled(src, dst, &clip);
> +
> + drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16, rotation);
> +
> + if (!can_position && plane_state->uapi.visible &&
> + !drm_rect_equals(dst, &clip)) {
> + DRM_DEBUG_KMS("Plane must cover entire CRTC\n");
> + drm_rect_debug_print("dst: ", dst, false);
> + drm_rect_debug_print("clip: ", &clip, false);
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> const struct drm_plane_helper_funcs intel_plane_helper_funcs = {
> .prepare_fb = intel_prepare_plane_fb,
> .cleanup_fb = intel_cleanup_plane_fb,
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> index c2a1e7c86e6c..d0a599d00ecd 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> @@ -53,6 +53,10 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
> int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
> struct intel_plane *plane,
> bool *need_cdclk_calc);
> +int intel_atomic_plane_check_clipping(struct intel_plane_state *plane_state,
> + struct intel_crtc_state *crtc_state,
> + int min_scale, int max_scale,
> + bool can_position);
> void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
> struct intel_plane_state *plane_state);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index d5a6f07bb674..357cc2bce300 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -4409,12 +4409,10 @@ i9xx_plane_check(struct intel_crtc_state *crtc_state,
> if (ret)
> return ret;
>
> - ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
> - &crtc_state->uapi,
> - DRM_PLANE_HELPER_NO_SCALING,
> - DRM_PLANE_HELPER_NO_SCALING,
> - i9xx_plane_has_windowing(plane),
> - true);
> + ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,
> + DRM_PLANE_HELPER_NO_SCALING,
> + DRM_PLANE_HELPER_NO_SCALING,
> + i9xx_plane_has_windowing(plane));
> if (ret)
> return ret;
>
> @@ -11611,11 +11609,10 @@ static int intel_check_cursor(struct intel_crtc_state *crtc_state,
> return -EINVAL;
> }
>
> - ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
> - &crtc_state->uapi,
> - DRM_PLANE_HELPER_NO_SCALING,
> - DRM_PLANE_HELPER_NO_SCALING,
> - true, true);
> + ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,
> + DRM_PLANE_HELPER_NO_SCALING,
> + DRM_PLANE_HELPER_NO_SCALING,
> + true);
> if (ret)
> return ret;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 2da11ab6343c..9e235210adc7 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -2047,10 +2047,8 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state,
> }
> }
>
> - ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
> - &crtc_state->uapi,
> - min_scale, max_scale,
> - true, true);
> + ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,
> + min_scale, max_scale, true);
> if (ret)
> return ret;
>
> @@ -2105,11 +2103,10 @@ vlv_sprite_check(struct intel_crtc_state *crtc_state,
> if (ret)
> return ret;
>
> - ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
> - &crtc_state->uapi,
> - DRM_PLANE_HELPER_NO_SCALING,
> - DRM_PLANE_HELPER_NO_SCALING,
> - true, true);
> + ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,
> + DRM_PLANE_HELPER_NO_SCALING,
> + DRM_PLANE_HELPER_NO_SCALING,
> + true);
> if (ret)
> return ret;
>
> @@ -2316,10 +2313,8 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
> max_scale = skl_plane_max_scale(dev_priv, fb);
> }
>
> - ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
> - &crtc_state->uapi,
> - min_scale, max_scale,
> - true, true);
> + ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,
> + min_scale, max_scale, true);
> if (ret)
> return ret;
>
> --
> 2.19.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v10 10/11] drm/i915: Ensure correct master/slave enable/disable sequence
2020-10-08 21:45 ` [Intel-gfx] [PATCH v10 10/11] drm/i915: Ensure correct master/slave enable/disable sequence Manasi Navare
@ 2020-10-19 16:26 ` Ville Syrjälä
2020-10-19 23:05 ` Navare, Manasi
0 siblings, 1 reply; 50+ messages in thread
From: Ville Syrjälä @ 2020-10-19 16:26 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
On Thu, Oct 08, 2020 at 02:45:34PM -0700, Manasi Navare wrote:
> From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
>
> Enabling is done in a special sequence and so should plane updates
> be. Ideally the end user never notices the second pipe is used.
>
> This way ideally everything will be tear free, and updates are
> really atomic as userspace expects it.
>
> This uses generic modeset_enables() calls like trans port sync
> but still has special handling for disable since for slave we
> should not disable things like encoder, plls that are not enabled
> for slave.
>
> v3:
> * Fixes in enable and disable sequence from testing (Manasi)
> v2:
> * Manual Rebase (Manasi)
> * Refactoring on intel_update_crtc and enable_crtc and removing
> special trans_port_sync_update (Manasi)
>
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 55 ++++++++++++++------
> drivers/gpu/drm/i915/display/intel_sprite.c | 5 +-
> 2 files changed, 43 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 357cc2bce300..101ddd0b48ab 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -15878,6 +15878,9 @@ static void intel_enable_crtc(struct intel_atomic_state *state,
>
> dev_priv->display.crtc_enable(state, crtc);
>
> + if (new_crtc_state->bigjoiner_slave)
> + return;
> +
> /* vblanks work again, re-enable pipe CRC. */
> intel_crtc_enable_pipe_crc(crtc);
> }
> @@ -15914,9 +15917,7 @@ static void intel_update_crtc(struct intel_atomic_state *state,
>
> commit_pipe_config(state, crtc);
>
> - if (new_crtc_state->bigjoiner) {
> - /* Not supported yet */
> - } else if (INTEL_GEN(dev_priv) >= 9)
> + if (INTEL_GEN(dev_priv) >= 9)
> skl_update_planes_on_crtc(state, crtc);
> else
> i9xx_update_planes_on_crtc(state, crtc);
> @@ -15945,9 +15946,17 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
> drm_WARN_ON(&dev_priv->drm, old_crtc_state->bigjoiner_slave);
>
> intel_crtc_disable_planes(state, crtc);
> - if (old_crtc_state->bigjoiner)
> +
> + /*
> + * We still need special handling for disabling bigjoiner master
> + * and slaves since for slave we do not have encoder or plls
> + * so we dont need to disable those.
> + */
> + if (old_crtc_state->bigjoiner) {
> intel_crtc_disable_planes(state,
> old_crtc_state->bigjoiner_linked_crtc);
> + old_crtc_state->bigjoiner_linked_crtc->active = false;
> + }
>
> /*
> * We need to disable pipe CRC before disabling the pipe,
> @@ -15977,7 +15986,7 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state)
> /* Only disable port sync and MST slaves */
> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> new_crtc_state, i) {
> - if (!needs_modeset(new_crtc_state) || old_crtc_state->bigjoiner_slave)
> + if (!needs_modeset(new_crtc_state) || old_crtc_state->bigjoiner)
> continue;
>
> if (!old_crtc_state->hw.active)
> @@ -16040,6 +16049,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
> struct intel_crtc *crtc;
> struct intel_crtc_state *old_crtc_state, *new_crtc_state;
> struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
> + struct skl_ddb_entry new_entries[I915_MAX_PIPES] = {};
> u8 update_pipes = 0, modeset_pipes = 0;
> int i;
>
> @@ -16056,6 +16066,14 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
> } else {
> modeset_pipes |= BIT(pipe);
> }
> +
> + new_entries[i] = new_crtc_state->wm.skl.ddb;
> +
> + /* ignore allocations for crtc's that have been turned off during modeset. */
> + if (needs_modeset(new_crtc_state))
> + continue;
> +
> + entries[i] = old_crtc_state->wm.skl.ddb;
> }
>
> /*
> @@ -16071,28 +16089,28 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> new_crtc_state, i) {
> enum pipe pipe = crtc->pipe;
> + bool ddb_changed;
>
> if ((update_pipes & BIT(pipe)) == 0)
> continue;
>
> - if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
> + if (skl_ddb_allocation_overlaps(&new_entries[pipe],
> entries, I915_MAX_PIPES, pipe))
> continue;
>
> - entries[pipe] = new_crtc_state->wm.skl.ddb;
> + ddb_changed = !skl_ddb_entry_equal(&new_entries[pipe], &entries[pipe]);
> + entries[pipe] = new_entries[pipe];
> update_pipes &= ~BIT(pipe);
>
> - intel_update_crtc(state, crtc);
> -
> /*
> * If this is an already active pipe, it's DDB changed,
> * and this isn't the last pipe that needs updating
> * then we need to wait for a vblank to pass for the
> * new ddb allocation to take effect.
> */
> - if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
> - &old_crtc_state->wm.skl.ddb) &&
> - (update_pipes | modeset_pipes))
> + intel_update_crtc(state, crtc);
> +
> + if (ddb_changed && (update_pipes | modeset_pipes))
> intel_wait_for_vblank(dev_priv, pipe);
What are these ddb changes trying to achieve?
> }
> }
> @@ -16110,7 +16128,8 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
> continue;
>
> if (intel_dp_mst_is_slave_trans(new_crtc_state) ||
> - is_trans_port_sync_master(new_crtc_state))
> + is_trans_port_sync_master(new_crtc_state) ||
> + (new_crtc_state->bigjoiner && !new_crtc_state->bigjoiner_slave))
> continue;
>
> modeset_pipes &= ~BIT(pipe);
> @@ -16120,7 +16139,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
>
> /*
> * Then we enable all remaining pipes that depend on other
> - * pipes: MST slaves and port sync masters.
> + * pipes: MST slaves and port sync masters, big joiner master
> */
> for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> enum pipe pipe = crtc->pipe;
> @@ -16128,6 +16147,10 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
> if ((modeset_pipes & BIT(pipe)) == 0)
> continue;
>
> + WARN_ON(skl_ddb_allocation_overlaps(&new_entries[pipe],
> + entries, I915_MAX_PIPES, pipe));
> +
> + entries[pipe] = new_entries[pipe];
> modeset_pipes &= ~BIT(pipe);
>
> intel_enable_crtc(state, crtc);
> @@ -16142,10 +16165,10 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
> if ((update_pipes & BIT(pipe)) == 0)
> continue;
>
> - drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
> + drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_entries[pipe],
> entries, I915_MAX_PIPES, pipe));
>
> - entries[pipe] = new_crtc_state->wm.skl.ddb;
> + entries[pipe] = new_entries[pipe];
> update_pipes &= ~BIT(pipe);
>
> intel_update_crtc(state, crtc);
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 9e235210adc7..1c740a22a8d7 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -103,6 +103,8 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
>
> /* FIXME needs to be calibrated sensibly */
> min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
> + new_crtc_state->bigjoiner ?
> + 2 * VBLANK_EVASION_TIME_US :
> VBLANK_EVASION_TIME_US);
> max = vblank_start - 1;
>
> @@ -227,7 +229,8 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
>
> spin_lock(&crtc->base.dev->event_lock);
> drm_crtc_arm_vblank_event(&crtc->base,
> - new_crtc_state->uapi.event);
> + new_crtc_state->uapi.event);
> +
Spurious whitespace change.
> spin_unlock(&crtc->base.dev->event_lock);
>
> new_crtc_state->uapi.event = NULL;
> --
> 2.19.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v10 04/11] drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.
2020-10-15 16:26 ` Navare, Manasi
@ 2020-10-19 16:30 ` Ville Syrjälä
2020-10-19 22:51 ` Navare, Manasi
0 siblings, 1 reply; 50+ messages in thread
From: Ville Syrjälä @ 2020-10-19 16:30 UTC (permalink / raw)
To: Navare, Manasi; +Cc: intel-gfx
On Thu, Oct 15, 2020 at 09:26:45AM -0700, Navare, Manasi wrote:
> On Thu, Oct 15, 2020 at 02:52:47PM +0300, Ville Syrjälä wrote:
> > On Wed, Oct 14, 2020 at 12:04:10PM -0700, Navare, Manasi wrote:
> > > On Wed, Oct 14, 2020 at 02:26:34PM +0300, Ville Syrjälä wrote:
> > > > On Thu, Oct 08, 2020 at 02:45:28PM -0700, Manasi Navare wrote:
> > > > > From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > > > >
> > > > > Small changes to intel_dp_mode_valid(), allow listing modes that
> > > > > can only be supported in the bigjoiner configuration, which is
> > > > > not supported yet.
> > > > >
> > > > > eDP does not support bigjoiner, so do not expose bigjoiner only
> > > > > modes on the eDP port.
> > > > >
> > > > > v7:
> > > > > * Add can_bigjoiner() helper (Ville)
> > > > > * Pass bigjoiner to plane_size validation (Ville)
> > > > > v6:
> > > > > * Rebase after dp_downstream mode valid changes (Manasi)
> > > > > v5:
> > > > > * Increase max plane width to support 8K with bigjoiner (Maarten)
> > > > > v4:
> > > > > * Rebase (Manasi)
> > > > >
> > > > > Changes since v1:
> > > > > - Disallow bigjoiner on eDP.
> > > > > Changes since v2:
> > > > > - Rename intel_dp_downstream_max_dotclock to intel_dp_max_dotclock,
> > > > > and split off the downstream and source checking to its own function.
> > > > > (Ville)
> > > > > v3:
> > > > > * Rebase (Manasi)
> > > > >
> > > > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > > > > Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > > > > ---
> > > > > drivers/gpu/drm/i915/display/intel_display.c | 5 +-
> > > > > drivers/gpu/drm/i915/display/intel_display.h | 3 +-
> > > > > drivers/gpu/drm/i915/display/intel_dp.c | 126 +++++++++++++++----
> > > > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
> > > > > drivers/gpu/drm/i915/display/intel_dsi.c | 2 +-
> > > > > drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
> > > > > 6 files changed, 111 insertions(+), 29 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > index 723766b1eae3..cc540c7b7dcd 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > @@ -17642,7 +17642,8 @@ intel_mode_valid(struct drm_device *dev,
> > > > >
> > > > > enum drm_mode_status
> > > > > intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
> > > > > - const struct drm_display_mode *mode)
> > > > > + const struct drm_display_mode *mode,
> > > > > + bool bigjoiner)
> > > > > {
> > > > > int plane_width_max, plane_height_max;
> > > > >
> > > > > @@ -17659,7 +17660,7 @@ intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
> > > > > * too big for that.
> > > > > */
> > > > > if (INTEL_GEN(dev_priv) >= 11) {
> > > > > - plane_width_max = 5120;
> > > > > + plane_width_max = 5120 << bigjoiner;
> > > > > plane_height_max = 4320;
> > > > > } else {
> > > > > plane_width_max = 5120;
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> > > > > index d10b7c8cde3f..3d860a9da8fe 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_display.h
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.h
> > > > > @@ -496,7 +496,8 @@ u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
> > > > > bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
> > > > > enum drm_mode_status
> > > > > intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
> > > > > - const struct drm_display_mode *mode);
> > > > > + const struct drm_display_mode *mode,
> > > > > + bool bigjoiner);
> > > > > enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
> > > > > bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > > index 8a522edd7386..af2ff425e5d5 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > > @@ -247,6 +247,29 @@ intel_dp_max_data_rate(int max_link_clock, int max_lanes)
> > > > > return max_link_clock * max_lanes;
> > > > > }
> > > > >
> > > > > +static int source_max_dotclock(struct intel_dp *intel_dp, bool allow_bigjoiner)
> > > > > +{
> > > > > + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> > > > > + struct intel_encoder *encoder = &intel_dig_port->base;
> > > > > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > > > > +
> > > > > + if (allow_bigjoiner && INTEL_GEN(dev_priv) >= 11 && !intel_dp_is_edp(intel_dp))
> > > > > + return 2 * dev_priv->max_dotclk_freq;
> > > > > +
> > > > > + return dev_priv->max_dotclk_freq;
> > > > > +}
> > > > > +
> > > > > +static int
> > > > > +intel_dp_max_dotclock(struct intel_dp *intel_dp, bool allow_bigjoiner)
> > > > > +{
> > > > > + int max_dotclk = source_max_dotclock(intel_dp, allow_bigjoiner);
> > > > > +
> > > > > + if (intel_dp->dfp.max_dotclock)
> > > >
> > > > No. dfp checks should stay where they are.
> > >
> > > I am using dfp.max_dotclock because we populate that with drm_dp_downstream_max_dotclock()
> > > should that be used here directly from drm_dp_downstream_max_dotclock instead of using dfp.maxdotclock ?
> >
> > Can you explain how bigjoiner and DFP dotclock limits relate to each
> > other?
>
> Before the dfp dotclock checks were added, we were obtaining the max dotclock as min (source_max_dotclock, downstream max dotclock from dpcd)
> And thats why I was using the dfp.max_dotclock
>
> But while addressing your feedback , I have now max_dotclock = source max dotclock
> and the downstream max dotclock checks happen in intel_dp_mode_valid_downstream(), so I think we dont need to consider
> this here in max dotclock computation.
>
> Is this correct?
DFP's have nothing to do with bigjoiner. It is a purely internal
implemntation detail of our display engine. So mixing up the two
would be very wrong.
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v10 07/11] drm/i915: Make hardware readout work on i915.
2020-10-08 21:45 ` [Intel-gfx] [PATCH v10 07/11] drm/i915: Make hardware readout work on i915 Manasi Navare
2020-10-11 20:18 ` kernel test robot
@ 2020-10-19 16:36 ` Ville Syrjälä
2020-10-19 22:45 ` Navare, Manasi
1 sibling, 1 reply; 50+ messages in thread
From: Ville Syrjälä @ 2020-10-19 16:36 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
On Thu, Oct 08, 2020 at 02:45:31PM -0700, Manasi Navare wrote:
> From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
>
> Unfortunately I have no way to test this, but it should be correct
> if the bios sets up bigjoiner in a sane way.
>
> Skip iterating over bigjoiner slaves, only the master has the state we
> care about.
>
> Add the width of the bigjoiner slave to the reconstructed fb.
>
> Hide the bigjoiner slave to userspace, and double the mode on bigjoiner
> master.
>
> And last, disable bigjoiner slave from primary if reconstruction fails.
>
> v2:
> * Manual Rebase (Manasi)
>
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 64 +++++++++++++++++++-
> 1 file changed, 62 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index faf8bf757bed..aa981aa4f6a1 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -3619,6 +3619,8 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
> struct intel_plane *intel_plane = to_intel_plane(primary);
> struct intel_plane_state *intel_state =
> to_intel_plane_state(plane_state);
> + struct intel_crtc_state *crtc_state =
Whitespace fail. Didn't checkpatch complain?
> + to_intel_crtc_state(intel_crtc->base.state);
> struct drm_framebuffer *fb;
> struct i915_vma *vma;
>
> @@ -3641,7 +3643,7 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
> if (c == &intel_crtc->base)
> continue;
>
> - if (!to_intel_crtc(c)->active)
> + if (!to_intel_crtc_state(c->state)->uapi.active)
> continue;
>
> state = to_intel_plane_state(c->primary->state);
> @@ -3663,6 +3665,11 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
> * pretend the BIOS never had it enabled.
> */
> intel_plane_disable_noatomic(intel_crtc, intel_plane);
> + if (crtc_state->bigjoiner) {
> + struct intel_crtc *slave =
> + crtc_state->bigjoiner_linked_crtc;
> + intel_plane_disable_noatomic(slave, to_intel_plane(slave->base.primary));
> + }
>
> return;
>
> @@ -10687,6 +10694,7 @@ static void
> skl_get_initial_plane_config(struct intel_crtc *crtc,
> struct intel_initial_plane_config *plane_config)
> {
> + struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct intel_plane *plane = to_intel_plane(crtc->base.primary);
> @@ -10795,6 +10803,18 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
> fb->height = ((val >> 16) & 0xffff) + 1;
> fb->width = ((val >> 0) & 0xffff) + 1;
>
> + /* add bigjoiner slave as well, if the fb stretches both */
> + if (crtc_state->bigjoiner) {
> + enum pipe bigjoiner_pipe = crtc_state->bigjoiner_linked_crtc->pipe;
> +
> + if (fb->width == crtc_state->pipe_src_w &&
> + (intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & 0xfffff000) == plane_config->base) {
> + val = intel_de_read(dev_priv, PLANE_SIZE(bigjoiner_pipe, plane_id));
> + fb->height += ((val >> 16) & 0xfff) + 1;
> + fb->width += ((val >> 0) & 0x1fff) + 1;
This looks wrong.
> + }
> + }
> +
> val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id));
> stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
> fb->pitches[0] = (val & 0x3ff) * stride_mult;
> @@ -18793,7 +18813,8 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc,
>
> /* Adjust the state of the output pipe according to whether we
> * have active connectors/encoders. */
> - if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc))
> + if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc) &&
> + !crtc_state->bigjoiner_slave)
> intel_crtc_disable_noatomic(crtc, ctx);
>
> if (crtc_state->hw.active || HAS_GMCH(dev_priv)) {
> @@ -19072,6 +19093,9 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> struct intel_plane *plane;
> int min_cdclk = 0;
>
> + if (crtc_state->bigjoiner_slave)
> + continue;
> +
> if (crtc_state->hw.active) {
> struct drm_display_mode mode;
>
> @@ -19096,6 +19120,9 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> mode.hdisplay = crtc_state->pipe_src_w;
> mode.vdisplay = crtc_state->pipe_src_h;
>
> + if (crtc_state->bigjoiner)
> + mode.hdisplay *= 2;
> +
> intel_crtc_compute_pixel_rate(crtc_state);
>
> intel_crtc_update_active_timings(crtc_state);
> @@ -19146,6 +19173,39 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> intel_bw_crtc_update(bw_state, crtc_state);
>
> intel_pipe_config_sanity_check(dev_priv, crtc_state);
> +
> + /* discard our incomplete slave state, copy it from master */
Wasn't expecting this many horrible hacks around readout. So basiclly it
looks like we have very little in terms of useful readout+state
checking.
> + if (crtc_state->bigjoiner && crtc_state->hw.active) {
> + struct intel_crtc *slave = crtc_state->bigjoiner_linked_crtc;
> + struct intel_crtc_state *slave_crtc_state =
> + to_intel_crtc_state(slave->base.state);
> +
> + copy_bigjoiner_crtc_state(slave_crtc_state, crtc_state);
> + slave->base.mode = crtc->base.mode;
> +
> + cdclk_state->min_cdclk[slave->pipe] = min_cdclk;
> + cdclk_state->min_voltage_level[slave->pipe] =
> + crtc_state->min_voltage_level;
> +
> + for_each_intel_plane_on_crtc(&dev_priv->drm, slave, plane) {
> + const struct intel_plane_state *plane_state =
> + to_intel_plane_state(plane->base.state);
> +
> + /*
> + * FIXME don't have the fb yet, so can't
> + * use intel_plane_data_rate() :(
> + */
> + if (plane_state->uapi.visible)
> + crtc_state->data_rate[plane->id] =
> + 4 * crtc_state->pixel_rate;
> + else
> + crtc_state->data_rate[plane->id] = 0;
> + }
> +
> + intel_bw_crtc_update(bw_state, slave_crtc_state);
> + drm_calc_timestamping_constants(&slave->base,
> + &slave_crtc_state->hw.adjusted_mode);
> + }
> }
> }
>
> --
> 2.19.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v10 07/11] drm/i915: Make hardware readout work on i915.
2020-10-19 16:36 ` Ville Syrjälä
@ 2020-10-19 22:45 ` Navare, Manasi
2020-10-20 18:45 ` Ville Syrjälä
0 siblings, 1 reply; 50+ messages in thread
From: Navare, Manasi @ 2020-10-19 22:45 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Mon, Oct 19, 2020 at 07:36:59PM +0300, Ville Syrjälä wrote:
> On Thu, Oct 08, 2020 at 02:45:31PM -0700, Manasi Navare wrote:
> > From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> >
> > Unfortunately I have no way to test this, but it should be correct
> > if the bios sets up bigjoiner in a sane way.
> >
> > Skip iterating over bigjoiner slaves, only the master has the state we
> > care about.
> >
> > Add the width of the bigjoiner slave to the reconstructed fb.
> >
> > Hide the bigjoiner slave to userspace, and double the mode on bigjoiner
> > master.
> >
> > And last, disable bigjoiner slave from primary if reconstruction fails.
> >
> > v2:
> > * Manual Rebase (Manasi)
> >
> > Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 64 +++++++++++++++++++-
> > 1 file changed, 62 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index faf8bf757bed..aa981aa4f6a1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -3619,6 +3619,8 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
> > struct intel_plane *intel_plane = to_intel_plane(primary);
> > struct intel_plane_state *intel_state =
> > to_intel_plane_state(plane_state);
> > + struct intel_crtc_state *crtc_state =
>
> Whitespace fail. Didn't checkpatch complain?
I will fix this
>
> > + to_intel_crtc_state(intel_crtc->base.state);
> > struct drm_framebuffer *fb;
> > struct i915_vma *vma;
> >
> > @@ -3641,7 +3643,7 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
> > if (c == &intel_crtc->base)
> > continue;
> >
> > - if (!to_intel_crtc(c)->active)
> > + if (!to_intel_crtc_state(c->state)->uapi.active)
> > continue;
> >
> > state = to_intel_plane_state(c->primary->state);
> > @@ -3663,6 +3665,11 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
> > * pretend the BIOS never had it enabled.
> > */
> > intel_plane_disable_noatomic(intel_crtc, intel_plane);
> > + if (crtc_state->bigjoiner) {
> > + struct intel_crtc *slave =
> > + crtc_state->bigjoiner_linked_crtc;
> > + intel_plane_disable_noatomic(slave, to_intel_plane(slave->base.primary));
> > + }
> >
> > return;
> >
> > @@ -10687,6 +10694,7 @@ static void
> > skl_get_initial_plane_config(struct intel_crtc *crtc,
> > struct intel_initial_plane_config *plane_config)
> > {
> > + struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
> > struct drm_device *dev = crtc->base.dev;
> > struct drm_i915_private *dev_priv = to_i915(dev);
> > struct intel_plane *plane = to_intel_plane(crtc->base.primary);
> > @@ -10795,6 +10803,18 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
> > fb->height = ((val >> 16) & 0xffff) + 1;
> > fb->width = ((val >> 0) & 0xffff) + 1;
> >
> > + /* add bigjoiner slave as well, if the fb stretches both */
> > + if (crtc_state->bigjoiner) {
> > + enum pipe bigjoiner_pipe = crtc_state->bigjoiner_linked_crtc->pipe;
> > +
> > + if (fb->width == crtc_state->pipe_src_w &&
> > + (intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & 0xfffff000) == plane_config->base) {
> > + val = intel_de_read(dev_priv, PLANE_SIZE(bigjoiner_pipe, plane_id));
> > + fb->height += ((val >> 16) & 0xfff) + 1;
> > + fb->width += ((val >> 0) & 0x1fff) + 1;
>
> This looks wrong.
Why is it wrong? Double checked the plane size width and height bits from bspec
and the mask looks correct here.
Can you elaborate on what is wrong here?
>
> > + }
> > + }
> > +
> > val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id));
> > stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
> > fb->pitches[0] = (val & 0x3ff) * stride_mult;
> > @@ -18793,7 +18813,8 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc,
> >
> > /* Adjust the state of the output pipe according to whether we
> > * have active connectors/encoders. */
> > - if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc))
> > + if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc) &&
> > + !crtc_state->bigjoiner_slave)
> > intel_crtc_disable_noatomic(crtc, ctx);
> >
> > if (crtc_state->hw.active || HAS_GMCH(dev_priv)) {
> > @@ -19072,6 +19093,9 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> > struct intel_plane *plane;
> > int min_cdclk = 0;
> >
> > + if (crtc_state->bigjoiner_slave)
> > + continue;
> > +
> > if (crtc_state->hw.active) {
> > struct drm_display_mode mode;
> >
> > @@ -19096,6 +19120,9 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> > mode.hdisplay = crtc_state->pipe_src_w;
> > mode.vdisplay = crtc_state->pipe_src_h;
> >
> > + if (crtc_state->bigjoiner)
> > + mode.hdisplay *= 2;
> > +
> > intel_crtc_compute_pixel_rate(crtc_state);
> >
> > intel_crtc_update_active_timings(crtc_state);
> > @@ -19146,6 +19173,39 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> > intel_bw_crtc_update(bw_state, crtc_state);
> >
> > intel_pipe_config_sanity_check(dev_priv, crtc_state);
> > +
> > + /* discard our incomplete slave state, copy it from master */
>
> Wasn't expecting this many horrible hacks around readout. So basiclly it
> looks like we have very little in terms of useful readout+state
> checking.
Yes we can fine tune this afterw e have basic functionality upstreamed.
Manasi
>
> > + if (crtc_state->bigjoiner && crtc_state->hw.active) {
> > + struct intel_crtc *slave = crtc_state->bigjoiner_linked_crtc;
> > + struct intel_crtc_state *slave_crtc_state =
> > + to_intel_crtc_state(slave->base.state);
> > +
> > + copy_bigjoiner_crtc_state(slave_crtc_state, crtc_state);
> > + slave->base.mode = crtc->base.mode;
> > +
> > + cdclk_state->min_cdclk[slave->pipe] = min_cdclk;
> > + cdclk_state->min_voltage_level[slave->pipe] =
> > + crtc_state->min_voltage_level;
> > +
> > + for_each_intel_plane_on_crtc(&dev_priv->drm, slave, plane) {
> > + const struct intel_plane_state *plane_state =
> > + to_intel_plane_state(plane->base.state);
> > +
> > + /*
> > + * FIXME don't have the fb yet, so can't
> > + * use intel_plane_data_rate() :(
> > + */
> > + if (plane_state->uapi.visible)
> > + crtc_state->data_rate[plane->id] =
> > + 4 * crtc_state->pixel_rate;
> > + else
> > + crtc_state->data_rate[plane->id] = 0;
> > + }
> > +
> > + intel_bw_crtc_update(bw_state, slave_crtc_state);
> > + drm_calc_timestamping_constants(&slave->base,
> > + &slave_crtc_state->hw.adjusted_mode);
> > + }
> > }
> > }
> >
> > --
> > 2.19.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v10 04/11] drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.
2020-10-19 16:30 ` Ville Syrjälä
@ 2020-10-19 22:51 ` Navare, Manasi
0 siblings, 0 replies; 50+ messages in thread
From: Navare, Manasi @ 2020-10-19 22:51 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Mon, Oct 19, 2020 at 07:30:07PM +0300, Ville Syrjälä wrote:
> On Thu, Oct 15, 2020 at 09:26:45AM -0700, Navare, Manasi wrote:
> > On Thu, Oct 15, 2020 at 02:52:47PM +0300, Ville Syrjälä wrote:
> > > On Wed, Oct 14, 2020 at 12:04:10PM -0700, Navare, Manasi wrote:
> > > > On Wed, Oct 14, 2020 at 02:26:34PM +0300, Ville Syrjälä wrote:
> > > > > On Thu, Oct 08, 2020 at 02:45:28PM -0700, Manasi Navare wrote:
> > > > > > From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > > > > >
> > > > > > Small changes to intel_dp_mode_valid(), allow listing modes that
> > > > > > can only be supported in the bigjoiner configuration, which is
> > > > > > not supported yet.
> > > > > >
> > > > > > eDP does not support bigjoiner, so do not expose bigjoiner only
> > > > > > modes on the eDP port.
> > > > > >
> > > > > > v7:
> > > > > > * Add can_bigjoiner() helper (Ville)
> > > > > > * Pass bigjoiner to plane_size validation (Ville)
> > > > > > v6:
> > > > > > * Rebase after dp_downstream mode valid changes (Manasi)
> > > > > > v5:
> > > > > > * Increase max plane width to support 8K with bigjoiner (Maarten)
> > > > > > v4:
> > > > > > * Rebase (Manasi)
> > > > > >
> > > > > > Changes since v1:
> > > > > > - Disallow bigjoiner on eDP.
> > > > > > Changes since v2:
> > > > > > - Rename intel_dp_downstream_max_dotclock to intel_dp_max_dotclock,
> > > > > > and split off the downstream and source checking to its own function.
> > > > > > (Ville)
> > > > > > v3:
> > > > > > * Rebase (Manasi)
> > > > > >
> > > > > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > > > > > Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > > > > > ---
> > > > > > drivers/gpu/drm/i915/display/intel_display.c | 5 +-
> > > > > > drivers/gpu/drm/i915/display/intel_display.h | 3 +-
> > > > > > drivers/gpu/drm/i915/display/intel_dp.c | 126 +++++++++++++++----
> > > > > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
> > > > > > drivers/gpu/drm/i915/display/intel_dsi.c | 2 +-
> > > > > > drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
> > > > > > 6 files changed, 111 insertions(+), 29 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > index 723766b1eae3..cc540c7b7dcd 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > @@ -17642,7 +17642,8 @@ intel_mode_valid(struct drm_device *dev,
> > > > > >
> > > > > > enum drm_mode_status
> > > > > > intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
> > > > > > - const struct drm_display_mode *mode)
> > > > > > + const struct drm_display_mode *mode,
> > > > > > + bool bigjoiner)
> > > > > > {
> > > > > > int plane_width_max, plane_height_max;
> > > > > >
> > > > > > @@ -17659,7 +17660,7 @@ intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
> > > > > > * too big for that.
> > > > > > */
> > > > > > if (INTEL_GEN(dev_priv) >= 11) {
> > > > > > - plane_width_max = 5120;
> > > > > > + plane_width_max = 5120 << bigjoiner;
> > > > > > plane_height_max = 4320;
> > > > > > } else {
> > > > > > plane_width_max = 5120;
> > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> > > > > > index d10b7c8cde3f..3d860a9da8fe 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_display.h
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.h
> > > > > > @@ -496,7 +496,8 @@ u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
> > > > > > bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
> > > > > > enum drm_mode_status
> > > > > > intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
> > > > > > - const struct drm_display_mode *mode);
> > > > > > + const struct drm_display_mode *mode,
> > > > > > + bool bigjoiner);
> > > > > > enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
> > > > > > bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > > > index 8a522edd7386..af2ff425e5d5 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > > > @@ -247,6 +247,29 @@ intel_dp_max_data_rate(int max_link_clock, int max_lanes)
> > > > > > return max_link_clock * max_lanes;
> > > > > > }
> > > > > >
> > > > > > +static int source_max_dotclock(struct intel_dp *intel_dp, bool allow_bigjoiner)
> > > > > > +{
> > > > > > + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> > > > > > + struct intel_encoder *encoder = &intel_dig_port->base;
> > > > > > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > > > > > +
> > > > > > + if (allow_bigjoiner && INTEL_GEN(dev_priv) >= 11 && !intel_dp_is_edp(intel_dp))
> > > > > > + return 2 * dev_priv->max_dotclk_freq;
> > > > > > +
> > > > > > + return dev_priv->max_dotclk_freq;
> > > > > > +}
> > > > > > +
> > > > > > +static int
> > > > > > +intel_dp_max_dotclock(struct intel_dp *intel_dp, bool allow_bigjoiner)
> > > > > > +{
> > > > > > + int max_dotclk = source_max_dotclock(intel_dp, allow_bigjoiner);
> > > > > > +
> > > > > > + if (intel_dp->dfp.max_dotclock)
> > > > >
> > > > > No. dfp checks should stay where they are.
> > > >
> > > > I am using dfp.max_dotclock because we populate that with drm_dp_downstream_max_dotclock()
> > > > should that be used here directly from drm_dp_downstream_max_dotclock instead of using dfp.maxdotclock ?
> > >
> > > Can you explain how bigjoiner and DFP dotclock limits relate to each
> > > other?
> >
> > Before the dfp dotclock checks were added, we were obtaining the max dotclock as min (source_max_dotclock, downstream max dotclock from dpcd)
> > And thats why I was using the dfp.max_dotclock
> >
> > But while addressing your feedback , I have now max_dotclock = source max dotclock
> > and the downstream max dotclock checks happen in intel_dp_mode_valid_downstream(), so I think we dont need to consider
> > this here in max dotclock computation.
> >
> > Is this correct?
>
> DFP's have nothing to do with bigjoiner. It is a purely internal
> implemntation detail of our display engine. So mixing up the two
> would be very wrong.
I understand that bigjoiner is a purely internal implementation
detail of our display engine, however whethera mode can be supported with bigjoiner
also depends on whether the clock of that mode is supported
by downstream port hence we were using the max downstream dotclock.
But I have removed the downstream port clock check for now and only using
the source dotclock check tod ecide on whether the mode is valid with bigjoiner or not since
if the downstream port doesnt support it, it will get pruned in the newly added
intel_dp_downstream_mode_valid() function.
Manasi
>
> --
> Ville Syrjälä
> Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v10 06/11] drm/i915: Enable big joiner support in enable and disable sequences.
2020-10-19 11:34 ` Jani Nikula
@ 2020-10-19 22:53 ` Navare, Manasi
0 siblings, 0 replies; 50+ messages in thread
From: Navare, Manasi @ 2020-10-19 22:53 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Mon, Oct 19, 2020 at 02:34:07PM +0300, Jani Nikula wrote:
> On Fri, 16 Oct 2020, "Navare, Manasi" <manasi.d.navare@intel.com> wrote:
> > I really want to push back on any design changes at this point since we have a working solution
> > and we currently dont have any special cases. Like I discussed with you all the commit modeset enables
> > code is now generic and similar to 2p2p.
> > These kind of changes/ optimizations can be done later. Like you suggested we should get the basic working
> > solution and support in.
>
> Like I said in [1], this is a big scary patch that has been reported to
> break DSI VDSC. I tried to skim through it, but it's really impossible
> to identify the one thing that could break DSI.
>
> I mean, even if you had the hardware to test, it could take days to
> identify the regressing part here.
>
> And this isn't really specific to DSI, but rather to *any* regression
> this might cause. Afterwards, would you stand a chance of telling what
> goes wrong if you get a bisect result?
Yes I agree, it took me ages to understand and inherit this patch from Maarten.
I will try to split this patch into multiple small patches in my next rev.
Manasi
>
>
> BR,
> Jani.
>
>
> [1] http://lore.kernel.org/r/87o8l5awvr.fsf@intel.com
>
>
> --
> Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v10 09/11] drm/i915: Add bigjoiner aware plane clipping checks
2020-10-19 16:20 ` Ville Syrjälä
@ 2020-10-19 22:56 ` Navare, Manasi
2020-10-20 18:51 ` Ville Syrjälä
0 siblings, 1 reply; 50+ messages in thread
From: Navare, Manasi @ 2020-10-19 22:56 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Mon, Oct 19, 2020 at 07:20:31PM +0300, Ville Syrjälä wrote:
> On Thu, Oct 08, 2020 at 02:45:33PM -0700, Manasi Navare wrote:
> > From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> >
> > We need to look at hw.fb for the framebuffer, and add the translation
> > for the slave_plane_state. With these changes we set the correct
> > rectangle on the bigjoiner slave, and don't set incorrect
> > src/dst/visibility on the slave plane.
> >
> > v2:
> > * Manual rebase (Manasi)
> >
> > Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > ---
> > .../gpu/drm/i915/display/intel_atomic_plane.c | 60 +++++++++++++++++++
> > .../gpu/drm/i915/display/intel_atomic_plane.h | 4 ++
> > drivers/gpu/drm/i915/display/intel_display.c | 19 +++---
> > drivers/gpu/drm/i915/display/intel_sprite.c | 21 +++----
> > 4 files changed, 80 insertions(+), 24 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > index a8f1fd85a6c0..09cb3adc36da 100644
> > --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > @@ -267,6 +267,9 @@ void intel_plane_copy_uapi_to_hw_state(const struct intel_crtc_state *crtc_state
> > plane_state->hw.rotation = from_plane_state->uapi.rotation;
> > plane_state->hw.color_encoding = from_plane_state->uapi.color_encoding;
> > plane_state->hw.color_range = from_plane_state->uapi.color_range;
> > +
> > + plane_state->uapi.src = drm_plane_state_src(&from_plane_state->uapi);
> > + plane_state->uapi.dst = drm_plane_state_dest(&from_plane_state->uapi);
> > }
> >
> > void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
> > @@ -519,6 +522,63 @@ void i9xx_update_planes_on_crtc(struct intel_atomic_state *state,
> > }
> > }
> >
> > +int intel_atomic_plane_check_clipping(struct intel_plane_state *plane_state,
> > + struct intel_crtc_state *crtc_state,
> > + int min_scale, int max_scale,
> > + bool can_position)
> > +{
> > + struct drm_framebuffer *fb = plane_state->hw.fb;
> > + struct drm_rect *src = &plane_state->uapi.src;
> > + struct drm_rect *dst = &plane_state->uapi.dst;
> > + unsigned int rotation = plane_state->uapi.rotation;
>
> hw.rotation
So use hw.rotation instead of uapi.rotation ?
Manasi
>
> The rest seems consistent.
>
> > + struct drm_rect clip = {};
> > + int hscale, vscale;
> > +
> > + if (!fb) {
> > + plane_state->uapi.visible = false;
> > + return 0;
> > + }
> > +
> > + drm_rect_rotate(src, fb->width << 16, fb->height << 16, rotation);
> > +
> > + /* Check scaling */
> > + hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
> > + vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
> > + if (hscale < 0 || vscale < 0) {
> > + DRM_DEBUG_KMS("Invalid scaling of plane\n");
> > + drm_rect_debug_print("src: ", src, true);
> > + drm_rect_debug_print("dst: ", dst, false);
> > + return -ERANGE;
> > + }
> > +
> > + if (crtc_state->hw.enable) {
> > + clip.x2 = crtc_state->pipe_src_w;
> > + clip.y2 = crtc_state->pipe_src_h;
> > + }
> > +
> > + /* right side of the image is on the slave crtc, adjust dst to match */
> > + if (crtc_state->bigjoiner_slave)
> > + drm_rect_translate(dst, -crtc_state->pipe_src_w, 0);
> > +
> > + /*
> > + * FIXME: This might need further adjustment for seamless scaling
> > + * with phase information, for the 2p2 and 2p1 scenarios.
> > + */
> > + plane_state->uapi.visible = drm_rect_clip_scaled(src, dst, &clip);
> > +
> > + drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16, rotation);
> > +
> > + if (!can_position && plane_state->uapi.visible &&
> > + !drm_rect_equals(dst, &clip)) {
> > + DRM_DEBUG_KMS("Plane must cover entire CRTC\n");
> > + drm_rect_debug_print("dst: ", dst, false);
> > + drm_rect_debug_print("clip: ", &clip, false);
> > + return -EINVAL;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > const struct drm_plane_helper_funcs intel_plane_helper_funcs = {
> > .prepare_fb = intel_prepare_plane_fb,
> > .cleanup_fb = intel_cleanup_plane_fb,
> > diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> > index c2a1e7c86e6c..d0a599d00ecd 100644
> > --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> > +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> > @@ -53,6 +53,10 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
> > int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
> > struct intel_plane *plane,
> > bool *need_cdclk_calc);
> > +int intel_atomic_plane_check_clipping(struct intel_plane_state *plane_state,
> > + struct intel_crtc_state *crtc_state,
> > + int min_scale, int max_scale,
> > + bool can_position);
> > void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
> > struct intel_plane_state *plane_state);
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index d5a6f07bb674..357cc2bce300 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -4409,12 +4409,10 @@ i9xx_plane_check(struct intel_crtc_state *crtc_state,
> > if (ret)
> > return ret;
> >
> > - ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
> > - &crtc_state->uapi,
> > - DRM_PLANE_HELPER_NO_SCALING,
> > - DRM_PLANE_HELPER_NO_SCALING,
> > - i9xx_plane_has_windowing(plane),
> > - true);
> > + ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,
> > + DRM_PLANE_HELPER_NO_SCALING,
> > + DRM_PLANE_HELPER_NO_SCALING,
> > + i9xx_plane_has_windowing(plane));
> > if (ret)
> > return ret;
> >
> > @@ -11611,11 +11609,10 @@ static int intel_check_cursor(struct intel_crtc_state *crtc_state,
> > return -EINVAL;
> > }
> >
> > - ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
> > - &crtc_state->uapi,
> > - DRM_PLANE_HELPER_NO_SCALING,
> > - DRM_PLANE_HELPER_NO_SCALING,
> > - true, true);
> > + ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,
> > + DRM_PLANE_HELPER_NO_SCALING,
> > + DRM_PLANE_HELPER_NO_SCALING,
> > + true);
> > if (ret)
> > return ret;
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> > index 2da11ab6343c..9e235210adc7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> > @@ -2047,10 +2047,8 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state,
> > }
> > }
> >
> > - ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
> > - &crtc_state->uapi,
> > - min_scale, max_scale,
> > - true, true);
> > + ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,
> > + min_scale, max_scale, true);
> > if (ret)
> > return ret;
> >
> > @@ -2105,11 +2103,10 @@ vlv_sprite_check(struct intel_crtc_state *crtc_state,
> > if (ret)
> > return ret;
> >
> > - ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
> > - &crtc_state->uapi,
> > - DRM_PLANE_HELPER_NO_SCALING,
> > - DRM_PLANE_HELPER_NO_SCALING,
> > - true, true);
> > + ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,
> > + DRM_PLANE_HELPER_NO_SCALING,
> > + DRM_PLANE_HELPER_NO_SCALING,
> > + true);
> > if (ret)
> > return ret;
> >
> > @@ -2316,10 +2313,8 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
> > max_scale = skl_plane_max_scale(dev_priv, fb);
> > }
> >
> > - ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
> > - &crtc_state->uapi,
> > - min_scale, max_scale,
> > - true, true);
> > + ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,
> > + min_scale, max_scale, true);
> > if (ret)
> > return ret;
> >
> > --
> > 2.19.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v10 10/11] drm/i915: Ensure correct master/slave enable/disable sequence
2020-10-19 16:26 ` Ville Syrjälä
@ 2020-10-19 23:05 ` Navare, Manasi
0 siblings, 0 replies; 50+ messages in thread
From: Navare, Manasi @ 2020-10-19 23:05 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Mon, Oct 19, 2020 at 07:26:19PM +0300, Ville Syrjälä wrote:
> On Thu, Oct 08, 2020 at 02:45:34PM -0700, Manasi Navare wrote:
> > From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> >
> > Enabling is done in a special sequence and so should plane updates
> > be. Ideally the end user never notices the second pipe is used.
> >
> > This way ideally everything will be tear free, and updates are
> > really atomic as userspace expects it.
> >
> > This uses generic modeset_enables() calls like trans port sync
> > but still has special handling for disable since for slave we
> > should not disable things like encoder, plls that are not enabled
> > for slave.
> >
> > v3:
> > * Fixes in enable and disable sequence from testing (Manasi)
> > v2:
> > * Manual Rebase (Manasi)
> > * Refactoring on intel_update_crtc and enable_crtc and removing
> > special trans_port_sync_update (Manasi)
> >
> > Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 55 ++++++++++++++------
> > drivers/gpu/drm/i915/display/intel_sprite.c | 5 +-
> > 2 files changed, 43 insertions(+), 17 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index 357cc2bce300..101ddd0b48ab 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -15878,6 +15878,9 @@ static void intel_enable_crtc(struct intel_atomic_state *state,
> >
> > dev_priv->display.crtc_enable(state, crtc);
> >
> > + if (new_crtc_state->bigjoiner_slave)
> > + return;
> > +
> > /* vblanks work again, re-enable pipe CRC. */
> > intel_crtc_enable_pipe_crc(crtc);
> > }
> > @@ -15914,9 +15917,7 @@ static void intel_update_crtc(struct intel_atomic_state *state,
> >
> > commit_pipe_config(state, crtc);
> >
> > - if (new_crtc_state->bigjoiner) {
> > - /* Not supported yet */
> > - } else if (INTEL_GEN(dev_priv) >= 9)
> > + if (INTEL_GEN(dev_priv) >= 9)
> > skl_update_planes_on_crtc(state, crtc);
> > else
> > i9xx_update_planes_on_crtc(state, crtc);
> > @@ -15945,9 +15946,17 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
> > drm_WARN_ON(&dev_priv->drm, old_crtc_state->bigjoiner_slave);
> >
> > intel_crtc_disable_planes(state, crtc);
> > - if (old_crtc_state->bigjoiner)
> > +
> > + /*
> > + * We still need special handling for disabling bigjoiner master
> > + * and slaves since for slave we do not have encoder or plls
> > + * so we dont need to disable those.
> > + */
> > + if (old_crtc_state->bigjoiner) {
> > intel_crtc_disable_planes(state,
> > old_crtc_state->bigjoiner_linked_crtc);
> > + old_crtc_state->bigjoiner_linked_crtc->active = false;
> > + }
> >
> > /*
> > * We need to disable pipe CRC before disabling the pipe,
> > @@ -15977,7 +15986,7 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state)
> > /* Only disable port sync and MST slaves */
> > for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> > new_crtc_state, i) {
> > - if (!needs_modeset(new_crtc_state) || old_crtc_state->bigjoiner_slave)
> > + if (!needs_modeset(new_crtc_state) || old_crtc_state->bigjoiner)
> > continue;
> >
> > if (!old_crtc_state->hw.active)
> > @@ -16040,6 +16049,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
> > struct intel_crtc *crtc;
> > struct intel_crtc_state *old_crtc_state, *new_crtc_state;
> > struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
> > + struct skl_ddb_entry new_entries[I915_MAX_PIPES] = {};
> > u8 update_pipes = 0, modeset_pipes = 0;
> > int i;
> >
> > @@ -16056,6 +16066,14 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
> > } else {
> > modeset_pipes |= BIT(pipe);
> > }
> > +
> > + new_entries[i] = new_crtc_state->wm.skl.ddb;
> > +
> > + /* ignore allocations for crtc's that have been turned off during modeset. */
> > + if (needs_modeset(new_crtc_state))
> > + continue;
> > +
> > + entries[i] = old_crtc_state->wm.skl.ddb;
> > }
> >
> > /*
> > @@ -16071,28 +16089,28 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
> > for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> > new_crtc_state, i) {
> > enum pipe pipe = crtc->pipe;
> > + bool ddb_changed;
> >
> > if ((update_pipes & BIT(pipe)) == 0)
> > continue;
> >
> > - if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
> > + if (skl_ddb_allocation_overlaps(&new_entries[pipe],
> > entries, I915_MAX_PIPES, pipe))
> > continue;
> >
> > - entries[pipe] = new_crtc_state->wm.skl.ddb;
> > + ddb_changed = !skl_ddb_entry_equal(&new_entries[pipe], &entries[pipe]);
> > + entries[pipe] = new_entries[pipe];
> > update_pipes &= ~BIT(pipe);
> >
> > - intel_update_crtc(state, crtc);
> > -
> > /*
> > * If this is an already active pipe, it's DDB changed,
> > * and this isn't the last pipe that needs updating
> > * then we need to wait for a vblank to pass for the
> > * new ddb allocation to take effect.
> > */
> > - if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
> > - &old_crtc_state->wm.skl.ddb) &&
> > - (update_pipes | modeset_pipes))
> > + intel_update_crtc(state, crtc);
> > +
> > + if (ddb_changed && (update_pipes | modeset_pipes))
> > intel_wait_for_vblank(dev_priv, pipe);
>
> What are these ddb changes trying to achieve?
Maarten had these in the attempt of making sure we account for master and slave ddb entries.
Do we jus remove these changes for now since we are treating them like 2p2p now?
>
> > }
> > }
> > @@ -16110,7 +16128,8 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
> > continue;
> >
> > if (intel_dp_mst_is_slave_trans(new_crtc_state) ||
> > - is_trans_port_sync_master(new_crtc_state))
> > + is_trans_port_sync_master(new_crtc_state) ||
> > + (new_crtc_state->bigjoiner && !new_crtc_state->bigjoiner_slave))
> > continue;
> >
> > modeset_pipes &= ~BIT(pipe);
> > @@ -16120,7 +16139,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
> >
> > /*
> > * Then we enable all remaining pipes that depend on other
> > - * pipes: MST slaves and port sync masters.
> > + * pipes: MST slaves and port sync masters, big joiner master
> > */
> > for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> > enum pipe pipe = crtc->pipe;
> > @@ -16128,6 +16147,10 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
> > if ((modeset_pipes & BIT(pipe)) == 0)
> > continue;
> >
> > + WARN_ON(skl_ddb_allocation_overlaps(&new_entries[pipe],
> > + entries, I915_MAX_PIPES, pipe));
> > +
> > + entries[pipe] = new_entries[pipe];
> > modeset_pipes &= ~BIT(pipe);
> >
> > intel_enable_crtc(state, crtc);
> > @@ -16142,10 +16165,10 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
> > if ((update_pipes & BIT(pipe)) == 0)
> > continue;
> >
> > - drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
> > + drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_entries[pipe],
> > entries, I915_MAX_PIPES, pipe));
> >
> > - entries[pipe] = new_crtc_state->wm.skl.ddb;
> > + entries[pipe] = new_entries[pipe];
> > update_pipes &= ~BIT(pipe);
> >
> > intel_update_crtc(state, crtc);
> > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> > index 9e235210adc7..1c740a22a8d7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> > @@ -103,6 +103,8 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
> >
> > /* FIXME needs to be calibrated sensibly */
> > min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
> > + new_crtc_state->bigjoiner ?
> > + 2 * VBLANK_EVASION_TIME_US :
> > VBLANK_EVASION_TIME_US);
> > max = vblank_start - 1;
> >
> > @@ -227,7 +229,8 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
> >
> > spin_lock(&crtc->base.dev->event_lock);
> > drm_crtc_arm_vblank_event(&crtc->base,
> > - new_crtc_state->uapi.event);
> > + new_crtc_state->uapi.event);
> > +
>
> Spurious whitespace change.
Yes will fix that, everything else here looks good?
Manasi
>
> > spin_unlock(&crtc->base.dev->event_lock);
> >
> > new_crtc_state->uapi.event = NULL;
> > --
> > 2.19.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v10 04/11] drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.
2020-10-08 21:45 ` [Intel-gfx] [PATCH v10 04/11] drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3 Manasi Navare
2020-10-14 11:26 ` Ville Syrjälä
@ 2020-10-20 18:39 ` Ville Syrjälä
2020-10-20 18:53 ` Navare, Manasi
1 sibling, 1 reply; 50+ messages in thread
From: Ville Syrjälä @ 2020-10-20 18:39 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
On Thu, Oct 08, 2020 at 02:45:28PM -0700, Manasi Navare wrote:
> From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
>
> Small changes to intel_dp_mode_valid(), allow listing modes that
> can only be supported in the bigjoiner configuration, which is
> not supported yet.
>
> eDP does not support bigjoiner, so do not expose bigjoiner only
> modes on the eDP port.
>
> v7:
> * Add can_bigjoiner() helper (Ville)
> * Pass bigjoiner to plane_size validation (Ville)
> v6:
> * Rebase after dp_downstream mode valid changes (Manasi)
> v5:
> * Increase max plane width to support 8K with bigjoiner (Maarten)
> v4:
> * Rebase (Manasi)
>
> Changes since v1:
> - Disallow bigjoiner on eDP.
> Changes since v2:
> - Rename intel_dp_downstream_max_dotclock to intel_dp_max_dotclock,
> and split off the downstream and source checking to its own function.
> (Ville)
> v3:
> * Rebase (Manasi)
>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 5 +-
> drivers/gpu/drm/i915/display/intel_display.h | 3 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 126 +++++++++++++++----
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
> drivers/gpu/drm/i915/display/intel_dsi.c | 2 +-
> drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
> 6 files changed, 111 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 723766b1eae3..cc540c7b7dcd 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -17642,7 +17642,8 @@ intel_mode_valid(struct drm_device *dev,
>
> enum drm_mode_status
> intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
> - const struct drm_display_mode *mode)
> + const struct drm_display_mode *mode,
> + bool bigjoiner)
> {
> int plane_width_max, plane_height_max;
>
> @@ -17659,7 +17660,7 @@ intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
> * too big for that.
> */
> if (INTEL_GEN(dev_priv) >= 11) {
> - plane_width_max = 5120;
> + plane_width_max = 5120 << bigjoiner;
> plane_height_max = 4320;
> } else {
> plane_width_max = 5120;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index d10b7c8cde3f..3d860a9da8fe 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -496,7 +496,8 @@ u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
> bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
> enum drm_mode_status
> intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
> - const struct drm_display_mode *mode);
> + const struct drm_display_mode *mode,
> + bool bigjoiner);
> enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
> bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 8a522edd7386..af2ff425e5d5 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -247,6 +247,29 @@ intel_dp_max_data_rate(int max_link_clock, int max_lanes)
> return max_link_clock * max_lanes;
> }
>
> +static int source_max_dotclock(struct intel_dp *intel_dp, bool allow_bigjoiner)
> +{
> + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> + struct intel_encoder *encoder = &intel_dig_port->base;
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +
> + if (allow_bigjoiner && INTEL_GEN(dev_priv) >= 11 && !intel_dp_is_edp(intel_dp))
Wasn't this supposed to be s/edp/port==A/ ?
> + return 2 * dev_priv->max_dotclk_freq;
> +
> + return dev_priv->max_dotclk_freq;
> +}
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v10 07/11] drm/i915: Make hardware readout work on i915.
2020-10-19 22:45 ` Navare, Manasi
@ 2020-10-20 18:45 ` Ville Syrjälä
2020-10-20 18:57 ` Navare, Manasi
0 siblings, 1 reply; 50+ messages in thread
From: Ville Syrjälä @ 2020-10-20 18:45 UTC (permalink / raw)
To: Navare, Manasi; +Cc: intel-gfx
On Mon, Oct 19, 2020 at 03:45:04PM -0700, Navare, Manasi wrote:
> On Mon, Oct 19, 2020 at 07:36:59PM +0300, Ville Syrjälä wrote:
> > On Thu, Oct 08, 2020 at 02:45:31PM -0700, Manasi Navare wrote:
> > > From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > >
> > > Unfortunately I have no way to test this, but it should be correct
> > > if the bios sets up bigjoiner in a sane way.
> > >
> > > Skip iterating over bigjoiner slaves, only the master has the state we
> > > care about.
> > >
> > > Add the width of the bigjoiner slave to the reconstructed fb.
> > >
> > > Hide the bigjoiner slave to userspace, and double the mode on bigjoiner
> > > master.
> > >
> > > And last, disable bigjoiner slave from primary if reconstruction fails.
> > >
> > > v2:
> > > * Manual Rebase (Manasi)
> > >
> > > Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_display.c | 64 +++++++++++++++++++-
> > > 1 file changed, 62 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > index faf8bf757bed..aa981aa4f6a1 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -3619,6 +3619,8 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
> > > struct intel_plane *intel_plane = to_intel_plane(primary);
> > > struct intel_plane_state *intel_state =
> > > to_intel_plane_state(plane_state);
> > > + struct intel_crtc_state *crtc_state =
> >
> > Whitespace fail. Didn't checkpatch complain?
>
> I will fix this
>
> >
> > > + to_intel_crtc_state(intel_crtc->base.state);
> > > struct drm_framebuffer *fb;
> > > struct i915_vma *vma;
> > >
> > > @@ -3641,7 +3643,7 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
> > > if (c == &intel_crtc->base)
> > > continue;
> > >
> > > - if (!to_intel_crtc(c)->active)
> > > + if (!to_intel_crtc_state(c->state)->uapi.active)
> > > continue;
> > >
> > > state = to_intel_plane_state(c->primary->state);
> > > @@ -3663,6 +3665,11 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
> > > * pretend the BIOS never had it enabled.
> > > */
> > > intel_plane_disable_noatomic(intel_crtc, intel_plane);
> > > + if (crtc_state->bigjoiner) {
> > > + struct intel_crtc *slave =
> > > + crtc_state->bigjoiner_linked_crtc;
> > > + intel_plane_disable_noatomic(slave, to_intel_plane(slave->base.primary));
> > > + }
> > >
> > > return;
> > >
> > > @@ -10687,6 +10694,7 @@ static void
> > > skl_get_initial_plane_config(struct intel_crtc *crtc,
> > > struct intel_initial_plane_config *plane_config)
> > > {
> > > + struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
> > > struct drm_device *dev = crtc->base.dev;
> > > struct drm_i915_private *dev_priv = to_i915(dev);
> > > struct intel_plane *plane = to_intel_plane(crtc->base.primary);
> > > @@ -10795,6 +10803,18 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
> > > fb->height = ((val >> 16) & 0xffff) + 1;
> > > fb->width = ((val >> 0) & 0xffff) + 1;
> > >
> > > + /* add bigjoiner slave as well, if the fb stretches both */
> > > + if (crtc_state->bigjoiner) {
> > > + enum pipe bigjoiner_pipe = crtc_state->bigjoiner_linked_crtc->pipe;
> > > +
> > > + if (fb->width == crtc_state->pipe_src_w &&
> > > + (intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & 0xfffff000) == plane_config->base) {
> > > + val = intel_de_read(dev_priv, PLANE_SIZE(bigjoiner_pipe, plane_id));
> > > + fb->height += ((val >> 16) & 0xfff) + 1;
> > > + fb->width += ((val >> 0) & 0x1fff) + 1;
> >
> > This looks wrong.
>
> Why is it wrong? Double checked the plane size width and height bits from bspec
> and the mask looks correct here.
> Can you elaborate on what is wrong here?
The pipes are side-by-side.
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v10 09/11] drm/i915: Add bigjoiner aware plane clipping checks
2020-10-19 22:56 ` Navare, Manasi
@ 2020-10-20 18:51 ` Ville Syrjälä
0 siblings, 0 replies; 50+ messages in thread
From: Ville Syrjälä @ 2020-10-20 18:51 UTC (permalink / raw)
To: Navare, Manasi; +Cc: intel-gfx
On Mon, Oct 19, 2020 at 03:56:37PM -0700, Navare, Manasi wrote:
> On Mon, Oct 19, 2020 at 07:20:31PM +0300, Ville Syrjälä wrote:
> > On Thu, Oct 08, 2020 at 02:45:33PM -0700, Manasi Navare wrote:
> > > From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > >
> > > We need to look at hw.fb for the framebuffer, and add the translation
> > > for the slave_plane_state. With these changes we set the correct
> > > rectangle on the bigjoiner slave, and don't set incorrect
> > > src/dst/visibility on the slave plane.
> > >
> > > v2:
> > > * Manual rebase (Manasi)
> > >
> > > Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > > ---
> > > .../gpu/drm/i915/display/intel_atomic_plane.c | 60 +++++++++++++++++++
> > > .../gpu/drm/i915/display/intel_atomic_plane.h | 4 ++
> > > drivers/gpu/drm/i915/display/intel_display.c | 19 +++---
> > > drivers/gpu/drm/i915/display/intel_sprite.c | 21 +++----
> > > 4 files changed, 80 insertions(+), 24 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > > index a8f1fd85a6c0..09cb3adc36da 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > > @@ -267,6 +267,9 @@ void intel_plane_copy_uapi_to_hw_state(const struct intel_crtc_state *crtc_state
> > > plane_state->hw.rotation = from_plane_state->uapi.rotation;
> > > plane_state->hw.color_encoding = from_plane_state->uapi.color_encoding;
> > > plane_state->hw.color_range = from_plane_state->uapi.color_range;
> > > +
> > > + plane_state->uapi.src = drm_plane_state_src(&from_plane_state->uapi);
> > > + plane_state->uapi.dst = drm_plane_state_dest(&from_plane_state->uapi);
> > > }
> > >
> > > void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
> > > @@ -519,6 +522,63 @@ void i9xx_update_planes_on_crtc(struct intel_atomic_state *state,
> > > }
> > > }
> > >
> > > +int intel_atomic_plane_check_clipping(struct intel_plane_state *plane_state,
> > > + struct intel_crtc_state *crtc_state,
> > > + int min_scale, int max_scale,
> > > + bool can_position)
> > > +{
> > > + struct drm_framebuffer *fb = plane_state->hw.fb;
> > > + struct drm_rect *src = &plane_state->uapi.src;
> > > + struct drm_rect *dst = &plane_state->uapi.dst;
> > > + unsigned int rotation = plane_state->uapi.rotation;
> >
> > hw.rotation
>
> So use hw.rotation instead of uapi.rotation ?
Yes.
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v10 04/11] drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.
2020-10-20 18:39 ` Ville Syrjälä
@ 2020-10-20 18:53 ` Navare, Manasi
0 siblings, 0 replies; 50+ messages in thread
From: Navare, Manasi @ 2020-10-20 18:53 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Tue, Oct 20, 2020 at 09:39:53PM +0300, Ville Syrjälä wrote:
> On Thu, Oct 08, 2020 at 02:45:28PM -0700, Manasi Navare wrote:
> > From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> >
> > Small changes to intel_dp_mode_valid(), allow listing modes that
> > can only be supported in the bigjoiner configuration, which is
> > not supported yet.
> >
> > eDP does not support bigjoiner, so do not expose bigjoiner only
> > modes on the eDP port.
> >
> > v7:
> > * Add can_bigjoiner() helper (Ville)
> > * Pass bigjoiner to plane_size validation (Ville)
> > v6:
> > * Rebase after dp_downstream mode valid changes (Manasi)
> > v5:
> > * Increase max plane width to support 8K with bigjoiner (Maarten)
> > v4:
> > * Rebase (Manasi)
> >
> > Changes since v1:
> > - Disallow bigjoiner on eDP.
> > Changes since v2:
> > - Rename intel_dp_downstream_max_dotclock to intel_dp_max_dotclock,
> > and split off the downstream and source checking to its own function.
> > (Ville)
> > v3:
> > * Rebase (Manasi)
> >
> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 5 +-
> > drivers/gpu/drm/i915/display/intel_display.h | 3 +-
> > drivers/gpu/drm/i915/display/intel_dp.c | 126 +++++++++++++++----
> > drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_dsi.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
> > 6 files changed, 111 insertions(+), 29 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index 723766b1eae3..cc540c7b7dcd 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -17642,7 +17642,8 @@ intel_mode_valid(struct drm_device *dev,
> >
> > enum drm_mode_status
> > intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
> > - const struct drm_display_mode *mode)
> > + const struct drm_display_mode *mode,
> > + bool bigjoiner)
> > {
> > int plane_width_max, plane_height_max;
> >
> > @@ -17659,7 +17660,7 @@ intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
> > * too big for that.
> > */
> > if (INTEL_GEN(dev_priv) >= 11) {
> > - plane_width_max = 5120;
> > + plane_width_max = 5120 << bigjoiner;
> > plane_height_max = 4320;
> > } else {
> > plane_width_max = 5120;
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> > index d10b7c8cde3f..3d860a9da8fe 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display.h
> > @@ -496,7 +496,8 @@ u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
> > bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
> > enum drm_mode_status
> > intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
> > - const struct drm_display_mode *mode);
> > + const struct drm_display_mode *mode,
> > + bool bigjoiner);
> > enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
> > bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 8a522edd7386..af2ff425e5d5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -247,6 +247,29 @@ intel_dp_max_data_rate(int max_link_clock, int max_lanes)
> > return max_link_clock * max_lanes;
> > }
> >
> > +static int source_max_dotclock(struct intel_dp *intel_dp, bool allow_bigjoiner)
> > +{
> > + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> > + struct intel_encoder *encoder = &intel_dig_port->base;
> > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > +
> > + if (allow_bigjoiner && INTEL_GEN(dev_priv) >= 11 && !intel_dp_is_edp(intel_dp))
>
> Wasn't this supposed to be s/edp/port==A/ ?
Yes will use the new function intel_dp_can_bigjoiner() here instead that checks for PORT A
Manasi
>
> > + return 2 * dev_priv->max_dotclk_freq;
> > +
> > + return dev_priv->max_dotclk_freq;
> > +}
> --
> Ville Syrjälä
> Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v10 07/11] drm/i915: Make hardware readout work on i915.
2020-10-20 18:45 ` Ville Syrjälä
@ 2020-10-20 18:57 ` Navare, Manasi
2020-10-20 21:57 ` Navare, Manasi
0 siblings, 1 reply; 50+ messages in thread
From: Navare, Manasi @ 2020-10-20 18:57 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Tue, Oct 20, 2020 at 09:45:02PM +0300, Ville Syrjälä wrote:
> On Mon, Oct 19, 2020 at 03:45:04PM -0700, Navare, Manasi wrote:
> > On Mon, Oct 19, 2020 at 07:36:59PM +0300, Ville Syrjälä wrote:
> > > On Thu, Oct 08, 2020 at 02:45:31PM -0700, Manasi Navare wrote:
> > > > From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > > >
> > > > Unfortunately I have no way to test this, but it should be correct
> > > > if the bios sets up bigjoiner in a sane way.
> > > >
> > > > Skip iterating over bigjoiner slaves, only the master has the state we
> > > > care about.
> > > >
> > > > Add the width of the bigjoiner slave to the reconstructed fb.
> > > >
> > > > Hide the bigjoiner slave to userspace, and double the mode on bigjoiner
> > > > master.
> > > >
> > > > And last, disable bigjoiner slave from primary if reconstruction fails.
> > > >
> > > > v2:
> > > > * Manual Rebase (Manasi)
> > > >
> > > > Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_display.c | 64 +++++++++++++++++++-
> > > > 1 file changed, 62 insertions(+), 2 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > > index faf8bf757bed..aa981aa4f6a1 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > @@ -3619,6 +3619,8 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
> > > > struct intel_plane *intel_plane = to_intel_plane(primary);
> > > > struct intel_plane_state *intel_state =
> > > > to_intel_plane_state(plane_state);
> > > > + struct intel_crtc_state *crtc_state =
> > >
> > > Whitespace fail. Didn't checkpatch complain?
> >
> > I will fix this
> >
> > >
> > > > + to_intel_crtc_state(intel_crtc->base.state);
> > > > struct drm_framebuffer *fb;
> > > > struct i915_vma *vma;
> > > >
> > > > @@ -3641,7 +3643,7 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
> > > > if (c == &intel_crtc->base)
> > > > continue;
> > > >
> > > > - if (!to_intel_crtc(c)->active)
> > > > + if (!to_intel_crtc_state(c->state)->uapi.active)
> > > > continue;
> > > >
> > > > state = to_intel_plane_state(c->primary->state);
> > > > @@ -3663,6 +3665,11 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
> > > > * pretend the BIOS never had it enabled.
> > > > */
> > > > intel_plane_disable_noatomic(intel_crtc, intel_plane);
> > > > + if (crtc_state->bigjoiner) {
> > > > + struct intel_crtc *slave =
> > > > + crtc_state->bigjoiner_linked_crtc;
> > > > + intel_plane_disable_noatomic(slave, to_intel_plane(slave->base.primary));
> > > > + }
> > > >
> > > > return;
> > > >
> > > > @@ -10687,6 +10694,7 @@ static void
> > > > skl_get_initial_plane_config(struct intel_crtc *crtc,
> > > > struct intel_initial_plane_config *plane_config)
> > > > {
> > > > + struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
> > > > struct drm_device *dev = crtc->base.dev;
> > > > struct drm_i915_private *dev_priv = to_i915(dev);
> > > > struct intel_plane *plane = to_intel_plane(crtc->base.primary);
> > > > @@ -10795,6 +10803,18 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
> > > > fb->height = ((val >> 16) & 0xffff) + 1;
> > > > fb->width = ((val >> 0) & 0xffff) + 1;
> > > >
> > > > + /* add bigjoiner slave as well, if the fb stretches both */
> > > > + if (crtc_state->bigjoiner) {
> > > > + enum pipe bigjoiner_pipe = crtc_state->bigjoiner_linked_crtc->pipe;
> > > > +
> > > > + if (fb->width == crtc_state->pipe_src_w &&
> > > > + (intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & 0xfffff000) == plane_config->base) {
> > > > + val = intel_de_read(dev_priv, PLANE_SIZE(bigjoiner_pipe, plane_id));
> > > > + fb->height += ((val >> 16) & 0xfff) + 1;
> > > > + fb->width += ((val >> 0) & 0x1fff) + 1;
> > >
> > > This looks wrong.
> >
> > Why is it wrong? Double checked the plane size width and height bits from bspec
> > and the mask looks correct here.
> > Can you elaborate on what is wrong here?
>
> The pipes are side-by-side.
Yes the master and slave pipes are consecutive, still not sure what is required to correct the logic here
Manasi
>
> --
> Ville Syrjälä
> Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v10 07/11] drm/i915: Make hardware readout work on i915.
2020-10-20 18:57 ` Navare, Manasi
@ 2020-10-20 21:57 ` Navare, Manasi
0 siblings, 0 replies; 50+ messages in thread
From: Navare, Manasi @ 2020-10-20 21:57 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Tue, Oct 20, 2020 at 11:57:52AM -0700, Navare, Manasi wrote:
> On Tue, Oct 20, 2020 at 09:45:02PM +0300, Ville Syrjälä wrote:
> > On Mon, Oct 19, 2020 at 03:45:04PM -0700, Navare, Manasi wrote:
> > > On Mon, Oct 19, 2020 at 07:36:59PM +0300, Ville Syrjälä wrote:
> > > > On Thu, Oct 08, 2020 at 02:45:31PM -0700, Manasi Navare wrote:
> > > > > From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > > > >
> > > > > Unfortunately I have no way to test this, but it should be correct
> > > > > if the bios sets up bigjoiner in a sane way.
> > > > >
> > > > > Skip iterating over bigjoiner slaves, only the master has the state we
> > > > > care about.
> > > > >
> > > > > Add the width of the bigjoiner slave to the reconstructed fb.
> > > > >
> > > > > Hide the bigjoiner slave to userspace, and double the mode on bigjoiner
> > > > > master.
> > > > >
> > > > > And last, disable bigjoiner slave from primary if reconstruction fails.
> > > > >
> > > > > v2:
> > > > > * Manual Rebase (Manasi)
> > > > >
> > > > > Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > > > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > > > > ---
> > > > > drivers/gpu/drm/i915/display/intel_display.c | 64 +++++++++++++++++++-
> > > > > 1 file changed, 62 insertions(+), 2 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > index faf8bf757bed..aa981aa4f6a1 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > @@ -3619,6 +3619,8 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
> > > > > struct intel_plane *intel_plane = to_intel_plane(primary);
> > > > > struct intel_plane_state *intel_state =
> > > > > to_intel_plane_state(plane_state);
> > > > > + struct intel_crtc_state *crtc_state =
> > > >
> > > > Whitespace fail. Didn't checkpatch complain?
> > >
> > > I will fix this
> > >
> > > >
> > > > > + to_intel_crtc_state(intel_crtc->base.state);
> > > > > struct drm_framebuffer *fb;
> > > > > struct i915_vma *vma;
> > > > >
> > > > > @@ -3641,7 +3643,7 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
> > > > > if (c == &intel_crtc->base)
> > > > > continue;
> > > > >
> > > > > - if (!to_intel_crtc(c)->active)
> > > > > + if (!to_intel_crtc_state(c->state)->uapi.active)
> > > > > continue;
> > > > >
> > > > > state = to_intel_plane_state(c->primary->state);
> > > > > @@ -3663,6 +3665,11 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
> > > > > * pretend the BIOS never had it enabled.
> > > > > */
> > > > > intel_plane_disable_noatomic(intel_crtc, intel_plane);
> > > > > + if (crtc_state->bigjoiner) {
> > > > > + struct intel_crtc *slave =
> > > > > + crtc_state->bigjoiner_linked_crtc;
> > > > > + intel_plane_disable_noatomic(slave, to_intel_plane(slave->base.primary));
> > > > > + }
> > > > >
> > > > > return;
> > > > >
> > > > > @@ -10687,6 +10694,7 @@ static void
> > > > > skl_get_initial_plane_config(struct intel_crtc *crtc,
> > > > > struct intel_initial_plane_config *plane_config)
> > > > > {
> > > > > + struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
> > > > > struct drm_device *dev = crtc->base.dev;
> > > > > struct drm_i915_private *dev_priv = to_i915(dev);
> > > > > struct intel_plane *plane = to_intel_plane(crtc->base.primary);
> > > > > @@ -10795,6 +10803,18 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
> > > > > fb->height = ((val >> 16) & 0xffff) + 1;
> > > > > fb->width = ((val >> 0) & 0xffff) + 1;
> > > > >
> > > > > + /* add bigjoiner slave as well, if the fb stretches both */
> > > > > + if (crtc_state->bigjoiner) {
> > > > > + enum pipe bigjoiner_pipe = crtc_state->bigjoiner_linked_crtc->pipe;
> > > > > +
> > > > > + if (fb->width == crtc_state->pipe_src_w &&
> > > > > + (intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & 0xfffff000) == plane_config->base) {
> > > > > + val = intel_de_read(dev_priv, PLANE_SIZE(bigjoiner_pipe, plane_id));
> > > > > + fb->height += ((val >> 16) & 0xfff) + 1;
> > > > > + fb->width += ((val >> 0) & 0x1fff) + 1;
> > > >
> > > > This looks wrong.
> > >
> > > Why is it wrong? Double checked the plane size width and height bits from bspec
> > > and the mask looks correct here.
> > > Can you elaborate on what is wrong here?
> >
> > The pipes are side-by-side.
Gotcha, so Only the fb->width needs to be modified to add the width of slave pipe and keep height as is
Right? I will fix this in the next rev
Manasi
>
> Yes the master and slave pipes are consecutive, still not sure what is required to correct the logic here
>
> Manasi
>
> >
> > --
> > Ville Syrjälä
> > Intel
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
end of thread, other threads:[~2020-10-20 21:56 UTC | newest]
Thread overview: 50+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-10-08 21:45 [Intel-gfx] [PATCH v10 01/11] HAX to make DSC work on the icelake test system Manasi Navare
2020-10-08 21:45 ` [Intel-gfx] [PATCH v10 02/11] drm/i915/display: Rename pipe_timings to transcoder_timings Manasi Navare
2020-10-08 21:45 ` [Intel-gfx] [PATCH v10 03/11] drm/i915: Add hw.pipe_mode to allow bigjoiner pipe/transcoder split Manasi Navare
2020-10-08 21:45 ` [Intel-gfx] [PATCH v10 04/11] drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3 Manasi Navare
2020-10-14 11:26 ` Ville Syrjälä
2020-10-14 19:04 ` Navare, Manasi
2020-10-15 11:52 ` Ville Syrjälä
2020-10-15 16:26 ` Navare, Manasi
2020-10-19 16:30 ` Ville Syrjälä
2020-10-19 22:51 ` Navare, Manasi
2020-10-20 18:39 ` Ville Syrjälä
2020-10-20 18:53 ` Navare, Manasi
2020-10-08 21:45 ` [Intel-gfx] [PATCH v10 05/11] drm/i915: Try to make bigjoiner work in atomic check Manasi Navare
2020-10-11 11:18 ` kernel test robot
2020-10-14 11:33 ` Ville Syrjälä
2020-10-14 19:09 ` Navare, Manasi
2020-10-08 21:45 ` [Intel-gfx] [PATCH v10 06/11] drm/i915: Enable big joiner support in enable and disable sequences Manasi Navare
2020-10-14 11:07 ` Jani Nikula
2020-10-15 13:07 ` Ville Syrjälä
2020-10-15 16:37 ` Navare, Manasi
2020-10-16 16:06 ` Ville Syrjälä
2020-10-16 18:17 ` Navare, Manasi
2020-10-16 18:50 ` Ville Syrjälä
2020-10-16 19:24 ` Navare, Manasi
2020-10-19 11:34 ` Jani Nikula
2020-10-19 22:53 ` Navare, Manasi
2020-10-08 21:45 ` [Intel-gfx] [PATCH v10 07/11] drm/i915: Make hardware readout work on i915 Manasi Navare
2020-10-11 20:18 ` kernel test robot
2020-10-19 16:36 ` Ville Syrjälä
2020-10-19 22:45 ` Navare, Manasi
2020-10-20 18:45 ` Ville Syrjälä
2020-10-20 18:57 ` Navare, Manasi
2020-10-20 21:57 ` Navare, Manasi
2020-10-08 21:45 ` [Intel-gfx] [PATCH v10 08/11] drm/i915: Link planes in a bigjoiner configuration, v3 Manasi Navare
2020-10-08 21:45 ` [Intel-gfx] [PATCH v10 09/11] drm/i915: Add bigjoiner aware plane clipping checks Manasi Navare
2020-10-19 16:20 ` Ville Syrjälä
2020-10-19 22:56 ` Navare, Manasi
2020-10-20 18:51 ` Ville Syrjälä
2020-10-08 21:45 ` [Intel-gfx] [PATCH v10 10/11] drm/i915: Ensure correct master/slave enable/disable sequence Manasi Navare
2020-10-19 16:26 ` Ville Syrjälä
2020-10-19 23:05 ` Navare, Manasi
2020-10-08 21:45 ` [Intel-gfx] [PATCH v10 11/11] drm/i915: Add debugfs dumping for bigjoiner, v3 Manasi Navare
2020-10-08 22:15 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v10,01/11] HAX to make DSC work on the icelake test system Patchwork
2020-10-08 22:17 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-10-08 22:33 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-09 1:32 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-10-13 19:19 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v10,01/11] HAX to make DSC work on the icelake test system (rev2) Patchwork
2020-10-13 19:21 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-10-13 19:45 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-14 14:32 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.