* [RFC] drm/hdcp: Max MST content streams
@ 2020-10-19 7:12 ` Anshuman Gupta
0 siblings, 0 replies; 10+ messages in thread
From: Anshuman Gupta @ 2020-10-19 7:12 UTC (permalink / raw)
To: dri-devel, intel-gfx; +Cc: Anshuman Gupta, Sean Paul
Let's define Maximum MST content streams up to four
generically which can be supported by modern display
controllers.
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
include/drm/drm_hdcp.h | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
index fe58dbb46962..ac22c246542a 100644
--- a/include/drm/drm_hdcp.h
+++ b/include/drm/drm_hdcp.h
@@ -101,11 +101,11 @@
/* Following Macros take a byte at a time for bit(s) masking */
/*
- * TODO: This has to be changed for DP MST, as multiple stream on
- * same port is possible.
- * For HDCP2.2 on HDMI and DP SST this value is always 1.
+ * TODO: HDCP_2_2_MAX_CONTENT_STREAMS_CNT is based upon actual
+ * H/W MST streams capacity.
+ * This required to be moved out to platform specific header.
*/
-#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 1
+#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 4
#define HDCP_2_2_TXCAP_MASK_LEN 2
#define HDCP_2_2_RXCAPS_LEN 3
#define HDCP_2_2_RX_REPEATER(x) ((x) & BIT(0))
--
2.26.2
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] [RFC] drm/hdcp: Max MST content streams
@ 2020-10-19 7:12 ` Anshuman Gupta
0 siblings, 0 replies; 10+ messages in thread
From: Anshuman Gupta @ 2020-10-19 7:12 UTC (permalink / raw)
To: dri-devel, intel-gfx; +Cc: Sean Paul
Let's define Maximum MST content streams up to four
generically which can be supported by modern display
controllers.
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
include/drm/drm_hdcp.h | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
index fe58dbb46962..ac22c246542a 100644
--- a/include/drm/drm_hdcp.h
+++ b/include/drm/drm_hdcp.h
@@ -101,11 +101,11 @@
/* Following Macros take a byte at a time for bit(s) masking */
/*
- * TODO: This has to be changed for DP MST, as multiple stream on
- * same port is possible.
- * For HDCP2.2 on HDMI and DP SST this value is always 1.
+ * TODO: HDCP_2_2_MAX_CONTENT_STREAMS_CNT is based upon actual
+ * H/W MST streams capacity.
+ * This required to be moved out to platform specific header.
*/
-#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 1
+#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 4
#define HDCP_2_2_TXCAP_MASK_LEN 2
#define HDCP_2_2_RXCAPS_LEN 3
#define HDCP_2_2_RX_REPEATER(x) ((x) & BIT(0))
--
2.26.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/hdcp: Max MST content streams
2020-10-19 7:12 ` [Intel-gfx] " Anshuman Gupta
(?)
@ 2020-10-19 8:14 ` Patchwork
-1 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2020-10-19 8:14 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 4963 bytes --]
== Series Details ==
Series: drm/hdcp: Max MST content streams
URL : https://patchwork.freedesktop.org/series/82806/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9161 -> Patchwork_18724
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/index.html
Known issues
------------
Here are the changes found in Patchwork_18724 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_close_race@basic-threads:
- fi-byt-j1900: [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/fi-byt-j1900/igt@gem_close_race@basic-threads.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/fi-byt-j1900/igt@gem_close_race@basic-threads.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
#### Possible fixes ####
* igt@core_hotunplug@unbind-rebind:
- {fi-tgl-dsi}: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/fi-tgl-dsi/igt@core_hotunplug@unbind-rebind.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/fi-tgl-dsi/igt@core_hotunplug@unbind-rebind.html
* igt@gem_exec_suspend@basic-s0:
- fi-tgl-u2: [FAIL][9] ([i915#1888]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/fi-tgl-u2/igt@gem_exec_suspend@basic-s0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/fi-tgl-u2/igt@gem_exec_suspend@basic-s0.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- {fi-kbl-7560u}: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/fi-kbl-7560u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/fi-kbl-7560u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
- fi-kbl-r: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/fi-kbl-r/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/fi-kbl-r/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@vgem_basic@unload:
- fi-skl-guc: [DMESG-WARN][15] ([i915#2203]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/fi-skl-guc/igt@vgem_basic@unload.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/fi-skl-guc/igt@vgem_basic@unload.html
#### Warnings ####
* igt@core_hotunplug@unbind-rebind:
- fi-icl-u2: [DMESG-WARN][17] ([i915#289]) -> [DMESG-WARN][18] ([i915#1982] / [i915#289])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/fi-icl-u2/igt@core_hotunplug@unbind-rebind.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/fi-icl-u2/igt@core_hotunplug@unbind-rebind.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
[i915#289]: https://gitlab.freedesktop.org/drm/intel/issues/289
Participating hosts (45 -> 39)
------------------------------
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_9161 -> Patchwork_18724
CI-20190529: 20190529
CI_DRM_9161: f474d6c53162f26d23510062d99569d3898639b1 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5821: 2bf22b1cff7905f7e214c0707941929a09450257 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18724: 60fa4b6886a33d0cb99abeaf6385076e283c0fdd @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
60fa4b6886a3 drm/hdcp: Max MST content streams
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/index.html
[-- Attachment #1.2: Type: text/html, Size: 6255 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/hdcp: Max MST content streams
2020-10-19 7:12 ` [Intel-gfx] " Anshuman Gupta
(?)
(?)
@ 2020-10-19 9:45 ` Patchwork
-1 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2020-10-19 9:45 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 18513 bytes --]
== Series Details ==
Series: drm/hdcp: Max MST content streams
URL : https://patchwork.freedesktop.org/series/82806/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9161_full -> Patchwork_18724_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_18724_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18724_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_18724_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_tiled_blits@basic:
- shard-snb: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/shard-snb7/igt@gem_tiled_blits@basic.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/shard-snb5/igt@gem_tiled_blits@basic.html
* igt@kms_flip@2x-flip-vs-expired-vblank@ab-vga1-hdmi-a1:
- shard-hsw: NOTRUN -> [INCOMPLETE][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/shard-hsw4/igt@kms_flip@2x-flip-vs-expired-vblank@ab-vga1-hdmi-a1.html
#### Warnings ####
* igt@runner@aborted:
- shard-iclb: ([FAIL][4], [FAIL][5]) ([i915#2439]) -> [FAIL][6]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/shard-iclb5/igt@runner@aborted.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/shard-iclb3/igt@runner@aborted.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/shard-iclb8/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_18724_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@preservation-s3@rcs0:
- shard-skl: [PASS][7] -> [INCOMPLETE][8] ([i915#198])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/shard-skl9/igt@gem_ctx_isolation@preservation-s3@rcs0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/shard-skl7/igt@gem_ctx_isolation@preservation-s3@rcs0.html
* igt@gem_exec_create@forked:
- shard-glk: [PASS][9] -> [DMESG-WARN][10] ([i915#118] / [i915#95]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/shard-glk8/igt@gem_exec_create@forked.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/shard-glk4/igt@gem_exec_create@forked.html
* igt@gem_mmap_gtt@medium-copy-xy:
- shard-snb: [PASS][11] -> [INCOMPLETE][12] ([i915#82])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/shard-snb5/igt@gem_mmap_gtt@medium-copy-xy.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/shard-snb7/igt@gem_mmap_gtt@medium-copy-xy.html
* igt@gem_mmap_offset@blt-coherency:
- shard-apl: [PASS][13] -> [FAIL][14] ([i915#1635])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/shard-apl3/igt@gem_mmap_offset@blt-coherency.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/shard-apl1/igt@gem_mmap_offset@blt-coherency.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy-gup@wc:
- shard-hsw: [PASS][15] -> [FAIL][16] ([i915#1888]) +3 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/shard-hsw1/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup@wc.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/shard-hsw1/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup@wc.html
* igt@i915_selftest@live@active:
- shard-skl: [PASS][17] -> [DMESG-FAIL][18] ([i915#666])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/shard-skl5/igt@i915_selftest@live@active.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/shard-skl5/igt@i915_selftest@live@active.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-180:
- shard-skl: [PASS][19] -> [FAIL][20] ([i915#1119])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/shard-skl8/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/shard-skl5/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html
* igt@kms_cursor_edge_walk@pipe-b-64x64-top-edge:
- shard-skl: [PASS][21] -> [DMESG-WARN][22] ([i915#1982]) +4 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/shard-skl1/igt@kms_cursor_edge_walk@pipe-b-64x64-top-edge.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/shard-skl9/igt@kms_cursor_edge_walk@pipe-b-64x64-top-edge.html
* igt@kms_flip@blocking-wf_vblank@a-edp1:
- shard-tglb: [PASS][23] -> [DMESG-WARN][24] ([i915#1982]) +3 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/shard-tglb8/igt@kms_flip@blocking-wf_vblank@a-edp1.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/shard-tglb6/igt@kms_flip@blocking-wf_vblank@a-edp1.html
* igt@kms_flip@flip-vs-absolute-wf_vblank@b-hdmi-a1:
- shard-glk: [PASS][25] -> [FAIL][26] ([i915#2122])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/shard-glk5/igt@kms_flip@flip-vs-absolute-wf_vblank@b-hdmi-a1.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/shard-glk8/igt@kms_flip@flip-vs-absolute-wf_vblank@b-hdmi-a1.html
* igt@kms_flip@flip-vs-expired-vblank@b-dp1:
- shard-kbl: [PASS][27] -> [FAIL][28] ([i915#79])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/shard-kbl6/igt@kms_flip@flip-vs-expired-vblank@b-dp1.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/shard-kbl4/igt@kms_flip@flip-vs-expired-vblank@b-dp1.html
* igt@kms_flip@wf_vblank-ts-check@a-dp1:
- shard-kbl: [PASS][29] -> [DMESG-WARN][30] ([i915#1982]) +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/shard-kbl4/igt@kms_flip@wf_vblank-ts-check@a-dp1.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/shard-kbl4/igt@kms_flip@wf_vblank-ts-check@a-dp1.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move:
- shard-snb: [PASS][31] -> [SKIP][32] ([fdo#109271])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/shard-snb4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/shard-snb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][33] -> [FAIL][34] ([fdo#108145] / [i915#265]) +1 similar issue
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_primary_page_flip:
- shard-iclb: [PASS][35] -> [SKIP][36] ([fdo#109441]) +2 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/shard-iclb8/igt@kms_psr@psr2_primary_page_flip.html
#### Possible fixes ####
* igt@gem_mmap_offset@blt-coherency:
- shard-glk: [FAIL][37] ([i915#2328]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/shard-glk5/igt@gem_mmap_offset@blt-coherency.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/shard-glk4/igt@gem_mmap_offset@blt-coherency.html
* igt@gem_partial_pwrite_pread@reads-display:
- shard-hsw: [FAIL][39] ([i915#1888] / [i915#2261]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/shard-hsw6/igt@gem_partial_pwrite_pread@reads-display.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/shard-hsw6/igt@gem_partial_pwrite_pread@reads-display.html
* igt@gem_sync@basic-all:
- shard-glk: [DMESG-WARN][41] ([i915#118] / [i915#95]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/shard-glk8/igt@gem_sync@basic-all.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/shard-glk6/igt@gem_sync@basic-all.html
* igt@gem_sync@basic-store-all:
- shard-iclb: [INCOMPLETE][43] -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/shard-iclb3/igt@gem_sync@basic-store-all.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/shard-iclb3/igt@gem_sync@basic-store-all.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy-gup@wb:
- shard-hsw: [FAIL][45] ([i915#1888]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/shard-hsw1/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup@wb.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/shard-hsw1/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup@wb.html
* igt@gem_userptr_blits@sync-unmap-cycles:
- shard-skl: [TIMEOUT][47] ([i915#2424]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/shard-skl1/igt@gem_userptr_blits@sync-unmap-cycles.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/shard-skl9/igt@gem_userptr_blits@sync-unmap-cycles.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-180:
- shard-apl: [DMESG-WARN][49] ([i915#1635] / [i915#1982]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/shard-apl2/igt@kms_big_fb@y-tiled-64bpp-rotate-180.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/shard-apl2/igt@kms_big_fb@y-tiled-64bpp-rotate-180.html
* igt@kms_cursor_edge_walk@pipe-c-256x256-bottom-edge:
- shard-skl: [DMESG-WARN][51] ([i915#1982]) -> [PASS][52] +4 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/shard-skl5/igt@kms_cursor_edge_walk@pipe-c-256x256-bottom-edge.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/shard-skl1/igt@kms_cursor_edge_walk@pipe-c-256x256-bottom-edge.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
- shard-hsw: [FAIL][53] ([i915#96]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/shard-hsw6/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/shard-hsw8/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-toggle:
- shard-tglb: [FAIL][55] ([i915#2346]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/shard-tglb7/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/shard-tglb6/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-snb: [DMESG-WARN][57] ([i915#42]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/shard-snb7/igt@kms_fbcon_fbt@fbc-suspend.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/shard-snb5/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@flip-vs-suspend@c-hdmi-a1:
- shard-hsw: [INCOMPLETE][59] ([i915#2055]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/shard-hsw2/igt@kms_flip@flip-vs-suspend@c-hdmi-a1.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/shard-hsw4/igt@kms_flip@flip-vs-suspend@c-hdmi-a1.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [FAIL][61] ([i915#1188]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/shard-skl5/igt@kms_hdr@bpc-switch.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/shard-skl1/igt@kms_hdr@bpc-switch.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
- shard-skl: [INCOMPLETE][63] ([i915#198]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/shard-skl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/shard-skl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [SKIP][65] ([fdo#109441]) -> [PASS][66] +2 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/shard-iclb4/igt@kms_psr@psr2_cursor_render.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
* igt@perf@blocking:
- shard-skl: [FAIL][67] ([i915#1542]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/shard-skl9/igt@perf@blocking.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/shard-skl1/igt@perf@blocking.html
* igt@perf_pmu@module-unload:
- shard-tglb: [DMESG-WARN][69] ([i915#1982]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/shard-tglb3/igt@perf_pmu@module-unload.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/shard-tglb2/igt@perf_pmu@module-unload.html
#### Warnings ####
* igt@i915_pm_rpm@modeset-lpsp:
- shard-tglb: [DMESG-WARN][71] ([i915#1982] / [i915#2411]) -> [DMESG-WARN][72] ([i915#2411])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/shard-tglb6/igt@i915_pm_rpm@modeset-lpsp.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/shard-tglb1/igt@i915_pm_rpm@modeset-lpsp.html
* igt@kms_content_protection@atomic:
- shard-apl: [FAIL][73] ([fdo#110321] / [fdo#110336] / [i915#1635]) -> [TIMEOUT][74] ([i915#1319] / [i915#1635])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/shard-apl6/igt@kms_content_protection@atomic.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/shard-apl6/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@srm:
- shard-apl: [TIMEOUT][75] ([i915#1319] / [i915#1635]) -> [FAIL][76] ([fdo#110321] / [i915#1635])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/shard-apl7/igt@kms_content_protection@srm.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/shard-apl2/igt@kms_content_protection@srm.html
* igt@runner@aborted:
- shard-glk: ([FAIL][77], [FAIL][78]) ([i915#1611] / [i915#1814] / [k.org#202321]) -> [FAIL][79] ([k.org#202321])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/shard-glk8/igt@runner@aborted.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/shard-glk6/igt@runner@aborted.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/shard-glk9/igt@runner@aborted.html
- shard-skl: [FAIL][80] ([i915#1611] / [i915#1814] / [i915#2029]) -> [FAIL][81] ([i915#2029] / [i915#2439])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9161/shard-skl2/igt@runner@aborted.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/shard-skl3/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321
[fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336
[i915#1119]: https://gitlab.freedesktop.org/drm/intel/issues/1119
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#1611]: https://gitlab.freedesktop.org/drm/intel/issues/1611
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
[i915#2055]: https://gitlab.freedesktop.org/drm/intel/issues/2055
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2261]: https://gitlab.freedesktop.org/drm/intel/issues/2261
[i915#2328]: https://gitlab.freedesktop.org/drm/intel/issues/2328
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2424]: https://gitlab.freedesktop.org/drm/intel/issues/2424
[i915#2439]: https://gitlab.freedesktop.org/drm/intel/issues/2439
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#42]: https://gitlab.freedesktop.org/drm/intel/issues/42
[i915#666]: https://gitlab.freedesktop.org/drm/intel/issues/666
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
[i915#96]: https://gitlab.freedesktop.org/drm/intel/issues/96
[k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_9161 -> Patchwork_18724
CI-20190529: 20190529
CI_DRM_9161: f474d6c53162f26d23510062d99569d3898639b1 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5821: 2bf22b1cff7905f7e214c0707941929a09450257 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18724: 60fa4b6886a33d0cb99abeaf6385076e283c0fdd @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18724/index.html
[-- Attachment #1.2: Type: text/html, Size: 21696 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [RFC] drm/hdcp: Max MST content streams
2020-10-19 7:12 ` [Intel-gfx] " Anshuman Gupta
@ 2020-10-20 9:42 ` Jani Nikula
-1 siblings, 0 replies; 10+ messages in thread
From: Jani Nikula @ 2020-10-20 9:42 UTC (permalink / raw)
To: Anshuman Gupta, dri-devel, intel-gfx; +Cc: Sean Paul, Thomas Zimmermann
On Mon, 19 Oct 2020, Anshuman Gupta <anshuman.gupta@intel.com> wrote:
> Let's define Maximum MST content streams up to four
> generically which can be supported by modern display
> controllers.
>
> Cc: Sean Paul <seanpaul@chromium.org>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Hey drm-misc maintainers,
I'd like to get an ack to merge this via drm-intel as part of [1].
Thanks,
Jani.
[1] http://lore.kernel.org/r/20201014045252.13608-1-anshuman.gupta@intel.com
> ---
> include/drm/drm_hdcp.h | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
> index fe58dbb46962..ac22c246542a 100644
> --- a/include/drm/drm_hdcp.h
> +++ b/include/drm/drm_hdcp.h
> @@ -101,11 +101,11 @@
>
> /* Following Macros take a byte at a time for bit(s) masking */
> /*
> - * TODO: This has to be changed for DP MST, as multiple stream on
> - * same port is possible.
> - * For HDCP2.2 on HDMI and DP SST this value is always 1.
> + * TODO: HDCP_2_2_MAX_CONTENT_STREAMS_CNT is based upon actual
> + * H/W MST streams capacity.
> + * This required to be moved out to platform specific header.
> */
> -#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 1
> +#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 4
> #define HDCP_2_2_TXCAP_MASK_LEN 2
> #define HDCP_2_2_RXCAPS_LEN 3
> #define HDCP_2_2_RX_REPEATER(x) ((x) & BIT(0))
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [RFC] drm/hdcp: Max MST content streams
@ 2020-10-20 9:42 ` Jani Nikula
0 siblings, 0 replies; 10+ messages in thread
From: Jani Nikula @ 2020-10-20 9:42 UTC (permalink / raw)
To: Anshuman Gupta, dri-devel, intel-gfx
Cc: Sean Paul, Thomas Zimmermann, Maxime Ripard
On Mon, 19 Oct 2020, Anshuman Gupta <anshuman.gupta@intel.com> wrote:
> Let's define Maximum MST content streams up to four
> generically which can be supported by modern display
> controllers.
>
> Cc: Sean Paul <seanpaul@chromium.org>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Hey drm-misc maintainers,
I'd like to get an ack to merge this via drm-intel as part of [1].
Thanks,
Jani.
[1] http://lore.kernel.org/r/20201014045252.13608-1-anshuman.gupta@intel.com
> ---
> include/drm/drm_hdcp.h | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
> index fe58dbb46962..ac22c246542a 100644
> --- a/include/drm/drm_hdcp.h
> +++ b/include/drm/drm_hdcp.h
> @@ -101,11 +101,11 @@
>
> /* Following Macros take a byte at a time for bit(s) masking */
> /*
> - * TODO: This has to be changed for DP MST, as multiple stream on
> - * same port is possible.
> - * For HDCP2.2 on HDMI and DP SST this value is always 1.
> + * TODO: HDCP_2_2_MAX_CONTENT_STREAMS_CNT is based upon actual
> + * H/W MST streams capacity.
> + * This required to be moved out to platform specific header.
> */
> -#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 1
> +#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 4
> #define HDCP_2_2_TXCAP_MASK_LEN 2
> #define HDCP_2_2_RXCAPS_LEN 3
> #define HDCP_2_2_RX_REPEATER(x) ((x) & BIT(0))
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [RFC] drm/hdcp: Max MST content streams
2020-10-20 9:42 ` Jani Nikula
@ 2020-10-20 9:47 ` Maarten Lankhorst
-1 siblings, 0 replies; 10+ messages in thread
From: Maarten Lankhorst @ 2020-10-20 9:47 UTC (permalink / raw)
To: Jani Nikula, Anshuman Gupta, dri-devel, intel-gfx
Cc: Sean Paul, Thomas Zimmermann
Op 20-10-2020 om 11:42 schreef Jani Nikula:
> On Mon, 19 Oct 2020, Anshuman Gupta <anshuman.gupta@intel.com> wrote:
>> Let's define Maximum MST content streams up to four
>> generically which can be supported by modern display
>> controllers.
>>
>> Cc: Sean Paul <seanpaul@chromium.org>
>> Cc: Ramalingam C <ramalingam.c@intel.com>
>> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> Hey drm-misc maintainers,
>
> I'd like to get an ack to merge this via drm-intel as part of [1].
>
> Thanks,
> Jani.
>
>
>
> [1] http://lore.kernel.org/r/20201014045252.13608-1-anshuman.gupta@intel.com
>
>
>
>> ---
>> include/drm/drm_hdcp.h | 8 ++++----
>> 1 file changed, 4 insertions(+), 4 deletions(-)
>>
>> diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
>> index fe58dbb46962..ac22c246542a 100644
>> --- a/include/drm/drm_hdcp.h
>> +++ b/include/drm/drm_hdcp.h
>> @@ -101,11 +101,11 @@
>>
>> /* Following Macros take a byte at a time for bit(s) masking */
>> /*
>> - * TODO: This has to be changed for DP MST, as multiple stream on
>> - * same port is possible.
>> - * For HDCP2.2 on HDMI and DP SST this value is always 1.
>> + * TODO: HDCP_2_2_MAX_CONTENT_STREAMS_CNT is based upon actual
>> + * H/W MST streams capacity.
>> + * This required to be moved out to platform specific header.
>> */
>> -#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 1
>> +#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 4
>> #define HDCP_2_2_TXCAP_MASK_LEN 2
>> #define HDCP_2_2_RXCAPS_LEN 3
>> #define HDCP_2_2_RX_REPEATER(x) ((x) & BIT(0))
Well since it's such a small change..
Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [RFC] drm/hdcp: Max MST content streams
@ 2020-10-20 9:47 ` Maarten Lankhorst
0 siblings, 0 replies; 10+ messages in thread
From: Maarten Lankhorst @ 2020-10-20 9:47 UTC (permalink / raw)
To: Jani Nikula, Anshuman Gupta, dri-devel, intel-gfx
Cc: Sean Paul, Thomas Zimmermann, Maxime Ripard
Op 20-10-2020 om 11:42 schreef Jani Nikula:
> On Mon, 19 Oct 2020, Anshuman Gupta <anshuman.gupta@intel.com> wrote:
>> Let's define Maximum MST content streams up to four
>> generically which can be supported by modern display
>> controllers.
>>
>> Cc: Sean Paul <seanpaul@chromium.org>
>> Cc: Ramalingam C <ramalingam.c@intel.com>
>> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> Hey drm-misc maintainers,
>
> I'd like to get an ack to merge this via drm-intel as part of [1].
>
> Thanks,
> Jani.
>
>
>
> [1] http://lore.kernel.org/r/20201014045252.13608-1-anshuman.gupta@intel.com
>
>
>
>> ---
>> include/drm/drm_hdcp.h | 8 ++++----
>> 1 file changed, 4 insertions(+), 4 deletions(-)
>>
>> diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
>> index fe58dbb46962..ac22c246542a 100644
>> --- a/include/drm/drm_hdcp.h
>> +++ b/include/drm/drm_hdcp.h
>> @@ -101,11 +101,11 @@
>>
>> /* Following Macros take a byte at a time for bit(s) masking */
>> /*
>> - * TODO: This has to be changed for DP MST, as multiple stream on
>> - * same port is possible.
>> - * For HDCP2.2 on HDMI and DP SST this value is always 1.
>> + * TODO: HDCP_2_2_MAX_CONTENT_STREAMS_CNT is based upon actual
>> + * H/W MST streams capacity.
>> + * This required to be moved out to platform specific header.
>> */
>> -#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 1
>> +#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 4
>> #define HDCP_2_2_TXCAP_MASK_LEN 2
>> #define HDCP_2_2_RXCAPS_LEN 3
>> #define HDCP_2_2_RX_REPEATER(x) ((x) & BIT(0))
Well since it's such a small change..
Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [RFC] drm/hdcp: Max MST content streams
2020-10-20 9:47 ` Maarten Lankhorst
@ 2020-10-20 10:17 ` Jani Nikula
-1 siblings, 0 replies; 10+ messages in thread
From: Jani Nikula @ 2020-10-20 10:17 UTC (permalink / raw)
To: Maarten Lankhorst, Anshuman Gupta, dri-devel, intel-gfx
Cc: Sean Paul, Thomas Zimmermann
On Tue, 20 Oct 2020, Maarten Lankhorst <maarten.lankhorst@linux.intel.com> wrote:
> Op 20-10-2020 om 11:42 schreef Jani Nikula:
>> On Mon, 19 Oct 2020, Anshuman Gupta <anshuman.gupta@intel.com> wrote:
>>> Let's define Maximum MST content streams up to four
>>> generically which can be supported by modern display
>>> controllers.
>>>
>>> Cc: Sean Paul <seanpaul@chromium.org>
>>> Cc: Ramalingam C <ramalingam.c@intel.com>
>>> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
>> Hey drm-misc maintainers,
>>
>> I'd like to get an ack to merge this via drm-intel as part of [1].
>>
>> Thanks,
>> Jani.
>>
>>
>>
>> [1] http://lore.kernel.org/r/20201014045252.13608-1-anshuman.gupta@intel.com
>>
>>
>>
>>> ---
>>> include/drm/drm_hdcp.h | 8 ++++----
>>> 1 file changed, 4 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
>>> index fe58dbb46962..ac22c246542a 100644
>>> --- a/include/drm/drm_hdcp.h
>>> +++ b/include/drm/drm_hdcp.h
>>> @@ -101,11 +101,11 @@
>>>
>>> /* Following Macros take a byte at a time for bit(s) masking */
>>> /*
>>> - * TODO: This has to be changed for DP MST, as multiple stream on
>>> - * same port is possible.
>>> - * For HDCP2.2 on HDMI and DP SST this value is always 1.
>>> + * TODO: HDCP_2_2_MAX_CONTENT_STREAMS_CNT is based upon actual
>>> + * H/W MST streams capacity.
>>> + * This required to be moved out to platform specific header.
>>> */
>>> -#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 1
>>> +#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 4
>>> #define HDCP_2_2_TXCAP_MASK_LEN 2
>>> #define HDCP_2_2_RXCAPS_LEN 3
>>> #define HDCP_2_2_RX_REPEATER(x) ((x) & BIT(0))
>
> Well since it's such a small change..
>
> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Thanks.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [RFC] drm/hdcp: Max MST content streams
@ 2020-10-20 10:17 ` Jani Nikula
0 siblings, 0 replies; 10+ messages in thread
From: Jani Nikula @ 2020-10-20 10:17 UTC (permalink / raw)
To: Maarten Lankhorst, Anshuman Gupta, dri-devel, intel-gfx
Cc: Sean Paul, Thomas Zimmermann, Maxime Ripard
On Tue, 20 Oct 2020, Maarten Lankhorst <maarten.lankhorst@linux.intel.com> wrote:
> Op 20-10-2020 om 11:42 schreef Jani Nikula:
>> On Mon, 19 Oct 2020, Anshuman Gupta <anshuman.gupta@intel.com> wrote:
>>> Let's define Maximum MST content streams up to four
>>> generically which can be supported by modern display
>>> controllers.
>>>
>>> Cc: Sean Paul <seanpaul@chromium.org>
>>> Cc: Ramalingam C <ramalingam.c@intel.com>
>>> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
>> Hey drm-misc maintainers,
>>
>> I'd like to get an ack to merge this via drm-intel as part of [1].
>>
>> Thanks,
>> Jani.
>>
>>
>>
>> [1] http://lore.kernel.org/r/20201014045252.13608-1-anshuman.gupta@intel.com
>>
>>
>>
>>> ---
>>> include/drm/drm_hdcp.h | 8 ++++----
>>> 1 file changed, 4 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
>>> index fe58dbb46962..ac22c246542a 100644
>>> --- a/include/drm/drm_hdcp.h
>>> +++ b/include/drm/drm_hdcp.h
>>> @@ -101,11 +101,11 @@
>>>
>>> /* Following Macros take a byte at a time for bit(s) masking */
>>> /*
>>> - * TODO: This has to be changed for DP MST, as multiple stream on
>>> - * same port is possible.
>>> - * For HDCP2.2 on HDMI and DP SST this value is always 1.
>>> + * TODO: HDCP_2_2_MAX_CONTENT_STREAMS_CNT is based upon actual
>>> + * H/W MST streams capacity.
>>> + * This required to be moved out to platform specific header.
>>> */
>>> -#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 1
>>> +#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 4
>>> #define HDCP_2_2_TXCAP_MASK_LEN 2
>>> #define HDCP_2_2_RXCAPS_LEN 3
>>> #define HDCP_2_2_RX_REPEATER(x) ((x) & BIT(0))
>
> Well since it's such a small change..
>
> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Thanks.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2020-10-20 10:17 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-10-19 7:12 [RFC] drm/hdcp: Max MST content streams Anshuman Gupta
2020-10-19 7:12 ` [Intel-gfx] " Anshuman Gupta
2020-10-19 8:14 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2020-10-19 9:45 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-10-20 9:42 ` [Intel-gfx] [RFC] " Jani Nikula
2020-10-20 9:42 ` Jani Nikula
2020-10-20 9:47 ` Maarten Lankhorst
2020-10-20 9:47 ` Maarten Lankhorst
2020-10-20 10:17 ` Jani Nikula
2020-10-20 10:17 ` Jani Nikula
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