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* [PATCH 0/7] dwc3-generic: Add Layerscape support
@ 2020-10-21  6:25 Ran Wang
  2020-10-21  6:25 ` [PATCH 1/7] usb: dwc3: Add frame length adjustment quirk Ran Wang
                   ` (7 more replies)
  0 siblings, 8 replies; 12+ messages in thread
From: Ran Wang @ 2020-10-21  6:25 UTC (permalink / raw)
  To: u-boot

Hello,

The purpose of this patch set is to switch from driver xhci-fsl to
dwc3-generic for DWC3 IP on Layerscape platforms. Whith this change, now
user can enable USB device mode by merely updating property 'dr_mode'
accordingly.

I also port some DWC3's errata workaorund from driver
xhci-fsl (by referring to Linux kernel mainline version implemenattion).

Besides that, I fixed a PHY init problem which observed on Lyerscape
platforms (such as LS1088ardb).

Regards,
Ran

Ran Wang (7):
  usb: dwc3: Add frame length adjustment quirk
  usb: dwc3: add disable receiver detection in P3 quirk
  usb: dwc3: Enable undefined length INCR burst type
  usb: dwc3-generic: fix dwc3_setup_phy() return -ENOTSUPP causing init
    failure
  usb: dwc3-generic: Add support for the layerscape
  configs: ls1088a: add usb mass storage (device mode) support
  arm: dts: ls1088a: change dwc3 compatible to match dwc3-generic driver

 arch/arm/dts/fsl-ls1088a.dtsi            |  40 ++++++---
 configs/ls1088aqds_defconfig             |   5 ++
 configs/ls1088aqds_qspi_defconfig        |   5 ++
 configs/ls1088aqds_sdcard_ifc_defconfig  |   5 ++
 configs/ls1088aqds_sdcard_qspi_defconfig |   5 ++
 configs/ls1088aqds_tfa_defconfig         |   5 ++
 configs/ls1088ardb_qspi_defconfig        |   5 ++
 configs/ls1088ardb_sdcard_qspi_defconfig |   5 ++
 configs/ls1088ardb_tfa_defconfig         |   5 ++
 drivers/usb/dwc3/core.c                  | 147 +++++++++++++++++++++++++++++++
 drivers/usb/dwc3/core.h                  |  21 +++++
 drivers/usb/dwc3/dwc3-generic.c          |   3 +-
 12 files changed, 240 insertions(+), 11 deletions(-)

-- 
2.7.4

^ permalink raw reply	[flat|nested] 12+ messages in thread
* [PATCH 1/7] usb: dwc3: Add frame length adjustment quirk
  2020-10-21  6:25 [PATCH 0/7] dwc3-generic: Add Layerscape support Ran Wang
@ 2020-10-21  6:25 ` Ran Wang
  2020-10-21  7:15   ` Marek Vasut
  2020-10-21  6:25 ` [PATCH 2/7] usb: dwc3: add disable receiver detection in P3 quirk Ran Wang
                   ` (6 subsequent siblings)
  7 siblings, 1 reply; 12+ messages in thread
From: Ran Wang @ 2020-10-21  6:25 UTC (permalink / raw)
  To: u-boot

Register Global frame length adjustment is used to do frame length
adjustment for SOF/ITP counter which is running on the ref_clk. Allow
updating it could help on avoiding potential USB 2.0 devices time-out over
a longer run.

Refer to Linux commit db2be4e9e30c (?usb: dwc3: Add frame length adjustment quirk?)

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
---
 drivers/usb/dwc3/core.c | 34 ++++++++++++++++++++++++++++++++++
 drivers/usb/dwc3/core.h |  7 +++++++
 2 files changed, 41 insertions(+)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 2e00353..b3d4751 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -310,6 +310,25 @@ static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
 	kfree(dwc->scratchbuf);
 }
 
+/*
+ * dwc3_frame_length_adjustment - Adjusts frame length if required
+ * @dwc3: Pointer to our controller context structure
+ * @val: Value of frame length
+ */
+static void dwc3_frame_length_adjustment(struct dwc3 *dwc, u32 val)
+{
+	u32 reg;
+	u32 dft;
+
+	reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
+	dft = reg & DWC3_GFLADJ_30MHZ_MASK;
+	if (dft != val) {
+		reg &= ~DWC3_GFLADJ_30MHZ_MASK;
+		reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | val;
+		dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
+	}
+}
+
 static void dwc3_core_num_eps(struct dwc3 *dwc)
 {
 	struct dwc3_hwparams	*parms = &dwc->hwparams;
@@ -569,6 +588,9 @@ static int dwc3_core_init(struct dwc3 *dwc)
 	if (ret)
 		goto err1;
 
+	if (dwc->fladj_quirk && dwc->revision >= DWC3_REVISION_250A)
+		dwc3_frame_length_adjustment(dwc, dwc->fladj);
+
 	return 0;
 
 err1:
@@ -958,6 +980,18 @@ void dwc3_of_parse(struct dwc3 *dwc)
 
 	dwc->hird_threshold = hird_threshold
 		| (dwc->is_utmi_l1_suspend << 4);
+
+	dwc->fladj_quirk = false;
+	if (!dev_read_u32(dev,
+			  "snps,quirk-frame-length-adjustment",
+			  &dwc->fladj)) {
+		if (dwc->fladj <=  DWC3_GFLADJ_30MHZ_MASK)
+			dwc->fladj_quirk = true;
+		else
+			dev_err(dev,
+				"snps,quirk-frame-length-adjustment invalid: 0x%x\n",
+				dwc->fladj);
+	}
 }
 
 int dwc3_init(struct dwc3 *dwc)
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 44533fd..4650216 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -115,6 +115,7 @@
 #define DWC3_GEVNTCOUNT(n)	(0xc40c + (n * 0x10))
 
 #define DWC3_GHWPARAMS8		0xc600
+#define DWC3_GFLADJ		0xc630
 
 /* Device Registers */
 #define DWC3_DCFG		0xc700
@@ -291,6 +292,10 @@
 #define DWC3_DCTL_ULSTCHNG_COMPLIANCE	(DWC3_DCTL_ULSTCHNGREQ(10))
 #define DWC3_DCTL_ULSTCHNG_LOOPBACK	(DWC3_DCTL_ULSTCHNGREQ(11))
 
+/* Global Frame Length Adjustment Register */
+#define DWC3_GFLADJ_30MHZ_SDBND_SEL	BIT(7)
+#define DWC3_GFLADJ_30MHZ_MASK		0x3f
+
 /* Device Event Enable Register */
 #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN	(1 << 12)
 #define DWC3_DEVTEN_EVNTOVERFLOWEN	(1 << 11)
@@ -764,6 +769,7 @@ struct dwc3 {
 	u32			num_event_buffers;
 	u32			u1u2;
 	u32			maximum_speed;
+	u32			fladj;
 	u32			revision;
 
 #define DWC3_REVISION_173A	0x5533173a
@@ -845,6 +851,7 @@ struct dwc3 {
 
 	unsigned		tx_de_emphasis_quirk:1;
 	unsigned		tx_de_emphasis:2;
+	unsigned		fladj_quirk:1;
 	int			index;
 	struct list_head        list;
 };
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 12+ messages in thread
* [PATCH 2/7] usb: dwc3: add disable receiver detection in P3 quirk
  2020-10-21  6:25 [PATCH 0/7] dwc3-generic: Add Layerscape support Ran Wang
  2020-10-21  6:25 ` [PATCH 1/7] usb: dwc3: Add frame length adjustment quirk Ran Wang
@ 2020-10-21  6:25 ` Ran Wang
  2020-10-21  6:25 ` [PATCH 3/7] usb: dwc3: Enable undefined length INCR burst type Ran Wang
                   ` (5 subsequent siblings)
  7 siblings, 0 replies; 12+ messages in thread
From: Ran Wang @ 2020-10-21  6:25 UTC (permalink / raw)
  To: u-boot

Some NXP Layerscape platforms are required to disable receiver detection in
P3 for correct detection of USB devices. If GUSB3PIPECTL(DISRXDETINP3)
is set, Core will change PHY power state to P2 and then perform
receiver detection. After receiver detection, Core will change
PHY power state to P3. Same quirk would be added in dts file in
future patches.

Refer to Linux commit e58dd357741b (?usb: dwc3: add disable receiver detection in P3 quirk?)

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
---
 drivers/usb/dwc3/core.c | 18 ++++++++++++++++++
 drivers/usb/dwc3/core.h |  1 +
 2 files changed, 19 insertions(+)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index b3d4751..f1b970e 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -591,6 +591,24 @@ static int dwc3_core_init(struct dwc3 *dwc)
 	if (dwc->fladj_quirk && dwc->revision >= DWC3_REVISION_250A)
 		dwc3_frame_length_adjustment(dwc, dwc->fladj);
 
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+	/*
+	 * A-010151: The dwc3 phy TSMC 28-nm HPM 0.9/1.8 V does not
+	 * reliably support Rx Detect in P3 mode(P3 is the default
+	 * setting). Therefore, some USB3.0 devices may not be detected
+	 * reliably in Super Speed mode. So, USB controller to configure
+	 * USB in P2 mode whenever the Receive Detect feature is required.
+	 * whenever the Receive Detect feature is required.
+	 */
+	if (dev_read_bool(dwc->dev, "snps,dis_rxdet_inp3_quirk")) {
+		if (dwc->dr_mode == USB_DR_MODE_HOST) {
+			reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
+			reg |= DWC3_GUSB3PIPECTL_DISRXDETP3;
+			dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
+		}
+	}
+#endif
+
 	return 0;
 
 err1:
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 4650216..e28001a 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -187,6 +187,7 @@
 /* Global USB3 PIPE Control Register */
 #define DWC3_GUSB3PIPECTL_PHYSOFTRST	(1 << 31)
 #define DWC3_GUSB3PIPECTL_U2SSINP3OK	(1 << 29)
+#define DWC3_GUSB3PIPECTL_DISRXDETP3	BIT(28)
 #define DWC3_GUSB3PIPECTL_REQP1P2P3	(1 << 24)
 #define DWC3_GUSB3PIPECTL_DEP1P2P3(n)	((n) << 19)
 #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK	DWC3_GUSB3PIPECTL_DEP1P2P3(7)
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 12+ messages in thread
* [PATCH 3/7] usb: dwc3: Enable undefined length INCR burst type
  2020-10-21  6:25 [PATCH 0/7] dwc3-generic: Add Layerscape support Ran Wang
  2020-10-21  6:25 ` [PATCH 1/7] usb: dwc3: Add frame length adjustment quirk Ran Wang
  2020-10-21  6:25 ` [PATCH 2/7] usb: dwc3: add disable receiver detection in P3 quirk Ran Wang
@ 2020-10-21  6:25 ` Ran Wang
  2020-10-21  6:25 ` [PATCH 4/7] usb: dwc3-generic: fix dwc3_setup_phy() return -ENOTSUPP causing init failure Ran Wang
                   ` (4 subsequent siblings)
  7 siblings, 0 replies; 12+ messages in thread
From: Ran Wang @ 2020-10-21  6:25 UTC (permalink / raw)
  To: u-boot

Enable the undefined length INCR burst type and set INCRx. Different
platforms may has the different burst size type. In order to get best
performance, we need to tune the burst size to one special value,
instead of the default value.

Refer to Linux commit (?usb: dwc3: Enable undefined length INCR burst type?)

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
---
 drivers/usb/dwc3/core.c | 95 +++++++++++++++++++++++++++++++++++++++++++++++++
 drivers/usb/dwc3/core.h | 13 +++++++
 2 files changed, 108 insertions(+)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index f1b970e..52d8242 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -310,6 +310,99 @@ static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
 	kfree(dwc->scratchbuf);
 }
 
+#if CONFIG_IS_ENABLED(DM_USB)
+/* set global incr burst type configuration registers */
+static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
+{
+	struct udevice *dev = dwc->dev;
+	bool incrx_mode;
+	u32 incrx_size;
+	u32 *vals;
+	u32 cfg;
+	int ntype;
+	int ret;
+	int i;
+
+	cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
+
+	/*
+	 * Handle property "snps,incr-burst-type-adjustment".
+	 * Get the number of value from this property:
+	 * result <= 0, means this property is not supported.
+	 * result = 1, means INCRx burst mode supported.
+	 * result > 1, means undefined length burst mode supported.
+	 */
+	ntype = dev_read_size(dev, "snps,incr-burst-type-adjustment") / sizeof(u32);
+	if (ntype <= 0)
+		return;
+
+	vals = memalign(CONFIG_SYS_CACHELINE_SIZE, ntype * sizeof(u32));
+	if (!vals) {
+		dev_err(dev, "Error to get memory\n");
+		return;
+	}
+
+	/* Get INCR burst type, and parse it */
+	ret = dev_read_u32_array(dev, "snps,incr-burst-type-adjustment", vals, ntype);
+	if (ret) {
+		kfree(vals);
+		dev_err(dev, "Error to get property\n");
+		return;
+	}
+
+	incrx_size = *vals;
+
+	if (ntype > 1) {
+		/* INCRX (undefined length) burst mode */
+		incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
+		for (i = 1; i < ntype; i++) {
+			if (vals[i] > incrx_size)
+				incrx_size = vals[i];
+		}
+	} else {
+		/* INCRX burst mode */
+		incrx_mode = INCRX_BURST_MODE;
+	}
+
+	kfree(vals);
+
+	/* Enable Undefined Length INCR Burst and Enable INCRx Burst */
+	cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
+	if (incrx_mode)
+		cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
+	switch (incrx_size) {
+	case 256:
+		cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
+		break;
+	case 128:
+		cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
+		break;
+	case 64:
+		cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
+		break;
+	case 32:
+		cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
+		break;
+	case 16:
+		cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
+		break;
+	case 8:
+		cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
+		break;
+	case 4:
+		cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
+		break;
+	case 1:
+		break;
+	default:
+		dev_err(dev, "Invalid property\n");
+		break;
+	}
+
+	dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
+}
+#endif
+
 /*
  * dwc3_frame_length_adjustment - Adjusts frame length if required
  * @dwc3: Pointer to our controller context structure
@@ -592,6 +685,8 @@ static int dwc3_core_init(struct dwc3 *dwc)
 		dwc3_frame_length_adjustment(dwc, dwc->fladj);
 
 #if CONFIG_IS_ENABLED(OF_CONTROL)
+	dwc3_set_incr_burst_type(dwc);
+
 	/*
 	 * A-010151: The dwc3 phy TSMC 28-nm HPM 0.9/1.8 V does not
 	 * reliably support Rx Detect in P3 mode(P3 is the default
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index e28001a..727e667 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -139,6 +139,17 @@
 
 /* Bit fields */
 
+/* Global SoC Bus Configuration INCRx Register 0 */
+#define DWC3_GSBUSCFG0_INCR256BRSTENA	BIT(7) /* INCR256 burst */
+#define DWC3_GSBUSCFG0_INCR128BRSTENA	BIT(6) /* INCR128 burst */
+#define DWC3_GSBUSCFG0_INCR64BRSTENA	BIT(5) /* INCR64 burst */
+#define DWC3_GSBUSCFG0_INCR32BRSTENA	BIT(4) /* INCR32 burst */
+#define DWC3_GSBUSCFG0_INCR16BRSTENA	BIT(3) /* INCR16 burst */
+#define DWC3_GSBUSCFG0_INCR8BRSTENA	BIT(2) /* INCR8 burst */
+#define DWC3_GSBUSCFG0_INCR4BRSTENA	BIT(1) /* INCR4 burst */
+#define DWC3_GSBUSCFG0_INCRBRSTENA	BIT(0) /* undefined length enable */
+#define DWC3_GSBUSCFG0_INCRBRST_MASK	0xff
+
 /* Global Configuration Register */
 #define DWC3_GCTL_PWRDNSCALE(n)	((n) << 19)
 #define DWC3_GCTL_U2RSTECN	(1 << 16)
@@ -857,6 +868,8 @@ struct dwc3 {
 	struct list_head        list;
 };
 
+#define INCRX_BURST_MODE 0
+#define INCRX_UNDEF_LENGTH_BURST_MODE 1
 /* -------------------------------------------------------------------------- */
 
 /* -------------------------------------------------------------------------- */
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 12+ messages in thread
* [PATCH 4/7] usb: dwc3-generic: fix dwc3_setup_phy() return -ENOTSUPP causing init failure
  2020-10-21  6:25 [PATCH 0/7] dwc3-generic: Add Layerscape support Ran Wang
                   ` (2 preceding siblings ...)
  2020-10-21  6:25 ` [PATCH 3/7] usb: dwc3: Enable undefined length INCR burst type Ran Wang
@ 2020-10-21  6:25 ` Ran Wang
  2020-10-21  6:25 ` [PATCH 5/7] usb: dwc3-generic: Add support for the layerscape Ran Wang
                   ` (3 subsequent siblings)
  7 siblings, 0 replies; 12+ messages in thread
From: Ran Wang @ 2020-10-21  6:25 UTC (permalink / raw)
  To: u-boot

Some SoC such as Layerscape serials which don't require PHY related
programming in dwc3-generic.c. In this case (CONFIG_PHY is not set), the
dwc3_setup_phy() will return -ENOTSUPP, causing the whole init fail.
That should be avoided.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
---
 drivers/usb/dwc3/dwc3-generic.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 36fa16a..d949083 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -74,7 +74,7 @@ static int dwc3_generic_probe(struct udevice *dev,
 	}
 
 	rc = dwc3_setup_phy(dev, &priv->phys);
-	if (rc)
+	if (rc && (rc != -ENOTSUPP))
 		return rc;
 
 	if (device_is_compatible(dev->parent, "rockchip,rk3399-dwc3"))
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 12+ messages in thread
* [PATCH 5/7] usb: dwc3-generic: Add support for the layerscape
  2020-10-21  6:25 [PATCH 0/7] dwc3-generic: Add Layerscape support Ran Wang
                   ` (3 preceding siblings ...)
  2020-10-21  6:25 ` [PATCH 4/7] usb: dwc3-generic: fix dwc3_setup_phy() return -ENOTSUPP causing init failure Ran Wang
@ 2020-10-21  6:25 ` Ran Wang
  2020-10-21  6:25 ` [PATCH 6/7] configs: ls1088a: add usb mass storage (device mode) support Ran Wang
                   ` (2 subsequent siblings)
  7 siblings, 0 replies; 12+ messages in thread
From: Ran Wang @ 2020-10-21  6:25 UTC (permalink / raw)
  To: u-boot

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
---
 drivers/usb/dwc3/dwc3-generic.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index d949083..66c878a 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -449,6 +449,7 @@ static const struct udevice_id dwc3_glue_ids[] = {
 	{ .compatible = "rockchip,rk3328-dwc3" },
 	{ .compatible = "rockchip,rk3399-dwc3" },
 	{ .compatible = "qcom,dwc3" },
+	{ .compatible = "nxp,layerscape-dwc3" },
 	{ }
 };
 
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 12+ messages in thread
* [PATCH 6/7] configs: ls1088a: add usb mass storage (device mode) support
  2020-10-21  6:25 [PATCH 0/7] dwc3-generic: Add Layerscape support Ran Wang
                   ` (4 preceding siblings ...)
  2020-10-21  6:25 ` [PATCH 5/7] usb: dwc3-generic: Add support for the layerscape Ran Wang
@ 2020-10-21  6:25 ` Ran Wang
  2020-10-21  6:25 ` [PATCH 7/7] arm: dts: ls1088a: change dwc3 compatible to match dwc3-generic driver Ran Wang
  2020-10-21  7:19 ` [PATCH 0/7] dwc3-generic: Add Layerscape support Marek Vasut
  7 siblings, 0 replies; 12+ messages in thread
From: Ran Wang @ 2020-10-21  6:25 UTC (permalink / raw)
  To: u-boot

Enable support for one of USB gadget function: ums. Also enable related
dependency items.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
---
 configs/ls1088aqds_defconfig             | 5 +++++
 configs/ls1088aqds_qspi_defconfig        | 5 +++++
 configs/ls1088aqds_sdcard_ifc_defconfig  | 5 +++++
 configs/ls1088aqds_sdcard_qspi_defconfig | 5 +++++
 configs/ls1088aqds_tfa_defconfig         | 5 +++++
 configs/ls1088ardb_qspi_defconfig        | 5 +++++
 configs/ls1088ardb_sdcard_qspi_defconfig | 5 +++++
 configs/ls1088ardb_tfa_defconfig         | 5 +++++
 8 files changed, 40 insertions(+)

diff --git a/configs/ls1088aqds_defconfig b/configs/ls1088aqds_defconfig
index 9642de2..d0668a9 100644
--- a/configs/ls1088aqds_defconfig
+++ b/configs/ls1088aqds_defconfig
@@ -67,8 +67,13 @@ CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_MISC=y
diff --git a/configs/ls1088aqds_qspi_defconfig b/configs/ls1088aqds_qspi_defconfig
index fcb7678..b53a103 100644
--- a/configs/ls1088aqds_qspi_defconfig
+++ b/configs/ls1088aqds_qspi_defconfig
@@ -70,8 +70,13 @@ CONFIG_FSL_DSPI=y
 CONFIG_FSL_QSPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_MISC=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls1088aqds_sdcard_ifc_defconfig b/configs/ls1088aqds_sdcard_ifc_defconfig
index 1f8398c..ed75364 100644
--- a/configs/ls1088aqds_sdcard_ifc_defconfig
+++ b/configs/ls1088aqds_sdcard_ifc_defconfig
@@ -75,8 +75,13 @@ CONFIG_DM_SCSI=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_MISC=y
diff --git a/configs/ls1088aqds_sdcard_qspi_defconfig b/configs/ls1088aqds_sdcard_qspi_defconfig
index 6558c16..8acc0ac 100644
--- a/configs/ls1088aqds_sdcard_qspi_defconfig
+++ b/configs/ls1088aqds_sdcard_qspi_defconfig
@@ -80,7 +80,12 @@ CONFIG_FSL_DSPI=y
 CONFIG_FSL_QSPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_MISC=y
diff --git a/configs/ls1088aqds_tfa_defconfig b/configs/ls1088aqds_tfa_defconfig
index 582cd85..6e6d45a 100644
--- a/configs/ls1088aqds_tfa_defconfig
+++ b/configs/ls1088aqds_tfa_defconfig
@@ -95,8 +95,13 @@ CONFIG_FSL_DSPI=y
 CONFIG_FSL_QSPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_MISC=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls1088ardb_qspi_defconfig b/configs/ls1088ardb_qspi_defconfig
index d7ecff2..884672a 100644
--- a/configs/ls1088ardb_qspi_defconfig
+++ b/configs/ls1088ardb_qspi_defconfig
@@ -72,8 +72,13 @@ CONFIG_FSL_DSPI=y
 CONFIG_FSL_QSPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_MISC=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls1088ardb_sdcard_qspi_defconfig b/configs/ls1088ardb_sdcard_qspi_defconfig
index 6adfadf..9af3d3a 100644
--- a/configs/ls1088ardb_sdcard_qspi_defconfig
+++ b/configs/ls1088ardb_sdcard_qspi_defconfig
@@ -82,7 +82,12 @@ CONFIG_FSL_DSPI=y
 CONFIG_FSL_QSPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_MISC=y
diff --git a/configs/ls1088ardb_tfa_defconfig b/configs/ls1088ardb_tfa_defconfig
index c6c860c..f55d60f 100644
--- a/configs/ls1088ardb_tfa_defconfig
+++ b/configs/ls1088ardb_tfa_defconfig
@@ -83,12 +83,17 @@ CONFIG_FSL_DSPI=y
 CONFIG_FSL_QSPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_ASIX88179=y
 CONFIG_USB_ETHER_RTL8152=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_MISC=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 12+ messages in thread
* [PATCH 7/7] arm: dts: ls1088a: change dwc3 compatible to match dwc3-generic driver
  2020-10-21  6:25 [PATCH 0/7] dwc3-generic: Add Layerscape support Ran Wang
                   ` (5 preceding siblings ...)
  2020-10-21  6:25 ` [PATCH 6/7] configs: ls1088a: add usb mass storage (device mode) support Ran Wang
@ 2020-10-21  6:25 ` Ran Wang
  2020-10-21  7:19 ` [PATCH 0/7] dwc3-generic: Add Layerscape support Marek Vasut
  7 siblings, 0 replies; 12+ messages in thread
From: Ran Wang @ 2020-10-21  6:25 UTC (permalink / raw)
  To: u-boot

Benefit is, besides host mode, now user can choose device mode with
setting of dr_mode = ?peripheral?;

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
---
 arch/arm/dts/fsl-ls1088a.dtsi | 40 ++++++++++++++++++++++++++++++----------
 1 file changed, 30 insertions(+), 10 deletions(-)

diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi
index 6653794..7184d3d 100644
--- a/arch/arm/dts/fsl-ls1088a.dtsi
+++ b/arch/arm/dts/fsl-ls1088a.dtsi
@@ -121,18 +121,38 @@
 		interrupts = <0 21 0x4>; /* Level high type */
 	};
 
-	usb0: usb3 at 3100000 {
-		compatible = "fsl,layerscape-dwc3";
-		reg = <0x0 0x3100000 0x0 0x10000>;
-		interrupts = <0 80 0x4>; /* Level high type */
-		dr_mode = "host";
+	usb0: usb at 3100000 {
+		compatible = "nxp,layerscape-dwc3";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		dwc3 {
+			compatible = "snps,dwc3";
+			reg = <0x0 0x3100000 0x0 0x10000>;
+			interrupts = <0 80 0x4>; /* Level high type */
+			dr_mode = "host";
+			maximum-speed = "super-speed";
+			snps,quirk-frame-length-adjustment = <0x20>;
+			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+			snps,dis_rxdet_inp3_quirk;
+		};
 	};
 
-	usb1: usb3 at 3110000 {
-		compatible = "fsl,layerscape-dwc3";
-		reg = <0x0 0x3110000 0x0 0x10000>;
-		interrupts = <0 81 0x4>; /* Level high type */
-		dr_mode = "host";
+	usb1: usb at 3110000 {
+		compatible = "nxp,layerscape-dwc3";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		dwc3 {
+			compatible = "snps,dwc3";
+			reg = <0x0 0x3110000 0x0 0x10000>;
+			interrupts = <0 81 0x4>; /* Level high type */
+			dr_mode = "host";
+			maximum-speed = "super-speed";
+			snps,quirk-frame-length-adjustment = <0x20>;
+			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+			snps,dis_rxdet_inp3_quirk;
+		};
 	};
 
 	pcie at 3400000 {
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 12+ messages in thread
* [PATCH 1/7] usb: dwc3: Add frame length adjustment quirk
  2020-10-21  6:25 ` [PATCH 1/7] usb: dwc3: Add frame length adjustment quirk Ran Wang
@ 2020-10-21  7:15   ` Marek Vasut
  2020-10-21  7:20     ` Ran Wang
  0 siblings, 1 reply; 12+ messages in thread
From: Marek Vasut @ 2020-10-21  7:15 UTC (permalink / raw)
  To: u-boot

On 10/21/20 8:25 AM, Ran Wang wrote:

[...]

> +static void dwc3_frame_length_adjustment(struct dwc3 *dwc, u32 val)
> +{
> +	u32 reg;
> +	u32 dft;
> +
> +	reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
> +	dft = reg & DWC3_GFLADJ_30MHZ_MASK;
> +	if (dft != val) {

Is there a point to this test or could this entire function be turned
into clrsetbits_le32() ?

> +		reg &= ~DWC3_GFLADJ_30MHZ_MASK;
> +		reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | val;
> +		dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
> +	}
> +}

[...]

^ permalink raw reply	[flat|nested] 12+ messages in thread
* [PATCH 0/7] dwc3-generic: Add Layerscape support
  2020-10-21  6:25 [PATCH 0/7] dwc3-generic: Add Layerscape support Ran Wang
                   ` (6 preceding siblings ...)
  2020-10-21  6:25 ` [PATCH 7/7] arm: dts: ls1088a: change dwc3 compatible to match dwc3-generic driver Ran Wang
@ 2020-10-21  7:19 ` Marek Vasut
  2020-10-21  9:40   ` Ran Wang
  7 siblings, 1 reply; 12+ messages in thread
From: Marek Vasut @ 2020-10-21  7:19 UTC (permalink / raw)
  To: u-boot

On 10/21/20 8:25 AM, Ran Wang wrote:
> Hello,
> 
> The purpose of this patch set is to switch from driver xhci-fsl to
> dwc3-generic for DWC3 IP on Layerscape platforms. Whith this change, now
> user can enable USB device mode by merely updating property 'dr_mode'
> accordingly.
> 
> I also port some DWC3's errata workaorund from driver
> xhci-fsl (by referring to Linux kernel mainline version implemenattion).
> 
> Besides that, I fixed a PHY init problem which observed on Lyerscape
> platforms (such as LS1088ardb).

Looks good to me.

+CC Bin .

^ permalink raw reply	[flat|nested] 12+ messages in thread
* [PATCH 1/7] usb: dwc3: Add frame length adjustment quirk
  2020-10-21  7:15   ` Marek Vasut
@ 2020-10-21  7:20     ` Ran Wang
  0 siblings, 0 replies; 12+ messages in thread
From: Ran Wang @ 2020-10-21  7:20 UTC (permalink / raw)
  To: u-boot

Hi Marek,

On Wednesday, October 21, 2020 3:15 PM, Marek Vasut wrote:
> 
> On 10/21/20 8:25 AM, Ran Wang wrote:
> 
> [...]
> 
> > +static void dwc3_frame_length_adjustment(struct dwc3 *dwc, u32 val) {
> > +	u32 reg;
> > +	u32 dft;
> > +
> > +	reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
> > +	dft = reg & DWC3_GFLADJ_30MHZ_MASK;
> > +	if (dft != val) {
> 
> Is there a point to this test or could this entire function be turned into
> clrsetbits_le32() ?

I think the purpose is avoiding unnecessary write to GFLADJ to reduce potential impact on HW logic, especially counter/timer related.

Regards,
Ran

> > +		reg &= ~DWC3_GFLADJ_30MHZ_MASK;
> > +		reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | val;
> > +		dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
> > +	}
> > +}
> 
> [...]

^ permalink raw reply	[flat|nested] 12+ messages in thread
* [PATCH 0/7] dwc3-generic: Add Layerscape support
  2020-10-21  7:19 ` [PATCH 0/7] dwc3-generic: Add Layerscape support Marek Vasut
@ 2020-10-21  9:40   ` Ran Wang
  0 siblings, 0 replies; 12+ messages in thread
From: Ran Wang @ 2020-10-21  9:40 UTC (permalink / raw)
  To: u-boot

Hi Marek, Bin,

On Wednesday, October 21, 2020 3:19 PM, Marek Vasut wrote:
> 
> On 10/21/20 8:25 AM, Ran Wang wrote:
> > Hello,
> >
> > The purpose of this patch set is to switch from driver xhci-fsl to
> > dwc3-generic for DWC3 IP on Layerscape platforms. Whith this change,
> > now user can enable USB device mode by merely updating property 'dr_mode'
> > accordingly.
> >
> > I also port some DWC3's errata workaorund from driver xhci-fsl (by
> > referring to Linux kernel mainline version implemenattion).
> >
> > Besides that, I fixed a PHY init problem which observed on Lyerscape
> > platforms (such as LS1088ardb).
> 
> Looks good to me.

Please ignore this version, I just found a side effect to Linux kernel USB function, will send out v2 soon.

Regards,
Ran

> +CC Bin .

^ permalink raw reply	[flat|nested] 12+ messages in thread
end of thread, other threads:[~2020-10-21  9:40 UTC | newest]

Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-10-21  6:25 [PATCH 0/7] dwc3-generic: Add Layerscape support Ran Wang
2020-10-21  6:25 ` [PATCH 1/7] usb: dwc3: Add frame length adjustment quirk Ran Wang
2020-10-21  7:15   ` Marek Vasut
2020-10-21  7:20     ` Ran Wang
2020-10-21  6:25 ` [PATCH 2/7] usb: dwc3: add disable receiver detection in P3 quirk Ran Wang
2020-10-21  6:25 ` [PATCH 3/7] usb: dwc3: Enable undefined length INCR burst type Ran Wang
2020-10-21  6:25 ` [PATCH 4/7] usb: dwc3-generic: fix dwc3_setup_phy() return -ENOTSUPP causing init failure Ran Wang
2020-10-21  6:25 ` [PATCH 5/7] usb: dwc3-generic: Add support for the layerscape Ran Wang
2020-10-21  6:25 ` [PATCH 6/7] configs: ls1088a: add usb mass storage (device mode) support Ran Wang
2020-10-21  6:25 ` [PATCH 7/7] arm: dts: ls1088a: change dwc3 compatible to match dwc3-generic driver Ran Wang
2020-10-21  7:19 ` [PATCH 0/7] dwc3-generic: Add Layerscape support Marek Vasut
2020-10-21  9:40   ` Ran Wang

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