From: Catalin Marinas <catalin.marinas@arm.com> To: Marc Zyngier <maz@kernel.org> Cc: Qais Yousef <qais.yousef@arm.com>, Will Deacon <will@kernel.org>, "Peter Zijlstra (Intel)" <peterz@infradead.org>, Morten Rasmussen <morten.rasmussen@arm.com>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Linus Torvalds <torvalds@linux-foundation.org>, James Morse <james.morse@arm.com>, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org Subject: Re: [RFC PATCH v2 4/4] arm64: Export id_aar64fpr0 via sysfs Date: Wed, 21 Oct 2020 13:15:59 +0100 [thread overview] Message-ID: <20201021121559.GB3976@gaia> (raw) In-Reply-To: <63fead90e91e08a1b173792b06995765@kernel.org> On Wed, Oct 21, 2020 at 12:09:58PM +0100, Marc Zyngier wrote: > On 2020-10-21 11:46, Qais Yousef wrote: > > Example output. I was surprised that the 2nd field (bits[7:4]) is > > printed out > > although it's set as FTR_HIDDEN. > > > > # cat /sys/devices/system/cpu/cpu*/regs/identification/id_aa64pfr0 > > 0x0000000000000011 > > 0x0000000000000011 > > 0x0000000000000011 > > 0x0000000000000011 > > 0x0000000000000011 > > 0x0000000000000011 > > > > # echo 1 > /proc/sys/kernel/enable_asym_32bit > > > > # cat /sys/devices/system/cpu/cpu*/regs/identification/id_aa64pfr0 > > 0x0000000000000011 > > 0x0000000000000011 > > 0x0000000000000012 > > 0x0000000000000012 > > 0x0000000000000011 > > 0x0000000000000011 > > This looks like a terrible userspace interface. It exposes unrelated > features, Not sure why the EL1 field ended up in here, that's not relevant to the user. > and doesn't expose the single useful information that the kernel has: > the cpumask describing the CPUs supporting AArch32 at EL0. Why not expose > this synthetic piece of information which requires very little effort from > userspace and doesn't spit out unrelated stuff? I thought the whole idea is to try and avoid the "very little effort" part ;). > Not to mention the discrepancy with what userspace gets while reading > the same register via the MRS emulation. > > Granted, the cpumask doesn't fit the cpu*/regs/identification hierarchy, > but I don't think this fits either. We already expose MIDR and REVIDR via the current sysfs interface. We can expand it to include _all_ the other ID_* regs currently available to user via the MRS emulation and we won't have to debate what a new interface would look like. The MRS emulation and the sysfs info should probably match, though that means we need to expose the ID_AA64PFR0_EL1.EL0 field which we currently don't. I do agree that an AArch32 cpumask is an easier option both from the kernel implementation perspective and from the application usability one, though not as easy as automatic task placement by the scheduler (my first preference, followed by the id_* regs and the aarch32 mask, though not a strong preference for any). -- Catalin
WARNING: multiple messages have this Message-ID (diff)
From: Catalin Marinas <catalin.marinas@arm.com> To: Marc Zyngier <maz@kernel.org> Cc: linux-arch@vger.kernel.org, Will Deacon <will@kernel.org>, "Peter Zijlstra \(Intel\)" <peterz@infradead.org>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Morten Rasmussen <morten.rasmussen@arm.com>, James Morse <james.morse@arm.com>, Linus Torvalds <torvalds@linux-foundation.org>, Qais Yousef <qais.yousef@arm.com>, linux-arm-kernel@lists.infradead.org Subject: Re: [RFC PATCH v2 4/4] arm64: Export id_aar64fpr0 via sysfs Date: Wed, 21 Oct 2020 13:15:59 +0100 [thread overview] Message-ID: <20201021121559.GB3976@gaia> (raw) In-Reply-To: <63fead90e91e08a1b173792b06995765@kernel.org> On Wed, Oct 21, 2020 at 12:09:58PM +0100, Marc Zyngier wrote: > On 2020-10-21 11:46, Qais Yousef wrote: > > Example output. I was surprised that the 2nd field (bits[7:4]) is > > printed out > > although it's set as FTR_HIDDEN. > > > > # cat /sys/devices/system/cpu/cpu*/regs/identification/id_aa64pfr0 > > 0x0000000000000011 > > 0x0000000000000011 > > 0x0000000000000011 > > 0x0000000000000011 > > 0x0000000000000011 > > 0x0000000000000011 > > > > # echo 1 > /proc/sys/kernel/enable_asym_32bit > > > > # cat /sys/devices/system/cpu/cpu*/regs/identification/id_aa64pfr0 > > 0x0000000000000011 > > 0x0000000000000011 > > 0x0000000000000012 > > 0x0000000000000012 > > 0x0000000000000011 > > 0x0000000000000011 > > This looks like a terrible userspace interface. It exposes unrelated > features, Not sure why the EL1 field ended up in here, that's not relevant to the user. > and doesn't expose the single useful information that the kernel has: > the cpumask describing the CPUs supporting AArch32 at EL0. Why not expose > this synthetic piece of information which requires very little effort from > userspace and doesn't spit out unrelated stuff? I thought the whole idea is to try and avoid the "very little effort" part ;). > Not to mention the discrepancy with what userspace gets while reading > the same register via the MRS emulation. > > Granted, the cpumask doesn't fit the cpu*/regs/identification hierarchy, > but I don't think this fits either. We already expose MIDR and REVIDR via the current sysfs interface. We can expand it to include _all_ the other ID_* regs currently available to user via the MRS emulation and we won't have to debate what a new interface would look like. The MRS emulation and the sysfs info should probably match, though that means we need to expose the ID_AA64PFR0_EL1.EL0 field which we currently don't. I do agree that an AArch32 cpumask is an easier option both from the kernel implementation perspective and from the application usability one, though not as easy as automatic task placement by the scheduler (my first preference, followed by the id_* regs and the aarch32 mask, though not a strong preference for any). -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-10-21 12:16 UTC|newest] Thread overview: 114+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-10-21 10:46 [RFC PATCH v2 0/4] Add support for Asymmetric AArch32 systems Qais Yousef 2020-10-21 10:46 ` Qais Yousef 2020-10-21 10:46 ` [RFC PATCH v2 1/4] arm64: kvm: Handle " Qais Yousef 2020-10-21 10:46 ` Qais Yousef 2020-10-21 12:02 ` Marc Zyngier 2020-10-21 12:02 ` Marc Zyngier 2020-10-21 13:35 ` Qais Yousef 2020-10-21 13:35 ` Qais Yousef 2020-10-21 13:51 ` Marc Zyngier 2020-10-21 13:51 ` Marc Zyngier 2020-10-21 14:38 ` Qais Yousef 2020-10-21 14:38 ` Qais Yousef 2020-11-02 17:58 ` Qais Yousef 2020-11-02 17:58 ` Qais Yousef 2020-10-21 10:46 ` [RFC PATCH v2 2/4] arm64: Add support for asymmetric AArch32 EL0 configurations Qais Yousef 2020-10-21 10:46 ` Qais Yousef 2020-10-21 15:39 ` Will Deacon 2020-10-21 15:39 ` Will Deacon 2020-10-21 16:21 ` Qais Yousef 2020-10-21 16:21 ` Qais Yousef 2020-10-21 16:52 ` Catalin Marinas 2020-10-21 16:52 ` Catalin Marinas 2020-10-21 17:39 ` Will Deacon 2020-10-21 17:39 ` Will Deacon 2020-10-22 9:53 ` Catalin Marinas 2020-10-22 9:53 ` Catalin Marinas 2020-10-21 10:46 ` [RFC PATCH v2 3/4] arm64: export emulate_sys_reg() Qais Yousef 2020-10-21 10:46 ` Qais Yousef 2020-10-21 10:46 ` [RFC PATCH v2 4/4] arm64: Export id_aar64fpr0 via sysfs Qais Yousef 2020-10-21 10:46 ` Qais Yousef 2020-10-21 11:09 ` Marc Zyngier 2020-10-21 11:09 ` Marc Zyngier 2020-10-21 11:25 ` Greg Kroah-Hartman 2020-10-21 11:25 ` Greg Kroah-Hartman 2020-10-21 11:46 ` Marc Zyngier 2020-10-21 11:46 ` Marc Zyngier 2020-10-21 12:11 ` Greg Kroah-Hartman 2020-10-21 12:11 ` Greg Kroah-Hartman 2020-10-21 13:18 ` Qais Yousef 2020-10-21 13:18 ` Qais Yousef 2020-10-21 12:15 ` Catalin Marinas [this message] 2020-10-21 12:15 ` Catalin Marinas 2020-10-21 13:20 ` Qais Yousef 2020-10-21 13:20 ` Qais Yousef 2020-10-21 13:33 ` Morten Rasmussen 2020-10-21 13:33 ` Morten Rasmussen 2020-10-21 14:09 ` Catalin Marinas 2020-10-21 14:09 ` Catalin Marinas 2020-10-21 14:41 ` Morten Rasmussen 2020-10-21 14:41 ` Morten Rasmussen 2020-10-21 14:45 ` Will Deacon 2020-10-21 14:45 ` Will Deacon 2020-10-21 15:10 ` Catalin Marinas 2020-10-21 15:10 ` Catalin Marinas 2020-10-21 15:37 ` Will Deacon 2020-10-21 15:37 ` Will Deacon 2020-10-21 16:18 ` Catalin Marinas 2020-10-21 16:18 ` Catalin Marinas 2020-10-21 17:19 ` Will Deacon 2020-10-21 17:19 ` Will Deacon 2020-10-22 9:55 ` Morten Rasmussen 2020-10-22 9:55 ` Morten Rasmussen 2020-10-21 14:31 ` Qais Yousef 2020-10-21 14:31 ` Qais Yousef 2020-10-22 10:16 ` Morten Rasmussen 2020-10-22 10:16 ` Morten Rasmussen 2020-10-22 10:48 ` Qais Yousef 2020-10-22 10:48 ` Qais Yousef 2020-10-21 14:41 ` Will Deacon 2020-10-21 14:41 ` Will Deacon 2020-10-21 15:03 ` Qais Yousef 2020-10-21 15:03 ` Qais Yousef 2020-10-21 15:23 ` Will Deacon 2020-10-21 15:23 ` Will Deacon 2020-10-21 16:07 ` Qais Yousef 2020-10-21 16:07 ` Qais Yousef 2020-10-21 17:23 ` Will Deacon 2020-10-21 17:23 ` Will Deacon 2020-10-21 19:57 ` Qais Yousef 2020-10-21 19:57 ` Qais Yousef 2020-10-21 20:26 ` Will Deacon 2020-10-21 20:26 ` Will Deacon 2020-10-22 8:16 ` Catalin Marinas 2020-10-22 8:16 ` Catalin Marinas 2020-10-22 9:58 ` Qais Yousef 2020-10-22 9:58 ` Qais Yousef 2020-10-22 13:47 ` Qais Yousef 2020-10-22 13:47 ` Qais Yousef 2020-10-22 13:55 ` Greg Kroah-Hartman 2020-10-22 13:55 ` Greg Kroah-Hartman 2020-10-22 14:31 ` Catalin Marinas 2020-10-22 14:31 ` Catalin Marinas 2020-10-22 14:34 ` Qais Yousef 2020-10-22 14:34 ` Qais Yousef 2020-10-26 19:02 ` Qais Yousef 2020-10-26 19:02 ` Qais Yousef 2020-10-26 19:08 ` Greg Kroah-Hartman 2020-10-26 19:08 ` Greg Kroah-Hartman 2020-10-26 19:18 ` Qais Yousef 2020-10-26 19:18 ` Qais Yousef 2020-10-21 11:28 ` Greg Kroah-Hartman 2020-10-21 11:28 ` Greg Kroah-Hartman 2020-10-21 13:22 ` Qais Yousef 2020-10-21 13:22 ` Qais Yousef 2020-10-21 11:26 ` [RFC PATCH v2 0/4] Add support for Asymmetric AArch32 systems Greg Kroah-Hartman 2020-10-21 11:26 ` Greg Kroah-Hartman 2020-10-21 13:15 ` Qais Yousef 2020-10-21 13:15 ` Qais Yousef 2020-10-21 13:31 ` Greg Kroah-Hartman 2020-10-21 13:31 ` Greg Kroah-Hartman 2020-10-21 13:55 ` Qais Yousef 2020-10-21 13:55 ` Qais Yousef 2020-10-21 14:35 ` Catalin Marinas 2020-10-21 14:35 ` Catalin Marinas
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20201021121559.GB3976@gaia \ --to=catalin.marinas@arm.com \ --cc=gregkh@linuxfoundation.org \ --cc=james.morse@arm.com \ --cc=linux-arch@vger.kernel.org \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=maz@kernel.org \ --cc=morten.rasmussen@arm.com \ --cc=peterz@infradead.org \ --cc=qais.yousef@arm.com \ --cc=torvalds@linux-foundation.org \ --cc=will@kernel.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.