[Intel-gfx] [PATCH 00/18] Introduce Alderlake-S

[Intel-gfx] [PATCH 00/18] Introduce Alderlake-S

[Aditya Swarup]

Alder Lake-S (ADL-S) is another gen12 platform and a TGL variant, with 
5 combo phy outputs with the following port/phy assignment:

        DDI-A   (port A) <-> PHY-A
        DDI-TC1 (port D) <-> PHY-B
        DDI-TC2 (port E) <-> PHY-C
        DDI-TC3 (port F) <-> PHY-D
        DDI-TC4 (port G) <-> PHY-E

It has 1 eDP, 2 HDMI and 2 DP++ display outputs.

Aditya Swarup (5):
  drm/i915/adl_s: Configure DPLL for ADL-S
  drm/i915/adl_s: Configure Port clock registers for ADL-S
  drm/i915/adl_s: Setup display outputs and HTI support for ADL-S
  drm/i915/adl_s: Add adl-s ddc pin mapping
  drm/i915/adl_s: Add vbt port and aux channel settings for adls

Anusha Srivatsa (5):
  drm/i915/adl_s: Add PCH support
  drm/i915/adl_s: Add Interrupt Support
  drm/i915/adl_s: Add PHYs for Alderlake S
  drm/i915/adl_s: Add display, gt, ctx and ADL-S whitelist WA
  drm/i915/adl_s: Load DMC

Caz Yokoyama (2):
  drm/i915/adl_s: Add ADL-S platform info and PCI ids
  x86/gpu: add ADL_S stolen memory support

José Roberto de Souza (1):
  drm/i915/display: Add HAS_D12_PLANE_MINIMIZATION

Matt Roper (3):
  drm/i915/adl_s: Update combo PHY master/slave relationships
  drm/i915/adl_s: Update PHY_MISC programming
  drm/i915/adl_s: Re-use TGL GuC/HuC firmware

Tejas Upadhyay (1):
  drm/i915/adl_s: Update memory bandwidth parameters

Yokoyama, Caz (1):
  drm/i915/adl_s: MCHBAR memory info registers are moved

 arch/x86/kernel/early-quirks.c                |  1 +
 drivers/gpu/drm/i915/display/intel_bios.c     | 55 +++++++++++++---
 drivers/gpu/drm/i915/display/intel_bw.c       |  8 +++
 .../gpu/drm/i915/display/intel_combo_phy.c    | 23 +++++--
 drivers/gpu/drm/i915/display/intel_csr.c      | 10 ++-
 drivers/gpu/drm/i915/display/intel_ddi.c      | 64 +++++++++++++------
 drivers/gpu/drm/i915/display/intel_display.c  | 34 ++++++++--
 .../drm/i915/display/intel_display_power.c    |  7 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 38 +++++++++--
 drivers/gpu/drm/i915/display/intel_hdmi.c     | 20 +++++-
 drivers/gpu/drm/i915/display/intel_sprite.c   |  4 +-
 drivers/gpu/drm/i915/display/intel_vbt_defs.h |  4 ++
 drivers/gpu/drm/i915/gt/intel_workarounds.c   | 29 ++++++++-
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c      |  4 +-
 drivers/gpu/drm/i915/i915_drv.h               | 12 ++++
 drivers/gpu/drm/i915/i915_irq.c               | 24 +++++--
 drivers/gpu/drm/i915/i915_pci.c               | 13 ++++
 drivers/gpu/drm/i915/i915_reg.h               | 59 +++++++++++++++--
 drivers/gpu/drm/i915/intel_device_info.c      |  9 ++-
 drivers/gpu/drm/i915/intel_device_info.h      |  1 +
 drivers/gpu/drm/i915/intel_dram.c             | 18 +++++-
 drivers/gpu/drm/i915/intel_pch.c              |  8 ++-
 drivers/gpu/drm/i915/intel_pch.h              |  3 +
 include/drm/i915_pciids.h                     | 13 ++++
 24 files changed, 392 insertions(+), 69 deletions(-)

-- 
2.27.0

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[Intel-gfx] [PATCH 01/18] drm/i915/adl_s: Add ADL-S platform info and PCI ids

[Aditya Swarup]

From: Caz Yokoyama <caz.yokoyama@intel.com>

- Add the initial platform information for Alderlake-S.
- Specify ppgtt_size value
- Add dma_mask_size
- Add ADLS REVIDs
- HW tracking(Selective Update Tracking Enable) has been removed from
  ADLS. Disable PSR2 till we enable software/manual tracking.

Bspec: 53597
Bspec: 53648
Bspec: 53655
Bspec: 48028
Bspec: 53650
BSpec: 50422

Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Caz Yokoyama <caz.yokoyama@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h          |  9 +++++++++
 drivers/gpu/drm/i915/i915_pci.c          | 12 ++++++++++++
 drivers/gpu/drm/i915/intel_device_info.c |  1 +
 drivers/gpu/drm/i915/intel_device_info.h |  1 +
 include/drm/i915_pciids.h                | 13 +++++++++++++
 5 files changed, 36 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bcd8650603d8..4fea3d5e01f4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1424,6 +1424,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_TIGERLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
 #define IS_ROCKETLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
 #define IS_DG1(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG1)
+#define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
 				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
 #define IS_BDW_ULT(dev_priv) \
@@ -1613,6 +1614,14 @@ tgl_revids_get(struct drm_i915_private *dev_priv)
 #define IS_DG1_REVID(p, since, until) \
 	(IS_DG1(p) && IS_REVID(p, since, until))
 
+#define ADLS_REVID_A0		0x0
+#define ADLS_REVID_B0		0x4
+#define ADLS_REVID_C0		0x8
+#define ADLS_REVID_D0		0xC
+
+#define IS_ADLS_REVID(p, since, until) \
+       (IS_ALDERLAKE_S(p) && IS_REVID(p, since, until))
+
 #define IS_LP(dev_priv)	(INTEL_INFO(dev_priv)->is_lp)
 #define IS_GEN9_LP(dev_priv)	(IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
 #define IS_GEN9_BC(dev_priv)	(IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 27964ac0638a..d39a7389b305 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -924,6 +924,17 @@ static const struct intel_device_info dg1_info __maybe_unused = {
 	.ppgtt_size = 47,
 };
 
+static const struct intel_device_info adl_s_info = {
+	GEN12_FEATURES,
+	PLATFORM(INTEL_ALDERLAKE_S),
+	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
+	.require_force_probe = 1,
+	.display.has_psr_hw_tracking = 0,
+	.platform_engine_mask =
+		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
+	.dma_mask_size = 46,
+};
+
 #undef GEN
 #undef PLATFORM
 
@@ -1000,6 +1011,7 @@ static const struct pci_device_id pciidlist[] = {
 	INTEL_JSL_IDS(&jsl_info),
 	INTEL_TGL_12_IDS(&tgl_info),
 	INTEL_RKL_IDS(&rkl_info),
+	INTEL_ADLS_IDS(&adl_s_info),
 	{0, 0, 0}
 };
 MODULE_DEVICE_TABLE(pci, pciidlist);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index e67cec8fa2aa..7310e019c611 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -66,6 +66,7 @@ static const char * const platform_names[] = {
 	PLATFORM_NAME(TIGERLAKE),
 	PLATFORM_NAME(ROCKETLAKE),
 	PLATFORM_NAME(DG1),
+	PLATFORM_NAME(ALDERLAKE_S),
 };
 #undef PLATFORM_NAME
 
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index d92fa041c700..360f3f1835f5 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -84,6 +84,7 @@ enum intel_platform {
 	INTEL_TIGERLAKE,
 	INTEL_ROCKETLAKE,
 	INTEL_DG1,
+	INTEL_ALDERLAKE_S,
 	INTEL_MAX_PLATFORMS
 };
 
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 3b5ed1e4f3ec..9a0d58524cb1 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -635,4 +635,17 @@
 	INTEL_VGA_DEVICE(0x4907, info), \
 	INTEL_VGA_DEVICE(0x4908, info)
 
+/* ADL-S */
+#define INTEL_ADLS_IDS(info) \
+	INTEL_VGA_DEVICE(0x4680, info), \
+	INTEL_VGA_DEVICE(0x4681, info), \
+	INTEL_VGA_DEVICE(0x4682, info), \
+	INTEL_VGA_DEVICE(0x4683, info), \
+	INTEL_VGA_DEVICE(0x4690, info), \
+	INTEL_VGA_DEVICE(0x4691, info), \
+	INTEL_VGA_DEVICE(0x4692, info), \
+	INTEL_VGA_DEVICE(0x4693, info), \
+	INTEL_VGA_DEVICE(0x4698, info), \
+	INTEL_VGA_DEVICE(0x4699, info)
+
 #endif /* _I915_PCIIDS_H */
-- 
2.27.0

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[Intel-gfx] [PATCH 02/18] x86/gpu: add ADL_S stolen memory support

[Aditya Swarup]

From: Caz Yokoyama <caz.yokoyama@intel.com>

ADL_S re-uses the same stolen memory registers as TGL and ICL.

Bspec: 52055
Bspec: 49589
Bspec: 49636

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Caz Yokoyama <caz.yokoyama@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
 arch/x86/kernel/early-quirks.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index a4b5af03dcc1..6edd1e2ee8af 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -551,6 +551,7 @@ static const struct pci_device_id intel_early_ids[] __initconst = {
 	INTEL_EHL_IDS(&gen11_early_ops),
 	INTEL_TGL_12_IDS(&gen11_early_ops),
 	INTEL_RKL_IDS(&gen11_early_ops),
+	INTEL_ADLS_IDS(&gen11_early_ops),
 };
 
 struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0, 0);
-- 
2.27.0

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[Intel-gfx] [PATCH 03/18] drm/i915/adl_s: Add PCH support

[Aditya Swarup]

From: Anusha Srivatsa <anusha.srivatsa@intel.com>

Add support for Alderpoint(ADP) PCH used with Alderlake-S.

Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Caz Yokoyama <caz.yokoyama@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
 drivers/gpu/drm/i915/intel_pch.c | 8 +++++++-
 drivers/gpu/drm/i915/intel_pch.h | 3 +++
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c
index f31c0dabd0cc..7fac9686a0c0 100644
--- a/drivers/gpu/drm/i915/intel_pch.c
+++ b/drivers/gpu/drm/i915/intel_pch.c
@@ -128,6 +128,10 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
 		drm_dbg_kms(&dev_priv->drm, "Found Jasper Lake PCH\n");
 		drm_WARN_ON(&dev_priv->drm, !IS_JSL_EHL(dev_priv));
 		return PCH_JSP;
+	case INTEL_PCH_ADP_DEVICE_ID_TYPE:
+		DRM_DEBUG_KMS("Found Alder Lake PCH\n");
+		WARN_ON(!IS_ALDERLAKE_S(dev_priv));
+		return PCH_ADP;
 	default:
 		return PCH_NONE;
 	}
@@ -155,7 +159,9 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv)
 	 * make an educated guess as to which PCH is really there.
 	 */
 
-	if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv))
+	if (IS_ALDERLAKE_S(dev_priv))
+		id = INTEL_PCH_ADP_DEVICE_ID_TYPE;
+	else if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv))
 		id = INTEL_PCH_TGP_DEVICE_ID_TYPE;
 	else if (IS_JSL_EHL(dev_priv))
 		id = INTEL_PCH_MCC_DEVICE_ID_TYPE;
diff --git a/drivers/gpu/drm/i915/intel_pch.h b/drivers/gpu/drm/i915/intel_pch.h
index 06d2cd50af0b..7318377503b0 100644
--- a/drivers/gpu/drm/i915/intel_pch.h
+++ b/drivers/gpu/drm/i915/intel_pch.h
@@ -26,6 +26,7 @@ enum intel_pch {
 	PCH_JSP,	/* Jasper Lake PCH */
 	PCH_MCC,        /* Mule Creek Canyon PCH */
 	PCH_TGP,	/* Tiger Lake PCH */
+	PCH_ADP,	/* Alder Lake PCH */
 
 	/* Fake PCHs, functionality handled on the same PCI dev */
 	PCH_DG1 = 1024,
@@ -53,12 +54,14 @@ enum intel_pch {
 #define INTEL_PCH_TGP2_DEVICE_ID_TYPE		0x4380
 #define INTEL_PCH_JSP_DEVICE_ID_TYPE		0x4D80
 #define INTEL_PCH_JSP2_DEVICE_ID_TYPE		0x3880
+#define INTEL_PCH_ADP_DEVICE_ID_TYPE		0x7A80
 #define INTEL_PCH_P2X_DEVICE_ID_TYPE		0x7100
 #define INTEL_PCH_P3X_DEVICE_ID_TYPE		0x7000
 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE		0x2900 /* qemu q35 has 2918 */
 
 #define INTEL_PCH_TYPE(dev_priv)		((dev_priv)->pch_type)
 #define INTEL_PCH_ID(dev_priv)			((dev_priv)->pch_id)
+#define HAS_PCH_ADP(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_ADP)
 #define HAS_PCH_DG1(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_DG1)
 #define HAS_PCH_JSP(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_JSP)
 #define HAS_PCH_MCC(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_MCC)
-- 
2.27.0

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[Intel-gfx] [PATCH 04/18] drm/i915/adl_s: Add Interrupt Support

[Aditya Swarup]

From: Anusha Srivatsa <anusha.srivatsa@intel.com>

ADLS follows ICP/TGP like interrupts. Reuse hpd_icp and introduce
ADLS DDI and HPD masks for setting up hpd interrupts.

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 20 ++++++++++++++++----
 drivers/gpu/drm/i915/i915_reg.h |  3 +++
 2 files changed, 19 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b753c77c9a77..9033221995ad 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -179,8 +179,9 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
 	if (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))
 		return;
 
-	if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv) ||
-	    HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv))
+	if (HAS_PCH_ADP(dev_priv) || HAS_PCH_TGP(dev_priv) ||
+	    HAS_PCH_JSP(dev_priv) || HAS_PCH_ICP(dev_priv) ||
+	    HAS_PCH_MCC(dev_priv))
 		hpd->pch_hpd = hpd_icp;
 	else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv))
 		hpd->pch_hpd = hpd_spt;
@@ -1864,7 +1865,10 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
 	u32 ddi_hotplug_trigger, tc_hotplug_trigger;
 	u32 pin_mask = 0, long_mask = 0;
 
-	if (HAS_PCH_TGP(dev_priv)) {
+	if (IS_ALDERLAKE_S(dev_priv)) {
+		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ADLS;
+		tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
+	} else if (HAS_PCH_TGP(dev_priv)) {
 		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
 		tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
 	} else if (HAS_PCH_JSP(dev_priv)) {
@@ -3252,6 +3256,12 @@ static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv)
 			  TGP_DDI_HPD_ENABLE_MASK, 0);
 }
 
+static void adls_hpd_irq_setup(struct drm_i915_private *dev_priv)
+{
+	icp_hpd_irq_setup(dev_priv,
+			  ADLS_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE_MASK);
+}
+
 static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
 {
 	u32 hotplug;
@@ -4162,7 +4172,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
 		if (I915_HAS_HOTPLUG(dev_priv))
 			dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
 	} else {
-		if (HAS_PCH_JSP(dev_priv))
+		if (IS_ALDERLAKE_S(dev_priv))
+			dev_priv->display.hpd_irq_setup = adls_hpd_irq_setup;
+		else if (HAS_PCH_JSP(dev_priv))
 			dev_priv->display.hpd_irq_setup = jsp_hpd_irq_setup;
 		else if (HAS_PCH_MCC(dev_priv))
 			dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 83ddea1cd174..f6b844ca7a9f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8343,6 +8343,7 @@ enum {
 					 SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
 					 SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
 					 SDE_TC_HOTPLUG_ICP(PORT_TC1))
+#define SDE_DDI_MASK_ADLS		 SDE_DDI_HOTPLUG_ICP(PORT_A)
 
 #define SDEISR  _MMIO(0xc4000)
 #define SDEIMR  _MMIO(0xc4004)
@@ -8438,6 +8439,8 @@ enum {
 					 ICP_TC_HPD_ENABLE(PORT_TC5) | \
 					 ICP_TC_HPD_ENABLE_MASK)
 
+#define ADLS_DDI_HPD_ENABLE_MASK	 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A)
+
 #define _PCH_DPLL_A              0xc6014
 #define _PCH_DPLL_B              0xc6018
 #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
-- 
2.27.0

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[Intel-gfx] [PATCH 05/18] drm/i915/adl_s: Add PHYs for Alderlake S

[Aditya Swarup]

From: Anusha Srivatsa <anusha.srivatsa@intel.com>

Alderlake-S has 5 combo phys, add reg definitions for
combo phys and update the port to phy helper for ADL-S.

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 8 ++++++--
 drivers/gpu/drm/i915/i915_reg.h              | 5 ++++-
 2 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 60bacdbe7f92..70ca5d2e5b0a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7333,6 +7333,8 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
 {
 	if (phy == PHY_NONE)
 		return false;
+	else if (IS_ALDERLAKE_S(dev_priv))
+		return phy <= PHY_E;
 	else if (IS_ROCKETLAKE(dev_priv))
 		return phy <= PHY_D;
 	else if (IS_JSL_EHL(dev_priv))
@@ -7345,7 +7347,7 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
 
 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
 {
-	if (IS_ROCKETLAKE(dev_priv))
+	if (IS_ROCKETLAKE(dev_priv) || IS_ALDERLAKE_S(dev_priv))
 		return false;
 	else if (INTEL_GEN(dev_priv) >= 12)
 		return phy >= PHY_D && phy <= PHY_I;
@@ -7357,7 +7359,9 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
 
 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
 {
-	if (IS_ROCKETLAKE(i915) && port >= PORT_D)
+	if (IS_ALDERLAKE_S(i915) && port >= PORT_D)
+		return (enum phy)port - 2;
+	else if (IS_ROCKETLAKE(i915) && port >= PORT_D)
 		return (enum phy)port - 1;
 	else if (IS_JSL_EHL(i915) && port == PORT_D)
 		return PHY_A;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f6b844ca7a9f..85c5e4fb3e7c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1870,10 +1870,13 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define _ICL_COMBOPHY_B			0x6C000
 #define _EHL_COMBOPHY_C			0x160000
 #define _RKL_COMBOPHY_D			0x161000
+#define _ADL_COMBOPHY_E			0x16B000
+
 #define _ICL_COMBOPHY(phy)		_PICK(phy, _ICL_COMBOPHY_A, \
 					      _ICL_COMBOPHY_B, \
 					      _EHL_COMBOPHY_C, \
-					      _RKL_COMBOPHY_D)
+					      _RKL_COMBOPHY_D, \
+					      _ADL_COMBOPHY_E)
 
 /* CNL/ICL Port CL_DW registers */
 #define _ICL_PORT_CL_DW(dw, phy)	(_ICL_COMBOPHY(phy) + \
-- 
2.27.0

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[Intel-gfx] [PATCH 06/18] drm/i915/adl_s: Configure DPLL for ADL-S

[Aditya Swarup]

Add changes for configuring DPLL for ADL-S
- Reusing DG1 DPLL 2 & DPLL 3 for ADL-S
- Extend CNL macro to choose DPLL_ENABLE
  for ADL-S.
- Select CFGCR0 and CFGCR1 for ADL-S plls.

On BSpec: 53720 PLL arrangement dig for adls:
DPLL2 cfgcr is programmed using _ADLS_DPLL3_CFGCR(0/1)
DPLL3 cfgcr is programmed using _ADLS_DPLL4_CFGCR(0/1)

Bspec: 50288
Bspec: 50289
Bspec: 49443

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 38 +++++++++++++++++--
 drivers/gpu/drm/i915/i915_reg.h               | 19 +++++++++-
 2 files changed, 52 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index eaef7a2d041f..f96ce228555a 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3546,7 +3546,13 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state,
 
 	icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
 
-	if (IS_DG1(dev_priv)) {
+	if (IS_ALDERLAKE_S(dev_priv)) {
+		dpll_mask =
+			BIT(DPLL_ID_DG1_DPLL3) |
+			BIT(DPLL_ID_DG1_DPLL2) |
+			BIT(DPLL_ID_ICL_DPLL1) |
+			BIT(DPLL_ID_ICL_DPLL0);
+	} else if (IS_DG1(dev_priv)) {
 		if (port == PORT_D || port == PORT_E) {
 			dpll_mask =
 				BIT(DPLL_ID_DG1_DPLL2) |
@@ -3852,7 +3858,10 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
 	if (!(val & PLL_ENABLE))
 		goto out;
 
-	if (IS_DG1(dev_priv)) {
+	if (IS_ALDERLAKE_S(dev_priv)) {
+		hw_state->cfgcr0 = intel_de_read(dev_priv, ADLS_DPLL_CFGCR0(id));
+		hw_state->cfgcr1 = intel_de_read(dev_priv, ADLS_DPLL_CFGCR1(id));
+	} else if (IS_DG1(dev_priv)) {
 		hw_state->cfgcr0 = intel_de_read(dev_priv, DG1_DPLL_CFGCR0(id));
 		hw_state->cfgcr1 = intel_de_read(dev_priv, DG1_DPLL_CFGCR1(id));
 	} else if (IS_ROCKETLAKE(dev_priv)) {
@@ -3908,7 +3917,10 @@ static void icl_dpll_write(struct drm_i915_private *dev_priv,
 	const enum intel_dpll_id id = pll->info->id;
 	i915_reg_t cfgcr0_reg, cfgcr1_reg;
 
-	if (IS_DG1(dev_priv)) {
+	if (IS_ALDERLAKE_S(dev_priv)) {
+		cfgcr0_reg = ADLS_DPLL_CFGCR0(id);
+		cfgcr1_reg = ADLS_DPLL_CFGCR1(id);
+	} else if (IS_DG1(dev_priv)) {
 		cfgcr0_reg = DG1_DPLL_CFGCR0(id);
 		cfgcr1_reg = DG1_DPLL_CFGCR1(id);
 	} else if (IS_ROCKETLAKE(dev_priv)) {
@@ -4371,6 +4383,22 @@ static const struct intel_dpll_mgr dg1_pll_mgr = {
 	.dump_hw_state = icl_dump_hw_state,
 };
 
+static const struct dpll_info adls_plls[] = {
+	{ "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
+	{ "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
+	{ "DPLL 2", &combo_pll_funcs, DPLL_ID_DG1_DPLL2, 0 },
+	{ "DPLL 3", &combo_pll_funcs, DPLL_ID_DG1_DPLL3, 0 },
+	{ },
+};
+
+static const struct intel_dpll_mgr adls_pll_mgr = {
+	.dpll_info = adls_plls,
+	.get_dplls = icl_get_dplls,
+	.put_dplls = icl_put_dplls,
+	.update_ref_clks = icl_update_dpll_ref_clks,
+	.dump_hw_state = icl_dump_hw_state,
+};
+
 /**
  * intel_shared_dpll_init - Initialize shared DPLLs
  * @dev: drm device
@@ -4384,7 +4412,9 @@ void intel_shared_dpll_init(struct drm_device *dev)
 	const struct dpll_info *dpll_info;
 	int i;
 
-	if (IS_DG1(dev_priv))
+	if (IS_ALDERLAKE_S(dev_priv))
+		dpll_mgr = &adls_pll_mgr;
+	else if (IS_DG1(dev_priv))
 		dpll_mgr = &dg1_pll_mgr;
 	else if (IS_ROCKETLAKE(dev_priv))
 		dpll_mgr = &rkl_pll_mgr;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 85c5e4fb3e7c..e617d24a2912 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10314,11 +10314,14 @@ enum skl_power_gate {
 /* CNL PLL */
 #define DPLL0_ENABLE		0x46010
 #define DPLL1_ENABLE		0x46014
+#define _ADLS_DPLL2_ENABLE	0x46018
+#define _ADLS_DPLL3_ENABLE	0x46030
 #define  PLL_ENABLE		(1 << 31)
 #define  PLL_LOCK		(1 << 30)
 #define  PLL_POWER_ENABLE	(1 << 27)
 #define  PLL_POWER_STATE	(1 << 26)
-#define CNL_DPLL_ENABLE(pll)	_MMIO_PLL(pll, DPLL0_ENABLE, DPLL1_ENABLE)
+#define CNL_DPLL_ENABLE(pll)	_MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
+					   _ADLS_DPLL2_ENABLE, _ADLS_DPLL3_ENABLE)
 
 #define TBT_PLL_ENABLE		_MMIO(0x46020)
 
@@ -10564,6 +10567,20 @@ enum skl_power_gate {
 						   _DG1_DPLL2_CFGCR1, \
 						   _DG1_DPLL3_CFGCR1)
 
+#define _ADLS_DPLL3_CFGCR0		0x1642C0
+#define _ADLS_DPLL4_CFGCR0		0x164294
+#define ADLS_DPLL_CFGCR0(pll)		_MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
+						   _TGL_DPLL1_CFGCR0, \
+						   _ADLS_DPLL3_CFGCR0, \
+						   _ADLS_DPLL4_CFGCR0)
+
+#define _ADLS_DPLL3_CFGCR1		0x1642C4
+#define _ADLS_DPLL4_CFGCR1		0x164298
+#define ADLS_DPLL_CFGCR1(pll)		_MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
+						   _TGL_DPLL1_CFGCR1, \
+						   _ADLS_DPLL3_CFGCR1, \
+						   _ADLS_DPLL4_CFGCR1)
+
 #define _DKL_PHY1_BASE			0x168000
 #define _DKL_PHY2_BASE			0x169000
 #define _DKL_PHY3_BASE			0x16A000
-- 
2.27.0

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[Intel-gfx] [PATCH 07/18] drm/i915/adl_s: Configure Port clock registers for ADL-S

[Aditya Swarup]

Add changes to configure port clock registers for ADL-S. Combo phy port
clocks are configured by DPCLKA_CFGCR0 and DPCLKA_CFGCR1 registers.

The DDI to internal clock mappings in DPCLKA_CFGCR0 register for ADL-S
translates to
DDI A -> DDIA
DDI B -> USBC1
DDI I -> USBC2

For DPCLKA_CFGCR1
DDI J -> USBC3
DDI K -> USBC4

Bspec: 50287
Bspec: 53812
Bspec: 53723

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c     | 64 +++++++++++++-------
 drivers/gpu/drm/i915/display/intel_display.c | 18 +++++-
 drivers/gpu/drm/i915/i915_reg.h              | 25 +++++++-
 3 files changed, 84 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 09811be08cfe..670be712f6ba 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2976,25 +2976,30 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
-	u32 val;
+	u32 val, mask, sel;
+	i915_reg_t reg;
+
+	if (IS_ALDERLAKE_S(dev_priv)) {
+		reg = ADLS_DPCLKA_CFGCR(phy);
+		mask = ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy);
+		sel = ((pll->info->id) << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy));
+	} else if (IS_ROCKETLAKE(dev_priv)) {
+		reg = ICL_DPCLKA_CFGCR0;
+		mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+		sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
+	} else {
+		reg = ICL_DPCLKA_CFGCR0;
+		mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+		sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
+	}
 
 	mutex_lock(&dev_priv->dpll.lock);
 
-	val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
+	val = intel_de_read(dev_priv, reg);
 	drm_WARN_ON(&dev_priv->drm,
 		    (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
 
 	if (intel_phy_is_combo(dev_priv, phy)) {
-		u32 mask, sel;
-
-		if (IS_ROCKETLAKE(dev_priv)) {
-			mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
-			sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
-		} else {
-			mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
-			sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
-		}
-
 		/*
 		 * Even though this register references DDIs, note that we
 		 * want to pass the PHY rather than the port (DDI).  For
@@ -3007,12 +3012,12 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
 		 */
 		val &= ~mask;
 		val |= sel;
-		intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
-		intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0);
+		intel_de_write(dev_priv, reg, val);
+		intel_de_posting_read(dev_priv, reg);
 	}
 
 	val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
-	intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
+	intel_de_write(dev_priv, reg, val);
 
 	mutex_unlock(&dev_priv->dpll.lock);
 }
@@ -3025,9 +3030,17 @@ static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
 
 	mutex_lock(&dev_priv->dpll.lock);
 
-	val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
+	if (IS_ALDERLAKE_S(dev_priv))
+		val = intel_de_read(dev_priv, ADLS_DPCLKA_CFGCR(phy));
+	else
+		val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
+
 	val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
-	intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
+
+	if (IS_ALDERLAKE_S(dev_priv))
+		intel_de_write(dev_priv, ADLS_DPCLKA_CFGCR(phy), val);
+	else
+		intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
 
 	mutex_unlock(&dev_priv->dpll.lock);
 }
@@ -3036,13 +3049,19 @@ static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
 				      u32 port_mask, bool ddi_clk_needed)
 {
 	enum port port;
+	bool ddi_clk_off;
 	u32 val;
 
-	val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
 	for_each_port_masked(port, port_mask) {
 		enum phy phy = intel_port_to_phy(dev_priv, port);
-		bool ddi_clk_off = val & icl_dpclka_cfgcr0_clk_off(dev_priv,
-								   phy);
+
+		if (IS_ALDERLAKE_S(dev_priv))
+			val = intel_de_read(dev_priv, ADLS_DPCLKA_CFGCR(phy));
+		else
+			val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
+
+		ddi_clk_off = val & icl_dpclka_cfgcr0_clk_off(dev_priv,
+							      phy);
 
 		if (ddi_clk_needed == !ddi_clk_off)
 			continue;
@@ -3058,7 +3077,10 @@ static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
 			   "PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
 			   phy_name(phy));
 		val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
-		intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
+		if (IS_ALDERLAKE_S(dev_priv))
+			intel_de_write(dev_priv, ADLS_DPCLKA_CFGCR(phy), val);
+		else
+			intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
 	}
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 70ca5d2e5b0a..b3714ed00786 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10958,6 +10958,20 @@ static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
 	icl_set_active_port_dpll(pipe_config, port_dpll_id);
 }
 
+static void adls_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
+			     struct intel_crtc_state *pipe_config)
+{
+	enum phy phy = intel_port_to_phy(dev_priv, port);
+	enum intel_dpll_id id;
+	u32 val;
+
+	val = I915_READ(ADLS_DPCLKA_CFGCR(phy));
+	val &= ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy);
+	id = val >> ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy);
+
+	pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
+}
+
 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
 				enum port port,
 				struct intel_crtc_state *pipe_config)
@@ -11205,7 +11219,9 @@ static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
 			port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
 	}
 
-	if (INTEL_GEN(dev_priv) >= 11)
+	if (IS_ALDERLAKE_S(dev_priv))
+		adls_get_ddi_pll(dev_priv, port, pipe_config);
+	else if (INTEL_GEN(dev_priv) >= 11)
 		icl_get_ddi_pll(dev_priv, port, pipe_config);
 	else if (IS_CANNONLAKE(dev_priv))
 		cnl_get_ddi_pll(dev_priv, port, pipe_config);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e617d24a2912..604fce828a7d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -230,12 +230,14 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define _TRANS(tran, a, b)		_PICK_EVEN(tran, a, b)
 #define _PORT(port, a, b)		_PICK_EVEN(port, a, b)
 #define _PLL(pll, a, b)			_PICK_EVEN(pll, a, b)
+#define _PHY(phy, a, b)                 _PICK_EVEN(phy, a, b)
 
 #define _MMIO_PIPE(pipe, a, b)		_MMIO(_PIPE(pipe, a, b))
 #define _MMIO_PLANE(plane, a, b)	_MMIO(_PLANE(plane, a, b))
 #define _MMIO_TRANS(tran, a, b)		_MMIO(_TRANS(tran, a, b))
 #define _MMIO_PORT(port, a, b)		_MMIO(_PORT(port, a, b))
 #define _MMIO_PLL(pll, a, b)		_MMIO(_PLL(pll, a, b))
+#define _MMIO_PHY(phy, a, b)            _MMIO(_PHY(phy, a, b))
 
 #define _PHY3(phy, ...)			_PICK(phy, __VA_ARGS__)
 
@@ -10297,7 +10299,7 @@ enum skl_power_gate {
 #define  DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port)	((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
 
 #define ICL_DPCLKA_CFGCR0			_MMIO(0x164280)
-#define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)	(1 << _PICK(phy, 10, 11, 24))
+#define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)	(1 << _PICK(phy, 10, 11, 24, 4, 5))
 #define  RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)	REG_BIT((phy) + 10)
 #define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)	(1 << ((tc_port) < PORT_TC4 ? \
 						       (tc_port) + 12 : \
@@ -10311,6 +10313,27 @@ enum skl_power_gate {
 #define  RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \
 	((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
 
+/* ADLS Clocks */
+#define _ADLS_DPCLKA_CFGCR0			0x164280
+#define _ADLS_DPCLKA_CFGCR1			0x1642BC
+#define ADLS_DPCLKA_CFGCR(phy)			_MMIO_PHY((phy) / 3, \
+							  _ADLS_DPCLKA_CFGCR0, \
+							  _ADLS_DPCLKA_CFGCR1)
+#define  ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)		(((phy) % 3) * 2)
+/* ADLS DPCLKA_CFGCR0 DDI mask */
+#define  ADLS_DPCLKA_DDII_SEL_MASK			REG_GENMASK(5, 4)
+#define  ADLS_DPCLKA_DDIB_SEL_MASK			REG_GENMASK(3, 2)
+#define  ADLS_DPCLKA_DDIA_SEL_MASK			REG_GENMASK(1, 0)
+/* ADLS DPCLKA_CFGCR1 DDI mask */
+#define  ADLS_DPCLKA_DDIK_SEL_MASK			REG_GENMASK(3, 2)
+#define  ADLS_DPCLKA_DDIJ_SEL_MASK			REG_GENMASK(1, 0)
+#define  ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy)	_PICK((phy), \
+							ADLS_DPCLKA_DDIA_SEL_MASK, \
+							ADLS_DPCLKA_DDIB_SEL_MASK, \
+							ADLS_DPCLKA_DDII_SEL_MASK, \
+							ADLS_DPCLKA_DDIJ_SEL_MASK, \
+							ADLS_DPCLKA_DDIK_SEL_MASK)
+
 /* CNL PLL */
 #define DPLL0_ENABLE		0x46010
 #define DPLL1_ENABLE		0x46014
-- 
2.27.0

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[Intel-gfx] [PATCH 08/18] drm/i915/adl_s: Setup display outputs and HTI support for ADL-S

[Aditya Swarup]

Initialize display outputs and add HTI support for ADL-S. ADL-S has 5
display outputs -> 1 eDP, 2 HDMI and 2 DP++ outputs.

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 8 +++++++-
 drivers/gpu/drm/i915/i915_pci.c              | 1 +
 drivers/gpu/drm/i915/i915_reg.h              | 2 +-
 3 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index b3714ed00786..d13b774a9254 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -17116,7 +17116,13 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
 	if (!HAS_DISPLAY(dev_priv))
 		return;
 
-	if (IS_ROCKETLAKE(dev_priv)) {
+	if (IS_ALDERLAKE_S(dev_priv)) {
+		intel_ddi_init(dev_priv, PORT_A);
+		intel_ddi_init(dev_priv, PORT_D);	/* DDI TC1 */
+		intel_ddi_init(dev_priv, PORT_E);	/* DDI TC2 */
+		intel_ddi_init(dev_priv, PORT_F);	/* DDI TC3 */
+		intel_ddi_init(dev_priv, PORT_G);	/* DDI TC4 */
+	} else if (IS_ROCKETLAKE(dev_priv)) {
 		intel_ddi_init(dev_priv, PORT_A);
 		intel_ddi_init(dev_priv, PORT_B);
 		intel_ddi_init(dev_priv, PORT_D);	/* DDI TC1 */
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d39a7389b305..b4d5939f108a 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -929,6 +929,7 @@ static const struct intel_device_info adl_s_info = {
 	PLATFORM(INTEL_ALDERLAKE_S),
 	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
 	.require_force_probe = 1,
+	.display.has_hti = 1,
 	.display.has_psr_hw_tracking = 0,
 	.platform_engine_mask =
 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 604fce828a7d..267e6602a05b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2928,7 +2928,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define MBUS_BBOX_CTL_S2		_MMIO(0x45044)
 
 #define HDPORT_STATE			_MMIO(0x45050)
-#define   HDPORT_DPLL_USED_MASK		REG_GENMASK(14, 12)
+#define   HDPORT_DPLL_USED_MASK		REG_GENMASK(15, 12)
 #define   HDPORT_PHY_USED_DP(phy)	REG_BIT(2 * (phy) + 2)
 #define   HDPORT_PHY_USED_HDMI(phy)	REG_BIT(2 * (phy) + 1)
 #define   HDPORT_ENABLED		REG_BIT(0)
-- 
2.27.0

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[Intel-gfx] [PATCH 09/18] drm/i915/adl_s: Add adl-s ddc pin mapping

[Aditya Swarup]

ADL-S requires TC pins to set up ddc for Combo PHY B, C, D and E.
Combo PHY A still uses the old ddc pin mapping.

From VBT, ddc pin info suggests the following mapping:
VBT 			               DRIVER
DDI B->ddc_pin=2 should translate to PORT_D->0x9
DDI C->ddc_pin=3 should translate to PORT_E->0xa
DDI D->ddc_pin=4 should translate to PORT_F->0xb
DDI E->ddc_pin=5 should translate to PORT_G->0xc

Adding pin map to facilitate this translation as we cannot use existing
icl ddc pin map due to conflict with DDI B and DDI C info.

Bspec:20124
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c     | 13 +++++++++++-
 drivers/gpu/drm/i915/display/intel_hdmi.c     | 20 ++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_vbt_defs.h |  4 ++++
 3 files changed, 35 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 0a309645fe06..f602013a764a 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1623,12 +1623,23 @@ static const u8 icp_ddc_pin_map[] = {
 	[TGL_DDC_BUS_PORT_6] = GMBUS_PIN_14_TC6_TGP,
 };
 
+static const u8 adls_ddc_pin_map[] = {
+	[ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,
+	[ADLS_DDC_BUS_PORT_TC1] = GMBUS_PIN_9_TC1_ICP,
+	[ADLS_DDC_BUS_PORT_TC2] = GMBUS_PIN_10_TC2_ICP,
+	[ADLS_DDC_BUS_PORT_TC3] = GMBUS_PIN_11_TC3_ICP,
+	[ADLS_DDC_BUS_PORT_TC4] = GMBUS_PIN_12_TC4_ICP,
+};
+
 static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
 {
 	const u8 *ddc_pin_map;
 	int n_entries;
 
-	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) {
+	if (IS_ALDERLAKE_S(dev_priv)) {
+		ddc_pin_map = adls_ddc_pin_map;
+		n_entries = ARRAY_SIZE(adls_ddc_pin_map);
+	} else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) {
 		return vbt_pin;
 	} else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
 		ddc_pin_map = icp_ddc_pin_map;
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index f90838bc74fb..8fdf0623d663 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -3145,6 +3145,22 @@ static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
 	return intel_port_to_phy(dev_priv, port) + 1;
 }
 
+static u8 adls_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
+{
+	enum phy phy = intel_port_to_phy(dev_priv, port);
+
+	WARN_ON(port == PORT_B || port == PORT_C);
+
+	/*
+	 * Pin mapping for ADL-S requires TC pins for all combo phy outputs
+	 * except first combo output.
+	 */
+	if (IS_ALDERLAKE_S(dev_priv) && phy >= PHY_B)
+		return GMBUS_PIN_9_TC1_ICP + phy - PHY_B;
+
+	return GMBUS_PIN_1_BXT + phy;
+}
+
 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
 			      enum port port)
 {
@@ -3182,7 +3198,9 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
 		return ddc_pin;
 	}
 
-	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+	if (IS_ALDERLAKE_S(dev_priv))
+		ddc_pin = adls_port_to_ddc_pin(dev_priv, port);
+	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
 		ddc_pin = dg1_port_to_ddc_pin(dev_priv, port);
 	else if (IS_ROCKETLAKE(dev_priv))
 		ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 49b4b5fca941..32d1b4f05760 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -325,6 +325,10 @@ enum vbt_gmbus_ddi {
 	ICL_DDC_BUS_PORT_4,
 	TGL_DDC_BUS_PORT_5,
 	TGL_DDC_BUS_PORT_6,
+	ADLS_DDC_BUS_PORT_TC1 = 0x2,
+	ADLS_DDC_BUS_PORT_TC2,
+	ADLS_DDC_BUS_PORT_TC3,
+	ADLS_DDC_BUS_PORT_TC4
 };
 
 #define DP_AUX_A 0x40
-- 
2.27.0

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[Intel-gfx] [PATCH 10/18] drm/i915/adl_s: Add vbt port and aux channel settings for adls

[Aditya Swarup]

- ADL-S driver internal mapping uses PORT D, E, F, G for Combo phy B, C, D and E.
- Add ADLS specific port mappings for vbt port dvo settings.
- Select appropriate AUX CH specific to ADLS based on port mapping.

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c | 42 +++++++++++++++++++----
 1 file changed, 35 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index f602013a764a..36e0a7a5c52b 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1711,8 +1711,26 @@ static enum port dvo_port_to_port(struct drm_i915_private *dev_priv,
 		[PORT_D] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
 		[PORT_E] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
 	};
+	/*
+	 * Alderlake S ports used in the driver are PORT_A, PORT_D, PORT_E,
+	 * PORT_F and PORT_G, we need to map that to correct VBT sections.
+	 */
+	static const int adls_port_mapping[][3] = {
+		[PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },
+		[PORT_B] = { -1 },
+		[PORT_C] = { -1 },
+		[PORT_D] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },
+		[PORT_E] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
+		[PORT_F] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
+		[PORT_G] = { DVO_PORT_HDMIE, DVO_PORT_DPE, -1 },
+	};
 
-	if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
+	if (IS_ALDERLAKE_S(dev_priv))
+		return __dvo_port_to_port(ARRAY_SIZE(adls_port_mapping),
+					  ARRAY_SIZE(adls_port_mapping[0]),
+					  adls_port_mapping,
+					  dvo_port);
+	else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
 		return __dvo_port_to_port(ARRAY_SIZE(rkl_port_mapping),
 					  ARRAY_SIZE(rkl_port_mapping[0]),
 					  rkl_port_mapping,
@@ -2674,18 +2692,28 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv,
 		aux_ch = AUX_CH_A;
 		break;
 	case DP_AUX_B:
-		aux_ch = AUX_CH_B;
+		aux_ch = (IS_ALDERLAKE_S(dev_priv)) ?
+			AUX_CH_D : AUX_CH_B;
 		break;
 	case DP_AUX_C:
-		aux_ch = (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) ?
-			AUX_CH_D : AUX_CH_C;
+		if (IS_ALDERLAKE_S(dev_priv))
+			aux_ch = AUX_CH_E;
+		else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
+			aux_ch = AUX_CH_D;
+		else
+			aux_ch = AUX_CH_C;
 		break;
 	case DP_AUX_D:
-		aux_ch = (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) ?
-			AUX_CH_E : AUX_CH_D;
+		if (IS_ALDERLAKE_S(dev_priv))
+			aux_ch = AUX_CH_F;
+		else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
+			aux_ch = AUX_CH_E;
+		else
+			aux_ch = AUX_CH_D;
 		break;
 	case DP_AUX_E:
-		aux_ch = AUX_CH_E;
+		aux_ch = (IS_ALDERLAKE_S(dev_priv)) ?
+			AUX_CH_G : AUX_CH_E;
 		break;
 	case DP_AUX_F:
 		aux_ch = AUX_CH_F;
-- 
2.27.0

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[Intel-gfx] [PATCH 11/18] drm/i915/adl_s: Update combo PHY master/slave relationships

[Aditya Swarup]

From: Matt Roper <matthew.d.roper@intel.com>

ADL-S switches up which PHYs are considered a master to other PHYs;
PHY-C is no longer a master, but PHY-D is now.

Bspec: 49291
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
 drivers/gpu/drm/i915/display/intel_combo_phy.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index d5ad61e4083e..55d2d2d9efbb 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -246,14 +246,21 @@ static bool phy_is_master(struct drm_i915_private *dev_priv, enum phy phy)
 	 * RKL,DG1:
 	 *   A(master) -> B(slave)
 	 *   C(master) -> D(slave)
+	 * ADL-S:
+	 *   A(master) -> B(slave), C(slave)
+	 *   D(master) -> E(slave)
 	 *
 	 * We must set the IREFGEN bit for any PHY acting as a master
 	 * to another PHY.
 	 */
-	if ((IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) && phy == PHY_C)
+	if (phy == PHY_A)
 		return true;
+	else if (IS_ALDERLAKE_S(dev_priv))
+		return phy == PHY_D;
+	else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
+		return phy == PHY_C;
 
-	return phy == PHY_A;
+	return false;
 }
 
 static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
-- 
2.27.0

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[Intel-gfx] [PATCH 12/18] drm/i915/adl_s: Update PHY_MISC programming

[Aditya Swarup]

From: Matt Roper <matthew.d.roper@intel.com>

ADL-S has instances of the PHY_MISC register on the first three PHYs,
but only expects the "DE to IO Comp Pwr Down" bit (the only bit we touch
on non-EHL platforms) to be programmed for PHY A.

Bspec: 50107
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
 drivers/gpu/drm/i915/display/intel_combo_phy.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index 55d2d2d9efbb..5a71adbd7a4d 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -187,10 +187,16 @@ static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy)
 	 * Some platforms only expect PHY_MISC to be programmed for PHY-A and
 	 * PHY-B and may not even have instances of the register for the
 	 * other combo PHY's.
+	 *
+	 * ADL-S technically has three instances of PHY_MISC, but only requires
+	 * that we program it for PHY A.
 	 */
-	if (IS_JSL_EHL(i915) ||
-	    IS_ROCKETLAKE(i915) ||
-	    IS_DG1(i915))
+
+	if (IS_ALDERLAKE_S(i915))
+		return phy == PHY_A;
+	else if (IS_JSL_EHL(i915) ||
+		 IS_ROCKETLAKE(i915) ||
+		 IS_DG1(i915))
 		return phy < PHY_C;
 
 	return true;
-- 
2.27.0

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[Intel-gfx] [PATCH 13/18] drm/i915/adl_s: Add display, gt, ctx and ADL-S whitelist WA

[Aditya Swarup]

From: Anusha Srivatsa <anusha.srivatsa@intel.com>

- Inherit the gen12 workarounds.
- Add placeholders to setup GT WA.
- Extend permanent driver WA Wa_1409767108 to adl-s and
  Wa_14010685332 to adl-s.
- Extend permanent driver WA Wa_1606054188 to adl-s
- Add Wa_14011765242 for adl-s A0 stepping.

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
 .../drm/i915/display/intel_display_power.c    |  7 +++--
 drivers/gpu/drm/i915/display/intel_sprite.c   |  2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   | 29 +++++++++++++++++--
 drivers/gpu/drm/i915/i915_irq.c               |  2 +-
 drivers/gpu/drm/i915/intel_device_info.c      |  6 +++-
 5 files changed, 37 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 689922480661..acc63ab2bc78 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5288,9 +5288,10 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
 	unsigned long abox_mask = INTEL_INFO(dev_priv)->abox_mask;
 	int config, i;
 
-	if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
+	if (IS_ALDERLAKE_S(dev_priv) ||
+	    IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
 	    IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
-		/* Wa_1409767108:tgl,dg1 */
+		/* Wa_1409767108:tgl,dg1,adl-s */
 		table = wa_1409767108_buddy_page_masks;
 	else
 		table = tgl_buddy_page_masks;
@@ -5328,7 +5329,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
 
 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 
-	/* Wa_14011294188:ehl,jsl,tgl,rkl */
+	/* Wa_14011294188:ehl,jsl,tgl,rkl,adl-s */
 	if (INTEL_PCH_TYPE(dev_priv) >= PCH_JSP &&
 	    INTEL_PCH_TYPE(dev_priv) < PCH_DG1)
 		intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 0,
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 88bfebdf9228..d4b5fc9e2704 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2226,7 +2226,7 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
 	}
 
 	/* Wa_1606054188:tgl */
-	if (IS_TIGERLAKE(dev_priv) &&
+	if ((IS_TIGERLAKE(dev_priv) || IS_ALDERLAKE_S(dev_priv)) &&
 	    plane_state->ckey.flags & I915_SET_COLORKEY_SOURCE &&
 	    intel_format_is_p01x(fb->format->format)) {
 		drm_dbg_kms(&dev_priv->drm,
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index fed9503a7c4e..8136d13462b5 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -686,6 +686,12 @@ static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine,
 			  DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE);
 }
 
+static void adls_ctx_workarounds_init(struct intel_engine_cs *engine,
+				      struct i915_wa_list *wal)
+{
+	gen12_ctx_workarounds_init(engine, wal);
+}
+
 static void
 __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
 			   struct i915_wa_list *wal,
@@ -698,7 +704,9 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
 
 	wa_init_start(wal, name, engine->name);
 
-	if (IS_DG1(i915))
+	if (IS_ALDERLAKE_S(i915))
+		adls_ctx_workarounds_init(engine, wal);
+	else if (IS_DG1(i915))
 		dg1_ctx_workarounds_init(engine, wal);
 	else if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915))
 		tgl_ctx_workarounds_init(engine, wal);
@@ -1284,10 +1292,18 @@ dg1_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 			    VSUNIT_CLKGATE_DIS_TGL);
 }
 
+static void
+adls_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
+{
+	gen12_gt_workarounds_init(i915, wal);
+}
+
 static void
 gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
 {
-	if (IS_DG1(i915))
+	if (IS_ALDERLAKE_S(i915))
+		adls_gt_workarounds_init(i915, wal);
+	else if (IS_DG1(i915))
 		dg1_gt_workarounds_init(i915, wal);
 	else if (IS_TIGERLAKE(i915))
 		tgl_gt_workarounds_init(i915, wal);
@@ -1668,6 +1684,11 @@ static void dg1_whitelist_build(struct intel_engine_cs *engine)
 				  RING_FORCE_TO_NONPRIV_ACCESS_RD);
 }
 
+static void adls_whitelist_build(struct intel_engine_cs *engine)
+{
+	tgl_whitelist_build(engine);
+}
+
 void intel_engine_init_whitelist(struct intel_engine_cs *engine)
 {
 	struct drm_i915_private *i915 = engine->i915;
@@ -1675,7 +1696,9 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
 
 	wa_init_start(w, "whitelist", engine->name);
 
-	if (IS_DG1(i915))
+	if (IS_ALDERLAKE_S(i915))
+		adls_whitelist_build(engine);
+	else if (IS_DG1(i915))
 		dg1_whitelist_build(engine);
 	else if (IS_GEN(i915, 12))
 		tgl_whitelist_build(engine);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 9033221995ad..32cb12c4b6dd 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3045,7 +3045,7 @@ static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
 	if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
 		GEN3_IRQ_RESET(uncore, SDE);
 
-	/* Wa_14010685332:icl,jsl,ehl,tgl,rkl */
+	/* Wa_14010685332:icl,jsl,ehl,tgl,rkl,adl-s A0 */
 	if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
 		intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
 				 SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 7310e019c611..4fffa8295d06 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -394,7 +394,11 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 	struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
 	enum pipe pipe;
 
-	if (INTEL_GEN(dev_priv) >= 10) {
+	/* Wa_14011765242: adl-s A0 */
+	if (IS_ADLS_REVID(dev_priv, ADLS_REVID_A0, ADLS_REVID_A0))
+		for_each_pipe(dev_priv, pipe)
+			runtime->num_scalers[pipe] = 0;
+	else if (INTEL_GEN(dev_priv) >= 10) {
 		for_each_pipe(dev_priv, pipe)
 			runtime->num_scalers[pipe] = 2;
 	} else if (IS_GEN(dev_priv, 9)) {
-- 
2.27.0

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[Intel-gfx] [PATCH 14/18] drm/i915/adl_s: MCHBAR memory info registers are moved

[Aditya Swarup]

From: "Yokoyama, Caz" <caz.yokoyama@intel.com>

The crwebview indicates on ADL-S that some of our MCHBAR
registers have moved from their traditional 0x50XX offsets to
new locations. The meaning and bit layout of the registers
remain same.

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Yokoyama, Caz <caz.yokoyama@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h   |  5 +++++
 drivers/gpu/drm/i915/intel_dram.c | 18 +++++++++++++++---
 2 files changed, 20 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 267e6602a05b..067e3710d38d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10836,6 +10836,8 @@ enum skl_power_gate {
 #define  SKL_DRAM_DDR_TYPE_LPDDR3		(2 << 0)
 #define  SKL_DRAM_DDR_TYPE_LPDDR4		(3 << 0)
 
+#define  ADLS_MAD_INTER_CHANNEL_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6048)
+
 #define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
 #define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010)
 #define  SKL_DRAM_S_SHIFT			16
@@ -10863,6 +10865,9 @@ enum skl_power_gate {
 #define  CNL_DRAM_RANK_3			(0x2 << 9)
 #define  CNL_DRAM_RANK_4			(0x3 << 9)
 
+#define ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR		_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6054)
+#define ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR		_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6058)
+
 /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
  * since on HSW we can't write to it using I915_WRITE. */
 #define D_COMP_HSW			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
diff --git a/drivers/gpu/drm/i915/intel_dram.c b/drivers/gpu/drm/i915/intel_dram.c
index 4754296a250e..e7427e5f4130 100644
--- a/drivers/gpu/drm/i915/intel_dram.c
+++ b/drivers/gpu/drm/i915/intel_dram.c
@@ -184,13 +184,21 @@ skl_dram_get_channels_info(struct drm_i915_private *i915)
 	u32 val;
 	int ret;
 
-	val = intel_uncore_read(&i915->uncore,
+	if (IS_ALDERLAKE_S(i915))
+		val = intel_uncore_read(&i915->uncore,
+				ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR);
+	else
+		val = intel_uncore_read(&i915->uncore,
 				SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
 	ret = skl_dram_get_channel_info(i915, &ch0, 0, val);
 	if (ret == 0)
 		dram_info->num_channels++;
 
-	val = intel_uncore_read(&i915->uncore,
+	if (IS_ALDERLAKE_S(i915))
+		val = intel_uncore_read(&i915->uncore,
+				ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR);
+	else
+		val = intel_uncore_read(&i915->uncore,
 				SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
 	ret = skl_dram_get_channel_info(i915, &ch1, 1, val);
 	if (ret == 0)
@@ -231,7 +239,11 @@ skl_get_dram_type(struct drm_i915_private *i915)
 {
 	u32 val;
 
-	val = intel_uncore_read(&i915->uncore,
+	if (IS_ALDERLAKE_S(i915))
+		val = intel_uncore_read(&i915->uncore,
+				ADLS_MAD_INTER_CHANNEL_0_0_0_MCHBAR);
+	else
+		val = intel_uncore_read(&i915->uncore,
 				SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN);
 
 	switch (val & SKL_DRAM_DDR_TYPE_MASK) {
-- 
2.27.0

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[Intel-gfx] [PATCH 15/18] drm/i915/adl_s: Re-use TGL GuC/HuC firmware

[Aditya Swarup]

From: Matt Roper <matthew.d.roper@intel.com>

ADL-S, like RKL, uses the same internal device ID for the GuC and HuC as
TGL did, making them all firmware-compatible.  Let's re-use TGL's
firmware for ADL-S.

Bspec: 50668
Cc: John Harrison <John.C.Harrison@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 037bcaf3c8b5..f1ddd01e49d3 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -48,9 +48,11 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
  * between 33.0 and 35.2 are only related to new additions to support new Gen12
  * features.
  *
- * Note that RKL uses the same firmware as TGL.
+ * Note that RKL and ADL-S have the same GuC/HuC device ID's and use the same
+ * firmware as TGL.
  */
 #define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \
+	fw_def(ALDERLAKE_S, 0, guc_def(tgl, 35, 2, 0), huc_def(tgl,  7, 5, 0)) \
 	fw_def(ROCKETLAKE,  0, guc_def(tgl, 35, 2, 0), huc_def(tgl,  7, 5, 0)) \
 	fw_def(TIGERLAKE,   0, guc_def(tgl, 35, 2, 0), huc_def(tgl,  7, 5, 0)) \
 	fw_def(JASPERLAKE,  0, guc_def(ehl, 33, 0, 4), huc_def(ehl,  9, 0, 0)) \
-- 
2.27.0

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[Intel-gfx] [PATCH 16/18] drm/i915/display: Add HAS_D12_PLANE_MINIMIZATION

[Aditya Swarup]

From: José Roberto de Souza <jose.souza@intel.com>

- As RKL and ADL-S only have 5 planes, primary and 4 sprites and
  the cursor plane, let's group the handling together under
  HAS_D12_PLANE_MINIMIZATION.
- Also use macro to select pipe irq fault error mask.

BSpec: 49251
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
 drivers/gpu/drm/i915/display/intel_sprite.c | 2 +-
 drivers/gpu/drm/i915/i915_drv.h             | 3 +++
 drivers/gpu/drm/i915/i915_irq.c             | 2 +-
 drivers/gpu/drm/i915/intel_device_info.c    | 2 +-
 4 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index d4b5fc9e2704..00d9836e77dd 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -351,7 +351,7 @@ int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
 
 static u8 icl_nv12_y_plane_mask(struct drm_i915_private *i915)
 {
-	if (IS_ROCKETLAKE(i915))
+	if (HAS_D12_PLANE_MINIMIZATION(i915))
 		return BIT(PLANE_SPRITE2) | BIT(PLANE_SPRITE3);
 	else
 		return BIT(PLANE_SPRITE4) | BIT(PLANE_SPRITE5);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4fea3d5e01f4..75954a2f4932 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1765,6 +1765,9 @@ tgl_revids_get(struct drm_i915_private *dev_priv)
 #define INTEL_DISPLAY_ENABLED(dev_priv) \
 	(drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !(dev_priv)->params.disable_display)
 
+#define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \
+					      IS_ALDERLAKE_S(dev_priv))
+
 static inline bool intel_vtd_active(void)
 {
 #ifdef CONFIG_INTEL_IOMMU
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 32cb12c4b6dd..a888b7c14ad2 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2220,7 +2220,7 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
 
 static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
 {
-	if (IS_ROCKETLAKE(dev_priv))
+	if (HAS_D12_PLANE_MINIMIZATION(dev_priv))
 		return RKL_DE_PIPE_IRQ_FAULT_ERRORS;
 	else if (INTEL_GEN(dev_priv) >= 11)
 		return GEN11_DE_PIPE_IRQ_FAULT_ERRORS;
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 4fffa8295d06..850f8141d80c 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -409,7 +409,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 
 	BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);
 
-	if (IS_ROCKETLAKE(dev_priv))
+	if (HAS_D12_PLANE_MINIMIZATION(dev_priv))
 		for_each_pipe(dev_priv, pipe)
 			runtime->num_sprites[pipe] = 4;
 	else if (INTEL_GEN(dev_priv) >= 11)
-- 
2.27.0

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[Intel-gfx] [PATCH 17/18] drm/i915/adl_s: Update memory bandwidth parameters

[Aditya Swarup]

From: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>

Just like RKL, the ADL_S platform also has different memory
characteristics from past platforms.  Update the values used
by our memory bandwidth calculations accordingly.

Bspec: 64631
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index bd060404d249..32522ec1ffb9 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -205,6 +205,12 @@ static const struct intel_sa_info rkl_sa_info = {
 	.displayrtids = 128,
 };
 
+static const struct intel_sa_info adls_sa_info = {
+	.deburst = 16,
+	.deprogbwlimit = 38, /* GB/s */
+	.displayrtids = 256,
+};
+
 static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa)
 {
 	struct intel_qgv_info qi = {};
@@ -317,6 +323,8 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
 
 	if (IS_ROCKETLAKE(dev_priv))
 		icl_get_bw_info(dev_priv, &rkl_sa_info);
+	else if (IS_ALDERLAKE_S(dev_priv))
+		icl_get_bw_info(dev_priv, &adls_sa_info);
 	else if (IS_GEN(dev_priv, 12))
 		icl_get_bw_info(dev_priv, &tgl_sa_info);
 	else if (IS_GEN(dev_priv, 11))
-- 
2.27.0

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[Intel-gfx] [PATCH 18/18] drm/i915/adl_s: Load DMC

[Aditya Swarup]

From: Anusha Srivatsa <anusha.srivatsa@intel.com>

Load DMC on ADL_S v2.01. This is the first offcial
release of DMC for ADL_S.

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
 drivers/gpu/drm/i915/display/intel_csr.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c
index 67dc64df78a5..db9f219c4b5a 100644
--- a/drivers/gpu/drm/i915/display/intel_csr.c
+++ b/drivers/gpu/drm/i915/display/intel_csr.c
@@ -40,6 +40,10 @@
 
 #define GEN12_CSR_MAX_FW_SIZE		ICL_CSR_MAX_FW_SIZE
 
+#define ADLS_CSR_PATH			"i915/adls_dmc_ver2_01.bin"
+#define ADLS_CSR_VERSION_REQUIRED	CSR_VERSION(2, 1)
+MODULE_FIRMWARE(ADLS_CSR_PATH);
+
 #define DG1_CSR_PATH			"i915/dg1_dmc_ver2_02.bin"
 #define DG1_CSR_VERSION_REQUIRED	CSR_VERSION(2, 2)
 MODULE_FIRMWARE(DG1_CSR_PATH);
@@ -689,7 +693,11 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
 	 */
 	intel_csr_runtime_pm_get(dev_priv);
 
-	if (IS_DG1(dev_priv)) {
+	if (IS_ALDERLAKE_S(dev_priv)) {
+		csr->fw_path = ADLS_CSR_PATH;
+		csr->required_version = ADLS_CSR_VERSION_REQUIRED;
+		csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
+	} else if (IS_DG1(dev_priv)) {
 		csr->fw_path = DG1_CSR_PATH;
 		csr->required_version = DG1_CSR_VERSION_REQUIRED;
 		csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
-- 
2.27.0

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Alderlake-S

[Patchwork]

== Series Details ==

Series: Introduce Alderlake-S
URL   : https://patchwork.freedesktop.org/series/82917/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
37adab61ebad drm/i915/adl_s: Add ADL-S platform info and PCI ids
-:54: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#54: FILE: drivers/gpu/drm/i915/i915_drv.h:1622:
+#define IS_ADLS_REVID(p, since, until) \
+       (IS_ALDERLAKE_S(p) && IS_REVID(p, since, until))

-:55: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#55: FILE: drivers/gpu/drm/i915/i915_drv.h:1623:
+       (IS_ALDERLAKE_S(p) && IS_REVID(p, since, until))$

-:123: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#123: FILE: include/drm/i915_pciids.h:639:
+#define INTEL_ADLS_IDS(info) \
+	INTEL_VGA_DEVICE(0x4680, info), \
+	INTEL_VGA_DEVICE(0x4681, info), \
+	INTEL_VGA_DEVICE(0x4682, info), \
+	INTEL_VGA_DEVICE(0x4683, info), \
+	INTEL_VGA_DEVICE(0x4690, info), \
+	INTEL_VGA_DEVICE(0x4691, info), \
+	INTEL_VGA_DEVICE(0x4692, info), \
+	INTEL_VGA_DEVICE(0x4693, info), \
+	INTEL_VGA_DEVICE(0x4698, info), \
+	INTEL_VGA_DEVICE(0x4699, info)

-:123: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#123: FILE: include/drm/i915_pciids.h:639:
+#define INTEL_ADLS_IDS(info) \
+	INTEL_VGA_DEVICE(0x4680, info), \
+	INTEL_VGA_DEVICE(0x4681, info), \
+	INTEL_VGA_DEVICE(0x4682, info), \
+	INTEL_VGA_DEVICE(0x4683, info), \
+	INTEL_VGA_DEVICE(0x4690, info), \
+	INTEL_VGA_DEVICE(0x4691, info), \
+	INTEL_VGA_DEVICE(0x4692, info), \
+	INTEL_VGA_DEVICE(0x4693, info), \
+	INTEL_VGA_DEVICE(0x4698, info), \
+	INTEL_VGA_DEVICE(0x4699, info)

total: 1 errors, 1 warnings, 2 checks, 76 lines checked
3f14bf129a7d x86/gpu: add ADL_S stolen memory support
9541e1b5d9c5 drm/i915/adl_s: Add PCH support
0cdf50266822 drm/i915/adl_s: Add Interrupt Support
8426881fd08d drm/i915/adl_s: Add PHYs for Alderlake S
eec312e2d54c drm/i915/adl_s: Configure DPLL for ADL-S
cf0751c1b462 drm/i915/adl_s: Configure Port clock registers for ADL-S
919fedfd3bf3 drm/i915/adl_s: Setup display outputs and HTI support for ADL-S
adec6f0e64aa drm/i915/adl_s: Add adl-s ddc pin mapping
5e3a85cbe54a drm/i915/adl_s: Add vbt port and aux channel settings for adls
-:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#10: 
- ADL-S driver internal mapping uses PORT D, E, F, G for Combo phy B, C, D and E.

total: 0 errors, 1 warnings, 0 checks, 61 lines checked
7fe0b1ea22d2 drm/i915/adl_s: Update combo PHY master/slave relationships
9f3a0b45ebec drm/i915/adl_s: Update PHY_MISC programming
1ad9fe655cde drm/i915/adl_s: Add display, gt, ctx and ADL-S whitelist WA
-:163: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Anusha Srivatsa <anusha.srivatsa@intel.com>'

total: 0 errors, 1 warnings, 0 checks, 110 lines checked
f3ca8144e558 drm/i915/adl_s: MCHBAR memory info registers are moved
-:56: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#56: FILE: drivers/gpu/drm/i915/intel_dram.c:189:
+		val = intel_uncore_read(&i915->uncore,
+				ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR);

-:59: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#59: FILE: drivers/gpu/drm/i915/intel_dram.c:192:
+		val = intel_uncore_read(&i915->uncore,
 				SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);

-:67: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#67: FILE: drivers/gpu/drm/i915/intel_dram.c:199:
+		val = intel_uncore_read(&i915->uncore,
+				ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR);

-:70: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#70: FILE: drivers/gpu/drm/i915/intel_dram.c:202:
+		val = intel_uncore_read(&i915->uncore,
 				SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);

-:80: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#80: FILE: drivers/gpu/drm/i915/intel_dram.c:244:
+		val = intel_uncore_read(&i915->uncore,
+				ADLS_MAD_INTER_CHANNEL_0_0_0_MCHBAR);

-:83: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#83: FILE: drivers/gpu/drm/i915/intel_dram.c:247:
+		val = intel_uncore_read(&i915->uncore,
 				SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN);

total: 0 errors, 0 warnings, 6 checks, 52 lines checked
e3638c808f9e drm/i915/adl_s: Re-use TGL GuC/HuC firmware
1a52773c70d3 drm/i915/display: Add HAS_D12_PLANE_MINIMIZATION
-:44: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#44: FILE: drivers/gpu/drm/i915/i915_drv.h:1768:
+#define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \
+					      IS_ALDERLAKE_S(dev_priv))

total: 0 errors, 0 warnings, 1 checks, 33 lines checked
8da8a7726ee0 drm/i915/adl_s: Update memory bandwidth parameters
7f707777a91f drm/i915/adl_s: Load DMC


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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Introduce Alderlake-S

[Patchwork]

== Series Details ==

Series: Introduce Alderlake-S
URL   : https://patchwork.freedesktop.org/series/82917/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_reset.c:1312:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:    expected void *in
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:    got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:    expected void const *src
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:    got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: warning: incorrect type in argument 2 (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:    expected void *in
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:    got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:    expected void const *src
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:    got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: warning: incorrect type in argument 2 (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:    expected unsigned int [usertype] *s
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:    got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: warning: incorrect type in argument 1 (different address spaces)
+drivers/gpu/drm/i915/gvt/mmio.c:290:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1440:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1494:15: warning: memset with byte count of 16777216
+./include/linux/seqlock.h:752:24: warning: trying to copy expression type 31
+./include/linux/seqlock.h:778:16: warning: trying to copy expression type 31
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block


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Re: [Intel-gfx] [PATCH 03/18] drm/i915/adl_s: Add PCH support

[Jani Nikula]

On Wed, 21 Oct 2020, Aditya Swarup <aditya.swarup@intel.com> wrote:
> From: Anusha Srivatsa <anusha.srivatsa@intel.com>
>
> Add support for Alderpoint(ADP) PCH used with Alderlake-S.
>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Caz Yokoyama <caz.yokoyama@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pch.c | 8 +++++++-
>  drivers/gpu/drm/i915/intel_pch.h | 3 +++
>  2 files changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c
> index f31c0dabd0cc..7fac9686a0c0 100644
> --- a/drivers/gpu/drm/i915/intel_pch.c
> +++ b/drivers/gpu/drm/i915/intel_pch.c
> @@ -128,6 +128,10 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
>  		drm_dbg_kms(&dev_priv->drm, "Found Jasper Lake PCH\n");
>  		drm_WARN_ON(&dev_priv->drm, !IS_JSL_EHL(dev_priv));
>  		return PCH_JSP;
> +	case INTEL_PCH_ADP_DEVICE_ID_TYPE:
> +		DRM_DEBUG_KMS("Found Alder Lake PCH\n");
> +		WARN_ON(!IS_ALDERLAKE_S(dev_priv));
> +		return PCH_ADP;

Please use drm_dbg_kms and drm_WARN_ON like above.

BR,
Jani.

>  	default:
>  		return PCH_NONE;
>  	}
> @@ -155,7 +159,9 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv)
>  	 * make an educated guess as to which PCH is really there.
>  	 */
>  
> -	if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv))
> +	if (IS_ALDERLAKE_S(dev_priv))
> +		id = INTEL_PCH_ADP_DEVICE_ID_TYPE;
> +	else if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv))
>  		id = INTEL_PCH_TGP_DEVICE_ID_TYPE;
>  	else if (IS_JSL_EHL(dev_priv))
>  		id = INTEL_PCH_MCC_DEVICE_ID_TYPE;
> diff --git a/drivers/gpu/drm/i915/intel_pch.h b/drivers/gpu/drm/i915/intel_pch.h
> index 06d2cd50af0b..7318377503b0 100644
> --- a/drivers/gpu/drm/i915/intel_pch.h
> +++ b/drivers/gpu/drm/i915/intel_pch.h
> @@ -26,6 +26,7 @@ enum intel_pch {
>  	PCH_JSP,	/* Jasper Lake PCH */
>  	PCH_MCC,        /* Mule Creek Canyon PCH */
>  	PCH_TGP,	/* Tiger Lake PCH */
> +	PCH_ADP,	/* Alder Lake PCH */
>  
>  	/* Fake PCHs, functionality handled on the same PCI dev */
>  	PCH_DG1 = 1024,
> @@ -53,12 +54,14 @@ enum intel_pch {
>  #define INTEL_PCH_TGP2_DEVICE_ID_TYPE		0x4380
>  #define INTEL_PCH_JSP_DEVICE_ID_TYPE		0x4D80
>  #define INTEL_PCH_JSP2_DEVICE_ID_TYPE		0x3880
> +#define INTEL_PCH_ADP_DEVICE_ID_TYPE		0x7A80
>  #define INTEL_PCH_P2X_DEVICE_ID_TYPE		0x7100
>  #define INTEL_PCH_P3X_DEVICE_ID_TYPE		0x7000
>  #define INTEL_PCH_QEMU_DEVICE_ID_TYPE		0x2900 /* qemu q35 has 2918 */
>  
>  #define INTEL_PCH_TYPE(dev_priv)		((dev_priv)->pch_type)
>  #define INTEL_PCH_ID(dev_priv)			((dev_priv)->pch_id)
> +#define HAS_PCH_ADP(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_ADP)
>  #define HAS_PCH_DG1(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_DG1)
>  #define HAS_PCH_JSP(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_JSP)
>  #define HAS_PCH_MCC(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_MCC)

-- 
Jani Nikula, Intel Open Source Graphics Center
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Re: [Intel-gfx] [PATCH 07/18] drm/i915/adl_s: Configure Port clock registers for ADL-S

[Jani Nikula]

On Wed, 21 Oct 2020, Aditya Swarup <aditya.swarup@intel.com> wrote:
> Add changes to configure port clock registers for ADL-S. Combo phy port
> clocks are configured by DPCLKA_CFGCR0 and DPCLKA_CFGCR1 registers.
>
> The DDI to internal clock mappings in DPCLKA_CFGCR0 register for ADL-S
> translates to
> DDI A -> DDIA
> DDI B -> USBC1
> DDI I -> USBC2
>
> For DPCLKA_CFGCR1
> DDI J -> USBC3
> DDI K -> USBC4
>
> Bspec: 50287
> Bspec: 53812
> Bspec: 53723
>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c     | 64 +++++++++++++-------
>  drivers/gpu/drm/i915/display/intel_display.c | 18 +++++-
>  drivers/gpu/drm/i915/i915_reg.h              | 25 +++++++-
>  3 files changed, 84 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 09811be08cfe..670be712f6ba 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2976,25 +2976,30 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
>  	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> -	u32 val;
> +	u32 val, mask, sel;
> +	i915_reg_t reg;
> +
> +	if (IS_ALDERLAKE_S(dev_priv)) {
> +		reg = ADLS_DPCLKA_CFGCR(phy);
> +		mask = ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy);
> +		sel = ((pll->info->id) << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy));
> +	} else if (IS_ROCKETLAKE(dev_priv)) {
> +		reg = ICL_DPCLKA_CFGCR0;
> +		mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> +		sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
> +	} else {
> +		reg = ICL_DPCLKA_CFGCR0;
> +		mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> +		sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
> +	}
>  
>  	mutex_lock(&dev_priv->dpll.lock);
>  
> -	val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
> +	val = intel_de_read(dev_priv, reg);
>  	drm_WARN_ON(&dev_priv->drm,
>  		    (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
>  
>  	if (intel_phy_is_combo(dev_priv, phy)) {
> -		u32 mask, sel;
> -
> -		if (IS_ROCKETLAKE(dev_priv)) {
> -			mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> -			sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
> -		} else {
> -			mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> -			sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
> -		}
> -
>  		/*
>  		 * Even though this register references DDIs, note that we
>  		 * want to pass the PHY rather than the port (DDI).  For
> @@ -3007,12 +3012,12 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
>  		 */
>  		val &= ~mask;
>  		val |= sel;
> -		intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
> -		intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0);
> +		intel_de_write(dev_priv, reg, val);
> +		intel_de_posting_read(dev_priv, reg);
>  	}
>  
>  	val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
> -	intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
> +	intel_de_write(dev_priv, reg, val);
>  
>  	mutex_unlock(&dev_priv->dpll.lock);
>  }
> @@ -3025,9 +3030,17 @@ static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
>  
>  	mutex_lock(&dev_priv->dpll.lock);
>  
> -	val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
> +	if (IS_ALDERLAKE_S(dev_priv))
> +		val = intel_de_read(dev_priv, ADLS_DPCLKA_CFGCR(phy));
> +	else
> +		val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
> +
>  	val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
> -	intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
> +
> +	if (IS_ALDERLAKE_S(dev_priv))
> +		intel_de_write(dev_priv, ADLS_DPCLKA_CFGCR(phy), val);
> +	else
> +		intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
>  
>  	mutex_unlock(&dev_priv->dpll.lock);
>  }
> @@ -3036,13 +3049,19 @@ static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
>  				      u32 port_mask, bool ddi_clk_needed)
>  {
>  	enum port port;
> +	bool ddi_clk_off;
>  	u32 val;
>  
> -	val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
>  	for_each_port_masked(port, port_mask) {
>  		enum phy phy = intel_port_to_phy(dev_priv, port);
> -		bool ddi_clk_off = val & icl_dpclka_cfgcr0_clk_off(dev_priv,
> -								   phy);
> +
> +		if (IS_ALDERLAKE_S(dev_priv))
> +			val = intel_de_read(dev_priv, ADLS_DPCLKA_CFGCR(phy));
> +		else
> +			val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
> +
> +		ddi_clk_off = val & icl_dpclka_cfgcr0_clk_off(dev_priv,
> +							      phy);
>  
>  		if (ddi_clk_needed == !ddi_clk_off)
>  			continue;
> @@ -3058,7 +3077,10 @@ static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
>  			   "PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
>  			   phy_name(phy));
>  		val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
> -		intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
> +		if (IS_ALDERLAKE_S(dev_priv))
> +			intel_de_write(dev_priv, ADLS_DPCLKA_CFGCR(phy), val);
> +		else
> +			intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
>  	}
>  }
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 70ca5d2e5b0a..b3714ed00786 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -10958,6 +10958,20 @@ static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
>  	icl_set_active_port_dpll(pipe_config, port_dpll_id);
>  }
>  
> +static void adls_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
> +			     struct intel_crtc_state *pipe_config)
> +{
> +	enum phy phy = intel_port_to_phy(dev_priv, port);
> +	enum intel_dpll_id id;
> +	u32 val;
> +
> +	val = I915_READ(ADLS_DPCLKA_CFGCR(phy));

Please use intel_de_read().

BR,
Jani.

> +	val &= ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy);
> +	id = val >> ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy);
> +
> +	pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
> +}
> +
>  static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
>  				enum port port,
>  				struct intel_crtc_state *pipe_config)
> @@ -11205,7 +11219,9 @@ static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
>  			port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
>  	}
>  
> -	if (INTEL_GEN(dev_priv) >= 11)
> +	if (IS_ALDERLAKE_S(dev_priv))
> +		adls_get_ddi_pll(dev_priv, port, pipe_config);
> +	else if (INTEL_GEN(dev_priv) >= 11)
>  		icl_get_ddi_pll(dev_priv, port, pipe_config);
>  	else if (IS_CANNONLAKE(dev_priv))
>  		cnl_get_ddi_pll(dev_priv, port, pipe_config);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e617d24a2912..604fce828a7d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -230,12 +230,14 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  #define _TRANS(tran, a, b)		_PICK_EVEN(tran, a, b)
>  #define _PORT(port, a, b)		_PICK_EVEN(port, a, b)
>  #define _PLL(pll, a, b)			_PICK_EVEN(pll, a, b)
> +#define _PHY(phy, a, b)                 _PICK_EVEN(phy, a, b)
>  
>  #define _MMIO_PIPE(pipe, a, b)		_MMIO(_PIPE(pipe, a, b))
>  #define _MMIO_PLANE(plane, a, b)	_MMIO(_PLANE(plane, a, b))
>  #define _MMIO_TRANS(tran, a, b)		_MMIO(_TRANS(tran, a, b))
>  #define _MMIO_PORT(port, a, b)		_MMIO(_PORT(port, a, b))
>  #define _MMIO_PLL(pll, a, b)		_MMIO(_PLL(pll, a, b))
> +#define _MMIO_PHY(phy, a, b)            _MMIO(_PHY(phy, a, b))
>  
>  #define _PHY3(phy, ...)			_PICK(phy, __VA_ARGS__)
>  
> @@ -10297,7 +10299,7 @@ enum skl_power_gate {
>  #define  DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port)	((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
>  
>  #define ICL_DPCLKA_CFGCR0			_MMIO(0x164280)
> -#define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)	(1 << _PICK(phy, 10, 11, 24))
> +#define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)	(1 << _PICK(phy, 10, 11, 24, 4, 5))
>  #define  RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)	REG_BIT((phy) + 10)
>  #define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)	(1 << ((tc_port) < PORT_TC4 ? \
>  						       (tc_port) + 12 : \
> @@ -10311,6 +10313,27 @@ enum skl_power_gate {
>  #define  RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \
>  	((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
>  
> +/* ADLS Clocks */
> +#define _ADLS_DPCLKA_CFGCR0			0x164280
> +#define _ADLS_DPCLKA_CFGCR1			0x1642BC
> +#define ADLS_DPCLKA_CFGCR(phy)			_MMIO_PHY((phy) / 3, \
> +							  _ADLS_DPCLKA_CFGCR0, \
> +							  _ADLS_DPCLKA_CFGCR1)
> +#define  ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)		(((phy) % 3) * 2)
> +/* ADLS DPCLKA_CFGCR0 DDI mask */
> +#define  ADLS_DPCLKA_DDII_SEL_MASK			REG_GENMASK(5, 4)
> +#define  ADLS_DPCLKA_DDIB_SEL_MASK			REG_GENMASK(3, 2)
> +#define  ADLS_DPCLKA_DDIA_SEL_MASK			REG_GENMASK(1, 0)
> +/* ADLS DPCLKA_CFGCR1 DDI mask */
> +#define  ADLS_DPCLKA_DDIK_SEL_MASK			REG_GENMASK(3, 2)
> +#define  ADLS_DPCLKA_DDIJ_SEL_MASK			REG_GENMASK(1, 0)
> +#define  ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy)	_PICK((phy), \
> +							ADLS_DPCLKA_DDIA_SEL_MASK, \
> +							ADLS_DPCLKA_DDIB_SEL_MASK, \
> +							ADLS_DPCLKA_DDII_SEL_MASK, \
> +							ADLS_DPCLKA_DDIJ_SEL_MASK, \
> +							ADLS_DPCLKA_DDIK_SEL_MASK)
> +
>  /* CNL PLL */
>  #define DPLL0_ENABLE		0x46010
>  #define DPLL1_ENABLE		0x46014

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.BAT: success for Introduce Alderlake-S

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 5351 bytes --]

== Series Details ==

Series: Introduce Alderlake-S
URL   : https://patchwork.freedesktop.org/series/82917/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9176 -> Patchwork_18752
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18752/index.html

Known issues
------------

  Here are the changes found in Patchwork_18752 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_hotunplug@unbind-rebind:
    - fi-icl-y:           [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9176/fi-icl-y/igt@core_hotunplug@unbind-rebind.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18752/fi-icl-y/igt@core_hotunplug@unbind-rebind.html

  * igt@i915_module_load@reload:
    - fi-tgl-u2:          [PASS][3] -> [DMESG-WARN][4] ([i915#1982] / [k.org#205379])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9176/fi-tgl-u2/igt@i915_module_load@reload.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18752/fi-tgl-u2/igt@i915_module_load@reload.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - fi-icl-u2:          [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) +1 similar issue
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9176/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18752/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  
#### Possible fixes ####

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - fi-byt-j1900:       [DMESG-WARN][7] ([i915#1982]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9176/fi-byt-j1900/igt@i915_pm_rpm@basic-pci-d3-state.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18752/fi-byt-j1900/igt@i915_pm_rpm@basic-pci-d3-state.html

  * igt@kms_chamelium@hdmi-crc-fast:
    - fi-kbl-7500u:       [DMESG-WARN][9] ([i915#1982] / [i915#2203]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9176/fi-kbl-7500u/igt@kms_chamelium@hdmi-crc-fast.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18752/fi-kbl-7500u/igt@kms_chamelium@hdmi-crc-fast.html

  * igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
    - fi-icl-u2:          [DMESG-WARN][11] ([i915#1982]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9176/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18752/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html

  
#### Warnings ####

  * igt@kms_chamelium@dp-crc-fast:
    - fi-kbl-7500u:       [DMESG-FAIL][13] ([i915#165] / [i915#262]) -> [FAIL][14] ([i915#1161] / [i915#262])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9176/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18752/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html

  
  [i915#1161]: https://gitlab.freedesktop.org/drm/intel/issues/1161
  [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
  [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
  [k.org#205379]: https://bugzilla.kernel.org/show_bug.cgi?id=205379


Participating hosts (45 -> 38)
------------------------------

  Missing    (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_9176 -> Patchwork_18752

  CI-20190529: 20190529
  CI_DRM_9176: e3d4f747f53899164788f2008a16c82d236b762a @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5822: b4bcf05cb9839037128905deda7146434155cc41 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_18752: 7f707777a91f136fa59c8f7e7eba97763039758c @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

7f707777a91f drm/i915/adl_s: Load DMC
8da8a7726ee0 drm/i915/adl_s: Update memory bandwidth parameters
1a52773c70d3 drm/i915/display: Add HAS_D12_PLANE_MINIMIZATION
e3638c808f9e drm/i915/adl_s: Re-use TGL GuC/HuC firmware
f3ca8144e558 drm/i915/adl_s: MCHBAR memory info registers are moved
1ad9fe655cde drm/i915/adl_s: Add display, gt, ctx and ADL-S whitelist WA
9f3a0b45ebec drm/i915/adl_s: Update PHY_MISC programming
7fe0b1ea22d2 drm/i915/adl_s: Update combo PHY master/slave relationships
5e3a85cbe54a drm/i915/adl_s: Add vbt port and aux channel settings for adls
adec6f0e64aa drm/i915/adl_s: Add adl-s ddc pin mapping
919fedfd3bf3 drm/i915/adl_s: Setup display outputs and HTI support for ADL-S
cf0751c1b462 drm/i915/adl_s: Configure Port clock registers for ADL-S
eec312e2d54c drm/i915/adl_s: Configure DPLL for ADL-S
8426881fd08d drm/i915/adl_s: Add PHYs for Alderlake S
0cdf50266822 drm/i915/adl_s: Add Interrupt Support
9541e1b5d9c5 drm/i915/adl_s: Add PCH support
3f14bf129a7d x86/gpu: add ADL_S stolen memory support
37adab61ebad drm/i915/adl_s: Add ADL-S platform info and PCI ids

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18752/index.html

[-- Attachment #1.2: Type: text/html, Size: 6612 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.IGT: failure for Introduce Alderlake-S

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 15229 bytes --]

== Series Details ==

Series: Introduce Alderlake-S
URL   : https://patchwork.freedesktop.org/series/82917/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9176_full -> Patchwork_18752_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_18752_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_18752_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_18752_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_sequence@queue-busy:
    - shard-skl:          [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9176/shard-skl2/igt@kms_sequence@queue-busy.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18752/shard-skl2/igt@kms_sequence@queue-busy.html

  
Known issues
------------

  Here are the changes found in Patchwork_18752_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_reloc@basic-many-active@vecs0:
    - shard-glk:          [PASS][3] -> [FAIL][4] ([i915#2389]) +2 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9176/shard-glk3/igt@gem_exec_reloc@basic-many-active@vecs0.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18752/shard-glk4/igt@gem_exec_reloc@basic-many-active@vecs0.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-apl:          [PASS][5] -> [DMESG-WARN][6] ([i915#1436] / [i915#1635] / [i915#716])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9176/shard-apl2/igt@gen9_exec_parse@allowed-all.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18752/shard-apl1/igt@gen9_exec_parse@allowed-all.html

  * igt@i915_suspend@debugfs-reader:
    - shard-kbl:          [PASS][7] -> [INCOMPLETE][8] ([i915#155])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9176/shard-kbl1/igt@i915_suspend@debugfs-reader.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18752/shard-kbl4/igt@i915_suspend@debugfs-reader.html

  * igt@kms_cursor_edge_walk@pipe-b-128x128-top-edge:
    - shard-glk:          [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) +1 similar issue
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9176/shard-glk1/igt@kms_cursor_edge_walk@pipe-b-128x128-top-edge.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18752/shard-glk5/igt@kms_cursor_edge_walk@pipe-b-128x128-top-edge.html

  * igt@kms_cursor_edge_walk@pipe-b-256x256-right-edge:
    - shard-skl:          [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) +6 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9176/shard-skl5/igt@kms_cursor_edge_walk@pipe-b-256x256-right-edge.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18752/shard-skl6/igt@kms_cursor_edge_walk@pipe-b-256x256-right-edge.html

  * igt@kms_flip@flip-vs-expired-vblank@c-edp1:
    - shard-skl:          [PASS][13] -> [FAIL][14] ([i915#79])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9176/shard-skl1/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18752/shard-skl5/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html

  * igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a1:
    - shard-glk:          [PASS][15] -> [FAIL][16] ([i915#79])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9176/shard-glk8/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a1.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18752/shard-glk9/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a1.html

  * igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary:
    - shard-tglb:         [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) +1 similar issue
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9176/shard-tglb3/igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18752/shard-tglb6/igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary.html
    - shard-kbl:          [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) +1 similar issue
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9176/shard-kbl1/igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18752/shard-kbl4/igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary.html

  * igt@kms_hdr@bpc-switch:
    - shard-skl:          [PASS][21] -> [FAIL][22] ([i915#1188])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9176/shard-skl4/igt@kms_hdr@bpc-switch.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18752/shard-skl4/igt@kms_hdr@bpc-switch.html

  * igt@kms_psr2_su@page_flip:
    - shard-iclb:         [PASS][23] -> [SKIP][24] ([fdo#109642] / [fdo#111068])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9176/shard-iclb2/igt@kms_psr2_su@page_flip.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18752/shard-iclb3/igt@kms_psr2_su@page_flip.html

  * igt@kms_psr@psr2_sprite_mmap_gtt:
    - shard-iclb:         [PASS][25] -> [SKIP][26] ([fdo#109441]) +1 similar issue
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9176/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18752/shard-iclb1/igt@kms_psr@psr2_sprite_mmap_gtt.html

  * igt@perf@polling:
    - shard-hsw:          [PASS][27] -> [SKIP][28] ([fdo#109271])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9176/shard-hsw7/igt@perf@polling.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18752/shard-hsw1/igt@perf@polling.html

  
#### Possible fixes ####

  * igt@device_reset@unbind-reset-rebind:
    - shard-iclb:         [DMESG-WARN][29] ([i915#1982]) -> [PASS][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9176/shard-iclb6/igt@device_reset@unbind-reset-rebind.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18752/shard-iclb1/igt@device_reset@unbind-reset-rebind.html

  * igt@feature_discovery@psr2:
    - shard-iclb:         [SKIP][31] ([i915#658]) -> [PASS][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9176/shard-iclb4/igt@feature_discovery@psr2.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18752/shard-iclb2/igt@feature_discovery@psr2.html

  * igt@gem_eio@in-flight-contexts-10ms:
    - shard-skl:          [INCOMPLETE][33] ([i915#1909]) -> [PASS][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9176/shard-skl1/igt@gem_eio@in-flight-contexts-10ms.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18752/shard-skl3/igt@gem_eio@in-flight-contexts-10ms.html

  * igt@gem_exec_flush@basic-wb-prw-default:
    - shard-skl:          [DMESG-WARN][35] ([i915#1982]) -> [PASS][36] +7 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9176/shard-skl4/igt@gem_exec_flush@basic-wb-prw-default.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18752/shard-skl4/igt@gem_exec_flush@basic-wb-prw-default.html

  * igt@kms_cursor_crc@pipe-c-cursor-128x128-onscreen:
    - shard-skl:          [FAIL][37] ([i915#54]) -> [PASS][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9176/shard-skl9/igt@kms_cursor_crc@pipe-c-cursor-128x128-onscreen.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18752/shard-skl3/igt@kms_cursor_crc@pipe-c-cursor-128x128-onscreen.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-skl:          [FAIL][39] ([i915#2346]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9176/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18752/shard-skl9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_flip@2x-plain-flip-ts-check@bc-vga1-hdmi-a1:
    - shard-hsw:          [INCOMPLETE][41] -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9176/shard-hsw2/igt@kms_flip@2x-plain-flip-ts-check@bc-vga1-hdmi-a1.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18752/shard-hsw8/igt@kms_flip@2x-plain-flip-ts-check@bc-vga1-hdmi-a1.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1:
    - shard-skl:          [FAIL][43] ([i915#2122]) -> [PASS][44] +2 similar issues
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9176/shard-skl3/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18752/shard-skl6/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html

  * igt@kms_frontbuffer_tracking@fbc-stridechange:
    - shard-tglb:         [DMESG-WARN][45] ([i915#1982]) -> [PASS][46] +1 similar issue
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9176/shard-tglb2/igt@kms_frontbuffer_tracking@fbc-stridechange.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18752/shard-tglb8/igt@kms_frontbuffer_tracking@fbc-stridechange.html
    - shard-glk:          [DMESG-WARN][47] ([i915#1982]) -> [PASS][48] +1 similar issue
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9176/shard-glk7/igt@kms_frontbuffer_tracking@fbc-stridechange.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18752/shard-glk4/igt@kms_frontbuffer_tracking@fbc-stridechange.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-skl:          [FAIL][49] ([i915#1188]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9176/shard-skl5/igt@kms_hdr@bpc-switch-dpms.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18752/shard-skl6/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [FAIL][51] ([fdo#108145] / [i915#265]) -> [PASS][52] +1 similar issue
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9176/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18752/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_psr@psr2_cursor_plane_move:
    - shard-iclb:         [SKIP][53] ([fdo#109441]) -> [PASS][54] +1 similar issue
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9176/shard-iclb4/igt@kms_psr@psr2_cursor_plane_move.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18752/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html

  * igt@perf@polling-parameterized:
    - shard-skl:          [FAIL][55] ([i915#1542]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9176/shard-skl9/igt@perf@polling-parameterized.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18752/shard-skl5/igt@perf@polling-parameterized.html

  
#### Warnings ####

  * igt@core_hotunplug@hotrebind-lateclose:
    - shard-hsw:          [FAIL][57] -> [WARN][58] ([i915#2283])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9176/shard-hsw7/igt@core_hotunplug@hotrebind-lateclose.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18752/shard-hsw1/igt@core_hotunplug@hotrebind-lateclose.html

  * igt@kms_frontbuffer_tracking@fbcpsr-suspend:
    - shard-tglb:         [DMESG-WARN][59] ([i915#2411]) -> [DMESG-WARN][60] ([i915#1982] / [i915#2411])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9176/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18752/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
    - shard-tglb:         [INCOMPLETE][61] ([i915#2411] / [i915#456]) -> [DMESG-WARN][62] ([i915#2411])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9176/shard-tglb1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18752/shard-tglb8/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html

  * igt@runner@aborted:
    - shard-skl:          [FAIL][63] ([i915#1436] / [i915#1814] / [i915#2439]) -> [FAIL][64] ([i915#1436])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9176/shard-skl1/igt@runner@aborted.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18752/shard-skl4/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
  [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
  [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
  [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
  [i915#1909]: https://gitlab.freedesktop.org/drm/intel/issues/1909
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
  [i915#2283]: https://gitlab.freedesktop.org/drm/intel/issues/2283
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389
  [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
  [i915#2439]: https://gitlab.freedesktop.org/drm/intel/issues/2439
  [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456
  [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79


Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * Linux: CI_DRM_9176 -> Patchwork_18752

  CI-20190529: 20190529
  CI_DRM_9176: e3d4f747f53899164788f2008a16c82d236b762a @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5822: b4bcf05cb9839037128905deda7146434155cc41 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_18752: 7f707777a91f136fa59c8f7e7eba97763039758c @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18752/index.html

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Re: [Intel-gfx] [PATCH 04/18] drm/i915/adl_s: Add Interrupt Support

[Lucas De Marchi]

On Wed, Oct 21, 2020 at 06:31:59AM -0700, Aditya Swarup wrote:
>From: Anusha Srivatsa <anusha.srivatsa@intel.com>
>
>ADLS follows ICP/TGP like interrupts. Reuse hpd_icp and introduce
>ADLS DDI and HPD masks for setting up hpd interrupts.
>
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>Cc: Jani Nikula <jani.nikula@intel.com>
>Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>Cc: Imre Deak <imre.deak@intel.com>
>Cc: Matt Roper <matthew.d.roper@intel.com>
>Cc: José Roberto de Souza <jose.souza@intel.com>
>Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
>---
> drivers/gpu/drm/i915/i915_irq.c | 20 ++++++++++++++++----
> drivers/gpu/drm/i915/i915_reg.h |  3 +++
> 2 files changed, 19 insertions(+), 4 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>index b753c77c9a77..9033221995ad 100644
>--- a/drivers/gpu/drm/i915/i915_irq.c
>+++ b/drivers/gpu/drm/i915/i915_irq.c
>@@ -179,8 +179,9 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)

you still need to assign hpd_pin to do the mapping between port and hpd
pin. Earlier this was done in the irq handler itself, but now is done in
intel_ddi_init(). See what I did for DG1:
https://patchwork.freedesktop.org/patch/396062/?series=82905&rev=1

Lucas De Marchi

> 	if (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))
> 		return;
>
>-	if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv) ||
>-	    HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv))
>+	if (HAS_PCH_ADP(dev_priv) || HAS_PCH_TGP(dev_priv) ||
>+	    HAS_PCH_JSP(dev_priv) || HAS_PCH_ICP(dev_priv) ||
>+	    HAS_PCH_MCC(dev_priv))
> 		hpd->pch_hpd = hpd_icp;
> 	else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv))
> 		hpd->pch_hpd = hpd_spt;
>@@ -1864,7 +1865,10 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
> 	u32 ddi_hotplug_trigger, tc_hotplug_trigger;
> 	u32 pin_mask = 0, long_mask = 0;
>
>-	if (HAS_PCH_TGP(dev_priv)) {
>+	if (IS_ALDERLAKE_S(dev_priv)) {
>+		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ADLS;
>+		tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
>+	} else if (HAS_PCH_TGP(dev_priv)) {
> 		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
> 		tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
> 	} else if (HAS_PCH_JSP(dev_priv)) {
>@@ -3252,6 +3256,12 @@ static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv)
> 			  TGP_DDI_HPD_ENABLE_MASK, 0);
> }
>
>+static void adls_hpd_irq_setup(struct drm_i915_private *dev_priv)
>+{
>+	icp_hpd_irq_setup(dev_priv,
>+			  ADLS_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE_MASK);
>+}
>+
> static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
> {
> 	u32 hotplug;
>@@ -4162,7 +4172,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
> 		if (I915_HAS_HOTPLUG(dev_priv))
> 			dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
> 	} else {
>-		if (HAS_PCH_JSP(dev_priv))
>+		if (IS_ALDERLAKE_S(dev_priv))
>+			dev_priv->display.hpd_irq_setup = adls_hpd_irq_setup;
>+		else if (HAS_PCH_JSP(dev_priv))
> 			dev_priv->display.hpd_irq_setup = jsp_hpd_irq_setup;
> 		else if (HAS_PCH_MCC(dev_priv))
> 			dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup;
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 83ddea1cd174..f6b844ca7a9f 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -8343,6 +8343,7 @@ enum {
> 					 SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
> 					 SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
> 					 SDE_TC_HOTPLUG_ICP(PORT_TC1))
>+#define SDE_DDI_MASK_ADLS		 SDE_DDI_HOTPLUG_ICP(PORT_A)
>
> #define SDEISR  _MMIO(0xc4000)
> #define SDEIMR  _MMIO(0xc4004)
>@@ -8438,6 +8439,8 @@ enum {
> 					 ICP_TC_HPD_ENABLE(PORT_TC5) | \
> 					 ICP_TC_HPD_ENABLE_MASK)
>
>+#define ADLS_DDI_HPD_ENABLE_MASK	 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A)
>+
> #define _PCH_DPLL_A              0xc6014
> #define _PCH_DPLL_B              0xc6018
> #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
>-- 
>2.27.0
>
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Re: [Intel-gfx] [PATCH 02/18] x86/gpu: add ADL_S stolen memory support

[Matt Roper]

On Wed, Oct 21, 2020 at 06:31:57AM -0700, Aditya Swarup wrote:
> From: Caz Yokoyama <caz.yokoyama@intel.com>
> 
> ADL_S re-uses the same stolen memory registers as TGL and ICL.
> 
> Bspec: 52055
> Bspec: 49589
> Bspec: 49636
> 
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Caz Yokoyama <caz.yokoyama@intel.com>
> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>

I think you need to Cc the x86 maintainers on this patch and get their
ack to merge it through the i915 tree.


Matt

> ---
>  arch/x86/kernel/early-quirks.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
> index a4b5af03dcc1..6edd1e2ee8af 100644
> --- a/arch/x86/kernel/early-quirks.c
> +++ b/arch/x86/kernel/early-quirks.c
> @@ -551,6 +551,7 @@ static const struct pci_device_id intel_early_ids[] __initconst = {
>  	INTEL_EHL_IDS(&gen11_early_ops),
>  	INTEL_TGL_12_IDS(&gen11_early_ops),
>  	INTEL_RKL_IDS(&gen11_early_ops),
> +	INTEL_ADLS_IDS(&gen11_early_ops),
>  };
>  
>  struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0, 0);
> -- 
> 2.27.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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Re: [Intel-gfx] [PATCH 02/18] x86/gpu: add ADL_S stolen memory support

[Lucas De Marchi]

On Wed, Oct 21, 2020 at 01:43:42PM -0700, Matt Roper wrote:
>On Wed, Oct 21, 2020 at 06:31:57AM -0700, Aditya Swarup wrote:
>> From: Caz Yokoyama <caz.yokoyama@intel.com>
>>
>> ADL_S re-uses the same stolen memory registers as TGL and ICL.
>>
>> Bspec: 52055
>> Bspec: 49589
>> Bspec: 49636
>>
>> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> Cc: Jani Nikula <jani.nikula@intel.com>
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Cc: Imre Deak <imre.deak@intel.com>
>> Signed-off-by: Caz Yokoyama <caz.yokoyama@intel.com>
>> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
>
>I think you need to Cc the x86 maintainers on this patch and get their
>ack to merge it through the i915 tree.

Yeah, but make sure to mention the dependency on the first patch so they
don't try to apply and get a build error. See
https://lore.kernel.org/intel-gfx/alpine.DEB.2.21.1907170845470.1767@nanos.tec.linutronix.de/

Also see https://lore.kernel.org/intel-gfx/20200520093025.GD1457@zn.tnic/

For the patch itself,

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

thanks
Lucas De Marchi

>
>
>Matt
>
>> ---
>>  arch/x86/kernel/early-quirks.c | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
>> index a4b5af03dcc1..6edd1e2ee8af 100644
>> --- a/arch/x86/kernel/early-quirks.c
>> +++ b/arch/x86/kernel/early-quirks.c
>> @@ -551,6 +551,7 @@ static const struct pci_device_id intel_early_ids[] __initconst = {
>>  	INTEL_EHL_IDS(&gen11_early_ops),
>>  	INTEL_TGL_12_IDS(&gen11_early_ops),
>>  	INTEL_RKL_IDS(&gen11_early_ops),
>> +	INTEL_ADLS_IDS(&gen11_early_ops),
>>  };
>>
>>  struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0, 0);
>> --
>> 2.27.0
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>-- 
>Matt Roper
>Graphics Software Engineer
>VTT-OSGC Platform Enablement
>Intel Corporation
>(916) 356-2795
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Re: [Intel-gfx] [PATCH 04/18] drm/i915/adl_s: Add Interrupt Support

[Aditya Swarup]

On 10/21/20 10:28 AM, Lucas De Marchi wrote:
> On Wed, Oct 21, 2020 at 06:31:59AM -0700, Aditya Swarup wrote:
>> From: Anusha Srivatsa <anusha.srivatsa@intel.com>
>>
>> ADLS follows ICP/TGP like interrupts. Reuse hpd_icp and introduce
>> ADLS DDI and HPD masks for setting up hpd interrupts.
>>
>> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>> Cc: Jani Nikula <jani.nikula@intel.com>
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Cc: Imre Deak <imre.deak@intel.com>
>> Cc: Matt Roper <matthew.d.roper@intel.com>
>> Cc: José Roberto de Souza <jose.souza@intel.com>
>> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_irq.c | 20 ++++++++++++++++----
>> drivers/gpu/drm/i915/i915_reg.h |  3 +++
>> 2 files changed, 19 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>> index b753c77c9a77..9033221995ad 100644
>> --- a/drivers/gpu/drm/i915/i915_irq.c
>> +++ b/drivers/gpu/drm/i915/i915_irq.c
>> @@ -179,8 +179,9 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
> 
> you still need to assign hpd_pin to do the mapping between port and hpd
> pin. Earlier this was done in the irq handler itself, but now is done in
> intel_ddi_init(). See what I did for DG1:
> https://patchwork.freedesktop.org/patch/396062/?series=82905&rev=1

I don't think that is required as for all Gen12+ platforms, tgl_hpd_pin is used for assignment
and the logic works for adl-s with PORT A mapping staying the same and for ports greater than
PORT D, HPD_PORT_TC1 is used as starting offset.

From intel_ddi_init()
else if (INTEL_GEN(dev_priv) >= 12)
                encoder->hpd_pin = tgl_hpd_pin(dev_priv, port);

Also, I have tested this code wrt hotplugs on the system and it works for all ports.

Regards,
Aditya Swarup
> 
> Lucas De Marchi
> 
>>     if (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))
>>         return;
>>
>> -    if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv) ||
>> -        HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv))
>> +    if (HAS_PCH_ADP(dev_priv) || HAS_PCH_TGP(dev_priv) ||
>> +        HAS_PCH_JSP(dev_priv) || HAS_PCH_ICP(dev_priv) ||
>> +        HAS_PCH_MCC(dev_priv))
>>         hpd->pch_hpd = hpd_icp;
>>     else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv))
>>         hpd->pch_hpd = hpd_spt;
>> @@ -1864,7 +1865,10 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
>>     u32 ddi_hotplug_trigger, tc_hotplug_trigger;
>>     u32 pin_mask = 0, long_mask = 0;
>>
>> -    if (HAS_PCH_TGP(dev_priv)) {
>> +    if (IS_ALDERLAKE_S(dev_priv)) {
>> +        ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ADLS;
>> +        tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
>> +    } else if (HAS_PCH_TGP(dev_priv)) {
>>         ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
>>         tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
>>     } else if (HAS_PCH_JSP(dev_priv)) {
>> @@ -3252,6 +3256,12 @@ static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv)
>>               TGP_DDI_HPD_ENABLE_MASK, 0);
>> }
>>
>> +static void adls_hpd_irq_setup(struct drm_i915_private *dev_priv)
>> +{
>> +    icp_hpd_irq_setup(dev_priv,
>> +              ADLS_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE_MASK);
>> +}
>> +
>> static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
>> {
>>     u32 hotplug;
>> @@ -4162,7 +4172,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>>         if (I915_HAS_HOTPLUG(dev_priv))
>>             dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
>>     } else {
>> -        if (HAS_PCH_JSP(dev_priv))
>> +        if (IS_ALDERLAKE_S(dev_priv))
>> +            dev_priv->display.hpd_irq_setup = adls_hpd_irq_setup;
>> +        else if (HAS_PCH_JSP(dev_priv))
>>             dev_priv->display.hpd_irq_setup = jsp_hpd_irq_setup;
>>         else if (HAS_PCH_MCC(dev_priv))
>>             dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup;
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 83ddea1cd174..f6b844ca7a9f 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -8343,6 +8343,7 @@ enum {
>>                      SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
>>                      SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
>>                      SDE_TC_HOTPLUG_ICP(PORT_TC1))
>> +#define SDE_DDI_MASK_ADLS         SDE_DDI_HOTPLUG_ICP(PORT_A)
>>
>> #define SDEISR  _MMIO(0xc4000)
>> #define SDEIMR  _MMIO(0xc4004)
>> @@ -8438,6 +8439,8 @@ enum {
>>                      ICP_TC_HPD_ENABLE(PORT_TC5) | \
>>                      ICP_TC_HPD_ENABLE_MASK)
>>
>> +#define ADLS_DDI_HPD_ENABLE_MASK     SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A)
>> +
>> #define _PCH_DPLL_A              0xc6014
>> #define _PCH_DPLL_B              0xc6018
>> #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
>> -- 
>> 2.27.0
>>

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Re: [Intel-gfx] [PATCH 04/18] drm/i915/adl_s: Add Interrupt Support

[Lucas De Marchi]

On Thu, Oct 22, 2020 at 04:26:15PM -0700, Aditya Swarup wrote:
>On 10/21/20 10:28 AM, Lucas De Marchi wrote:
>> On Wed, Oct 21, 2020 at 06:31:59AM -0700, Aditya Swarup wrote:
>>> From: Anusha Srivatsa <anusha.srivatsa@intel.com>
>>>
>>> ADLS follows ICP/TGP like interrupts. Reuse hpd_icp and introduce
>>> ADLS DDI and HPD masks for setting up hpd interrupts.
>>>
>>> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>>> Cc: Jani Nikula <jani.nikula@intel.com>
>>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>> Cc: Imre Deak <imre.deak@intel.com>
>>> Cc: Matt Roper <matthew.d.roper@intel.com>
>>> Cc: José Roberto de Souza <jose.souza@intel.com>
>>> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>>> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/i915_irq.c | 20 ++++++++++++++++----
>>> drivers/gpu/drm/i915/i915_reg.h |  3 +++
>>> 2 files changed, 19 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>>> index b753c77c9a77..9033221995ad 100644
>>> --- a/drivers/gpu/drm/i915/i915_irq.c
>>> +++ b/drivers/gpu/drm/i915/i915_irq.c
>>> @@ -179,8 +179,9 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
>>
>> you still need to assign hpd_pin to do the mapping between port and hpd
>> pin. Earlier this was done in the irq handler itself, but now is done in
>> intel_ddi_init(). See what I did for DG1:
>> https://patchwork.freedesktop.org/patch/396062/?series=82905&rev=1
>
>I don't think that is required as for all Gen12+ platforms, tgl_hpd_pin is used for assignment
>and the logic works for adl-s with PORT A mapping staying the same and for ports greater than
>PORT D, HPD_PORT_TC1 is used as starting offset.
>
>From intel_ddi_init()
>else if (INTEL_GEN(dev_priv) >= 12)
>                encoder->hpd_pin = tgl_hpd_pin(dev_priv, port);

right... this is not like rkl/dg1 in which the hpd doesn't match the
port.

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

>
>Also, I have tested this code wrt hotplugs on the system and it works for all ports.
>
>Regards,
>Aditya Swarup
>>
>> Lucas De Marchi
>>
>>>     if (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))
>>>         return;
>>>
>>> -    if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv) ||
>>> -        HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv))
>>> +    if (HAS_PCH_ADP(dev_priv) || HAS_PCH_TGP(dev_priv) ||
>>> +        HAS_PCH_JSP(dev_priv) || HAS_PCH_ICP(dev_priv) ||
>>> +        HAS_PCH_MCC(dev_priv))
>>>         hpd->pch_hpd = hpd_icp;
>>>     else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv))
>>>         hpd->pch_hpd = hpd_spt;
>>> @@ -1864,7 +1865,10 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
>>>     u32 ddi_hotplug_trigger, tc_hotplug_trigger;
>>>     u32 pin_mask = 0, long_mask = 0;
>>>
>>> -    if (HAS_PCH_TGP(dev_priv)) {
>>> +    if (IS_ALDERLAKE_S(dev_priv)) {
>>> +        ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ADLS;
>>> +        tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
>>> +    } else if (HAS_PCH_TGP(dev_priv)) {
>>>         ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
>>>         tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
>>>     } else if (HAS_PCH_JSP(dev_priv)) {
>>> @@ -3252,6 +3256,12 @@ static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv)
>>>               TGP_DDI_HPD_ENABLE_MASK, 0);
>>> }
>>>
>>> +static void adls_hpd_irq_setup(struct drm_i915_private *dev_priv)
>>> +{
>>> +    icp_hpd_irq_setup(dev_priv,
>>> +              ADLS_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE_MASK);
>>> +}
>>> +
>>> static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
>>> {
>>>     u32 hotplug;
>>> @@ -4162,7 +4172,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>>>         if (I915_HAS_HOTPLUG(dev_priv))
>>>             dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
>>>     } else {
>>> -        if (HAS_PCH_JSP(dev_priv))
>>> +        if (IS_ALDERLAKE_S(dev_priv))
>>> +            dev_priv->display.hpd_irq_setup = adls_hpd_irq_setup;
>>> +        else if (HAS_PCH_JSP(dev_priv))
>>>             dev_priv->display.hpd_irq_setup = jsp_hpd_irq_setup;
>>>         else if (HAS_PCH_MCC(dev_priv))
>>>             dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup;
>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>> index 83ddea1cd174..f6b844ca7a9f 100644
>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>> @@ -8343,6 +8343,7 @@ enum {
>>>                      SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
>>>                      SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
>>>                      SDE_TC_HOTPLUG_ICP(PORT_TC1))
>>> +#define SDE_DDI_MASK_ADLS         SDE_DDI_HOTPLUG_ICP(PORT_A)
>>>
>>> #define SDEISR  _MMIO(0xc4000)
>>> #define SDEIMR  _MMIO(0xc4004)
>>> @@ -8438,6 +8439,8 @@ enum {
>>>                      ICP_TC_HPD_ENABLE(PORT_TC5) | \
>>>                      ICP_TC_HPD_ENABLE_MASK)
>>>
>>> +#define ADLS_DDI_HPD_ENABLE_MASK     SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A)
>>> +
>>> #define _PCH_DPLL_A              0xc6014
>>> #define _PCH_DPLL_B              0xc6018
>>> #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
>>> -- 
>>> 2.27.0
>>>
>
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Re: [Intel-gfx] [PATCH 01/18] drm/i915/adl_s: Add ADL-S platform info and PCI ids

[Matt Roper]

On Wed, Oct 21, 2020 at 06:31:56AM -0700, Aditya Swarup wrote:
> From: Caz Yokoyama <caz.yokoyama@intel.com>
> 
> - Add the initial platform information for Alderlake-S.
> - Specify ppgtt_size value
> - Add dma_mask_size
> - Add ADLS REVIDs
> - HW tracking(Selective Update Tracking Enable) has been removed from
>   ADLS. Disable PSR2 till we enable software/manual tracking.
> 
> Bspec: 53597
> Bspec: 53648
> Bspec: 53655
> Bspec: 48028
> Bspec: 53650
> BSpec: 50422
> 
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Caz Yokoyama <caz.yokoyama@intel.com>
> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h          |  9 +++++++++
>  drivers/gpu/drm/i915/i915_pci.c          | 12 ++++++++++++
>  drivers/gpu/drm/i915/intel_device_info.c |  1 +
>  drivers/gpu/drm/i915/intel_device_info.h |  1 +
>  include/drm/i915_pciids.h                | 13 +++++++++++++
>  5 files changed, 36 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index bcd8650603d8..4fea3d5e01f4 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1424,6 +1424,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  #define IS_TIGERLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
>  #define IS_ROCKETLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
>  #define IS_DG1(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG1)
> +#define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
>  #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
>  				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
>  #define IS_BDW_ULT(dev_priv) \
> @@ -1613,6 +1614,14 @@ tgl_revids_get(struct drm_i915_private *dev_priv)
>  #define IS_DG1_REVID(p, since, until) \
>  	(IS_DG1(p) && IS_REVID(p, since, until))
>  
> +#define ADLS_REVID_A0		0x0
> +#define ADLS_REVID_B0		0x4
> +#define ADLS_REVID_C0		0x8
> +#define ADLS_REVID_D0		0xC
> +
> +#define IS_ADLS_REVID(p, since, until) \
> +       (IS_ALDERLAKE_S(p) && IS_REVID(p, since, until))

Based on bspec 53655 it doesn't look like it's this simple anymore; the
display stepping and gfx/media stepping aren't the same for a given
revid.  We'll need to do something like we have on TGL and have a table
that maps them for use with IS_ADLS_GT_REVID() and IS_ADLS_DISP_REVID().


Matt

> +
>  #define IS_LP(dev_priv)	(INTEL_INFO(dev_priv)->is_lp)
>  #define IS_GEN9_LP(dev_priv)	(IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
>  #define IS_GEN9_BC(dev_priv)	(IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 27964ac0638a..d39a7389b305 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -924,6 +924,17 @@ static const struct intel_device_info dg1_info __maybe_unused = {
>  	.ppgtt_size = 47,
>  };
>  
> +static const struct intel_device_info adl_s_info = {
> +	GEN12_FEATURES,
> +	PLATFORM(INTEL_ALDERLAKE_S),
> +	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
> +	.require_force_probe = 1,
> +	.display.has_psr_hw_tracking = 0,
> +	.platform_engine_mask =
> +		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
> +	.dma_mask_size = 46,
> +};
> +
>  #undef GEN
>  #undef PLATFORM
>  
> @@ -1000,6 +1011,7 @@ static const struct pci_device_id pciidlist[] = {
>  	INTEL_JSL_IDS(&jsl_info),
>  	INTEL_TGL_12_IDS(&tgl_info),
>  	INTEL_RKL_IDS(&rkl_info),
> +	INTEL_ADLS_IDS(&adl_s_info),
>  	{0, 0, 0}
>  };
>  MODULE_DEVICE_TABLE(pci, pciidlist);
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index e67cec8fa2aa..7310e019c611 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -66,6 +66,7 @@ static const char * const platform_names[] = {
>  	PLATFORM_NAME(TIGERLAKE),
>  	PLATFORM_NAME(ROCKETLAKE),
>  	PLATFORM_NAME(DG1),
> +	PLATFORM_NAME(ALDERLAKE_S),
>  };
>  #undef PLATFORM_NAME
>  
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index d92fa041c700..360f3f1835f5 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -84,6 +84,7 @@ enum intel_platform {
>  	INTEL_TIGERLAKE,
>  	INTEL_ROCKETLAKE,
>  	INTEL_DG1,
> +	INTEL_ALDERLAKE_S,
>  	INTEL_MAX_PLATFORMS
>  };
>  
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 3b5ed1e4f3ec..9a0d58524cb1 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -635,4 +635,17 @@
>  	INTEL_VGA_DEVICE(0x4907, info), \
>  	INTEL_VGA_DEVICE(0x4908, info)
>  
> +/* ADL-S */
> +#define INTEL_ADLS_IDS(info) \
> +	INTEL_VGA_DEVICE(0x4680, info), \
> +	INTEL_VGA_DEVICE(0x4681, info), \
> +	INTEL_VGA_DEVICE(0x4682, info), \
> +	INTEL_VGA_DEVICE(0x4683, info), \
> +	INTEL_VGA_DEVICE(0x4690, info), \
> +	INTEL_VGA_DEVICE(0x4691, info), \
> +	INTEL_VGA_DEVICE(0x4692, info), \
> +	INTEL_VGA_DEVICE(0x4693, info), \
> +	INTEL_VGA_DEVICE(0x4698, info), \
> +	INTEL_VGA_DEVICE(0x4699, info)
> +
>  #endif /* _I915_PCIIDS_H */
> -- 
> 2.27.0
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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Re: [Intel-gfx] [PATCH 05/18] drm/i915/adl_s: Add PHYs for Alderlake S

[Matt Roper]

On Wed, Oct 21, 2020 at 06:32:00AM -0700, Aditya Swarup wrote:
> From: Anusha Srivatsa <anusha.srivatsa@intel.com>
> 
> Alderlake-S has 5 combo phys, add reg definitions for
> combo phys and update the port to phy helper for ADL-S.
> 
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 8 ++++++--
>  drivers/gpu/drm/i915/i915_reg.h              | 5 ++++-
>  2 files changed, 10 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 60bacdbe7f92..70ca5d2e5b0a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7333,6 +7333,8 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
>  {
>  	if (phy == PHY_NONE)
>  		return false;
> +	else if (IS_ALDERLAKE_S(dev_priv))
> +		return phy <= PHY_E;
>  	else if (IS_ROCKETLAKE(dev_priv))
>  		return phy <= PHY_D;
>  	else if (IS_JSL_EHL(dev_priv))
> @@ -7345,7 +7347,7 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
>  
>  bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
>  {
> -	if (IS_ROCKETLAKE(dev_priv))
> +	if (IS_ROCKETLAKE(dev_priv) || IS_ALDERLAKE_S(dev_priv))

Minor nitpick:  we're trying to be more consistent about placing the new
platforms first in conditions like this.

Aside from that,

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>


>  		return false;
>  	else if (INTEL_GEN(dev_priv) >= 12)
>  		return phy >= PHY_D && phy <= PHY_I;
> @@ -7357,7 +7359,9 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
>  
>  enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
>  {
> -	if (IS_ROCKETLAKE(i915) && port >= PORT_D)
> +	if (IS_ALDERLAKE_S(i915) && port >= PORT_D)
> +		return (enum phy)port - 2;
> +	else if (IS_ROCKETLAKE(i915) && port >= PORT_D)
>  		return (enum phy)port - 1;
>  	else if (IS_JSL_EHL(i915) && port == PORT_D)
>  		return PHY_A;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f6b844ca7a9f..85c5e4fb3e7c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1870,10 +1870,13 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  #define _ICL_COMBOPHY_B			0x6C000
>  #define _EHL_COMBOPHY_C			0x160000
>  #define _RKL_COMBOPHY_D			0x161000
> +#define _ADL_COMBOPHY_E			0x16B000
> +
>  #define _ICL_COMBOPHY(phy)		_PICK(phy, _ICL_COMBOPHY_A, \
>  					      _ICL_COMBOPHY_B, \
>  					      _EHL_COMBOPHY_C, \
> -					      _RKL_COMBOPHY_D)
> +					      _RKL_COMBOPHY_D, \
> +					      _ADL_COMBOPHY_E)
>  
>  /* CNL/ICL Port CL_DW registers */
>  #define _ICL_PORT_CL_DW(dw, phy)	(_ICL_COMBOPHY(phy) + \
> -- 
> 2.27.0
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 13/18] drm/i915/adl_s: Add display, gt, ctx and ADL-S whitelist WA

[Joonas Lahtinen]

+ Rodrigo,

Quoting Aditya Swarup (2020-10-21 16:32:08)
> From: Anusha Srivatsa <anusha.srivatsa@intel.com>
> 
> - Inherit the gen12 workarounds.
> - Add placeholders to setup GT WA.
> - Extend permanent driver WA Wa_1409767108 to adl-s and
>   Wa_14010685332 to adl-s.
> - Extend permanent driver WA Wa_1606054188 to adl-s
> - Add Wa_14011765242 for adl-s A0 stepping.

Rodrigo, Jani, any thoughts on if this patch should be split
between display and GT? In my thinking we should have a small
topic branch that introduces the base platform support, which
is merged to both trees. Then the respective patches split and
merged to -next and -gt-next. That way we would avoid the
conflicts that came from the Jasperlake patches.

Although, I'm not sure if our code splitting is yet as far that
we could enable the display with separate set of patches. I guess
it would be worthy testing if that can happen.

Regards, Joonas

> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
> ---
>  .../drm/i915/display/intel_display_power.c    |  7 +++--
>  drivers/gpu/drm/i915/display/intel_sprite.c   |  2 +-
>  drivers/gpu/drm/i915/gt/intel_workarounds.c   | 29 +++++++++++++++++--
>  drivers/gpu/drm/i915/i915_irq.c               |  2 +-
>  drivers/gpu/drm/i915/intel_device_info.c      |  6 +++-
>  5 files changed, 37 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 689922480661..acc63ab2bc78 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -5288,9 +5288,10 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
>         unsigned long abox_mask = INTEL_INFO(dev_priv)->abox_mask;
>         int config, i;
>  
> -       if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
> +       if (IS_ALDERLAKE_S(dev_priv) ||
> +           IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
>             IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
> -               /* Wa_1409767108:tgl,dg1 */
> +               /* Wa_1409767108:tgl,dg1,adl-s */
>                 table = wa_1409767108_buddy_page_masks;
>         else
>                 table = tgl_buddy_page_masks;
> @@ -5328,7 +5329,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
>  
>         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
>  
> -       /* Wa_14011294188:ehl,jsl,tgl,rkl */
> +       /* Wa_14011294188:ehl,jsl,tgl,rkl,adl-s */
>         if (INTEL_PCH_TYPE(dev_priv) >= PCH_JSP &&
>             INTEL_PCH_TYPE(dev_priv) < PCH_DG1)
>                 intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 0,
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 88bfebdf9228..d4b5fc9e2704 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -2226,7 +2226,7 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
>         }
>  
>         /* Wa_1606054188:tgl */
> -       if (IS_TIGERLAKE(dev_priv) &&
> +       if ((IS_TIGERLAKE(dev_priv) || IS_ALDERLAKE_S(dev_priv)) &&
>             plane_state->ckey.flags & I915_SET_COLORKEY_SOURCE &&
>             intel_format_is_p01x(fb->format->format)) {
>                 drm_dbg_kms(&dev_priv->drm,
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index fed9503a7c4e..8136d13462b5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -686,6 +686,12 @@ static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine,
>                           DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE);
>  }
>  
> +static void adls_ctx_workarounds_init(struct intel_engine_cs *engine,
> +                                     struct i915_wa_list *wal)
> +{
> +       gen12_ctx_workarounds_init(engine, wal);
> +}
> +
>  static void
>  __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
>                            struct i915_wa_list *wal,
> @@ -698,7 +704,9 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
>  
>         wa_init_start(wal, name, engine->name);
>  
> -       if (IS_DG1(i915))
> +       if (IS_ALDERLAKE_S(i915))
> +               adls_ctx_workarounds_init(engine, wal);
> +       else if (IS_DG1(i915))
>                 dg1_ctx_workarounds_init(engine, wal);
>         else if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915))
>                 tgl_ctx_workarounds_init(engine, wal);
> @@ -1284,10 +1292,18 @@ dg1_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
>                             VSUNIT_CLKGATE_DIS_TGL);
>  }
>  
> +static void
> +adls_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> +{
> +       gen12_gt_workarounds_init(i915, wal);
> +}
> +
>  static void
>  gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
>  {
> -       if (IS_DG1(i915))
> +       if (IS_ALDERLAKE_S(i915))
> +               adls_gt_workarounds_init(i915, wal);
> +       else if (IS_DG1(i915))
>                 dg1_gt_workarounds_init(i915, wal);
>         else if (IS_TIGERLAKE(i915))
>                 tgl_gt_workarounds_init(i915, wal);
> @@ -1668,6 +1684,11 @@ static void dg1_whitelist_build(struct intel_engine_cs *engine)
>                                   RING_FORCE_TO_NONPRIV_ACCESS_RD);
>  }
>  
> +static void adls_whitelist_build(struct intel_engine_cs *engine)
> +{
> +       tgl_whitelist_build(engine);
> +}
> +
>  void intel_engine_init_whitelist(struct intel_engine_cs *engine)
>  {
>         struct drm_i915_private *i915 = engine->i915;
> @@ -1675,7 +1696,9 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
>  
>         wa_init_start(w, "whitelist", engine->name);
>  
> -       if (IS_DG1(i915))
> +       if (IS_ALDERLAKE_S(i915))
> +               adls_whitelist_build(engine);
> +       else if (IS_DG1(i915))
>                 dg1_whitelist_build(engine);
>         else if (IS_GEN(i915, 12))
>                 tgl_whitelist_build(engine);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 9033221995ad..32cb12c4b6dd 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3045,7 +3045,7 @@ static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
>         if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
>                 GEN3_IRQ_RESET(uncore, SDE);
>  
> -       /* Wa_14010685332:icl,jsl,ehl,tgl,rkl */
> +       /* Wa_14010685332:icl,jsl,ehl,tgl,rkl,adl-s A0 */
>         if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
>                 intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
>                                  SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 7310e019c611..4fffa8295d06 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -394,7 +394,11 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>         struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
>         enum pipe pipe;
>  
> -       if (INTEL_GEN(dev_priv) >= 10) {
> +       /* Wa_14011765242: adl-s A0 */
> +       if (IS_ADLS_REVID(dev_priv, ADLS_REVID_A0, ADLS_REVID_A0))
> +               for_each_pipe(dev_priv, pipe)
> +                       runtime->num_scalers[pipe] = 0;
> +       else if (INTEL_GEN(dev_priv) >= 10) {
>                 for_each_pipe(dev_priv, pipe)
>                         runtime->num_scalers[pipe] = 2;
>         } else if (IS_GEN(dev_priv, 9)) {
> -- 
> 2.27.0
> 
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Re: [Intel-gfx] [PATCH 13/18] drm/i915/adl_s: Add display, gt, ctx and ADL-S whitelist WA

[Rodrigo Vivi]

On Wed, Nov 04, 2020 at 12:38:00PM +0200, Joonas Lahtinen wrote:
> + Rodrigo,
> 
> Quoting Aditya Swarup (2020-10-21 16:32:08)
> > From: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > 
> > - Inherit the gen12 workarounds.
> > - Add placeholders to setup GT WA.
> > - Extend permanent driver WA Wa_1409767108 to adl-s and
> >   Wa_14010685332 to adl-s.
> > - Extend permanent driver WA Wa_1606054188 to adl-s
> > - Add Wa_14011765242 for adl-s A0 stepping.
> 
> Rodrigo, Jani, any thoughts on if this patch should be split
> between display and GT?

I believe for this patch specifically it should be easy to break
the gt/ part of it as a preparation for the workarounds...

> In my thinking we should have a small
> topic branch that introduces the base platform support, which
> is merged to both trees. Then the respective patches split and
> merged to -next and -gt-next. That way we would avoid the
> conflicts that came from the Jasperlake patches.

With only this patch in mind I believe a topic branch is to heavy
of a process and that small conflicts should be okay to handle.
However I like the idea of the topic branch for the big chunk of
platform enabling patches.

> 
> Although, I'm not sure if our code splitting is yet as far that
> we could enable the display with separate set of patches. I guess
> it would be worthy testing if that can happen.

I agree.

> 
> Regards, Joonas
> 
> > Cc: Jani Nikula <jani.nikula@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Imre Deak <imre.deak@intel.com>
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
> > ---
> >  .../drm/i915/display/intel_display_power.c    |  7 +++--
> >  drivers/gpu/drm/i915/display/intel_sprite.c   |  2 +-
> >  drivers/gpu/drm/i915/gt/intel_workarounds.c   | 29 +++++++++++++++++--
> >  drivers/gpu/drm/i915/i915_irq.c               |  2 +-
> >  drivers/gpu/drm/i915/intel_device_info.c      |  6 +++-
> >  5 files changed, 37 insertions(+), 9 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index 689922480661..acc63ab2bc78 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -5288,9 +5288,10 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
> >         unsigned long abox_mask = INTEL_INFO(dev_priv)->abox_mask;
> >         int config, i;
> >  
> > -       if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
> > +       if (IS_ALDERLAKE_S(dev_priv) ||
> > +           IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
> >             IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
> > -               /* Wa_1409767108:tgl,dg1 */
> > +               /* Wa_1409767108:tgl,dg1,adl-s */
> >                 table = wa_1409767108_buddy_page_masks;
> >         else
> >                 table = tgl_buddy_page_masks;
> > @@ -5328,7 +5329,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
> >  
> >         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> >  
> > -       /* Wa_14011294188:ehl,jsl,tgl,rkl */
> > +       /* Wa_14011294188:ehl,jsl,tgl,rkl,adl-s */
> >         if (INTEL_PCH_TYPE(dev_priv) >= PCH_JSP &&
> >             INTEL_PCH_TYPE(dev_priv) < PCH_DG1)
> >                 intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 0,
> > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> > index 88bfebdf9228..d4b5fc9e2704 100644
> > --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> > @@ -2226,7 +2226,7 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
> >         }
> >  
> >         /* Wa_1606054188:tgl */
> > -       if (IS_TIGERLAKE(dev_priv) &&
> > +       if ((IS_TIGERLAKE(dev_priv) || IS_ALDERLAKE_S(dev_priv)) &&
> >             plane_state->ckey.flags & I915_SET_COLORKEY_SOURCE &&
> >             intel_format_is_p01x(fb->format->format)) {
> >                 drm_dbg_kms(&dev_priv->drm,
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index fed9503a7c4e..8136d13462b5 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -686,6 +686,12 @@ static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine,
> >                           DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE);
> >  }
> >  
> > +static void adls_ctx_workarounds_init(struct intel_engine_cs *engine,
> > +                                     struct i915_wa_list *wal)
> > +{
> > +       gen12_ctx_workarounds_init(engine, wal);
> > +}
> > +
> >  static void
> >  __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
> >                            struct i915_wa_list *wal,
> > @@ -698,7 +704,9 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
> >  
> >         wa_init_start(wal, name, engine->name);
> >  
> > -       if (IS_DG1(i915))
> > +       if (IS_ALDERLAKE_S(i915))
> > +               adls_ctx_workarounds_init(engine, wal);
> > +       else if (IS_DG1(i915))
> >                 dg1_ctx_workarounds_init(engine, wal);
> >         else if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915))
> >                 tgl_ctx_workarounds_init(engine, wal);
> > @@ -1284,10 +1292,18 @@ dg1_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> >                             VSUNIT_CLKGATE_DIS_TGL);
> >  }
> >  
> > +static void
> > +adls_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> > +{
> > +       gen12_gt_workarounds_init(i915, wal);
> > +}
> > +
> >  static void
> >  gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
> >  {
> > -       if (IS_DG1(i915))
> > +       if (IS_ALDERLAKE_S(i915))
> > +               adls_gt_workarounds_init(i915, wal);
> > +       else if (IS_DG1(i915))
> >                 dg1_gt_workarounds_init(i915, wal);
> >         else if (IS_TIGERLAKE(i915))
> >                 tgl_gt_workarounds_init(i915, wal);
> > @@ -1668,6 +1684,11 @@ static void dg1_whitelist_build(struct intel_engine_cs *engine)
> >                                   RING_FORCE_TO_NONPRIV_ACCESS_RD);
> >  }
> >  
> > +static void adls_whitelist_build(struct intel_engine_cs *engine)
> > +{
> > +       tgl_whitelist_build(engine);
> > +}
> > +
> >  void intel_engine_init_whitelist(struct intel_engine_cs *engine)
> >  {
> >         struct drm_i915_private *i915 = engine->i915;
> > @@ -1675,7 +1696,9 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
> >  
> >         wa_init_start(w, "whitelist", engine->name);
> >  
> > -       if (IS_DG1(i915))
> > +       if (IS_ALDERLAKE_S(i915))
> > +               adls_whitelist_build(engine);
> > +       else if (IS_DG1(i915))
> >                 dg1_whitelist_build(engine);
> >         else if (IS_GEN(i915, 12))
> >                 tgl_whitelist_build(engine);
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > index 9033221995ad..32cb12c4b6dd 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -3045,7 +3045,7 @@ static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
> >         if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> >                 GEN3_IRQ_RESET(uncore, SDE);
> >  
> > -       /* Wa_14010685332:icl,jsl,ehl,tgl,rkl */
> > +       /* Wa_14010685332:icl,jsl,ehl,tgl,rkl,adl-s A0 */
> >         if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
> >                 intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> >                                  SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> > index 7310e019c611..4fffa8295d06 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.c
> > +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > @@ -394,7 +394,11 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
> >         struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
> >         enum pipe pipe;
> >  
> > -       if (INTEL_GEN(dev_priv) >= 10) {
> > +       /* Wa_14011765242: adl-s A0 */
> > +       if (IS_ADLS_REVID(dev_priv, ADLS_REVID_A0, ADLS_REVID_A0))
> > +               for_each_pipe(dev_priv, pipe)
> > +                       runtime->num_scalers[pipe] = 0;
> > +       else if (INTEL_GEN(dev_priv) >= 10) {
> >                 for_each_pipe(dev_priv, pipe)
> >                         runtime->num_scalers[pipe] = 2;
> >         } else if (IS_GEN(dev_priv, 9)) {
> > -- 
> > 2.27.0
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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