From: Zhiqiang Hou <Zhiqiang.Hou@nxp.com> To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, lorenzo.pieralisi@arm.com, robh+dt@kernel.org, bhelgaas@google.com, shawnguo@kernel.org, leoyang.li@nxp.com, gustavo.pimentel@synopsys.com Cc: minghuan.Lian@nxp.com, mingkai.hu@nxp.com, roy.zang@nxp.com, Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Subject: [PATCHv2 3/7] dt-bindings: pci: layerscape-pci: Add a optional property big-endian Date: Tue, 27 Oct 2020 15:29:57 +0800 [thread overview] Message-ID: <20201027073001.41808-4-Zhiqiang.Hou@nxp.com> (raw) In-Reply-To: <20201027073001.41808-1-Zhiqiang.Hou@nxp.com> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> This property is to indicate the endianness when accessing the PEX_LUT and PF register block, so if these registers are implemented in big-endian, specify this property. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Acked-by: Rob Herring <robh@kernel.org> --- V2: - No change. Documentation/devicetree/bindings/pci/layerscape-pci.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index daa99f7d4c3f..0033c898976e 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -39,6 +39,10 @@ Required properties: of the data transferred from/to the IP block. This can avoid the software cache flush/invalid actions, and improve the performance significantly. +Optional properties: +- big-endian: If the PEX_LUT and PF register block is in big-endian, specify + this property. + Example: pcie@3400000 { -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Zhiqiang Hou <Zhiqiang.Hou@nxp.com> To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, lorenzo.pieralisi@arm.com, robh+dt@kernel.org, bhelgaas@google.com, shawnguo@kernel.org, leoyang.li@nxp.com, gustavo.pimentel@synopsys.com Cc: minghuan.Lian@nxp.com, Hou Zhiqiang <Zhiqiang.Hou@nxp.com>, mingkai.hu@nxp.com, roy.zang@nxp.com Subject: [PATCHv2 3/7] dt-bindings: pci: layerscape-pci: Add a optional property big-endian Date: Tue, 27 Oct 2020 15:29:57 +0800 [thread overview] Message-ID: <20201027073001.41808-4-Zhiqiang.Hou@nxp.com> (raw) In-Reply-To: <20201027073001.41808-1-Zhiqiang.Hou@nxp.com> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> This property is to indicate the endianness when accessing the PEX_LUT and PF register block, so if these registers are implemented in big-endian, specify this property. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Acked-by: Rob Herring <robh@kernel.org> --- V2: - No change. Documentation/devicetree/bindings/pci/layerscape-pci.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index daa99f7d4c3f..0033c898976e 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -39,6 +39,10 @@ Required properties: of the data transferred from/to the IP block. This can avoid the software cache flush/invalid actions, and improve the performance significantly. +Optional properties: +- big-endian: If the PEX_LUT and PF register block is in big-endian, specify + this property. + Example: pcie@3400000 { -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-10-27 7:42 UTC|newest] Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-10-27 7:29 [PATCHv2 0/7] PCI: layerscape: Add power management support Zhiqiang Hou 2020-10-27 7:29 ` Zhiqiang Hou 2020-10-27 7:29 ` [PATCHv2 1/7] PCI: dwc: Fix a bug of the case dw_pci->ops is NULL Zhiqiang Hou 2020-10-27 7:29 ` Zhiqiang Hou 2020-10-27 7:29 ` [PATCHv2 2/7] PCI: layerscape: Change to use the DWC common link-up check function Zhiqiang Hou 2020-10-27 7:29 ` Zhiqiang Hou 2020-10-27 7:29 ` Zhiqiang Hou [this message] 2020-10-27 7:29 ` [PATCHv2 3/7] dt-bindings: pci: layerscape-pci: Add a optional property big-endian Zhiqiang Hou 2020-10-27 7:29 ` [PATCHv2 4/7] arm64: dts: layerscape: Add big-endian property for PCIe nodes Zhiqiang Hou 2020-10-27 7:29 ` Zhiqiang Hou 2020-10-27 7:29 ` [PATCHv2 5/7] dt-bindings: pci: layerscape-pci: Update the description of SCFG property Zhiqiang Hou 2020-10-27 7:29 ` Zhiqiang Hou 2020-10-27 7:30 ` [PATCHv2 6/7] arm64: dts: ls1043a: Add SCFG phandle for PCIe nodes Zhiqiang Hou 2020-10-27 7:30 ` Zhiqiang Hou 2020-10-27 7:30 ` [PATCHv2 7/7] PCI: layerscape: Add power management support Zhiqiang Hou 2020-10-27 7:30 ` Zhiqiang Hou
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