From: Anshuman Gupta <anshuman.gupta@intel.com> To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: jani.nikula@intel.com, uma.shankar@intel.com, seanpaul@chromium.org, Anshuman Gupta <anshuman.gupta@intel.com>, juston.li@intel.com Subject: [PATCH v4 14/16] drm/i915/hdcp: Add HDCP 2.2 stream register Date: Tue, 27 Oct 2020 22:12:06 +0530 [thread overview] Message-ID: <20201027164208.10026-15-anshuman.gupta@intel.com> (raw) In-Reply-To: <20201027164208.10026-1-anshuman.gupta@intel.com> Add HDCP 2.2 DP MST HDCP2_STREAM_STATUS and HDCP2_AUTH_STREAM register in i915_reg header. Cc: Ramalingam C <ramalingam.c@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 77461cde6549..c9678c77883d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -9894,6 +9894,7 @@ enum skl_power_gate { _PORTD_HDCP2_BASE, \ _PORTE_HDCP2_BASE, \ _PORTF_HDCP2_BASE) + (x)) + #define PORT_HDCP2_AUTH(port) _PORT_HDCP2_BASE(port, 0x98) #define _TRANSA_HDCP2_AUTH 0x66498 #define _TRANSB_HDCP2_AUTH 0x66598 @@ -9933,6 +9934,35 @@ enum skl_power_gate { TRANS_HDCP2_STATUS(trans) : \ PORT_HDCP2_STATUS(port)) +#define PORT_HDCP2_STREAM_STATUS(port) _PORT_HDCP2_BASE(port, 0xC0) +#define _TRANSA_HDCP2_STREAM_STATUS 0x664C0 +#define _TRANSB_HDCP2_STREAM_STATUS 0x665C0 +#define TRANS_HDCP2_STREAM_STATUS(trans) _MMIO_TRANS(trans, \ + _TRANSA_HDCP2_STREAM_STATUS, \ + _TRANSB_HDCP2_STREAM_STATUS) +#define STREAM_ENCRYPTION_STATUS BIT(31) +#define STREAM_TYPE_STATUS BIT(30) +#define HDCP2_STREAM_STATUS(dev_priv, trans, port) \ + (INTEL_GEN(dev_priv) >= 12 ? \ + TRANS_HDCP2_STREAM_STATUS(trans) : \ + PORT_HDCP2_STREAM_STATUS(port)) + +#define _PORTA_HDCP2_AUTH_STREAM 0x66F00 +#define _PORTB_HDCP2_AUTH_STREAM 0x66F04 +#define PORT_HDCP2_AUTH_STREAM(port) _MMIO_PORT(port, \ + _PORTA_HDCP2_AUTH_STREAM, \ + _PORTB_HDCP2_AUTH_STREAM) +#define _TRANSA_HDCP2_AUTH_STREAM 0x66F00 +#define _TRANSB_HDCP2_AUTH_STREAM 0x66F04 +#define TRANS_HDCP2_AUTH_STREAM(trans) _MMIO_TRANS(trans, \ + _TRANSA_HDCP2_AUTH_STREAM, \ + _TRANSB_HDCP2_AUTH_STREAM) +#define AUTH_STREAM_TYPE BIT(31) +#define HDCP2_AUTH_STREAM(dev_priv, trans, port) \ + (INTEL_GEN(dev_priv) >= 12 ? \ + TRANS_HDCP2_AUTH_STREAM(trans) : \ + PORT_HDCP2_AUTH_STREAM(port)) + /* Per-pipe DDI Function Control */ #define _TRANS_DDI_FUNC_CTL_A 0x60400 #define _TRANS_DDI_FUNC_CTL_B 0x61400 -- 2.26.2 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
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From: Anshuman Gupta <anshuman.gupta@intel.com> To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: jani.nikula@intel.com, seanpaul@chromium.org Subject: [Intel-gfx] [PATCH v4 14/16] drm/i915/hdcp: Add HDCP 2.2 stream register Date: Tue, 27 Oct 2020 22:12:06 +0530 [thread overview] Message-ID: <20201027164208.10026-15-anshuman.gupta@intel.com> (raw) In-Reply-To: <20201027164208.10026-1-anshuman.gupta@intel.com> Add HDCP 2.2 DP MST HDCP2_STREAM_STATUS and HDCP2_AUTH_STREAM register in i915_reg header. Cc: Ramalingam C <ramalingam.c@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 77461cde6549..c9678c77883d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -9894,6 +9894,7 @@ enum skl_power_gate { _PORTD_HDCP2_BASE, \ _PORTE_HDCP2_BASE, \ _PORTF_HDCP2_BASE) + (x)) + #define PORT_HDCP2_AUTH(port) _PORT_HDCP2_BASE(port, 0x98) #define _TRANSA_HDCP2_AUTH 0x66498 #define _TRANSB_HDCP2_AUTH 0x66598 @@ -9933,6 +9934,35 @@ enum skl_power_gate { TRANS_HDCP2_STATUS(trans) : \ PORT_HDCP2_STATUS(port)) +#define PORT_HDCP2_STREAM_STATUS(port) _PORT_HDCP2_BASE(port, 0xC0) +#define _TRANSA_HDCP2_STREAM_STATUS 0x664C0 +#define _TRANSB_HDCP2_STREAM_STATUS 0x665C0 +#define TRANS_HDCP2_STREAM_STATUS(trans) _MMIO_TRANS(trans, \ + _TRANSA_HDCP2_STREAM_STATUS, \ + _TRANSB_HDCP2_STREAM_STATUS) +#define STREAM_ENCRYPTION_STATUS BIT(31) +#define STREAM_TYPE_STATUS BIT(30) +#define HDCP2_STREAM_STATUS(dev_priv, trans, port) \ + (INTEL_GEN(dev_priv) >= 12 ? \ + TRANS_HDCP2_STREAM_STATUS(trans) : \ + PORT_HDCP2_STREAM_STATUS(port)) + +#define _PORTA_HDCP2_AUTH_STREAM 0x66F00 +#define _PORTB_HDCP2_AUTH_STREAM 0x66F04 +#define PORT_HDCP2_AUTH_STREAM(port) _MMIO_PORT(port, \ + _PORTA_HDCP2_AUTH_STREAM, \ + _PORTB_HDCP2_AUTH_STREAM) +#define _TRANSA_HDCP2_AUTH_STREAM 0x66F00 +#define _TRANSB_HDCP2_AUTH_STREAM 0x66F04 +#define TRANS_HDCP2_AUTH_STREAM(trans) _MMIO_TRANS(trans, \ + _TRANSA_HDCP2_AUTH_STREAM, \ + _TRANSB_HDCP2_AUTH_STREAM) +#define AUTH_STREAM_TYPE BIT(31) +#define HDCP2_AUTH_STREAM(dev_priv, trans, port) \ + (INTEL_GEN(dev_priv) >= 12 ? \ + TRANS_HDCP2_AUTH_STREAM(trans) : \ + PORT_HDCP2_AUTH_STREAM(port)) + /* Per-pipe DDI Function Control */ #define _TRANS_DDI_FUNC_CTL_A 0x60400 #define _TRANS_DDI_FUNC_CTL_B 0x61400 -- 2.26.2 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-10-27 16:56 UTC|newest] Thread overview: 111+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-10-27 16:41 [PATCH v4 00/16] HDCP 2.2 and HDCP 1.4 Gen12 DP MST support Anshuman Gupta 2020-10-27 16:41 ` [Intel-gfx] " Anshuman Gupta 2020-10-27 16:41 ` [PATCH v4 01/16] drm/i915/hdcp: Update CP property in update_pipe Anshuman Gupta 2020-10-27 16:41 ` [Intel-gfx] " Anshuman Gupta 2020-11-02 7:45 ` Shankar, Uma 2020-11-02 7:45 ` [Intel-gfx] " Shankar, Uma 2020-11-05 13:18 ` Ramalingam C 2020-11-05 13:18 ` [Intel-gfx] " Ramalingam C 2020-11-05 13:21 ` Ramalingam C 2020-11-05 13:21 ` Ramalingam C 2020-11-05 13:26 ` Ramalingam C 2020-11-05 13:26 ` Ramalingam C 2020-10-27 16:41 ` [PATCH v4 02/16] drm/i915/hdcp: Get conn while content_type changed Anshuman Gupta 2020-10-27 16:41 ` [Intel-gfx] " Anshuman Gupta 2020-11-02 7:45 ` Shankar, Uma 2020-11-02 7:45 ` [Intel-gfx] " Shankar, Uma 2020-11-05 13:23 ` Ramalingam C 2020-11-05 13:23 ` [Intel-gfx] " Ramalingam C 2020-10-27 16:41 ` [PATCH v4 03/16] drm/i915/hotplug: Handle CP_IRQ for DP-MST Anshuman Gupta 2020-10-27 16:41 ` [Intel-gfx] " Anshuman Gupta 2020-11-06 12:00 ` Ramalingam C 2020-11-06 12:00 ` [Intel-gfx] " Ramalingam C 2020-10-27 16:41 ` [PATCH v4 04/16] drm/i915/hdcp: DP MST transcoder for link and stream Anshuman Gupta 2020-10-27 16:41 ` [Intel-gfx] " Anshuman Gupta 2020-11-05 13:52 ` Ramalingam C 2020-11-05 13:52 ` [Intel-gfx] " Ramalingam C 2020-10-27 16:41 ` [PATCH v4 05/16] drm/i915/hdcp: Move HDCP enc status timeout to header Anshuman Gupta 2020-10-27 16:41 ` [Intel-gfx] " Anshuman Gupta 2020-11-05 13:57 ` Ramalingam C 2020-11-05 13:57 ` [Intel-gfx] " Ramalingam C 2020-10-27 16:41 ` [PATCH v4 06/16] drm/i915/hdcp: HDCP stream encryption support Anshuman Gupta 2020-10-27 16:41 ` [Intel-gfx] " Anshuman Gupta 2020-11-02 7:47 ` Shankar, Uma 2020-11-02 7:47 ` [Intel-gfx] " Shankar, Uma 2020-11-05 15:34 ` Ramalingam C 2020-11-05 15:34 ` [Intel-gfx] " Ramalingam C 2020-11-06 5:22 ` Anshuman Gupta 2020-11-06 5:22 ` [Intel-gfx] " Anshuman Gupta 2020-11-06 7:52 ` Ramalingam C 2020-11-06 7:52 ` [Intel-gfx] " Ramalingam C 2020-10-27 16:41 ` [PATCH v4 07/16] drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST support Anshuman Gupta 2020-10-27 16:41 ` [Intel-gfx] " Anshuman Gupta 2020-11-02 7:47 ` Shankar, Uma 2020-11-02 7:47 ` [Intel-gfx] " Shankar, Uma 2020-11-05 15:41 ` Ramalingam C 2020-11-05 15:41 ` [Intel-gfx] " Ramalingam C 2020-11-06 6:36 ` Anshuman Gupta 2020-11-06 6:36 ` [Intel-gfx] " Anshuman Gupta 2020-10-27 16:42 ` [PATCH v4 08/16] drm/i915/hdcp: Pass dig_port to intel_hdcp_init Anshuman Gupta 2020-10-27 16:42 ` [Intel-gfx] " Anshuman Gupta 2020-11-05 16:39 ` Ramalingam C 2020-11-05 16:39 ` [Intel-gfx] " Ramalingam C 2020-11-06 4:50 ` Anshuman Gupta 2020-11-06 4:50 ` [Intel-gfx] " Anshuman Gupta 2020-11-06 7:48 ` Ramalingam C 2020-11-06 7:48 ` [Intel-gfx] " Ramalingam C 2020-10-27 16:42 ` [PATCH v4 09/16] drm/i915/hdcp: Encapsulate hdcp_port_data to dig_port Anshuman Gupta 2020-10-27 16:42 ` [Intel-gfx] " Anshuman Gupta 2020-11-06 11:34 ` Ramalingam C 2020-11-06 11:34 ` [Intel-gfx] " Ramalingam C 2020-10-27 16:42 ` [PATCH v4 10/16] misc/mei/hdcp: Fix AUTH_STREAM_REQ cmd buffer len Anshuman Gupta 2020-10-27 16:42 ` [Intel-gfx] " Anshuman Gupta 2020-11-05 16:07 ` Ramalingam C 2020-11-05 16:07 ` [Intel-gfx] " Ramalingam C 2020-10-27 16:42 ` [PATCH v4 11/16] drm/hdcp: Max MST content streams Anshuman Gupta 2020-10-27 16:42 ` [Intel-gfx] " Anshuman Gupta 2020-11-05 16:09 ` Ramalingam C 2020-11-05 16:09 ` [Intel-gfx] " Ramalingam C 2020-10-27 16:42 ` [PATCH v4 12/16] drm/i915/hdcp: MST streams support in hdcp port_data Anshuman Gupta 2020-10-27 16:42 ` [Intel-gfx] " Anshuman Gupta 2020-11-02 7:49 ` Shankar, Uma 2020-11-02 7:49 ` [Intel-gfx] " Shankar, Uma 2020-11-05 16:34 ` Ramalingam C 2020-11-05 16:34 ` [Intel-gfx] " Ramalingam C 2020-11-06 6:35 ` Anshuman Gupta 2020-11-06 6:35 ` [Intel-gfx] " Anshuman Gupta 2020-11-06 11:28 ` Ramalingam C 2020-11-06 11:28 ` [Intel-gfx] " Ramalingam C 2020-10-27 16:42 ` [PATCH v4 13/16] drm/i915/hdcp: Pass connector to check_2_2_link Anshuman Gupta 2020-10-27 16:42 ` [Intel-gfx] " Anshuman Gupta 2020-11-05 16:45 ` Ramalingam C 2020-11-05 16:45 ` [Intel-gfx] " Ramalingam C 2020-11-06 5:08 ` Anshuman Gupta 2020-11-06 5:08 ` [Intel-gfx] " Anshuman Gupta 2020-10-27 16:42 ` Anshuman Gupta [this message] 2020-10-27 16:42 ` [Intel-gfx] [PATCH v4 14/16] drm/i915/hdcp: Add HDCP 2.2 stream register Anshuman Gupta 2020-11-05 16:47 ` Ramalingam C 2020-11-05 16:47 ` [Intel-gfx] " Ramalingam C 2020-10-27 16:42 ` [PATCH v4 15/16] drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks Anshuman Gupta 2020-10-27 16:42 ` [Intel-gfx] " Anshuman Gupta 2020-11-02 7:49 ` Shankar, Uma 2020-11-02 7:49 ` [Intel-gfx] " Shankar, Uma 2020-11-03 6:27 ` Anshuman Gupta 2020-11-06 9:27 ` Ramalingam C 2020-11-06 11:12 ` Ramalingam C 2020-11-09 5:36 ` Anshuman Gupta 2020-11-09 8:38 ` Ramalingam C 2020-10-27 16:42 ` [PATCH v4 16/16] drm/i915/hdcp: Enable HDCP 2.2 MST support Anshuman Gupta 2020-10-27 16:42 ` [Intel-gfx] " Anshuman Gupta 2020-11-06 11:58 ` Ramalingam C 2020-11-06 11:58 ` [Intel-gfx] " Ramalingam C 2020-10-28 2:47 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (rev2) Patchwork 2020-10-28 2:49 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2020-10-28 3:17 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2020-10-28 6:40 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 2020-10-29 8:37 ` Anshuman Gupta 2020-10-29 22:11 ` Vudum, Lakshminarayana 2020-10-29 17:40 ` Patchwork 2020-10-29 17:54 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork 2020-11-02 9:02 ` Anshuman Gupta 2020-11-03 7:05 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (rev3) Patchwork
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