Re: [PATCH v16 00/15] mtd: spi-nor: add xSPI Octal DTR support

[Pratyush Yadav <p.yadav@ti.com>]

On 28/10/20 03:21PM, Tudor.Ambarus@microchip.com wrote:
> On 10/28/20 2:49 PM, Pratyush Yadav wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> > 
> > Hi Tudor,
> > 
> > On 28/10/20 07:53AM, Tudor.Ambarus@microchip.com wrote:
> >> Hi, Pratyush,
> >>
> >> On 10/5/20 6:31 PM, Pratyush Yadav wrote:
> >>> Tested on Micron MT35X and S28HS flashes for Octal DTR.
> >>
> >> Do these flashes define the "Command Sequences to Change to
> >> Octal DDR (8D-8D-8D) mode" table? Can't we use that table
> >> instead of defining our own octal dtr enable functions?
> > 
> > The Micron flash does not have this table. The Cypress flash does. The
> > problem is that one of the samples of the Cypress flash I tested on had
> > incorrect data in that table which meant the sequence would fail. The
> > newer samples of the flash have the correct data.
> 
> Can we differentiate the Cypress flashes?

No way I know of.

> Do you remember what was the incorrect data?

The address width for the write register command was 4 bytes when the 
flash uses 3 bytes by default.
 
> > 
> > I don't know how many of those faulty flashes are out there in the wild.
> > IMO, to be on the safe side spi_nor_cypress_octal_dtr_enable() needs to
> > be implemented. So from the point of view of this series there is no
> > need to parse the Octal DDR enable table.
> 
> Meh, we cover manufacturer's mistakes. On the long run, our aim should be
> to follow the SFDP standard and if a flash implements it wrong, to either
> fix it via a fixup hook (if the fix is minimal), or to skip the faulty
> table.
> 
> Regarding "Command Sequences to Change to Octal DDR (8D-8D-8D) mode"
> table. Have you looked over
> https://patchwork.ozlabs.org/project/linux-mtd/patch/1590737775-4798-4-git-send-email-masonccyang@mxic.com.tw/
> ?
> Is there a standard way to determine the offsets of opcode, addr and
> data in the cmd seq?

To be honest the spec does not say much about how the data should be 
interpreted so I am not sure either. My understanding is that those are 
effectively data bytes to send out on the bus.

One way to implement such a function, would be to put the first byte as 
the command opcode and the rest as data [0], with no address and dummy 
cycles. So no matter the address length, the controller should send out 
the bytes in sequence and then the flash can interpret them according to 
the address width it expects.

The downside is that someone debugging this on the controller's end 
might get confused seeing an opcode that expects an address phase but 
SPI NOR not sending one.

The other way would be to use the first byte as opcode, the next 
nor->addr_width bytes as address and the remaining as data, with no 
dummy cycles. This would fail if the 8D enable command does not use 
nor->addr_width address bytes [1].

I don't know which of the two is better but I think both are better than 
the switch-case hackery in Mason's patch which has to assume either the 
address width or the data length and leaves no way to play around with 
them in fixup hooks. If you have any better ideas I'm all ears.

[0] AFAIK many controllers can't have 0 command bytes.
[1] I'm not sure how common that would be though.
 
> Cheers,
> ta
> > 
> >> I see that Mason used this table for a macronix flash:
> >> https://patchwork.ozlabs.org/project/linux-mtd/patch/1590737775-4798-4-git-send-email-masonccyang@mxic.com.tw/
> >> https://patchwork.ozlabs.org/project/linux-mtd/patch/1590737775-4798-8-git-send-email-masonccyang@mxic.com.tw/
> >>
> >> Cheers,
> >> ta
> > 
> > --
> > Regards,
> > Pratyush Yadav
> > Texas Instruments India
> > 
> 

-- 
Regards,
Pratyush Yadav
Texas Instruments India