[Intel-gfx] [PATCH v3 00/19] drm/i915: Futher cleanup around hpd pins and port identfiers

[Intel-gfx] [PATCH v3 00/19] drm/i915: Futher cleanup around hpd pins and port identfiers

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Rebase of the remaining hpd cleanup series. Almost started
merging from the start but then realized some dg1 stuff landed
which needed some tweaking. So figured best repost the whole thing
one more time.

Only a few patches missing and r-b I think.

Main changes since last time:
- dg1 changes
- updated the rkl port->hpd pin function as well
- Lucas's HOTPLUG_MASK rename

Ville Syrjälä (19):
  drm/i915: s/PORT_TC/TC_PORT_/
  drm/i915: Add PORT_TCn aliases to enum port
  drm/i915: Give DDI encoders even better names
  drm/i915: Introduce AUX_CH_USBCn
  drm/i915: Pimp AUX CH names
  drm/i915: Use AUX_CH_USBCn for the RKL VBT AUX CH setup
  drm/i915: Parametrize BXT_DE_PORT_HP_DDI with hpd_pin
  drm/i915: Introduce GEN8_DE_PORT_HOTPLUG()
  drm/i915: s/port/hpd_pin/ for icp+ ddi hpd bits
  drm/i915: s/tc_port/hpd_pin/ in GEN11_{TC,TBT}_HOTPLUG()
  drm/i915: s/tc_port/hpd_pin/ in icp+ TC hotplug bits
  drm/i915: Relocate intel_hpd_{enabled,hotplug}_irqs()
  drm/i915: Split gen11_hpd_detection_setup() into tc vs. tbt variants
  drm/i915: Don't enable hpd detection logic from irq_postinstall()
  drm/i915: Rename 'tmp_mask'
  drm/i915: Remove the per-plaform IIR HPD masking
  drm/i915: Enable hpd logic only for ports that are present
  drm/i915: Use GEN3_IRQ_INIT() to init south interrupts in icp+
  drm/i915: Get rid of ibx_irq_pre_postinstall()

 drivers/gpu/drm/i915/display/intel_bios.c    |  18 +-
 drivers/gpu/drm/i915/display/intel_ddi.c     |  39 +-
 drivers/gpu/drm/i915/display/intel_display.c |  30 +-
 drivers/gpu/drm/i915/display/intel_display.h |  30 +-
 drivers/gpu/drm/i915/display/intel_dp.c      |  66 ++-
 drivers/gpu/drm/i915/display/intel_tc.c      |   2 +-
 drivers/gpu/drm/i915/gvt/display.c           |  15 +-
 drivers/gpu/drm/i915/i915_irq.c              | 565 ++++++++++---------
 drivers/gpu/drm/i915/i915_reg.h              | 123 ++--
 9 files changed, 503 insertions(+), 385 deletions(-)

-- 
2.26.2

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[Intel-gfx] [PATCH v3 01/19] drm/i915: s/PORT_TC/TC_PORT_/

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Make the namespacing for enum tc_port better by adding
the TC_ to the actual enum values.

v2: Drop the extra TC (Lucas)

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c |  2 +-
 drivers/gpu/drm/i915/display/intel_display.h | 14 ++--
 drivers/gpu/drm/i915/display/intel_tc.c      |  2 +-
 drivers/gpu/drm/i915/i915_irq.c              | 78 ++++++++++----------
 drivers/gpu/drm/i915/i915_reg.h              | 60 +++++++--------
 5 files changed, 78 insertions(+), 78 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f41b6f8b5618..da2a91122d44 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7474,7 +7474,7 @@ enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
 {
 	if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
-		return PORT_TC_NONE;
+		return TC_PORT_NONE;
 
 	if (INTEL_GEN(dev_priv) >= 12)
 		return port - PORT_D;
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 1b946209e06b..1b7ae1d507f2 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -244,14 +244,14 @@ static inline const char *port_identifier(enum port port)
 }
 
 enum tc_port {
-	PORT_TC_NONE = -1,
+	TC_PORT_NONE = -1,
 
-	PORT_TC1 = 0,
-	PORT_TC2,
-	PORT_TC3,
-	PORT_TC4,
-	PORT_TC5,
-	PORT_TC6,
+	TC_PORT_1 = 0,
+	TC_PORT_2,
+	TC_PORT_3,
+	TC_PORT_4,
+	TC_PORT_5,
+	TC_PORT_6,
 
 	I915_MAX_TC_PORTS
 };
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 8f67aef18b2d..1cb548d757e1 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -652,7 +652,7 @@ void intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy)
 	enum port port = dig_port->base.port;
 	enum tc_port tc_port = intel_port_to_tc(i915, port);
 
-	if (drm_WARN_ON(&i915->drm, tc_port == PORT_TC_NONE))
+	if (drm_WARN_ON(&i915->drm, tc_port == TC_PORT_NONE))
 		return;
 
 	snprintf(dig_port->tc_port_name, sizeof(dig_port->tc_port_name),
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index dc33c96d741d..ffa191913139 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -132,24 +132,24 @@ static const u32 hpd_bxt[HPD_NUM_PINS] = {
 };
 
 static const u32 hpd_gen11[HPD_NUM_PINS] = {
-	[HPD_PORT_TC1] = GEN11_TC_HOTPLUG(PORT_TC1) | GEN11_TBT_HOTPLUG(PORT_TC1),
-	[HPD_PORT_TC2] = GEN11_TC_HOTPLUG(PORT_TC2) | GEN11_TBT_HOTPLUG(PORT_TC2),
-	[HPD_PORT_TC3] = GEN11_TC_HOTPLUG(PORT_TC3) | GEN11_TBT_HOTPLUG(PORT_TC3),
-	[HPD_PORT_TC4] = GEN11_TC_HOTPLUG(PORT_TC4) | GEN11_TBT_HOTPLUG(PORT_TC4),
-	[HPD_PORT_TC5] = GEN11_TC_HOTPLUG(PORT_TC5) | GEN11_TBT_HOTPLUG(PORT_TC5),
-	[HPD_PORT_TC6] = GEN11_TC_HOTPLUG(PORT_TC6) | GEN11_TBT_HOTPLUG(PORT_TC6),
+	[HPD_PORT_TC1] = GEN11_TC_HOTPLUG(TC_PORT_1) | GEN11_TBT_HOTPLUG(TC_PORT_1),
+	[HPD_PORT_TC2] = GEN11_TC_HOTPLUG(TC_PORT_2) | GEN11_TBT_HOTPLUG(TC_PORT_2),
+	[HPD_PORT_TC3] = GEN11_TC_HOTPLUG(TC_PORT_3) | GEN11_TBT_HOTPLUG(TC_PORT_3),
+	[HPD_PORT_TC4] = GEN11_TC_HOTPLUG(TC_PORT_4) | GEN11_TBT_HOTPLUG(TC_PORT_4),
+	[HPD_PORT_TC5] = GEN11_TC_HOTPLUG(TC_PORT_5) | GEN11_TBT_HOTPLUG(TC_PORT_5),
+	[HPD_PORT_TC6] = GEN11_TC_HOTPLUG(TC_PORT_6) | GEN11_TBT_HOTPLUG(TC_PORT_6),
 };
 
 static const u32 hpd_icp[HPD_NUM_PINS] = {
 	[HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A),
 	[HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B),
 	[HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(PORT_C),
-	[HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(PORT_TC1),
-	[HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(PORT_TC2),
-	[HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(PORT_TC3),
-	[HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(PORT_TC4),
-	[HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(PORT_TC5),
-	[HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(PORT_TC6),
+	[HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(TC_PORT_1),
+	[HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(TC_PORT_2),
+	[HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(TC_PORT_3),
+	[HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(TC_PORT_4),
+	[HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(TC_PORT_5),
+	[HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(TC_PORT_6),
 };
 
 static const u32 hpd_sde_dg1[HPD_NUM_PINS] = {
@@ -1042,17 +1042,17 @@ static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
 {
 	switch (pin) {
 	case HPD_PORT_TC1:
-		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC1);
+		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_1);
 	case HPD_PORT_TC2:
-		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC2);
+		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_2);
 	case HPD_PORT_TC3:
-		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC3);
+		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_3);
 	case HPD_PORT_TC4:
-		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC4);
+		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_4);
 	case HPD_PORT_TC5:
-		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC5);
+		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_5);
 	case HPD_PORT_TC6:
-		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC6);
+		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_6);
 	default:
 		return false;
 	}
@@ -1092,17 +1092,17 @@ static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
 {
 	switch (pin) {
 	case HPD_PORT_TC1:
-		return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1);
+		return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_1);
 	case HPD_PORT_TC2:
-		return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2);
+		return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_2);
 	case HPD_PORT_TC3:
-		return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3);
+		return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_3);
 	case HPD_PORT_TC4:
-		return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4);
+		return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_4);
 	case HPD_PORT_TC5:
-		return val & ICP_TC_HPD_LONG_DETECT(PORT_TC5);
+		return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_5);
 	case HPD_PORT_TC6:
-		return val & ICP_TC_HPD_LONG_DETECT(PORT_TC6);
+		return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_6);
 	default:
 		return false;
 	}
@@ -1884,7 +1884,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
 		tc_hotplug_trigger = 0;
 	} else if (HAS_PCH_MCC(dev_priv)) {
 		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
-		tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(PORT_TC1);
+		tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(TC_PORT_1);
 	} else {
 		drm_WARN(&dev_priv->drm, !HAS_PCH_ICP(dev_priv),
 			 "Unrecognized PCH type 0x%x\n",
@@ -3252,7 +3252,7 @@ static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv,
 static void mcc_hpd_irq_setup(struct drm_i915_private *dev_priv)
 {
 	icp_hpd_irq_setup(dev_priv,
-			  ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE(PORT_TC1));
+			  ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE(TC_PORT_1));
 }
 
 /*
@@ -3286,21 +3286,21 @@ static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
 	u32 hotplug;
 
 	hotplug = I915_READ(GEN11_TC_HOTPLUG_CTL);
-	hotplug |= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) |
-		   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) |
-		   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) |
-		   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4) |
-		   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC5) |
-		   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC6);
+	hotplug |= GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_1) |
+		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_2) |
+		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_3) |
+		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_4) |
+		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_5) |
+		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_6);
 	I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug);
 
 	hotplug = I915_READ(GEN11_TBT_HOTPLUG_CTL);
-	hotplug |= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) |
-		   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) |
-		   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) |
-		   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4) |
-		   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC5) |
-		   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC6);
+	hotplug |= GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_1) |
+		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_2) |
+		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_3) |
+		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_4) |
+		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_5) |
+		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_6);
 	I915_WRITE(GEN11_TBT_HOTPLUG_CTL, hotplug);
 }
 
@@ -3675,7 +3675,7 @@ static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
 		icp_ddi_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK);
 	} else if (HAS_PCH_MCC(dev_priv)) {
 		icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
-		icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE(PORT_TC1));
+		icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE(TC_PORT_1));
 	} else {
 		icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
 		icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE_MASK);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8b021f77cb1f..4066cc509f27 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7891,19 +7891,19 @@ enum {
 #define GEN11_DE_HPD_IIR		_MMIO(0x44478)
 #define GEN11_DE_HPD_IER		_MMIO(0x4447c)
 #define  GEN11_TC_HOTPLUG(tc_port)		(1 << ((tc_port) + 16))
-#define  GEN11_DE_TC_HOTPLUG_MASK		(GEN11_TC_HOTPLUG(PORT_TC6) | \
-						 GEN11_TC_HOTPLUG(PORT_TC5) | \
-						 GEN11_TC_HOTPLUG(PORT_TC4) | \
-						 GEN11_TC_HOTPLUG(PORT_TC3) | \
-						 GEN11_TC_HOTPLUG(PORT_TC2) | \
-						 GEN11_TC_HOTPLUG(PORT_TC1))
+#define  GEN11_DE_TC_HOTPLUG_MASK		(GEN11_TC_HOTPLUG(TC_PORT_6) | \
+						 GEN11_TC_HOTPLUG(TC_PORT_5) | \
+						 GEN11_TC_HOTPLUG(TC_PORT_4) | \
+						 GEN11_TC_HOTPLUG(TC_PORT_3) | \
+						 GEN11_TC_HOTPLUG(TC_PORT_2) | \
+						 GEN11_TC_HOTPLUG(TC_PORT_1))
 #define  GEN11_TBT_HOTPLUG(tc_port)		(1 << (tc_port))
-#define  GEN11_DE_TBT_HOTPLUG_MASK		(GEN11_TBT_HOTPLUG(PORT_TC6) | \
-						 GEN11_TBT_HOTPLUG(PORT_TC5) | \
-						 GEN11_TBT_HOTPLUG(PORT_TC4) | \
-						 GEN11_TBT_HOTPLUG(PORT_TC3) | \
-						 GEN11_TBT_HOTPLUG(PORT_TC2) | \
-						 GEN11_TBT_HOTPLUG(PORT_TC1))
+#define  GEN11_DE_TBT_HOTPLUG_MASK		(GEN11_TBT_HOTPLUG(TC_PORT_6) | \
+						 GEN11_TBT_HOTPLUG(TC_PORT_5) | \
+						 GEN11_TBT_HOTPLUG(TC_PORT_4) | \
+						 GEN11_TBT_HOTPLUG(TC_PORT_3) | \
+						 GEN11_TBT_HOTPLUG(TC_PORT_2) | \
+						 GEN11_TBT_HOTPLUG(TC_PORT_1))
 
 #define GEN11_TBT_HOTPLUG_CTL				_MMIO(0x44030)
 #define GEN11_TC_HOTPLUG_CTL				_MMIO(0x44038)
@@ -8352,19 +8352,19 @@ enum {
 #define SDE_DDI_HOTPLUG_ICP(port)	(1 << ((port) + 16))
 #define SDE_DDI_MASK_ICP		(SDE_DDI_HOTPLUG_ICP(PORT_B) | \
 					 SDE_DDI_HOTPLUG_ICP(PORT_A))
-#define SDE_TC_MASK_ICP			(SDE_TC_HOTPLUG_ICP(PORT_TC4) | \
-					 SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
-					 SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
-					 SDE_TC_HOTPLUG_ICP(PORT_TC1))
+#define SDE_TC_MASK_ICP			(SDE_TC_HOTPLUG_ICP(TC_PORT_4) | \
+					 SDE_TC_HOTPLUG_ICP(TC_PORT_3) | \
+					 SDE_TC_HOTPLUG_ICP(TC_PORT_2) | \
+					 SDE_TC_HOTPLUG_ICP(TC_PORT_1))
 #define SDE_DDI_MASK_TGP		(SDE_DDI_HOTPLUG_ICP(PORT_C) | \
 					 SDE_DDI_HOTPLUG_ICP(PORT_B) | \
 					 SDE_DDI_HOTPLUG_ICP(PORT_A))
-#define SDE_TC_MASK_TGP			(SDE_TC_HOTPLUG_ICP(PORT_TC6) | \
-					 SDE_TC_HOTPLUG_ICP(PORT_TC5) | \
-					 SDE_TC_HOTPLUG_ICP(PORT_TC4) | \
-					 SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
-					 SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
-					 SDE_TC_HOTPLUG_ICP(PORT_TC1))
+#define SDE_TC_MASK_TGP			(SDE_TC_HOTPLUG_ICP(TC_PORT_6) | \
+					 SDE_TC_HOTPLUG_ICP(TC_PORT_5) | \
+					 SDE_TC_HOTPLUG_ICP(TC_PORT_4) | \
+					 SDE_TC_HOTPLUG_ICP(TC_PORT_3) | \
+					 SDE_TC_HOTPLUG_ICP(TC_PORT_2) | \
+					 SDE_TC_HOTPLUG_ICP(TC_PORT_1))
 #define SDE_DDI_MASK_DG1		(SDE_DDI_HOTPLUG_ICP(PORT_D) | \
 					 SDE_DDI_HOTPLUG_ICP(PORT_C) | \
 					 SDE_DDI_HOTPLUG_ICP(PORT_B) | \
@@ -8453,15 +8453,15 @@ enum {
 
 #define ICP_DDI_HPD_ENABLE_MASK		(SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
 					 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
-#define ICP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(PORT_TC4) | \
-					 ICP_TC_HPD_ENABLE(PORT_TC3) | \
-					 ICP_TC_HPD_ENABLE(PORT_TC2) | \
-					 ICP_TC_HPD_ENABLE(PORT_TC1))
+#define ICP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(TC_PORT_4) | \
+					 ICP_TC_HPD_ENABLE(TC_PORT_3) | \
+					 ICP_TC_HPD_ENABLE(TC_PORT_2) | \
+					 ICP_TC_HPD_ENABLE(TC_PORT_1))
 #define TGP_DDI_HPD_ENABLE_MASK		(SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_C) | \
 					 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
 					 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
-#define TGP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(PORT_TC6) | \
-					 ICP_TC_HPD_ENABLE(PORT_TC5) | \
+#define TGP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(TC_PORT_6) | \
+					 ICP_TC_HPD_ENABLE(TC_PORT_5) | \
 					 ICP_TC_HPD_ENABLE_MASK)
 #define DG1_DDI_HPD_ENABLE_MASK		(SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_D) | \
 					 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_C) | \
@@ -10327,9 +10327,9 @@ enum skl_power_gate {
 #define ICL_DPCLKA_CFGCR0			_MMIO(0x164280)
 #define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)	(1 << _PICK(phy, 10, 11, 24))
 #define  RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)	REG_BIT((phy) + 10)
-#define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)	(1 << ((tc_port) < PORT_TC4 ? \
+#define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)	(1 << ((tc_port) < TC_PORT_4 ? \
 						       (tc_port) + 12 : \
-						       (tc_port) - PORT_TC4 + 21))
+						       (tc_port) - TC_PORT_4 + 21))
 #define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)	((phy) * 2)
 #define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)	(3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
 #define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy)	((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
-- 
2.26.2

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[Intel-gfx] [PATCH v3 02/19] drm/i915: Add PORT_TCn aliases to enum port

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Since tgl the DDIs have been named A,B,C,TC1,TC2,TC3...
Add the appropriate enum values for the TC DDIs to enum port.

v2: Deal with rkl and dg1

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c    | 10 +++----
 drivers/gpu/drm/i915/display/intel_ddi.c     | 12 ++++-----
 drivers/gpu/drm/i915/display/intel_display.c | 28 ++++++++++----------
 drivers/gpu/drm/i915/display/intel_display.h |  8 ++++++
 4 files changed, 32 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 0a309645fe06..ff825be0ac88 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1688,17 +1688,15 @@ static enum port dvo_port_to_port(struct drm_i915_private *dev_priv,
 		[PORT_I] = { DVO_PORT_HDMII, DVO_PORT_DPI, -1 },
 	};
 	/*
-	 * Bspec lists the ports as A, B, C, D - however internally in our
-	 * driver we keep them as PORT_A, PORT_B, PORT_D and PORT_E so the
-	 * registers in Display Engine match the right offsets. Apply the
-	 * mapping here to translate from VBT to internal convention.
+	 * RKL VBT uses PHY based mapping. Combo PHYs A,B,C,D
+	 * map to DDI A,B,TC1,TC2 respectively.
 	 */
 	static const int rkl_port_mapping[][3] = {
 		[PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },
 		[PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },
 		[PORT_C] = { -1 },
-		[PORT_D] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
-		[PORT_E] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
+		[PORT_TC1] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
+		[PORT_TC2] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
 	};
 
 	if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 63380b166c25..24245157dcb9 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -5069,8 +5069,8 @@ static bool hti_uses_phy(struct drm_i915_private *i915, enum phy phy)
 static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv,
 				enum port port)
 {
-	if (port >= PORT_D)
-		return HPD_PORT_C + port - PORT_D;
+	if (port >= PORT_TC1)
+		return HPD_PORT_C + port - PORT_TC1;
 	else
 		return HPD_PORT_A + port - PORT_A;
 }
@@ -5078,8 +5078,8 @@ static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv,
 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv,
 				enum port port)
 {
-	if (port >= PORT_D)
-		return HPD_PORT_TC1 + port - PORT_D;
+	if (port >= PORT_TC1)
+		return HPD_PORT_TC1 + port - PORT_TC1;
 	else
 		return HPD_PORT_A + port - PORT_A;
 }
@@ -5090,8 +5090,8 @@ static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv,
 	if (HAS_PCH_TGP(dev_priv))
 		return tgl_hpd_pin(dev_priv, port);
 
-	if (port >= PORT_D)
-		return HPD_PORT_C + port - PORT_D;
+	if (port >= PORT_TC1)
+		return HPD_PORT_C + port - PORT_TC1;
 	else
 		return HPD_PORT_A + port - PORT_A;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index da2a91122d44..cddbda5303ff 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7463,12 +7463,12 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
 
 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
 {
-	if (IS_ROCKETLAKE(i915) && port >= PORT_D)
-		return (enum phy)port - 1;
+	if (IS_ROCKETLAKE(i915) && port >= PORT_TC1)
+		return PHY_C + port - PORT_TC1;
 	else if (IS_JSL_EHL(i915) && port == PORT_D)
 		return PHY_A;
 
-	return (enum phy)port;
+	return PHY_A + port - PORT_A;
 }
 
 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
@@ -7477,9 +7477,9 @@ enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
 		return TC_PORT_NONE;
 
 	if (INTEL_GEN(dev_priv) >= 12)
-		return port - PORT_D;
-
-	return port - PORT_C;
+		return TC_PORT_1 + port - PORT_TC1;
+	else
+		return TC_PORT_1 + port - PORT_C;
 }
 
 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
@@ -17216,17 +17216,17 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
 	if (IS_ROCKETLAKE(dev_priv)) {
 		intel_ddi_init(dev_priv, PORT_A);
 		intel_ddi_init(dev_priv, PORT_B);
-		intel_ddi_init(dev_priv, PORT_D);	/* DDI TC1 */
-		intel_ddi_init(dev_priv, PORT_E);	/* DDI TC2 */
+		intel_ddi_init(dev_priv, PORT_TC1);
+		intel_ddi_init(dev_priv, PORT_TC2);
 	} else if (INTEL_GEN(dev_priv) >= 12) {
 		intel_ddi_init(dev_priv, PORT_A);
 		intel_ddi_init(dev_priv, PORT_B);
-		intel_ddi_init(dev_priv, PORT_D);
-		intel_ddi_init(dev_priv, PORT_E);
-		intel_ddi_init(dev_priv, PORT_F);
-		intel_ddi_init(dev_priv, PORT_G);
-		intel_ddi_init(dev_priv, PORT_H);
-		intel_ddi_init(dev_priv, PORT_I);
+		intel_ddi_init(dev_priv, PORT_TC1);
+		intel_ddi_init(dev_priv, PORT_TC2);
+		intel_ddi_init(dev_priv, PORT_TC2);
+		intel_ddi_init(dev_priv, PORT_TC4);
+		intel_ddi_init(dev_priv, PORT_TC5);
+		intel_ddi_init(dev_priv, PORT_TC6);
 		icl_dsi_init(dev_priv);
 	} else if (IS_JSL_EHL(dev_priv)) {
 		intel_ddi_init(dev_priv, PORT_A);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 1b7ae1d507f2..747aec8e8580 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -208,6 +208,14 @@ enum port {
 	PORT_H,
 	PORT_I,
 
+	/* tgl+ */
+	PORT_TC1 = PORT_D,
+	PORT_TC2,
+	PORT_TC3,
+	PORT_TC4,
+	PORT_TC5,
+	PORT_TC6,
+
 	I915_MAX_PORTS
 };
 
-- 
2.26.2

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[Intel-gfx] [PATCH v3 03/19] drm/i915: Give DDI encoders even better names

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Let's pimp the DDI encoder->name to reflect what the spec calls them.
Ie. on pre-tgl DDI A-F, on tgl+ DDI A-C or DDI TC1-6.

Also since each encoder is really a combination of the DDI and the PHY
we include the PHY name as well.

ICL is a bit special since it already has the two different types
of DDIs (combo or TC) but it still calls them just DDI A-F regarless
of the type. For that let's add an extra "(TC)" note to remind
is which type of DDI it really is.

The code is darn ugly, but not sure there's much we can do about it.

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 27 ++++++++++++++++++++++--
 1 file changed, 25 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 24245157dcb9..19b16517a502 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -5174,8 +5174,31 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 
 	encoder = &dig_port->base;
 
-	drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
-			 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
+	if (INTEL_GEN(dev_priv) >= 12) {
+		enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
+
+		drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
+				 DRM_MODE_ENCODER_TMDS,
+				 "DDI %s%c/PHY %s%c",
+				 port >= PORT_TC1 ? "TC" : "",
+				 port >= PORT_TC1 ? port_name(port) : port - PORT_TC1 + '1',
+				 tc_port != TC_PORT_NONE ? "TC" : "",
+				 tc_port != TC_PORT_NONE ? phy_name(phy) : tc_port - TC_PORT_1 + '1');
+	} else if (INTEL_GEN(dev_priv) >= 11) {
+		enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
+
+		drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
+				 DRM_MODE_ENCODER_TMDS,
+				 "DDI %c%s/PHY %s%c",
+				 port_name(port),
+				 port >= PORT_C ? " (TC)" : "",
+				 tc_port != TC_PORT_NONE ? "TC" : "",
+				 tc_port != TC_PORT_NONE ? phy_name(phy) : tc_port - TC_PORT_1 + '1');
+	} else {
+		drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
+				 DRM_MODE_ENCODER_TMDS,
+				 "DDI %c/PHY %c", port_name(port),  phy_name(phy));
+	}
 
 	mutex_init(&dig_port->hdcp_mutex);
 	dig_port->num_hdcp_streams = 0;
-- 
2.26.2

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[Intel-gfx] [PATCH v3 04/19] drm/i915: Introduce AUX_CH_USBCn

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Just like with the DDIs tgl+ renamed the AUX CHs to reflect
the type of the DDI. Let's add the aliasing enum values for
the type-C AUX CHs.

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.h |  8 +++
 drivers/gpu/drm/i915/display/intel_dp.c      | 53 ++++++++++++++++++--
 2 files changed, 58 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 747aec8e8580..be774f216065 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -291,6 +291,14 @@ enum aux_ch {
 	AUX_CH_G,
 	AUX_CH_H,
 	AUX_CH_I,
+
+	/* tgl+ */
+	AUX_CH_USBC1 = AUX_CH_D,
+	AUX_CH_USBC2,
+	AUX_CH_USBC3,
+	AUX_CH_USBC4,
+	AUX_CH_USBC5,
+	AUX_CH_USBC6,
 };
 
 #define aux_ch_name(a) ((a) + 'A')
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 818daab252f3..b4f824383fe0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1774,7 +1774,6 @@ static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
 	case AUX_CH_D:
 	case AUX_CH_E:
 	case AUX_CH_F:
-	case AUX_CH_G:
 		return DP_AUX_CH_CTL(aux_ch);
 	default:
 		MISSING_CASE(aux_ch);
@@ -1795,7 +1794,52 @@ static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
 	case AUX_CH_D:
 	case AUX_CH_E:
 	case AUX_CH_F:
-	case AUX_CH_G:
+		return DP_AUX_CH_DATA(aux_ch, index);
+	default:
+		MISSING_CASE(aux_ch);
+		return DP_AUX_CH_DATA(AUX_CH_A, index);
+	}
+}
+
+static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp)
+{
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+	enum aux_ch aux_ch = dig_port->aux_ch;
+
+	switch (aux_ch) {
+	case AUX_CH_A:
+	case AUX_CH_B:
+	case AUX_CH_C:
+	case AUX_CH_USBC1:
+	case AUX_CH_USBC2:
+	case AUX_CH_USBC3:
+	case AUX_CH_USBC4:
+	case AUX_CH_USBC5:
+	case AUX_CH_USBC6:
+		return DP_AUX_CH_CTL(aux_ch);
+	default:
+		MISSING_CASE(aux_ch);
+		return DP_AUX_CH_CTL(AUX_CH_A);
+	}
+}
+
+static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index)
+{
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+	enum aux_ch aux_ch = dig_port->aux_ch;
+
+	switch (aux_ch) {
+	case AUX_CH_A:
+	case AUX_CH_B:
+	case AUX_CH_C:
+	case AUX_CH_USBC1:
+	case AUX_CH_USBC2:
+	case AUX_CH_USBC3:
+	case AUX_CH_USBC4:
+	case AUX_CH_USBC5:
+	case AUX_CH_USBC6:
 		return DP_AUX_CH_DATA(aux_ch, index);
 	default:
 		MISSING_CASE(aux_ch);
@@ -1816,7 +1860,10 @@ intel_dp_aux_init(struct intel_dp *intel_dp)
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct intel_encoder *encoder = &dig_port->base;
 
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (INTEL_GEN(dev_priv) >= 12) {
+		intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg;
+		intel_dp->aux_ch_data_reg = tgl_aux_data_reg;
+	} else if (INTEL_GEN(dev_priv) >= 9) {
 		intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
 		intel_dp->aux_ch_data_reg = skl_aux_data_reg;
 	} else if (HAS_PCH_SPLIT(dev_priv)) {
-- 
2.26.2

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[Intel-gfx] [PATCH v3 05/19] drm/i915: Pimp AUX CH names

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Let's make the AUX CH names match the spec (AUX A-F for pre-tgl,
AUX A-C or AUX USBC1-6 for tgl+). And while at it let's include
the full encoder name in the AUX CH name as well (as opposed to
just using port_name() which wouldn't give us the right thing on
tgl+).

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index b4f824383fe0..cf09aca7607b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1859,6 +1859,7 @@ intel_dp_aux_init(struct intel_dp *intel_dp)
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct intel_encoder *encoder = &dig_port->base;
+	enum aux_ch aux_ch = dig_port->aux_ch;
 
 	if (INTEL_GEN(dev_priv) >= 12) {
 		intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg;
@@ -1891,9 +1892,15 @@ intel_dp_aux_init(struct intel_dp *intel_dp)
 	drm_dp_aux_init(&intel_dp->aux);
 
 	/* Failure to allocate our preferred name is not critical */
-	intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/port %c",
-				       aux_ch_name(dig_port->aux_ch),
-				       port_name(encoder->port));
+	if (INTEL_GEN(dev_priv) >= 12 && aux_ch >= AUX_CH_USBC1)
+		intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX USBC%c/%s",
+					       aux_ch - AUX_CH_USBC1 + '1',
+					       encoder->base.name);
+	else
+		intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/%s",
+					       aux_ch_name(aux_ch),
+					       encoder->base.name);
+
 	intel_dp->aux.transfer = intel_dp_aux_transfer;
 }
 
-- 
2.26.2

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[Intel-gfx] [PATCH v3 06/19] drm/i915: Use AUX_CH_USBCn for the RKL VBT AUX CH setup

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

As with the VBT DVO port, RKL uses PHY based mapping for the
VBT AUX CH. Adjust the code to use the new AUX_USBCn names
and add a comment to explain the situation.

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index ff825be0ac88..4cc949b228f2 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2664,12 +2664,16 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv,
 		aux_ch = AUX_CH_B;
 		break;
 	case DP_AUX_C:
+		/*
+		 * RKL/DG1 VBT uses PHY based mapping. Combo PHYs A,B,C,D
+		 * map to DDI A,B,TC1,TC2 respectively.
+		 */
 		aux_ch = (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) ?
-			AUX_CH_D : AUX_CH_C;
+			AUX_CH_USBC1 : AUX_CH_C;
 		break;
 	case DP_AUX_D:
 		aux_ch = (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) ?
-			AUX_CH_E : AUX_CH_D;
+			AUX_CH_USBC2 : AUX_CH_D;
 		break;
 	case DP_AUX_E:
 		aux_ch = AUX_CH_E;
-- 
2.26.2

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[Intel-gfx] [PATCH v3 07/19] drm/i915: Parametrize BXT_DE_PORT_HP_DDI with hpd_pin

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Use hpd_pin to parametrize BXT_DE_PORT_HP_DDI() to make it clear
these have nothing to do with DDI ports or PHYs as such. The only
thing that matters is the HPD pin assignment.

v2: Remember the gvt

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/gvt/display.c | 13 +++++++------
 drivers/gpu/drm/i915/i915_irq.c    | 12 ++++++------
 drivers/gpu/drm/i915/i915_reg.h    | 12 ++++++------
 3 files changed, 19 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
index 7ba16ddfe75f..c124734e114c 100644
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -173,23 +173,24 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
 	int pipe;
 
 	if (IS_BROXTON(dev_priv)) {
-		vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~(BXT_DE_PORT_HP_DDIA |
-			BXT_DE_PORT_HP_DDIB |
-			BXT_DE_PORT_HP_DDIC);
+		vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
+			~(BXT_DE_PORT_HP_DDI(HPD_PORT_A) |
+			  BXT_DE_PORT_HP_DDI(HPD_PORT_B) |
+			  BXT_DE_PORT_HP_DDI(HPD_PORT_C));
 
 		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
 			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
-				BXT_DE_PORT_HP_DDIA;
+				BXT_DE_PORT_HP_DDI(HPD_PORT_A);
 		}
 
 		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
 			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
-				BXT_DE_PORT_HP_DDIB;
+				BXT_DE_PORT_HP_DDI(HPD_PORT_B);
 		}
 
 		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
 			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
-				BXT_DE_PORT_HP_DDIC;
+				BXT_DE_PORT_HP_DDI(HPD_PORT_C);
 		}
 
 		return;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index ffa191913139..252464d90575 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -126,9 +126,9 @@ static const u32 hpd_status_i915[HPD_NUM_PINS] = {
 };
 
 static const u32 hpd_bxt[HPD_NUM_PINS] = {
-	[HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
-	[HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
-	[HPD_PORT_C] = BXT_DE_PORT_HP_DDIC,
+	[HPD_PORT_A] = BXT_DE_PORT_HP_DDI(HPD_PORT_A),
+	[HPD_PORT_B] = BXT_DE_PORT_HP_DDI(HPD_PORT_B),
+	[HPD_PORT_C] = BXT_DE_PORT_HP_DDI(HPD_PORT_C),
 };
 
 static const u32 hpd_gen11[HPD_NUM_PINS] = {
@@ -3420,13 +3420,13 @@ static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
 	 * For BXT invert bit has to be set based on AOB design
 	 * for HPD detection logic, update it based on VBT fields.
 	 */
-	if ((enabled_irqs & BXT_DE_PORT_HP_DDIA) &&
+	if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_A)) &&
 	    intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
 		hotplug |= BXT_DDIA_HPD_INVERT;
-	if ((enabled_irqs & BXT_DE_PORT_HP_DDIB) &&
+	if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_B)) &&
 	    intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
 		hotplug |= BXT_DDIB_HPD_INVERT;
-	if ((enabled_irqs & BXT_DE_PORT_HP_DDIC) &&
+	if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_C)) &&
 	    intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
 		hotplug |= BXT_DDIC_HPD_INVERT;
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4066cc509f27..37038afd404f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7812,6 +7812,8 @@ enum {
 	(GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \
 	 GEN11_PIPE_PLANE5_FAULT)
 
+#define _HPD_PIN_DDI(hpd_pin)	((hpd_pin) - HPD_PORT_A)
+
 #define GEN8_DE_PORT_ISR _MMIO(0x44440)
 #define GEN8_DE_PORT_IMR _MMIO(0x44444)
 #define GEN8_DE_PORT_IIR _MMIO(0x44448)
@@ -7825,12 +7827,10 @@ enum {
 #define  GEN9_AUX_CHANNEL_B		(1 << 25)
 #define  DSI1_TE			(1 << 24)
 #define  DSI0_TE			(1 << 23)
-#define  BXT_DE_PORT_HP_DDIC		(1 << 5)
-#define  BXT_DE_PORT_HP_DDIB		(1 << 4)
-#define  BXT_DE_PORT_HP_DDIA		(1 << 3)
-#define  BXT_DE_PORT_HOTPLUG_MASK	(BXT_DE_PORT_HP_DDIA | \
-					 BXT_DE_PORT_HP_DDIB | \
-					 BXT_DE_PORT_HP_DDIC)
+#define  BXT_DE_PORT_HP_DDI(hpd_pin)	REG_BIT(3 + _HPD_PIN_DDI(hpd_pin))
+#define  BXT_DE_PORT_HOTPLUG_MASK	(BXT_DE_PORT_HP_DDI(HPD_PORT_A) | \
+					 BXT_DE_PORT_HP_DDI(HPD_PORT_B) | \
+					 BXT_DE_PORT_HP_DDI(HPD_PORT_C))
 #define  GEN8_PORT_DP_A_HOTPLUG		(1 << 3)
 #define  BXT_DE_PORT_GMBUS		(1 << 1)
 #define  GEN8_AUX_CHANNEL_A		(1 << 0)
-- 
2.26.2

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[Intel-gfx] [PATCH v3 08/19] drm/i915: Introduce GEN8_DE_PORT_HOTPLUG()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Unify the BDW/BXT hotplug bits. BDW only has port A, but that
matches BXT port A so we can shar the same macro for both.

v2: Remember the gvt

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/gvt/display.c | 14 +++++++-------
 drivers/gpu/drm/i915/i915_irq.c    | 18 +++++++++---------
 drivers/gpu/drm/i915/i915_reg.h    | 10 +++++-----
 3 files changed, 21 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
index c124734e114c..5b5c71a0b4af 100644
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -174,23 +174,23 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
 
 	if (IS_BROXTON(dev_priv)) {
 		vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
-			~(BXT_DE_PORT_HP_DDI(HPD_PORT_A) |
-			  BXT_DE_PORT_HP_DDI(HPD_PORT_B) |
-			  BXT_DE_PORT_HP_DDI(HPD_PORT_C));
+			~(GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) |
+			  GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) |
+			  GEN8_DE_PORT_HOTPLUG(HPD_PORT_C));
 
 		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
 			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
-				BXT_DE_PORT_HP_DDI(HPD_PORT_A);
+				GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);
 		}
 
 		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
 			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
-				BXT_DE_PORT_HP_DDI(HPD_PORT_B);
+				GEN8_DE_PORT_HOTPLUG(HPD_PORT_B);
 		}
 
 		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
 			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
-				BXT_DE_PORT_HP_DDI(HPD_PORT_C);
+				GEN8_DE_PORT_HOTPLUG(HPD_PORT_C);
 		}
 
 		return;
@@ -328,7 +328,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
 	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
 		if (IS_BROADWELL(dev_priv))
 			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
-				GEN8_PORT_DP_A_HOTPLUG;
+				GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);
 		else
 			vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT;
 
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 252464d90575..216d6247b30a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -71,7 +71,7 @@ static const u32 hpd_ivb[HPD_NUM_PINS] = {
 };
 
 static const u32 hpd_bdw[HPD_NUM_PINS] = {
-	[HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
+	[HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A),
 };
 
 static const u32 hpd_ibx[HPD_NUM_PINS] = {
@@ -126,9 +126,9 @@ static const u32 hpd_status_i915[HPD_NUM_PINS] = {
 };
 
 static const u32 hpd_bxt[HPD_NUM_PINS] = {
-	[HPD_PORT_A] = BXT_DE_PORT_HP_DDI(HPD_PORT_A),
-	[HPD_PORT_B] = BXT_DE_PORT_HP_DDI(HPD_PORT_B),
-	[HPD_PORT_C] = BXT_DE_PORT_HP_DDI(HPD_PORT_C),
+	[HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A),
+	[HPD_PORT_B] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_B),
+	[HPD_PORT_C] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_C),
 };
 
 static const u32 hpd_gen11[HPD_NUM_PINS] = {
@@ -2379,7 +2379,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 					found = true;
 				}
 			} else if (IS_BROADWELL(dev_priv)) {
-				tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
+				tmp_mask = iir & BDW_DE_PORT_HOTPLUG_MASK;
 				if (tmp_mask) {
 					ilk_hpd_irq_handler(dev_priv, tmp_mask);
 					found = true;
@@ -3420,13 +3420,13 @@ static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
 	 * For BXT invert bit has to be set based on AOB design
 	 * for HPD detection logic, update it based on VBT fields.
 	 */
-	if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_A)) &&
+	if ((enabled_irqs & GEN8_DE_PORT_HOTPLUG(HPD_PORT_A)) &&
 	    intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
 		hotplug |= BXT_DDIA_HPD_INVERT;
-	if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_B)) &&
+	if ((enabled_irqs & GEN8_DE_PORT_HOTPLUG(HPD_PORT_B)) &&
 	    intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
 		hotplug |= BXT_DDIB_HPD_INVERT;
-	if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_C)) &&
+	if ((enabled_irqs & GEN8_DE_PORT_HOTPLUG(HPD_PORT_C)) &&
 	    intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
 		hotplug |= BXT_DDIC_HPD_INVERT;
 
@@ -3595,7 +3595,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
 	if (IS_GEN9_LP(dev_priv))
 		de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
 	else if (IS_BROADWELL(dev_priv))
-		de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
+		de_port_enables |= BDW_DE_PORT_HOTPLUG_MASK;
 
 	if (INTEL_GEN(dev_priv) >= 12) {
 		enum transcoder trans;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 37038afd404f..950d2bd7d7a8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7827,11 +7827,11 @@ enum {
 #define  GEN9_AUX_CHANNEL_B		(1 << 25)
 #define  DSI1_TE			(1 << 24)
 #define  DSI0_TE			(1 << 23)
-#define  BXT_DE_PORT_HP_DDI(hpd_pin)	REG_BIT(3 + _HPD_PIN_DDI(hpd_pin))
-#define  BXT_DE_PORT_HOTPLUG_MASK	(BXT_DE_PORT_HP_DDI(HPD_PORT_A) | \
-					 BXT_DE_PORT_HP_DDI(HPD_PORT_B) | \
-					 BXT_DE_PORT_HP_DDI(HPD_PORT_C))
-#define  GEN8_PORT_DP_A_HOTPLUG		(1 << 3)
+#define  GEN8_DE_PORT_HOTPLUG(hpd_pin)	REG_BIT(3 + _HPD_PIN_DDI(hpd_pin))
+#define  BXT_DE_PORT_HOTPLUG_MASK	(GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | \
+					 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | \
+					 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C))
+#define  BDW_DE_PORT_HOTPLUG_MASK	GEN8_DE_PORT_HOTPLUG(HPD_PORT_A)
 #define  BXT_DE_PORT_GMBUS		(1 << 1)
 #define  GEN8_AUX_CHANNEL_A		(1 << 0)
 #define  TGL_DE_PORT_AUX_USBC6		(1 << 13)
-- 
2.26.2

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[Intel-gfx] [PATCH v3 09/19] drm/i915: s/port/hpd_pin/ for icp+ ddi hpd bits

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Use hpd_pin instead of port in the parametrized ICP+ DDI HPD
macros. Makes it clear what these refer to.

v2: Handle DG1

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 22 +++++++--------
 drivers/gpu/drm/i915/i915_reg.h | 50 ++++++++++++++++-----------------
 2 files changed, 36 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 216d6247b30a..d98420b62107 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -141,9 +141,9 @@ static const u32 hpd_gen11[HPD_NUM_PINS] = {
 };
 
 static const u32 hpd_icp[HPD_NUM_PINS] = {
-	[HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A),
-	[HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B),
-	[HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(PORT_C),
+	[HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A),
+	[HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
+	[HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
 	[HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(TC_PORT_1),
 	[HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(TC_PORT_2),
 	[HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(TC_PORT_3),
@@ -153,10 +153,10 @@ static const u32 hpd_icp[HPD_NUM_PINS] = {
 };
 
 static const u32 hpd_sde_dg1[HPD_NUM_PINS] = {
-	[HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A),
-	[HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B),
-	[HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(PORT_C),
-	[HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(PORT_D),
+	[HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A),
+	[HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
+	[HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
+	[HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_D),
 };
 
 static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
@@ -1076,13 +1076,13 @@ static bool icp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
 {
 	switch (pin) {
 	case HPD_PORT_A:
-		return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_A);
+		return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(HPD_PORT_A);
 	case HPD_PORT_B:
-		return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_B);
+		return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(HPD_PORT_B);
 	case HPD_PORT_C:
-		return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_C);
+		return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(HPD_PORT_C);
 	case HPD_PORT_D:
-		return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_D);
+		return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(HPD_PORT_D);
 	default:
 		return false;
 	}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 950d2bd7d7a8..eb36355ce913 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8349,26 +8349,26 @@ enum {
 /* south display engine interrupt: ICP/TGP */
 #define SDE_GMBUS_ICP			(1 << 23)
 #define SDE_TC_HOTPLUG_ICP(tc_port)	(1 << ((tc_port) + 24))
-#define SDE_DDI_HOTPLUG_ICP(port)	(1 << ((port) + 16))
-#define SDE_DDI_MASK_ICP		(SDE_DDI_HOTPLUG_ICP(PORT_B) | \
-					 SDE_DDI_HOTPLUG_ICP(PORT_A))
+#define SDE_DDI_HOTPLUG_ICP(hpd_pin)	REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
+#define SDE_DDI_MASK_ICP		(SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
+					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
 #define SDE_TC_MASK_ICP			(SDE_TC_HOTPLUG_ICP(TC_PORT_4) | \
 					 SDE_TC_HOTPLUG_ICP(TC_PORT_3) | \
 					 SDE_TC_HOTPLUG_ICP(TC_PORT_2) | \
 					 SDE_TC_HOTPLUG_ICP(TC_PORT_1))
-#define SDE_DDI_MASK_TGP		(SDE_DDI_HOTPLUG_ICP(PORT_C) | \
-					 SDE_DDI_HOTPLUG_ICP(PORT_B) | \
-					 SDE_DDI_HOTPLUG_ICP(PORT_A))
+#define SDE_DDI_MASK_TGP		(SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
+					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
+					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
 #define SDE_TC_MASK_TGP			(SDE_TC_HOTPLUG_ICP(TC_PORT_6) | \
 					 SDE_TC_HOTPLUG_ICP(TC_PORT_5) | \
 					 SDE_TC_HOTPLUG_ICP(TC_PORT_4) | \
 					 SDE_TC_HOTPLUG_ICP(TC_PORT_3) | \
 					 SDE_TC_HOTPLUG_ICP(TC_PORT_2) | \
 					 SDE_TC_HOTPLUG_ICP(TC_PORT_1))
-#define SDE_DDI_MASK_DG1		(SDE_DDI_HOTPLUG_ICP(PORT_D) | \
-					 SDE_DDI_HOTPLUG_ICP(PORT_C) | \
-					 SDE_DDI_HOTPLUG_ICP(PORT_B) | \
-					 SDE_DDI_HOTPLUG_ICP(PORT_A))
+#define SDE_DDI_MASK_DG1		(SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \
+					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
+					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
+					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
 
 #define SDEISR  _MMIO(0xc4000)
 #define SDEIMR  _MMIO(0xc4004)
@@ -8436,12 +8436,12 @@ enum {
  */
 
 #define SHOTPLUG_CTL_DDI				_MMIO(0xc4030)
-#define   SHOTPLUG_CTL_DDI_HPD_ENABLE(port)		(0x8 << (4 * (port)))
-#define   SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(port)	(0x3 << (4 * (port)))
-#define   SHOTPLUG_CTL_DDI_HPD_NO_DETECT(port)		(0x0 << (4 * (port)))
-#define   SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(port)	(0x1 << (4 * (port)))
-#define   SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(port)	(0x2 << (4 * (port)))
-#define   SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(port)	(0x3 << (4 * (port)))
+#define   SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin)			(0x8 << (_HPD_PIN_DDI(hpd_pin) * 4))
+#define   SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(hpd_pin)		(0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
+#define   SHOTPLUG_CTL_DDI_HPD_NO_DETECT(hpd_pin)		(0x0 << (_HPD_PIN_DDI(hpd_pin) * 4))
+#define   SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(hpd_pin)		(0x1 << (_HPD_PIN_DDI(hpd_pin) * 4))
+#define   SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(hpd_pin)		(0x2 << (_HPD_PIN_DDI(hpd_pin) * 4))
+#define   SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(hpd_pin)	(0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
 
 #define SHOTPLUG_CTL_TC				_MMIO(0xc4034)
 #define   ICP_TC_HPD_ENABLE(tc_port)		(8 << (tc_port) * 4)
@@ -8451,22 +8451,22 @@ enum {
 #define SHPD_FILTER_CNT				_MMIO(0xc4038)
 #define   SHPD_FILTER_CNT_500_ADJ		0x001D9
 
-#define ICP_DDI_HPD_ENABLE_MASK		(SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
-					 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
+#define ICP_DDI_HPD_ENABLE_MASK		(SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) | \
+					 SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A))
 #define ICP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(TC_PORT_4) | \
 					 ICP_TC_HPD_ENABLE(TC_PORT_3) | \
 					 ICP_TC_HPD_ENABLE(TC_PORT_2) | \
 					 ICP_TC_HPD_ENABLE(TC_PORT_1))
-#define TGP_DDI_HPD_ENABLE_MASK		(SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_C) | \
-					 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
-					 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
+#define TGP_DDI_HPD_ENABLE_MASK		(SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_C) | \
+					 SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) | \
+					 SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A))
 #define TGP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(TC_PORT_6) | \
 					 ICP_TC_HPD_ENABLE(TC_PORT_5) | \
 					 ICP_TC_HPD_ENABLE_MASK)
-#define DG1_DDI_HPD_ENABLE_MASK		(SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_D) | \
-					 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_C) | \
-					 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
-					 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
+#define DG1_DDI_HPD_ENABLE_MASK		(SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_D) | \
+					 SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_C) | \
+					 SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) | \
+					 SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A))
 
 #define _PCH_DPLL_A              0xc6014
 #define _PCH_DPLL_B              0xc6018
-- 
2.26.2

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[Intel-gfx] [PATCH v3 10/19] drm/i915: s/tc_port/hpd_pin/ in GEN11_{TC, TBT}_HOTPLUG()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Use hpd_pin instead of tc_port in the GEN11_{TC,TBT}_HOTPLUG()
to make it clear what they refer to.

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 48 ++++++++++++++++-----------------
 drivers/gpu/drm/i915/i915_reg.h | 37 ++++++++++++-------------
 2 files changed, 43 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d98420b62107..d3f35d9a02dd 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -132,12 +132,12 @@ static const u32 hpd_bxt[HPD_NUM_PINS] = {
 };
 
 static const u32 hpd_gen11[HPD_NUM_PINS] = {
-	[HPD_PORT_TC1] = GEN11_TC_HOTPLUG(TC_PORT_1) | GEN11_TBT_HOTPLUG(TC_PORT_1),
-	[HPD_PORT_TC2] = GEN11_TC_HOTPLUG(TC_PORT_2) | GEN11_TBT_HOTPLUG(TC_PORT_2),
-	[HPD_PORT_TC3] = GEN11_TC_HOTPLUG(TC_PORT_3) | GEN11_TBT_HOTPLUG(TC_PORT_3),
-	[HPD_PORT_TC4] = GEN11_TC_HOTPLUG(TC_PORT_4) | GEN11_TBT_HOTPLUG(TC_PORT_4),
-	[HPD_PORT_TC5] = GEN11_TC_HOTPLUG(TC_PORT_5) | GEN11_TBT_HOTPLUG(TC_PORT_5),
-	[HPD_PORT_TC6] = GEN11_TC_HOTPLUG(TC_PORT_6) | GEN11_TBT_HOTPLUG(TC_PORT_6),
+	[HPD_PORT_TC1] = GEN11_TC_HOTPLUG(HPD_PORT_TC1) | GEN11_TBT_HOTPLUG(HPD_PORT_TC1),
+	[HPD_PORT_TC2] = GEN11_TC_HOTPLUG(HPD_PORT_TC2) | GEN11_TBT_HOTPLUG(HPD_PORT_TC2),
+	[HPD_PORT_TC3] = GEN11_TC_HOTPLUG(HPD_PORT_TC3) | GEN11_TBT_HOTPLUG(HPD_PORT_TC3),
+	[HPD_PORT_TC4] = GEN11_TC_HOTPLUG(HPD_PORT_TC4) | GEN11_TBT_HOTPLUG(HPD_PORT_TC4),
+	[HPD_PORT_TC5] = GEN11_TC_HOTPLUG(HPD_PORT_TC5) | GEN11_TBT_HOTPLUG(HPD_PORT_TC5),
+	[HPD_PORT_TC6] = GEN11_TC_HOTPLUG(HPD_PORT_TC6) | GEN11_TBT_HOTPLUG(HPD_PORT_TC6),
 };
 
 static const u32 hpd_icp[HPD_NUM_PINS] = {
@@ -1042,17 +1042,17 @@ static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
 {
 	switch (pin) {
 	case HPD_PORT_TC1:
-		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_1);
+		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC1);
 	case HPD_PORT_TC2:
-		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_2);
+		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC2);
 	case HPD_PORT_TC3:
-		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_3);
+		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC3);
 	case HPD_PORT_TC4:
-		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_4);
+		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC4);
 	case HPD_PORT_TC5:
-		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_5);
+		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC5);
 	case HPD_PORT_TC6:
-		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_6);
+		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC6);
 	default:
 		return false;
 	}
@@ -3286,21 +3286,21 @@ static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
 	u32 hotplug;
 
 	hotplug = I915_READ(GEN11_TC_HOTPLUG_CTL);
-	hotplug |= GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_1) |
-		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_2) |
-		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_3) |
-		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_4) |
-		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_5) |
-		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_6);
+	hotplug |= GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) |
+		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) |
+		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) |
+		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) |
+		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) |
+		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6);
 	I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug);
 
 	hotplug = I915_READ(GEN11_TBT_HOTPLUG_CTL);
-	hotplug |= GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_1) |
-		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_2) |
-		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_3) |
-		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_4) |
-		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_5) |
-		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_6);
+	hotplug |= GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) |
+		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) |
+		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) |
+		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) |
+		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) |
+		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6);
 	I915_WRITE(GEN11_TBT_HOTPLUG_CTL, hotplug);
 }
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index eb36355ce913..cc43e2c5088b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7813,6 +7813,7 @@ enum {
 	 GEN11_PIPE_PLANE5_FAULT)
 
 #define _HPD_PIN_DDI(hpd_pin)	((hpd_pin) - HPD_PORT_A)
+#define _HPD_PIN_TC(hpd_pin)	((hpd_pin) - HPD_PORT_TC1)
 
 #define GEN8_DE_PORT_ISR _MMIO(0x44440)
 #define GEN8_DE_PORT_IMR _MMIO(0x44444)
@@ -7890,27 +7891,27 @@ enum {
 #define GEN11_DE_HPD_IMR		_MMIO(0x44474)
 #define GEN11_DE_HPD_IIR		_MMIO(0x44478)
 #define GEN11_DE_HPD_IER		_MMIO(0x4447c)
-#define  GEN11_TC_HOTPLUG(tc_port)		(1 << ((tc_port) + 16))
-#define  GEN11_DE_TC_HOTPLUG_MASK		(GEN11_TC_HOTPLUG(TC_PORT_6) | \
-						 GEN11_TC_HOTPLUG(TC_PORT_5) | \
-						 GEN11_TC_HOTPLUG(TC_PORT_4) | \
-						 GEN11_TC_HOTPLUG(TC_PORT_3) | \
-						 GEN11_TC_HOTPLUG(TC_PORT_2) | \
-						 GEN11_TC_HOTPLUG(TC_PORT_1))
-#define  GEN11_TBT_HOTPLUG(tc_port)		(1 << (tc_port))
-#define  GEN11_DE_TBT_HOTPLUG_MASK		(GEN11_TBT_HOTPLUG(TC_PORT_6) | \
-						 GEN11_TBT_HOTPLUG(TC_PORT_5) | \
-						 GEN11_TBT_HOTPLUG(TC_PORT_4) | \
-						 GEN11_TBT_HOTPLUG(TC_PORT_3) | \
-						 GEN11_TBT_HOTPLUG(TC_PORT_2) | \
-						 GEN11_TBT_HOTPLUG(TC_PORT_1))
+#define  GEN11_TC_HOTPLUG(hpd_pin)		REG_BIT(16 + _HPD_PIN_TC(hpd_pin))
+#define  GEN11_DE_TC_HOTPLUG_MASK		(GEN11_TC_HOTPLUG(HPD_PORT_TC6) | \
+						 GEN11_TC_HOTPLUG(HPD_PORT_TC5) | \
+						 GEN11_TC_HOTPLUG(HPD_PORT_TC4) | \
+						 GEN11_TC_HOTPLUG(HPD_PORT_TC3) | \
+						 GEN11_TC_HOTPLUG(HPD_PORT_TC2) | \
+						 GEN11_TC_HOTPLUG(HPD_PORT_TC1))
+#define  GEN11_TBT_HOTPLUG(hpd_pin)		REG_BIT(_HPD_PIN_TC(hpd_pin))
+#define  GEN11_DE_TBT_HOTPLUG_MASK		(GEN11_TBT_HOTPLUG(HPD_PORT_TC6) | \
+						 GEN11_TBT_HOTPLUG(HPD_PORT_TC5) | \
+						 GEN11_TBT_HOTPLUG(HPD_PORT_TC4) | \
+						 GEN11_TBT_HOTPLUG(HPD_PORT_TC3) | \
+						 GEN11_TBT_HOTPLUG(HPD_PORT_TC2) | \
+						 GEN11_TBT_HOTPLUG(HPD_PORT_TC1))
 
 #define GEN11_TBT_HOTPLUG_CTL				_MMIO(0x44030)
 #define GEN11_TC_HOTPLUG_CTL				_MMIO(0x44038)
-#define  GEN11_HOTPLUG_CTL_ENABLE(tc_port)		(8 << (tc_port) * 4)
-#define  GEN11_HOTPLUG_CTL_LONG_DETECT(tc_port)		(2 << (tc_port) * 4)
-#define  GEN11_HOTPLUG_CTL_SHORT_DETECT(tc_port)	(1 << (tc_port) * 4)
-#define  GEN11_HOTPLUG_CTL_NO_DETECT(tc_port)		(0 << (tc_port) * 4)
+#define  GEN11_HOTPLUG_CTL_ENABLE(hpd_pin)		(8 << (_HPD_PIN_TC(hpd_pin) * 4))
+#define  GEN11_HOTPLUG_CTL_LONG_DETECT(hpd_pin)		(2 << (_HPD_PIN_TC(hpd_pin) * 4))
+#define  GEN11_HOTPLUG_CTL_SHORT_DETECT(hpd_pin)	(1 << (_HPD_PIN_TC(hpd_pin) * 4))
+#define  GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin)		(0 << (_HPD_PIN_TC(hpd_pin) * 4))
 
 #define GEN11_GT_INTR_DW0		_MMIO(0x190018)
 #define  GEN11_CSME			(31)
-- 
2.26.2

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[Intel-gfx] [PATCH v3 11/19] drm/i915: s/tc_port/hpd_pin/ in icp+ TC hotplug bits

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Parametrize the icp+ TC HPD bits using hpd_pin rather than
tc_port so it's clear what kind of an animal we're dealing
with.

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 30 ++++++++++++-------------
 drivers/gpu/drm/i915/i915_reg.h | 40 ++++++++++++++++-----------------
 2 files changed, 35 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d3f35d9a02dd..70a37d4ca9e5 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -144,12 +144,12 @@ static const u32 hpd_icp[HPD_NUM_PINS] = {
 	[HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A),
 	[HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
 	[HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
-	[HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(TC_PORT_1),
-	[HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(TC_PORT_2),
-	[HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(TC_PORT_3),
-	[HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(TC_PORT_4),
-	[HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(TC_PORT_5),
-	[HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(TC_PORT_6),
+	[HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1),
+	[HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2),
+	[HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3),
+	[HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4),
+	[HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5),
+	[HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6),
 };
 
 static const u32 hpd_sde_dg1[HPD_NUM_PINS] = {
@@ -1092,17 +1092,17 @@ static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
 {
 	switch (pin) {
 	case HPD_PORT_TC1:
-		return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_1);
+		return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC1);
 	case HPD_PORT_TC2:
-		return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_2);
+		return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC2);
 	case HPD_PORT_TC3:
-		return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_3);
+		return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC3);
 	case HPD_PORT_TC4:
-		return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_4);
+		return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC4);
 	case HPD_PORT_TC5:
-		return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_5);
+		return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC5);
 	case HPD_PORT_TC6:
-		return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_6);
+		return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC6);
 	default:
 		return false;
 	}
@@ -1884,7 +1884,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
 		tc_hotplug_trigger = 0;
 	} else if (HAS_PCH_MCC(dev_priv)) {
 		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
-		tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(TC_PORT_1);
+		tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1);
 	} else {
 		drm_WARN(&dev_priv->drm, !HAS_PCH_ICP(dev_priv),
 			 "Unrecognized PCH type 0x%x\n",
@@ -3252,7 +3252,7 @@ static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv,
 static void mcc_hpd_irq_setup(struct drm_i915_private *dev_priv)
 {
 	icp_hpd_irq_setup(dev_priv,
-			  ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE(TC_PORT_1));
+			  ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE(HPD_PORT_TC1));
 }
 
 /*
@@ -3675,7 +3675,7 @@ static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
 		icp_ddi_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK);
 	} else if (HAS_PCH_MCC(dev_priv)) {
 		icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
-		icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE(TC_PORT_1));
+		icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE(HPD_PORT_TC1));
 	} else {
 		icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
 		icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE_MASK);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cc43e2c5088b..9e68ba254d51 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8349,23 +8349,23 @@ enum {
 
 /* south display engine interrupt: ICP/TGP */
 #define SDE_GMBUS_ICP			(1 << 23)
-#define SDE_TC_HOTPLUG_ICP(tc_port)	(1 << ((tc_port) + 24))
+#define SDE_TC_HOTPLUG_ICP(hpd_pin)	REG_BIT(24 + _HPD_PIN_TC(hpd_pin))
 #define SDE_DDI_HOTPLUG_ICP(hpd_pin)	REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
 #define SDE_DDI_MASK_ICP		(SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
 					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
-#define SDE_TC_MASK_ICP			(SDE_TC_HOTPLUG_ICP(TC_PORT_4) | \
-					 SDE_TC_HOTPLUG_ICP(TC_PORT_3) | \
-					 SDE_TC_HOTPLUG_ICP(TC_PORT_2) | \
-					 SDE_TC_HOTPLUG_ICP(TC_PORT_1))
+#define SDE_TC_MASK_ICP			(SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \
+					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \
+					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \
+					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1))
 #define SDE_DDI_MASK_TGP		(SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
 					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
 					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
-#define SDE_TC_MASK_TGP			(SDE_TC_HOTPLUG_ICP(TC_PORT_6) | \
-					 SDE_TC_HOTPLUG_ICP(TC_PORT_5) | \
-					 SDE_TC_HOTPLUG_ICP(TC_PORT_4) | \
-					 SDE_TC_HOTPLUG_ICP(TC_PORT_3) | \
-					 SDE_TC_HOTPLUG_ICP(TC_PORT_2) | \
-					 SDE_TC_HOTPLUG_ICP(TC_PORT_1))
+#define SDE_TC_MASK_TGP			(SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \
+					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5) | \
+					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \
+					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \
+					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \
+					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1))
 #define SDE_DDI_MASK_DG1		(SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \
 					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
 					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
@@ -8445,24 +8445,24 @@ enum {
 #define   SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(hpd_pin)	(0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
 
 #define SHOTPLUG_CTL_TC				_MMIO(0xc4034)
-#define   ICP_TC_HPD_ENABLE(tc_port)		(8 << (tc_port) * 4)
-#define   ICP_TC_HPD_LONG_DETECT(tc_port)	(2 << (tc_port) * 4)
-#define   ICP_TC_HPD_SHORT_DETECT(tc_port)	(1 << (tc_port) * 4)
+#define   ICP_TC_HPD_ENABLE(hpd_pin)		(8 << (_HPD_PIN_TC(hpd_pin) * 4))
+#define   ICP_TC_HPD_LONG_DETECT(hpd_pin)	(2 << (_HPD_PIN_TC(hpd_pin) * 4))
+#define   ICP_TC_HPD_SHORT_DETECT(hpd_pin)	(1 << (_HPD_PIN_TC(hpd_pin) * 4))
 
 #define SHPD_FILTER_CNT				_MMIO(0xc4038)
 #define   SHPD_FILTER_CNT_500_ADJ		0x001D9
 
 #define ICP_DDI_HPD_ENABLE_MASK		(SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) | \
 					 SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A))
-#define ICP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(TC_PORT_4) | \
-					 ICP_TC_HPD_ENABLE(TC_PORT_3) | \
-					 ICP_TC_HPD_ENABLE(TC_PORT_2) | \
-					 ICP_TC_HPD_ENABLE(TC_PORT_1))
+#define ICP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(HPD_PORT_TC4) | \
+					 ICP_TC_HPD_ENABLE(HPD_PORT_TC3) | \
+					 ICP_TC_HPD_ENABLE(HPD_PORT_TC2) | \
+					 ICP_TC_HPD_ENABLE(HPD_PORT_TC1))
 #define TGP_DDI_HPD_ENABLE_MASK		(SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_C) | \
 					 SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) | \
 					 SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A))
-#define TGP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(TC_PORT_6) | \
-					 ICP_TC_HPD_ENABLE(TC_PORT_5) | \
+#define TGP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(HPD_PORT_TC6) | \
+					 ICP_TC_HPD_ENABLE(HPD_PORT_TC5) | \
 					 ICP_TC_HPD_ENABLE_MASK)
 #define DG1_DDI_HPD_ENABLE_MASK		(SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_D) | \
 					 SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_C) | \
-- 
2.26.2

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[Intel-gfx] [PATCH v3 12/19] drm/i915: Relocate intel_hpd_{enabled, hotplug}_irqs()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Move intel_hpd_{enabled,hotplug}_irqs() closes to the beginning of
the file so we can use them in more places. No functional changes.

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 50 ++++++++++++++++-----------------
 1 file changed, 25 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 70a37d4ca9e5..b355e0307a8a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1205,6 +1205,31 @@ static void intel_get_hpd_pins(struct drm_i915_private *dev_priv,
 
 }
 
+static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
+				  const u32 hpd[HPD_NUM_PINS])
+{
+	struct intel_encoder *encoder;
+	u32 enabled_irqs = 0;
+
+	for_each_intel_encoder(&dev_priv->drm, encoder)
+		if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
+			enabled_irqs |= hpd[encoder->hpd_pin];
+
+	return enabled_irqs;
+}
+
+static u32 intel_hpd_hotplug_irqs(struct drm_i915_private *dev_priv,
+				  const u32 hpd[HPD_NUM_PINS])
+{
+	struct intel_encoder *encoder;
+	u32 hotplug_irqs = 0;
+
+	for_each_intel_encoder(&dev_priv->drm, encoder)
+		hotplug_irqs |= hpd[encoder->hpd_pin];
+
+	return hotplug_irqs;
+}
+
 static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
 {
 	wake_up_all(&dev_priv->gmbus_wait_queue);
@@ -3145,31 +3170,6 @@ static void cherryview_irq_reset(struct drm_i915_private *dev_priv)
 	spin_unlock_irq(&dev_priv->irq_lock);
 }
 
-static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
-				  const u32 hpd[HPD_NUM_PINS])
-{
-	struct intel_encoder *encoder;
-	u32 enabled_irqs = 0;
-
-	for_each_intel_encoder(&dev_priv->drm, encoder)
-		if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
-			enabled_irqs |= hpd[encoder->hpd_pin];
-
-	return enabled_irqs;
-}
-
-static u32 intel_hpd_hotplug_irqs(struct drm_i915_private *dev_priv,
-				  const u32 hpd[HPD_NUM_PINS])
-{
-	struct intel_encoder *encoder;
-	u32 hotplug_irqs = 0;
-
-	for_each_intel_encoder(&dev_priv->drm, encoder)
-		hotplug_irqs |= hpd[encoder->hpd_pin];
-
-	return hotplug_irqs;
-}
-
 static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
 {
 	u32 hotplug;
-- 
2.26.2

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[Intel-gfx] [PATCH v3 13/19] drm/i915: Split gen11_hpd_detection_setup() into tc vs. tbt variants

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

No reason to stuff both type-c and tbt into the same function.
Let's split this so we may more easily handle platforms that
lack the tbt spefific bits.

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b355e0307a8a..43e3e7f70c14 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3281,7 +3281,7 @@ static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv)
 			  DG1_DDI_HPD_ENABLE_MASK, 0);
 }
 
-static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
+static void gen11_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
 {
 	u32 hotplug;
 
@@ -3293,6 +3293,11 @@ static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
 		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) |
 		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6);
 	I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug);
+}
+
+static void gen11_tbt_hpd_detection_setup(struct drm_i915_private *dev_priv)
+{
+	u32 hotplug;
 
 	hotplug = I915_READ(GEN11_TBT_HOTPLUG_CTL);
 	hotplug |= GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) |
@@ -3318,7 +3323,8 @@ static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN11_DE_HPD_IMR, val);
 	POSTING_READ(GEN11_DE_HPD_IMR);
 
-	gen11_hpd_detection_setup(dev_priv);
+	gen11_tc_hpd_detection_setup(dev_priv);
+	gen11_tbt_hpd_detection_setup(dev_priv);
 
 	if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP)
 		icp_hpd_irq_setup(dev_priv,
@@ -3633,7 +3639,8 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
 
 		GEN3_IRQ_INIT(uncore, GEN11_DE_HPD_, ~de_hpd_masked,
 			      de_hpd_enables);
-		gen11_hpd_detection_setup(dev_priv);
+		gen11_tc_hpd_detection_setup(dev_priv);
+		gen11_tbt_hpd_detection_setup(dev_priv);
 	} else if (IS_GEN9_LP(dev_priv)) {
 		bxt_hpd_detection_setup(dev_priv);
 	} else if (IS_BROADWELL(dev_priv)) {
-- 
2.26.2

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[Intel-gfx] [PATCH v3 14/19] drm/i915: Don't enable hpd detection logic from irq_postinstall()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

No reason that I can see why we should enable the hpd detection logic
already during irq postinstall phase. We don't even do this on all
the platforms. We just need it before we actually enable the hotplug
interrupts in .hpd_irq_setup(), and in fact we already do it there as
well. Let's just eliminate the redundant early setup.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 40 +++------------------------------
 1 file changed, 3 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 43e3e7f70c14..3ff5747e755d 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3407,8 +3407,8 @@ static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
 	ibx_hpd_irq_setup(dev_priv);
 }
 
-static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
-				      u32 enabled_irqs)
+static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
+				    u32 enabled_irqs)
 {
 	u32 hotplug;
 
@@ -3439,11 +3439,6 @@ static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
 	I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
 }
 
-static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv)
-{
-	__bxt_hpd_detection_setup(dev_priv, BXT_DE_PORT_HOTPLUG_MASK);
-}
-
 static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
 {
 	u32 hotplug_irqs, enabled_irqs;
@@ -3453,7 +3448,7 @@ static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
 
 	bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
 
-	__bxt_hpd_detection_setup(dev_priv, enabled_irqs);
+	bxt_hpd_detection_setup(dev_priv, enabled_irqs);
 }
 
 static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
@@ -3472,12 +3467,6 @@ static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
 
 	gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
 	I915_WRITE(SDEIMR, ~mask);
-
-	if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
-	    HAS_PCH_LPT(dev_priv))
-		ibx_hpd_detection_setup(dev_priv);
-	else
-		spt_hpd_detection_setup(dev_priv);
 }
 
 static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
@@ -3517,8 +3506,6 @@ static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
 	GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask,
 		      display_mask | extra_mask);
 
-	ilk_hpd_detection_setup(dev_priv);
-
 	ibx_irq_postinstall(dev_priv);
 }
 
@@ -3639,12 +3626,6 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
 
 		GEN3_IRQ_INIT(uncore, GEN11_DE_HPD_, ~de_hpd_masked,
 			      de_hpd_enables);
-		gen11_tc_hpd_detection_setup(dev_priv);
-		gen11_tbt_hpd_detection_setup(dev_priv);
-	} else if (IS_GEN9_LP(dev_priv)) {
-		bxt_hpd_detection_setup(dev_priv);
-	} else if (IS_BROADWELL(dev_priv)) {
-		ilk_hpd_detection_setup(dev_priv);
 	}
 }
 
@@ -3672,21 +3653,6 @@ static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
 
 	gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
 	I915_WRITE(SDEIMR, ~mask);
-
-	if (HAS_PCH_DG1(dev_priv))
-		icp_ddi_hpd_detection_setup(dev_priv, DG1_DDI_HPD_ENABLE_MASK);
-	else if (HAS_PCH_TGP(dev_priv)) {
-		icp_ddi_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK);
-		icp_tc_hpd_detection_setup(dev_priv, TGP_TC_HPD_ENABLE_MASK);
-	} else if (HAS_PCH_JSP(dev_priv)) {
-		icp_ddi_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK);
-	} else if (HAS_PCH_MCC(dev_priv)) {
-		icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
-		icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE(HPD_PORT_TC1));
-	} else {
-		icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
-		icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE_MASK);
-	}
 }
 
 static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
-- 
2.26.2

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[Intel-gfx] [PATCH v3 15/19] drm/i915: Rename 'tmp_mask'

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Replace this silly tmp_mask with hotplug_trigger/te_trigger
where appropriate.

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 22 ++++++++++++----------
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 3ff5747e755d..788e32098d3a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2386,7 +2386,6 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 	if (master_ctl & GEN8_DE_PORT_IRQ) {
 		iir = I915_READ(GEN8_DE_PORT_IIR);
 		if (iir) {
-			u32 tmp_mask;
 			bool found = false;
 
 			I915_WRITE(GEN8_DE_PORT_IIR, iir);
@@ -2398,15 +2397,17 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 			}
 
 			if (IS_GEN9_LP(dev_priv)) {
-				tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
-				if (tmp_mask) {
-					bxt_hpd_irq_handler(dev_priv, tmp_mask);
+				u32 hotplug_trigger = iir & BXT_DE_PORT_HOTPLUG_MASK;
+
+				if (hotplug_trigger) {
+					bxt_hpd_irq_handler(dev_priv, hotplug_trigger);
 					found = true;
 				}
 			} else if (IS_BROADWELL(dev_priv)) {
-				tmp_mask = iir & BDW_DE_PORT_HOTPLUG_MASK;
-				if (tmp_mask) {
-					ilk_hpd_irq_handler(dev_priv, tmp_mask);
+				u32 hotplug_trigger = iir & BDW_DE_PORT_HOTPLUG_MASK;
+
+				if (hotplug_trigger) {
+					ilk_hpd_irq_handler(dev_priv, hotplug_trigger);
 					found = true;
 				}
 			}
@@ -2417,9 +2418,10 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 			}
 
 			if (INTEL_GEN(dev_priv) >= 11) {
-				tmp_mask = iir & (DSI0_TE | DSI1_TE);
-				if (tmp_mask) {
-					gen11_dsi_te_interrupt_handler(dev_priv, tmp_mask);
+				u32 te_trigger = iir & (DSI0_TE | DSI1_TE);
+
+				if (te_trigger) {
+					gen11_dsi_te_interrupt_handler(dev_priv, te_trigger);
 					found = true;
 				}
 			}
-- 
2.26.2

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[Intel-gfx] [PATCH v3 16/19] drm/i915: Remove the per-plaform IIR HPD masking

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We no longer unmask all HPD irqs, so we can drop the ugly per-platform
HPD IIR masking. IMR will prevent unsupported bits from appearing in
IIR.

v2: Deal with DG1
    Include "HOTPLUG" in the mask names (Lucas)

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 24 ++----------------------
 drivers/gpu/drm/i915/i915_reg.h | 15 +++------------
 2 files changed, 5 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 788e32098d3a..fa8a07c2f82d 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1895,30 +1895,10 @@ static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
 
 static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
 {
-	u32 ddi_hotplug_trigger, tc_hotplug_trigger;
+	u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_HOTPLUG_MASK_ICP;
+	u32 tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_MASK_ICP;
 	u32 pin_mask = 0, long_mask = 0;
 
-	if (HAS_PCH_DG1(dev_priv)) {
-		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_DG1;
-		tc_hotplug_trigger = 0;
-	} else if (HAS_PCH_TGP(dev_priv)) {
-		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
-		tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
-	} else if (HAS_PCH_JSP(dev_priv)) {
-		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
-		tc_hotplug_trigger = 0;
-	} else if (HAS_PCH_MCC(dev_priv)) {
-		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
-		tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1);
-	} else {
-		drm_WARN(&dev_priv->drm, !HAS_PCH_ICP(dev_priv),
-			 "Unrecognized PCH type 0x%x\n",
-			 INTEL_PCH_TYPE(dev_priv));
-
-		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
-		tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
-	}
-
 	if (ddi_hotplug_trigger) {
 		u32 dig_hotplug_reg;
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9e68ba254d51..eacec3c46a4d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8351,25 +8351,16 @@ enum {
 #define SDE_GMBUS_ICP			(1 << 23)
 #define SDE_TC_HOTPLUG_ICP(hpd_pin)	REG_BIT(24 + _HPD_PIN_TC(hpd_pin))
 #define SDE_DDI_HOTPLUG_ICP(hpd_pin)	REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
-#define SDE_DDI_MASK_ICP		(SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
-					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
-#define SDE_TC_MASK_ICP			(SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \
-					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \
-					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \
-					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1))
-#define SDE_DDI_MASK_TGP		(SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
+#define SDE_DDI_HOTPLUG_MASK_ICP	(SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \
+					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
 					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
 					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
-#define SDE_TC_MASK_TGP			(SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \
+#define SDE_TC_HOTPLUG_MASK_ICP		(SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \
 					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5) | \
 					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \
 					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \
 					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \
 					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1))
-#define SDE_DDI_MASK_DG1		(SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \
-					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
-					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
-					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
 
 #define SDEISR  _MMIO(0xc4000)
 #define SDEIMR  _MMIO(0xc4004)
-- 
2.26.2

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[Intel-gfx] [PATCH v3 17/19] drm/i915: Enable hpd logic only for ports that are present

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Let's enable the hardware hpd logic only for the ports we
can actually use.

In theory this may save some miniscule amounts of power,
and more importantly it eliminates a lot if platform specific
codepaths since the generic thing can now deal with any
combination of ports being present on each SKU.

v2: Deal with DG1

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 302 ++++++++++++++++++++++----------
 drivers/gpu/drm/i915/i915_reg.h |  17 --
 2 files changed, 205 insertions(+), 114 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index fa8a07c2f82d..2337416e581c 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -61,6 +61,8 @@
  */
 
 typedef bool (*long_pulse_detect_func)(enum hpd_pin pin, u32 val);
+typedef u32 (*hotplug_enables_func)(struct drm_i915_private *i915,
+				    enum hpd_pin pin);
 
 static const u32 hpd_ilk[HPD_NUM_PINS] = {
 	[HPD_PORT_A] = DE_DP_A_HOTPLUG,
@@ -1230,6 +1232,18 @@ static u32 intel_hpd_hotplug_irqs(struct drm_i915_private *dev_priv,
 	return hotplug_irqs;
 }
 
+static u32 intel_hpd_hotplug_enables(struct drm_i915_private *i915,
+				     hotplug_enables_func hotplug_enables)
+{
+	struct intel_encoder *encoder;
+	u32 hotplug = 0;
+
+	for_each_intel_encoder(&i915->drm, encoder)
+		hotplug |= hotplug_enables(i915, encoder->hpd_pin);
+
+	return hotplug;
+}
+
 static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
 {
 	wake_up_all(&dev_priv->gmbus_wait_queue);
@@ -3152,6 +3166,31 @@ static void cherryview_irq_reset(struct drm_i915_private *dev_priv)
 	spin_unlock_irq(&dev_priv->irq_lock);
 }
 
+static u32 ibx_hotplug_enables(struct drm_i915_private *i915,
+			       enum hpd_pin pin)
+{
+	switch (pin) {
+	case HPD_PORT_A:
+		/*
+		 * When CPU and PCH are on the same package, port A
+		 * HPD must be enabled in both north and south.
+		 */
+		return HAS_PCH_LPT_LP(i915) ?
+			PORTA_HOTPLUG_ENABLE : 0;
+	case HPD_PORT_B:
+		return PORTB_HOTPLUG_ENABLE |
+			PORTB_PULSE_DURATION_2ms;
+	case HPD_PORT_C:
+		return PORTC_HOTPLUG_ENABLE |
+			PORTC_PULSE_DURATION_2ms;
+	case HPD_PORT_D:
+		return PORTD_HOTPLUG_ENABLE |
+			PORTD_PULSE_DURATION_2ms;
+	default:
+		return 0;
+	}
+}
+
 static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
 {
 	u32 hotplug;
@@ -3162,18 +3201,14 @@ static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
 	 * The pulse duration bits are reserved on LPT+.
 	 */
 	hotplug = I915_READ(PCH_PORT_HOTPLUG);
-	hotplug &= ~(PORTB_PULSE_DURATION_MASK |
+	hotplug &= ~(PORTA_HOTPLUG_ENABLE |
+		     PORTB_HOTPLUG_ENABLE |
+		     PORTC_HOTPLUG_ENABLE |
+		     PORTD_HOTPLUG_ENABLE |
+		     PORTB_PULSE_DURATION_MASK |
 		     PORTC_PULSE_DURATION_MASK |
 		     PORTD_PULSE_DURATION_MASK);
-	hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
-	hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
-	hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
-	/*
-	 * When CPU and PCH are on the same package, port A
-	 * HPD must be enabled in both north and south.
-	 */
-	if (HAS_PCH_LPT_LP(dev_priv))
-		hotplug |= PORTA_HOTPLUG_ENABLE;
+	hotplug |= intel_hpd_hotplug_enables(dev_priv, ibx_hotplug_enables);
 	I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
 }
 
@@ -3189,28 +3224,63 @@ static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
 	ibx_hpd_detection_setup(dev_priv);
 }
 
-static void icp_ddi_hpd_detection_setup(struct drm_i915_private *dev_priv,
-					u32 enable_mask)
+static u32 icp_ddi_hotplug_enables(struct drm_i915_private *i915,
+				   enum hpd_pin pin)
+{
+	switch (pin) {
+	case HPD_PORT_A:
+	case HPD_PORT_B:
+	case HPD_PORT_C:
+		return SHOTPLUG_CTL_DDI_HPD_ENABLE(pin);
+	default:
+		return 0;
+	}
+}
+
+static u32 icp_tc_hotplug_enables(struct drm_i915_private *i915,
+				  enum hpd_pin pin)
+{
+	switch (pin) {
+	case HPD_PORT_TC1:
+	case HPD_PORT_TC2:
+	case HPD_PORT_TC3:
+	case HPD_PORT_TC4:
+	case HPD_PORT_TC5:
+	case HPD_PORT_TC6:
+		return ICP_TC_HPD_ENABLE(pin);
+	default:
+		return 0;
+	}
+}
+
+static void icp_ddi_hpd_detection_setup(struct drm_i915_private *dev_priv)
 {
 	u32 hotplug;
 
 	hotplug = I915_READ(SHOTPLUG_CTL_DDI);
-	hotplug |= enable_mask;
+	hotplug &= ~(SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A) |
+		     SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) |
+		     SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_C));
+	hotplug |= intel_hpd_hotplug_enables(dev_priv, icp_ddi_hotplug_enables);
 	I915_WRITE(SHOTPLUG_CTL_DDI, hotplug);
 }
 
-static void icp_tc_hpd_detection_setup(struct drm_i915_private *dev_priv,
-				       u32 enable_mask)
+static void icp_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
 {
 	u32 hotplug;
 
 	hotplug = I915_READ(SHOTPLUG_CTL_TC);
-	hotplug |= enable_mask;
+	hotplug &= ~(ICP_TC_HPD_ENABLE(HPD_PORT_TC1) |
+		     ICP_TC_HPD_ENABLE(HPD_PORT_TC2) |
+		     ICP_TC_HPD_ENABLE(HPD_PORT_TC3) |
+		     ICP_TC_HPD_ENABLE(HPD_PORT_TC4) |
+		     ICP_TC_HPD_ENABLE(HPD_PORT_TC5) |
+		     ICP_TC_HPD_ENABLE(HPD_PORT_TC6));
+	hotplug |= intel_hpd_hotplug_enables(dev_priv, icp_tc_hotplug_enables);
 	I915_WRITE(SHOTPLUG_CTL_TC, hotplug);
 }
 
-static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv,
-			      u32 ddi_enable_mask, u32 tc_enable_mask)
+static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv)
 {
 	u32 hotplug_irqs, enabled_irqs;
 
@@ -3222,30 +3292,24 @@ static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv,
 
 	ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
 
-	icp_ddi_hpd_detection_setup(dev_priv, ddi_enable_mask);
-	if (tc_enable_mask)
-		icp_tc_hpd_detection_setup(dev_priv, tc_enable_mask);
+	icp_ddi_hpd_detection_setup(dev_priv);
+	icp_tc_hpd_detection_setup(dev_priv);
 }
 
-/*
- * EHL doesn't need most of gen11_hpd_irq_setup, it's handling only the
- * equivalent of SDE.
- */
-static void mcc_hpd_irq_setup(struct drm_i915_private *dev_priv)
+static u32 gen11_hotplug_enables(struct drm_i915_private *i915,
+				 enum hpd_pin pin)
 {
-	icp_hpd_irq_setup(dev_priv,
-			  ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE(HPD_PORT_TC1));
-}
-
-/*
- * JSP behaves exactly the same as MCC above except that port C is mapped to
- * the DDI-C pins instead of the TC1 pins.  This means we should follow TGP's
- * masks & tables rather than ICP's masks & tables.
- */
-static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv)
-{
-	icp_hpd_irq_setup(dev_priv,
-			  TGP_DDI_HPD_ENABLE_MASK, 0);
+	switch (pin) {
+	case HPD_PORT_TC1:
+	case HPD_PORT_TC2:
+	case HPD_PORT_TC3:
+	case HPD_PORT_TC4:
+	case HPD_PORT_TC5:
+	case HPD_PORT_TC6:
+		return GEN11_HOTPLUG_CTL_ENABLE(pin);
+	default:
+		return 0;
+	}
 }
 
 static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv)
@@ -3259,8 +3323,7 @@ static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv)
 		INVERT_DDID_HPD);
 	I915_WRITE(SOUTH_CHICKEN1, val);
 
-	icp_hpd_irq_setup(dev_priv,
-			  DG1_DDI_HPD_ENABLE_MASK, 0);
+	icp_hpd_irq_setup(dev_priv);
 }
 
 static void gen11_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
@@ -3268,12 +3331,13 @@ static void gen11_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
 	u32 hotplug;
 
 	hotplug = I915_READ(GEN11_TC_HOTPLUG_CTL);
-	hotplug |= GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) |
-		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) |
-		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) |
-		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) |
-		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) |
-		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6);
+	hotplug &= ~(GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) |
+		     GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) |
+		     GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) |
+		     GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) |
+		     GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) |
+		     GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6));
+	hotplug |= intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables);
 	I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug);
 }
 
@@ -3282,12 +3346,13 @@ static void gen11_tbt_hpd_detection_setup(struct drm_i915_private *dev_priv)
 	u32 hotplug;
 
 	hotplug = I915_READ(GEN11_TBT_HOTPLUG_CTL);
-	hotplug |= GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) |
-		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) |
-		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) |
-		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) |
-		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) |
-		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6);
+	hotplug &= ~(GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) |
+		     GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) |
+		     GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) |
+		     GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) |
+		     GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) |
+		     GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6));
+	hotplug |= intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables);
 	I915_WRITE(GEN11_TBT_HOTPLUG_CTL, hotplug);
 }
 
@@ -3308,12 +3373,36 @@ static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
 	gen11_tc_hpd_detection_setup(dev_priv);
 	gen11_tbt_hpd_detection_setup(dev_priv);
 
-	if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP)
-		icp_hpd_irq_setup(dev_priv,
-				  TGP_DDI_HPD_ENABLE_MASK, TGP_TC_HPD_ENABLE_MASK);
-	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
-		icp_hpd_irq_setup(dev_priv,
-				  ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE_MASK);
+	if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
+		icp_hpd_irq_setup(dev_priv);
+}
+
+static u32 spt_hotplug_enables(struct drm_i915_private *i915,
+			       enum hpd_pin pin)
+{
+	switch (pin) {
+	case HPD_PORT_A:
+		return PORTA_HOTPLUG_ENABLE;
+	case HPD_PORT_B:
+		return PORTB_HOTPLUG_ENABLE;
+	case HPD_PORT_C:
+		return PORTC_HOTPLUG_ENABLE;
+	case HPD_PORT_D:
+		return PORTD_HOTPLUG_ENABLE;
+	default:
+		return 0;
+	}
+}
+
+static u32 spt_hotplug2_enables(struct drm_i915_private *i915,
+				enum hpd_pin pin)
+{
+	switch (pin) {
+	case HPD_PORT_E:
+		return PORTE_HOTPLUG_ENABLE;
+	default:
+		return 0;
+	}
 }
 
 static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
@@ -3330,14 +3419,16 @@ static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
 
 	/* Enable digital hotplug on the PCH */
 	hotplug = I915_READ(PCH_PORT_HOTPLUG);
-	hotplug |= PORTA_HOTPLUG_ENABLE |
-		   PORTB_HOTPLUG_ENABLE |
-		   PORTC_HOTPLUG_ENABLE |
-		   PORTD_HOTPLUG_ENABLE;
+	hotplug &= ~(PORTA_HOTPLUG_ENABLE |
+		     PORTB_HOTPLUG_ENABLE |
+		     PORTC_HOTPLUG_ENABLE |
+		     PORTD_HOTPLUG_ENABLE);
+	hotplug |= intel_hpd_hotplug_enables(dev_priv, spt_hotplug_enables);
 	I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
 
 	hotplug = I915_READ(PCH_PORT_HOTPLUG2);
-	hotplug |= PORTE_HOTPLUG_ENABLE;
+	hotplug &= ~PORTE_HOTPLUG_ENABLE;
+	hotplug |= intel_hpd_hotplug_enables(dev_priv, spt_hotplug2_enables);
 	I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
 }
 
@@ -3356,6 +3447,18 @@ static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
 	spt_hpd_detection_setup(dev_priv);
 }
 
+static u32 ilk_hotplug_enables(struct drm_i915_private *i915,
+			       enum hpd_pin pin)
+{
+	switch (pin) {
+	case HPD_PORT_A:
+		return DIGITAL_PORTA_HOTPLUG_ENABLE |
+			DIGITAL_PORTA_PULSE_DURATION_2ms;
+	default:
+		return 0;
+	}
+}
+
 static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv)
 {
 	u32 hotplug;
@@ -3366,9 +3469,9 @@ static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv)
 	 * The pulse duration bits are reserved on HSW+.
 	 */
 	hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
-	hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK;
-	hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE |
-		   DIGITAL_PORTA_PULSE_DURATION_2ms;
+	hotplug &= ~(DIGITAL_PORTA_HOTPLUG_ENABLE |
+		     DIGITAL_PORTA_PULSE_DURATION_MASK);
+	hotplug |= intel_hpd_hotplug_enables(dev_priv, ilk_hotplug_enables);
 	I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
 }
 
@@ -3389,35 +3492,44 @@ static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
 	ibx_hpd_irq_setup(dev_priv);
 }
 
-static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
-				    u32 enabled_irqs)
+static u32 bxt_hotplug_enables(struct drm_i915_private *i915,
+			       enum hpd_pin pin)
+{
+	u32 hotplug;
+
+	switch (pin) {
+	case HPD_PORT_A:
+		hotplug = PORTA_HOTPLUG_ENABLE;
+		if (intel_bios_is_port_hpd_inverted(i915, PORT_A))
+			hotplug |= BXT_DDIA_HPD_INVERT;
+		return hotplug;
+	case HPD_PORT_B:
+		hotplug = PORTB_HOTPLUG_ENABLE;
+		if (intel_bios_is_port_hpd_inverted(i915, PORT_B))
+			hotplug |= BXT_DDIB_HPD_INVERT;
+		return hotplug;
+	case HPD_PORT_C:
+		hotplug = PORTC_HOTPLUG_ENABLE;
+		if (intel_bios_is_port_hpd_inverted(i915, PORT_C))
+			hotplug |= BXT_DDIC_HPD_INVERT;
+		return hotplug;
+	default:
+		return 0;
+	}
+}
+
+static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv)
 {
 	u32 hotplug;
 
 	hotplug = I915_READ(PCH_PORT_HOTPLUG);
-	hotplug |= PORTA_HOTPLUG_ENABLE |
-		   PORTB_HOTPLUG_ENABLE |
-		   PORTC_HOTPLUG_ENABLE;
-
-	drm_dbg_kms(&dev_priv->drm,
-		    "Invert bit setting: hp_ctl:%x hp_port:%x\n",
-		    hotplug, enabled_irqs);
-	hotplug &= ~BXT_DDI_HPD_INVERT_MASK;
-
-	/*
-	 * For BXT invert bit has to be set based on AOB design
-	 * for HPD detection logic, update it based on VBT fields.
-	 */
-	if ((enabled_irqs & GEN8_DE_PORT_HOTPLUG(HPD_PORT_A)) &&
-	    intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
-		hotplug |= BXT_DDIA_HPD_INVERT;
-	if ((enabled_irqs & GEN8_DE_PORT_HOTPLUG(HPD_PORT_B)) &&
-	    intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
-		hotplug |= BXT_DDIB_HPD_INVERT;
-	if ((enabled_irqs & GEN8_DE_PORT_HOTPLUG(HPD_PORT_C)) &&
-	    intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
-		hotplug |= BXT_DDIC_HPD_INVERT;
-
+	hotplug &= ~(PORTA_HOTPLUG_ENABLE |
+		     PORTB_HOTPLUG_ENABLE |
+		     PORTC_HOTPLUG_ENABLE |
+		     BXT_DDIA_HPD_INVERT |
+		     BXT_DDIB_HPD_INVERT |
+		     BXT_DDIC_HPD_INVERT);
+	hotplug |= intel_hpd_hotplug_enables(dev_priv, bxt_hotplug_enables);
 	I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
 }
 
@@ -3430,7 +3542,7 @@ static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
 
 	bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
 
-	bxt_hpd_detection_setup(dev_priv, enabled_irqs);
+	bxt_hpd_detection_setup(dev_priv);
 }
 
 static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
@@ -4145,10 +4257,6 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
 	} else {
 		if (HAS_PCH_DG1(dev_priv))
 			dev_priv->display.hpd_irq_setup = dg1_hpd_irq_setup;
-		else if (HAS_PCH_JSP(dev_priv))
-			dev_priv->display.hpd_irq_setup = jsp_hpd_irq_setup;
-		else if (HAS_PCH_MCC(dev_priv))
-			dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup;
 		else if (INTEL_GEN(dev_priv) >= 11)
 			dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
 		else if (IS_GEN9_LP(dev_priv))
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index eacec3c46a4d..a5c55e0af2db 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8443,23 +8443,6 @@ enum {
 #define SHPD_FILTER_CNT				_MMIO(0xc4038)
 #define   SHPD_FILTER_CNT_500_ADJ		0x001D9
 
-#define ICP_DDI_HPD_ENABLE_MASK		(SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) | \
-					 SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A))
-#define ICP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(HPD_PORT_TC4) | \
-					 ICP_TC_HPD_ENABLE(HPD_PORT_TC3) | \
-					 ICP_TC_HPD_ENABLE(HPD_PORT_TC2) | \
-					 ICP_TC_HPD_ENABLE(HPD_PORT_TC1))
-#define TGP_DDI_HPD_ENABLE_MASK		(SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_C) | \
-					 SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) | \
-					 SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A))
-#define TGP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(HPD_PORT_TC6) | \
-					 ICP_TC_HPD_ENABLE(HPD_PORT_TC5) | \
-					 ICP_TC_HPD_ENABLE_MASK)
-#define DG1_DDI_HPD_ENABLE_MASK		(SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_D) | \
-					 SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_C) | \
-					 SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) | \
-					 SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A))
-
 #define _PCH_DPLL_A              0xc6014
 #define _PCH_DPLL_B              0xc6018
 #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
-- 
2.26.2

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[Intel-gfx] [PATCH v3 18/19] drm/i915: Use GEN3_IRQ_INIT() to init south interrupts in icp+

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

No reason not to use GEN3_IRQ_INIT() on icp+.

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 2337416e581c..95268fca2fbc 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3739,14 +3739,10 @@ static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
 
 static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
 {
+	struct intel_uncore *uncore = &dev_priv->uncore;
 	u32 mask = SDE_GMBUS_ICP;
 
-	drm_WARN_ON(&dev_priv->drm, I915_READ(SDEIER) != 0);
-	I915_WRITE(SDEIER, 0xffffffff);
-	POSTING_READ(SDEIER);
-
-	gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
-	I915_WRITE(SDEIMR, ~mask);
+	GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
 }
 
 static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
-- 
2.26.2

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[Intel-gfx] [PATCH v3 19/19] drm/i915: Get rid of ibx_irq_pre_postinstall()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

ibx_irq_pre_postinstall() looks totally pointless. We can just
init both SDEIMR and SDEIER at the same time before enabling the
master intererupt. It's equally racy as the other order due
to doing all of this from the postinstall stage with the interrupt
handler already in place. That is, safe with MSI but racy with
shared legacy interrupts. Fortunately we should have MSI on all ilk+.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 46 ++++++++++++---------------------
 1 file changed, 17 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 95268fca2fbc..fdd132e2ec76 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2910,24 +2910,6 @@ static void ibx_irq_reset(struct drm_i915_private *dev_priv)
 		I915_WRITE(SERR_INT, 0xffffffff);
 }
 
-/*
- * SDEIER is also touched by the interrupt handler to work around missed PCH
- * interrupts. Hence we can't update it after the interrupt handler is enabled -
- * instead we unconditionally enable all PCH interrupt sources here, but then
- * only unmask them as needed with SDEIMR.
- *
- * This function needs to be called before interrupts are enabled.
- */
-static void ibx_irq_pre_postinstall(struct drm_i915_private *dev_priv)
-{
-	if (HAS_PCH_NOP(dev_priv))
-		return;
-
-	drm_WARN_ON(&dev_priv->drm, I915_READ(SDEIER) != 0);
-	I915_WRITE(SDEIER, 0xffffffff);
-	POSTING_READ(SDEIER);
-}
-
 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
 {
 	struct intel_uncore *uncore = &dev_priv->uncore;
@@ -3545,8 +3527,20 @@ static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
 	bxt_hpd_detection_setup(dev_priv);
 }
 
+/*
+ * SDEIER is also touched by the interrupt handler to work around missed PCH
+ * interrupts. Hence we can't update it after the interrupt handler is enabled -
+ * instead we unconditionally enable all PCH interrupt sources here, but then
+ * only unmask them as needed with SDEIMR.
+ *
+ * Note that we currently do this after installing the interrupt handler,
+ * but before we enable the master interrupt. That should be sufficient
+ * to avoid races with the irq handler, assuming we have MSI. Shared legacy
+ * interrupts could still race.
+ */
 static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
 {
+	struct intel_uncore *uncore = &dev_priv->uncore;
 	u32 mask;
 
 	if (HAS_PCH_NOP(dev_priv))
@@ -3559,8 +3553,7 @@ static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
 	else
 		mask = SDE_GMBUS_CPT;
 
-	gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
-	I915_WRITE(SDEIMR, ~mask);
+	GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
 }
 
 static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
@@ -3593,14 +3586,12 @@ static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
 
 	dev_priv->irq_mask = ~display_mask;
 
-	ibx_irq_pre_postinstall(dev_priv);
+	ibx_irq_postinstall(dev_priv);
 
 	gen5_gt_irq_postinstall(&dev_priv->gt);
 
 	GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask,
 		      display_mask | extra_mask);
-
-	ibx_irq_postinstall(dev_priv);
 }
 
 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
@@ -3725,15 +3716,12 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
 
 static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
 {
-	if (HAS_PCH_SPLIT(dev_priv))
-		ibx_irq_pre_postinstall(dev_priv);
-
-	gen8_gt_irq_postinstall(&dev_priv->gt);
-	gen8_de_irq_postinstall(dev_priv);
-
 	if (HAS_PCH_SPLIT(dev_priv))
 		ibx_irq_postinstall(dev_priv);
 
+	gen8_gt_irq_postinstall(&dev_priv->gt);
+	gen8_de_irq_postinstall(dev_priv);
+
 	gen8_master_intr_enable(dev_priv->uncore.regs);
 }
 
-- 
2.26.2

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Re: [Intel-gfx] [PATCH v3 14/19] drm/i915: Don't enable hpd detection logic from irq_postinstall()

[Lucas De Marchi]

On Wed, Oct 28, 2020 at 11:33:18PM +0200, Ville Syrjälä wrote:
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>No reason that I can see why we should enable the hpd detection logic
>already during irq postinstall phase. We don't even do this on all
>the platforms. We just need it before we actually enable the hotplug
>interrupts in .hpd_irq_setup(), and in fact we already do it there as
>well. Let's just eliminate the redundant early setup.

yep, it makes sense. If CI is happy and doesn't explode in something
neither of us antecipated, I'm happy too.


Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/i915_irq.c | 40 +++------------------------------
> 1 file changed, 3 insertions(+), 37 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>index 43e3e7f70c14..3ff5747e755d 100644
>--- a/drivers/gpu/drm/i915/i915_irq.c
>+++ b/drivers/gpu/drm/i915/i915_irq.c
>@@ -3407,8 +3407,8 @@ static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
> 	ibx_hpd_irq_setup(dev_priv);
> }
>
>-static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
>-				      u32 enabled_irqs)
>+static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
>+				    u32 enabled_irqs)
> {
> 	u32 hotplug;
>
>@@ -3439,11 +3439,6 @@ static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
> 	I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
> }
>
>-static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv)
>-{
>-	__bxt_hpd_detection_setup(dev_priv, BXT_DE_PORT_HOTPLUG_MASK);
>-}
>-
> static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
> {
> 	u32 hotplug_irqs, enabled_irqs;
>@@ -3453,7 +3448,7 @@ static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
>
> 	bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
>
>-	__bxt_hpd_detection_setup(dev_priv, enabled_irqs);
>+	bxt_hpd_detection_setup(dev_priv, enabled_irqs);
> }
>
> static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
>@@ -3472,12 +3467,6 @@ static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
>
> 	gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
> 	I915_WRITE(SDEIMR, ~mask);
>-
>-	if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
>-	    HAS_PCH_LPT(dev_priv))
>-		ibx_hpd_detection_setup(dev_priv);
>-	else
>-		spt_hpd_detection_setup(dev_priv);
> }
>
> static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
>@@ -3517,8 +3506,6 @@ static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
> 	GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask,
> 		      display_mask | extra_mask);
>
>-	ilk_hpd_detection_setup(dev_priv);
>-
> 	ibx_irq_postinstall(dev_priv);
> }
>
>@@ -3639,12 +3626,6 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
>
> 		GEN3_IRQ_INIT(uncore, GEN11_DE_HPD_, ~de_hpd_masked,
> 			      de_hpd_enables);
>-		gen11_tc_hpd_detection_setup(dev_priv);
>-		gen11_tbt_hpd_detection_setup(dev_priv);
>-	} else if (IS_GEN9_LP(dev_priv)) {
>-		bxt_hpd_detection_setup(dev_priv);
>-	} else if (IS_BROADWELL(dev_priv)) {
>-		ilk_hpd_detection_setup(dev_priv);
> 	}
> }
>
>@@ -3672,21 +3653,6 @@ static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
>
> 	gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
> 	I915_WRITE(SDEIMR, ~mask);
>-
>-	if (HAS_PCH_DG1(dev_priv))
>-		icp_ddi_hpd_detection_setup(dev_priv, DG1_DDI_HPD_ENABLE_MASK);
>-	else if (HAS_PCH_TGP(dev_priv)) {
>-		icp_ddi_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK);
>-		icp_tc_hpd_detection_setup(dev_priv, TGP_TC_HPD_ENABLE_MASK);
>-	} else if (HAS_PCH_JSP(dev_priv)) {
>-		icp_ddi_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK);
>-	} else if (HAS_PCH_MCC(dev_priv)) {
>-		icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
>-		icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE(HPD_PORT_TC1));
>-	} else {
>-		icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
>-		icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE_MASK);
>-	}
> }
>
> static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
>-- 
>2.26.2
>
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Futher cleanup around hpd pins and port identfiers (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915: Futher cleanup around hpd pins and port identfiers (rev5)
URL   : https://patchwork.freedesktop.org/series/82411/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
ee08af3a4155 drm/i915: s/PORT_TC/TC_PORT_/
-:313: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'tc_port' - possible side-effects?
#313: FILE: drivers/gpu/drm/i915/i915_reg.h:10330:
+#define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)	(1 << ((tc_port) < TC_PORT_4 ? \
 						       (tc_port) + 12 : \
+						       (tc_port) - TC_PORT_4 + 21))

total: 0 errors, 0 warnings, 1 checks, 269 lines checked
fe19b59abf59 drm/i915: Add PORT_TCn aliases to enum port
287c7226cbc0 drm/i915: Give DDI encoders even better names
-:44: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#44: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:5186:
+				 tc_port != TC_PORT_NONE ? phy_name(phy) : tc_port - TC_PORT_1 + '1');

-:54: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#54: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:5196:
+				 tc_port != TC_PORT_NONE ? phy_name(phy) : tc_port - TC_PORT_1 + '1');

total: 0 errors, 2 warnings, 0 checks, 33 lines checked
5b31fc7d2973 drm/i915: Introduce AUX_CH_USBCn
907a6f378413 drm/i915: Pimp AUX CH names
cb0bc14e42f1 drm/i915: Use AUX_CH_USBCn for the RKL VBT AUX CH setup
00239142669f drm/i915: Parametrize BXT_DE_PORT_HP_DDI with hpd_pin
4a178195598a drm/i915: Introduce GEN8_DE_PORT_HOTPLUG()
60ce87b4b638 drm/i915: s/port/hpd_pin/ for icp+ ddi hpd bits
6d636206aba9 drm/i915: s/tc_port/hpd_pin/ in GEN11_{TC, TBT}_HOTPLUG()
8b3e20e749bc drm/i915: s/tc_port/hpd_pin/ in icp+ TC hotplug bits
15e7a4125c07 drm/i915: Relocate intel_hpd_{enabled, hotplug}_irqs()
2cecffb1a88e drm/i915: Split gen11_hpd_detection_setup() into tc vs. tbt variants
62b52af3a1fc drm/i915: Don't enable hpd detection logic from irq_postinstall()
567b2cbf4a84 drm/i915: Rename 'tmp_mask'
26e100e104d0 drm/i915: Remove the per-plaform IIR HPD masking
3059c7ee9196 drm/i915: Enable hpd logic only for ports that are present
f2def9dff59f drm/i915: Use GEN3_IRQ_INIT() to init south interrupts in icp+
bd3fd9cc28ab drm/i915: Get rid of ibx_irq_pre_postinstall()


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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Futher cleanup around hpd pins and port identfiers (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915: Futher cleanup around hpd pins and port identfiers (rev5)
URL   : https://patchwork.freedesktop.org/series/82411/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_reset.c:1312:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:    expected void *in
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:    got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:    expected void const *src
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:    got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: warning: incorrect type in argument 2 (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:    expected void *in
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:    got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:    expected void const *src
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:    got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: warning: incorrect type in argument 2 (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:    expected unsigned int [usertype] *s
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:    got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: warning: incorrect type in argument 1 (different address spaces)
+drivers/gpu/drm/i915/gvt/mmio.c:290:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1440:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1494:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/intel_wakeref.c:137:19: warning: context imbalance in 'wakeref_auto_timeout' - unexpected unlock
+./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31
+./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31
+./include/linux/seqlock.h:864:16: warning: trying to copy expression type 31
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block


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Re: [Intel-gfx] [PATCH v3 17/19] drm/i915: Enable hpd logic only for ports that are present

[Lucas De Marchi]

On Wed, Oct 28, 2020 at 11:33:21PM +0200, Ville Syrjälä wrote:
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Let's enable the hardware hpd logic only for the ports we
>can actually use.
>
>In theory this may save some miniscule amounts of power,
>and more importantly it eliminates a lot if platform specific
>codepaths since the generic thing can now deal with any
>combination of ports being present on each SKU.
>
>v2: Deal with DG1
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>


Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

>---
> drivers/gpu/drm/i915/i915_irq.c | 302 ++++++++++++++++++++++----------
> drivers/gpu/drm/i915/i915_reg.h |  17 --
> 2 files changed, 205 insertions(+), 114 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>index fa8a07c2f82d..2337416e581c 100644
>--- a/drivers/gpu/drm/i915/i915_irq.c
>+++ b/drivers/gpu/drm/i915/i915_irq.c
>@@ -61,6 +61,8 @@
>  */
>
> typedef bool (*long_pulse_detect_func)(enum hpd_pin pin, u32 val);
>+typedef u32 (*hotplug_enables_func)(struct drm_i915_private *i915,
>+				    enum hpd_pin pin);
>
> static const u32 hpd_ilk[HPD_NUM_PINS] = {
> 	[HPD_PORT_A] = DE_DP_A_HOTPLUG,
>@@ -1230,6 +1232,18 @@ static u32 intel_hpd_hotplug_irqs(struct drm_i915_private *dev_priv,
> 	return hotplug_irqs;
> }
>
>+static u32 intel_hpd_hotplug_enables(struct drm_i915_private *i915,
>+				     hotplug_enables_func hotplug_enables)
>+{
>+	struct intel_encoder *encoder;
>+	u32 hotplug = 0;
>+
>+	for_each_intel_encoder(&i915->drm, encoder)
>+		hotplug |= hotplug_enables(i915, encoder->hpd_pin);
>+
>+	return hotplug;
>+}
>+
> static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
> {
> 	wake_up_all(&dev_priv->gmbus_wait_queue);
>@@ -3152,6 +3166,31 @@ static void cherryview_irq_reset(struct drm_i915_private *dev_priv)
> 	spin_unlock_irq(&dev_priv->irq_lock);
> }
>
>+static u32 ibx_hotplug_enables(struct drm_i915_private *i915,
>+			       enum hpd_pin pin)
>+{
>+	switch (pin) {
>+	case HPD_PORT_A:
>+		/*
>+		 * When CPU and PCH are on the same package, port A
>+		 * HPD must be enabled in both north and south.
>+		 */
>+		return HAS_PCH_LPT_LP(i915) ?
>+			PORTA_HOTPLUG_ENABLE : 0;
>+	case HPD_PORT_B:
>+		return PORTB_HOTPLUG_ENABLE |
>+			PORTB_PULSE_DURATION_2ms;
>+	case HPD_PORT_C:
>+		return PORTC_HOTPLUG_ENABLE |
>+			PORTC_PULSE_DURATION_2ms;
>+	case HPD_PORT_D:
>+		return PORTD_HOTPLUG_ENABLE |
>+			PORTD_PULSE_DURATION_2ms;
>+	default:
>+		return 0;
>+	}
>+}
>+
> static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
> {
> 	u32 hotplug;
>@@ -3162,18 +3201,14 @@ static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
> 	 * The pulse duration bits are reserved on LPT+.
> 	 */
> 	hotplug = I915_READ(PCH_PORT_HOTPLUG);
>-	hotplug &= ~(PORTB_PULSE_DURATION_MASK |
>+	hotplug &= ~(PORTA_HOTPLUG_ENABLE |
>+		     PORTB_HOTPLUG_ENABLE |
>+		     PORTC_HOTPLUG_ENABLE |
>+		     PORTD_HOTPLUG_ENABLE |
>+		     PORTB_PULSE_DURATION_MASK |
> 		     PORTC_PULSE_DURATION_MASK |
> 		     PORTD_PULSE_DURATION_MASK);
>-	hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
>-	hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
>-	hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
>-	/*
>-	 * When CPU and PCH are on the same package, port A
>-	 * HPD must be enabled in both north and south.
>-	 */
>-	if (HAS_PCH_LPT_LP(dev_priv))
>-		hotplug |= PORTA_HOTPLUG_ENABLE;
>+	hotplug |= intel_hpd_hotplug_enables(dev_priv, ibx_hotplug_enables);
> 	I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
> }
>
>@@ -3189,28 +3224,63 @@ static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
> 	ibx_hpd_detection_setup(dev_priv);
> }
>
>-static void icp_ddi_hpd_detection_setup(struct drm_i915_private *dev_priv,
>-					u32 enable_mask)
>+static u32 icp_ddi_hotplug_enables(struct drm_i915_private *i915,
>+				   enum hpd_pin pin)
>+{
>+	switch (pin) {
>+	case HPD_PORT_A:
>+	case HPD_PORT_B:
>+	case HPD_PORT_C:
>+		return SHOTPLUG_CTL_DDI_HPD_ENABLE(pin);
>+	default:
>+		return 0;
>+	}
>+}
>+
>+static u32 icp_tc_hotplug_enables(struct drm_i915_private *i915,
>+				  enum hpd_pin pin)
>+{
>+	switch (pin) {
>+	case HPD_PORT_TC1:
>+	case HPD_PORT_TC2:
>+	case HPD_PORT_TC3:
>+	case HPD_PORT_TC4:
>+	case HPD_PORT_TC5:
>+	case HPD_PORT_TC6:
>+		return ICP_TC_HPD_ENABLE(pin);
>+	default:
>+		return 0;
>+	}
>+}
>+
>+static void icp_ddi_hpd_detection_setup(struct drm_i915_private *dev_priv)
> {
> 	u32 hotplug;
>
> 	hotplug = I915_READ(SHOTPLUG_CTL_DDI);
>-	hotplug |= enable_mask;
>+	hotplug &= ~(SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A) |
>+		     SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) |
>+		     SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_C));
>+	hotplug |= intel_hpd_hotplug_enables(dev_priv, icp_ddi_hotplug_enables);
> 	I915_WRITE(SHOTPLUG_CTL_DDI, hotplug);
> }
>
>-static void icp_tc_hpd_detection_setup(struct drm_i915_private *dev_priv,
>-				       u32 enable_mask)
>+static void icp_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
> {
> 	u32 hotplug;
>
> 	hotplug = I915_READ(SHOTPLUG_CTL_TC);
>-	hotplug |= enable_mask;
>+	hotplug &= ~(ICP_TC_HPD_ENABLE(HPD_PORT_TC1) |
>+		     ICP_TC_HPD_ENABLE(HPD_PORT_TC2) |
>+		     ICP_TC_HPD_ENABLE(HPD_PORT_TC3) |
>+		     ICP_TC_HPD_ENABLE(HPD_PORT_TC4) |
>+		     ICP_TC_HPD_ENABLE(HPD_PORT_TC5) |
>+		     ICP_TC_HPD_ENABLE(HPD_PORT_TC6));
>+	hotplug |= intel_hpd_hotplug_enables(dev_priv, icp_tc_hotplug_enables);
> 	I915_WRITE(SHOTPLUG_CTL_TC, hotplug);
> }
>
>-static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv,
>-			      u32 ddi_enable_mask, u32 tc_enable_mask)
>+static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv)
> {
> 	u32 hotplug_irqs, enabled_irqs;
>
>@@ -3222,30 +3292,24 @@ static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv,
>
> 	ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
>
>-	icp_ddi_hpd_detection_setup(dev_priv, ddi_enable_mask);
>-	if (tc_enable_mask)
>-		icp_tc_hpd_detection_setup(dev_priv, tc_enable_mask);
>+	icp_ddi_hpd_detection_setup(dev_priv);
>+	icp_tc_hpd_detection_setup(dev_priv);
> }
>
>-/*
>- * EHL doesn't need most of gen11_hpd_irq_setup, it's handling only the
>- * equivalent of SDE.
>- */
>-static void mcc_hpd_irq_setup(struct drm_i915_private *dev_priv)
>+static u32 gen11_hotplug_enables(struct drm_i915_private *i915,
>+				 enum hpd_pin pin)
> {
>-	icp_hpd_irq_setup(dev_priv,
>-			  ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE(HPD_PORT_TC1));
>-}
>-
>-/*
>- * JSP behaves exactly the same as MCC above except that port C is mapped to
>- * the DDI-C pins instead of the TC1 pins.  This means we should follow TGP's
>- * masks & tables rather than ICP's masks & tables.
>- */
>-static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv)
>-{
>-	icp_hpd_irq_setup(dev_priv,
>-			  TGP_DDI_HPD_ENABLE_MASK, 0);
>+	switch (pin) {
>+	case HPD_PORT_TC1:
>+	case HPD_PORT_TC2:
>+	case HPD_PORT_TC3:
>+	case HPD_PORT_TC4:
>+	case HPD_PORT_TC5:
>+	case HPD_PORT_TC6:
>+		return GEN11_HOTPLUG_CTL_ENABLE(pin);
>+	default:
>+		return 0;
>+	}
> }
>
> static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv)
>@@ -3259,8 +3323,7 @@ static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv)
> 		INVERT_DDID_HPD);
> 	I915_WRITE(SOUTH_CHICKEN1, val);
>
>-	icp_hpd_irq_setup(dev_priv,
>-			  DG1_DDI_HPD_ENABLE_MASK, 0);
>+	icp_hpd_irq_setup(dev_priv);
> }
>
> static void gen11_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
>@@ -3268,12 +3331,13 @@ static void gen11_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
> 	u32 hotplug;
>
> 	hotplug = I915_READ(GEN11_TC_HOTPLUG_CTL);
>-	hotplug |= GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) |
>-		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) |
>-		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) |
>-		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) |
>-		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) |
>-		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6);
>+	hotplug &= ~(GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) |
>+		     GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) |
>+		     GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) |
>+		     GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) |
>+		     GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) |
>+		     GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6));
>+	hotplug |= intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables);
> 	I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug);
> }
>
>@@ -3282,12 +3346,13 @@ static void gen11_tbt_hpd_detection_setup(struct drm_i915_private *dev_priv)
> 	u32 hotplug;
>
> 	hotplug = I915_READ(GEN11_TBT_HOTPLUG_CTL);
>-	hotplug |= GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) |
>-		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) |
>-		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) |
>-		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) |
>-		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) |
>-		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6);
>+	hotplug &= ~(GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) |
>+		     GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) |
>+		     GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) |
>+		     GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) |
>+		     GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) |
>+		     GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6));
>+	hotplug |= intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables);
> 	I915_WRITE(GEN11_TBT_HOTPLUG_CTL, hotplug);
> }
>
>@@ -3308,12 +3373,36 @@ static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
> 	gen11_tc_hpd_detection_setup(dev_priv);
> 	gen11_tbt_hpd_detection_setup(dev_priv);
>
>-	if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP)
>-		icp_hpd_irq_setup(dev_priv,
>-				  TGP_DDI_HPD_ENABLE_MASK, TGP_TC_HPD_ENABLE_MASK);
>-	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
>-		icp_hpd_irq_setup(dev_priv,
>-				  ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE_MASK);
>+	if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
>+		icp_hpd_irq_setup(dev_priv);
>+}
>+
>+static u32 spt_hotplug_enables(struct drm_i915_private *i915,
>+			       enum hpd_pin pin)
>+{
>+	switch (pin) {
>+	case HPD_PORT_A:
>+		return PORTA_HOTPLUG_ENABLE;
>+	case HPD_PORT_B:
>+		return PORTB_HOTPLUG_ENABLE;
>+	case HPD_PORT_C:
>+		return PORTC_HOTPLUG_ENABLE;
>+	case HPD_PORT_D:
>+		return PORTD_HOTPLUG_ENABLE;
>+	default:
>+		return 0;
>+	}
>+}
>+
>+static u32 spt_hotplug2_enables(struct drm_i915_private *i915,
>+				enum hpd_pin pin)
>+{
>+	switch (pin) {
>+	case HPD_PORT_E:
>+		return PORTE_HOTPLUG_ENABLE;
>+	default:
>+		return 0;
>+	}
> }
>
> static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
>@@ -3330,14 +3419,16 @@ static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
>
> 	/* Enable digital hotplug on the PCH */
> 	hotplug = I915_READ(PCH_PORT_HOTPLUG);
>-	hotplug |= PORTA_HOTPLUG_ENABLE |
>-		   PORTB_HOTPLUG_ENABLE |
>-		   PORTC_HOTPLUG_ENABLE |
>-		   PORTD_HOTPLUG_ENABLE;
>+	hotplug &= ~(PORTA_HOTPLUG_ENABLE |
>+		     PORTB_HOTPLUG_ENABLE |
>+		     PORTC_HOTPLUG_ENABLE |
>+		     PORTD_HOTPLUG_ENABLE);
>+	hotplug |= intel_hpd_hotplug_enables(dev_priv, spt_hotplug_enables);
> 	I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
>
> 	hotplug = I915_READ(PCH_PORT_HOTPLUG2);
>-	hotplug |= PORTE_HOTPLUG_ENABLE;
>+	hotplug &= ~PORTE_HOTPLUG_ENABLE;
>+	hotplug |= intel_hpd_hotplug_enables(dev_priv, spt_hotplug2_enables);
> 	I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
> }
>
>@@ -3356,6 +3447,18 @@ static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
> 	spt_hpd_detection_setup(dev_priv);
> }
>
>+static u32 ilk_hotplug_enables(struct drm_i915_private *i915,
>+			       enum hpd_pin pin)
>+{
>+	switch (pin) {
>+	case HPD_PORT_A:
>+		return DIGITAL_PORTA_HOTPLUG_ENABLE |
>+			DIGITAL_PORTA_PULSE_DURATION_2ms;
>+	default:
>+		return 0;
>+	}
>+}
>+
> static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv)
> {
> 	u32 hotplug;
>@@ -3366,9 +3469,9 @@ static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv)
> 	 * The pulse duration bits are reserved on HSW+.
> 	 */
> 	hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
>-	hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK;
>-	hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE |
>-		   DIGITAL_PORTA_PULSE_DURATION_2ms;
>+	hotplug &= ~(DIGITAL_PORTA_HOTPLUG_ENABLE |
>+		     DIGITAL_PORTA_PULSE_DURATION_MASK);
>+	hotplug |= intel_hpd_hotplug_enables(dev_priv, ilk_hotplug_enables);
> 	I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
> }
>
>@@ -3389,35 +3492,44 @@ static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
> 	ibx_hpd_irq_setup(dev_priv);
> }
>
>-static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
>-				    u32 enabled_irqs)
>+static u32 bxt_hotplug_enables(struct drm_i915_private *i915,
>+			       enum hpd_pin pin)
>+{
>+	u32 hotplug;
>+
>+	switch (pin) {
>+	case HPD_PORT_A:
>+		hotplug = PORTA_HOTPLUG_ENABLE;
>+		if (intel_bios_is_port_hpd_inverted(i915, PORT_A))
>+			hotplug |= BXT_DDIA_HPD_INVERT;
>+		return hotplug;
>+	case HPD_PORT_B:
>+		hotplug = PORTB_HOTPLUG_ENABLE;
>+		if (intel_bios_is_port_hpd_inverted(i915, PORT_B))
>+			hotplug |= BXT_DDIB_HPD_INVERT;
>+		return hotplug;
>+	case HPD_PORT_C:
>+		hotplug = PORTC_HOTPLUG_ENABLE;
>+		if (intel_bios_is_port_hpd_inverted(i915, PORT_C))
>+			hotplug |= BXT_DDIC_HPD_INVERT;
>+		return hotplug;
>+	default:
>+		return 0;
>+	}
>+}
>+
>+static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv)
> {
> 	u32 hotplug;
>
> 	hotplug = I915_READ(PCH_PORT_HOTPLUG);
>-	hotplug |= PORTA_HOTPLUG_ENABLE |
>-		   PORTB_HOTPLUG_ENABLE |
>-		   PORTC_HOTPLUG_ENABLE;
>-
>-	drm_dbg_kms(&dev_priv->drm,
>-		    "Invert bit setting: hp_ctl:%x hp_port:%x\n",
>-		    hotplug, enabled_irqs);
>-	hotplug &= ~BXT_DDI_HPD_INVERT_MASK;
>-
>-	/*
>-	 * For BXT invert bit has to be set based on AOB design
>-	 * for HPD detection logic, update it based on VBT fields.
>-	 */
>-	if ((enabled_irqs & GEN8_DE_PORT_HOTPLUG(HPD_PORT_A)) &&
>-	    intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
>-		hotplug |= BXT_DDIA_HPD_INVERT;
>-	if ((enabled_irqs & GEN8_DE_PORT_HOTPLUG(HPD_PORT_B)) &&
>-	    intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
>-		hotplug |= BXT_DDIB_HPD_INVERT;
>-	if ((enabled_irqs & GEN8_DE_PORT_HOTPLUG(HPD_PORT_C)) &&
>-	    intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
>-		hotplug |= BXT_DDIC_HPD_INVERT;
>-
>+	hotplug &= ~(PORTA_HOTPLUG_ENABLE |
>+		     PORTB_HOTPLUG_ENABLE |
>+		     PORTC_HOTPLUG_ENABLE |
>+		     BXT_DDIA_HPD_INVERT |
>+		     BXT_DDIB_HPD_INVERT |
>+		     BXT_DDIC_HPD_INVERT);
>+	hotplug |= intel_hpd_hotplug_enables(dev_priv, bxt_hotplug_enables);
> 	I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
> }
>
>@@ -3430,7 +3542,7 @@ static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
>
> 	bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
>
>-	bxt_hpd_detection_setup(dev_priv, enabled_irqs);
>+	bxt_hpd_detection_setup(dev_priv);
> }
>
> static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
>@@ -4145,10 +4257,6 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
> 	} else {
> 		if (HAS_PCH_DG1(dev_priv))
> 			dev_priv->display.hpd_irq_setup = dg1_hpd_irq_setup;
>-		else if (HAS_PCH_JSP(dev_priv))
>-			dev_priv->display.hpd_irq_setup = jsp_hpd_irq_setup;
>-		else if (HAS_PCH_MCC(dev_priv))
>-			dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup;
> 		else if (INTEL_GEN(dev_priv) >= 11)
> 			dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
> 		else if (IS_GEN9_LP(dev_priv))
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index eacec3c46a4d..a5c55e0af2db 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -8443,23 +8443,6 @@ enum {
> #define SHPD_FILTER_CNT				_MMIO(0xc4038)
> #define   SHPD_FILTER_CNT_500_ADJ		0x001D9
>
>-#define ICP_DDI_HPD_ENABLE_MASK		(SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) | \
>-					 SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A))
>-#define ICP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(HPD_PORT_TC4) | \
>-					 ICP_TC_HPD_ENABLE(HPD_PORT_TC3) | \
>-					 ICP_TC_HPD_ENABLE(HPD_PORT_TC2) | \
>-					 ICP_TC_HPD_ENABLE(HPD_PORT_TC1))
>-#define TGP_DDI_HPD_ENABLE_MASK		(SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_C) | \
>-					 SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) | \
>-					 SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A))
>-#define TGP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(HPD_PORT_TC6) | \
>-					 ICP_TC_HPD_ENABLE(HPD_PORT_TC5) | \
>-					 ICP_TC_HPD_ENABLE_MASK)
>-#define DG1_DDI_HPD_ENABLE_MASK		(SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_D) | \
>-					 SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_C) | \
>-					 SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) | \
>-					 SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A))
>-
> #define _PCH_DPLL_A              0xc6014
> #define _PCH_DPLL_B              0xc6018
> #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
>-- 
>2.26.2
>
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Re: [Intel-gfx] [PATCH v3 19/19] drm/i915: Get rid of ibx_irq_pre_postinstall()

[Lucas De Marchi]

On Wed, Oct 28, 2020 at 11:33:23PM +0200, Ville Syrjälä wrote:
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>ibx_irq_pre_postinstall() looks totally pointless. We can just
>init both SDEIMR and SDEIER at the same time before enabling the
>master intererupt. It's equally racy as the other order due

master interrupt

>to doing all of this from the postinstall stage with the interrupt
>handler already in place. That is, safe with MSI but racy with
>shared legacy interrupts. Fortunately we should have MSI on all ilk+.
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

>---
> drivers/gpu/drm/i915/i915_irq.c | 46 ++++++++++++---------------------
> 1 file changed, 17 insertions(+), 29 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>index 95268fca2fbc..fdd132e2ec76 100644
>--- a/drivers/gpu/drm/i915/i915_irq.c
>+++ b/drivers/gpu/drm/i915/i915_irq.c
>@@ -2910,24 +2910,6 @@ static void ibx_irq_reset(struct drm_i915_private *dev_priv)
> 		I915_WRITE(SERR_INT, 0xffffffff);
> }
>
>-/*
>- * SDEIER is also touched by the interrupt handler to work around missed PCH
>- * interrupts. Hence we can't update it after the interrupt handler is enabled -
>- * instead we unconditionally enable all PCH interrupt sources here, but then
>- * only unmask them as needed with SDEIMR.
>- *
>- * This function needs to be called before interrupts are enabled.
>- */
>-static void ibx_irq_pre_postinstall(struct drm_i915_private *dev_priv)
>-{
>-	if (HAS_PCH_NOP(dev_priv))
>-		return;
>-
>-	drm_WARN_ON(&dev_priv->drm, I915_READ(SDEIER) != 0);
>-	I915_WRITE(SDEIER, 0xffffffff);
>-	POSTING_READ(SDEIER);
>-}
>-
> static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
> {
> 	struct intel_uncore *uncore = &dev_priv->uncore;
>@@ -3545,8 +3527,20 @@ static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
> 	bxt_hpd_detection_setup(dev_priv);
> }
>
>+/*
>+ * SDEIER is also touched by the interrupt handler to work around missed PCH
>+ * interrupts. Hence we can't update it after the interrupt handler is enabled -
>+ * instead we unconditionally enable all PCH interrupt sources here, but then
>+ * only unmask them as needed with SDEIMR.
>+ *
>+ * Note that we currently do this after installing the interrupt handler,
>+ * but before we enable the master interrupt. That should be sufficient
>+ * to avoid races with the irq handler, assuming we have MSI. Shared legacy
>+ * interrupts could still race.
>+ */
> static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
> {
>+	struct intel_uncore *uncore = &dev_priv->uncore;
> 	u32 mask;
>
> 	if (HAS_PCH_NOP(dev_priv))
>@@ -3559,8 +3553,7 @@ static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
> 	else
> 		mask = SDE_GMBUS_CPT;
>
>-	gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
>-	I915_WRITE(SDEIMR, ~mask);
>+	GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> }
>
> static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
>@@ -3593,14 +3586,12 @@ static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
>
> 	dev_priv->irq_mask = ~display_mask;
>
>-	ibx_irq_pre_postinstall(dev_priv);
>+	ibx_irq_postinstall(dev_priv);
>
> 	gen5_gt_irq_postinstall(&dev_priv->gt);
>
> 	GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask,
> 		      display_mask | extra_mask);
>-
>-	ibx_irq_postinstall(dev_priv);
> }
>
> void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
>@@ -3725,15 +3716,12 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
>
> static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
> {
>-	if (HAS_PCH_SPLIT(dev_priv))
>-		ibx_irq_pre_postinstall(dev_priv);
>-
>-	gen8_gt_irq_postinstall(&dev_priv->gt);
>-	gen8_de_irq_postinstall(dev_priv);
>-
> 	if (HAS_PCH_SPLIT(dev_priv))
> 		ibx_irq_postinstall(dev_priv);
>
>+	gen8_gt_irq_postinstall(&dev_priv->gt);
>+	gen8_de_irq_postinstall(dev_priv);
>+
> 	gen8_master_intr_enable(dev_priv->uncore.regs);
> }
>
>-- 
>2.26.2
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Futher cleanup around hpd pins and port identfiers (rev5)

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 7277 bytes --]

== Series Details ==

Series: drm/i915: Futher cleanup around hpd pins and port identfiers (rev5)
URL   : https://patchwork.freedesktop.org/series/82411/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9214 -> Patchwork_18801
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/index.html

New tests
---------

  New tests have been introduced between CI_DRM_9214 and Patchwork_18801:

### New CI tests (1) ###

  * boot:
    - Statuses : 39 pass(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in Patchwork_18801 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_gttfill@basic:
    - fi-tgl-y:           [PASS][1] -> [DMESG-WARN][2] ([i915#402]) +2 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/fi-tgl-y/igt@gem_exec_gttfill@basic.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/fi-tgl-y/igt@gem_exec_gttfill@basic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - fi-bsw-kefka:       [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - fi-icl-u2:          [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  
#### Possible fixes ####

  * igt@debugfs_test@read_all_entries:
    - fi-tgl-y:           [DMESG-WARN][7] ([i915#402]) -> [PASS][8] +2 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/fi-tgl-y/igt@debugfs_test@read_all_entries.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/fi-tgl-y/igt@debugfs_test@read_all_entries.html
    - {fi-kbl-7560u}:     [INCOMPLETE][9] ([i915#2417]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/fi-kbl-7560u/igt@debugfs_test@read_all_entries.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/fi-kbl-7560u/igt@debugfs_test@read_all_entries.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - fi-bsw-kefka:       [DMESG-WARN][11] ([i915#1982]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
    - fi-apl-guc:         [DMESG-WARN][13] ([i915#1635] / [i915#1982]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/fi-apl-guc/igt@i915_pm_rpm@basic-pci-d3-state.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/fi-apl-guc/igt@i915_pm_rpm@basic-pci-d3-state.html

  * igt@kms_busy@basic@flip:
    - fi-kbl-soraka:      [DMESG-WARN][15] ([i915#1982]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/fi-kbl-soraka/igt@kms_busy@basic@flip.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/fi-kbl-soraka/igt@kms_busy@basic@flip.html
    - fi-tgl-y:           [DMESG-WARN][17] ([i915#1982]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/fi-tgl-y/igt@kms_busy@basic@flip.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/fi-tgl-y/igt@kms_busy@basic@flip.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-icl-u2:          [DMESG-WARN][19] ([i915#1982]) -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html

  * igt@vgem_basic@unload:
    - fi-skl-guc:         [DMESG-WARN][21] ([i915#2203]) -> [PASS][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/fi-skl-guc/igt@vgem_basic@unload.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/fi-skl-guc/igt@vgem_basic@unload.html

  
#### Warnings ####

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - fi-tgl-y:           [DMESG-WARN][23] ([i915#1982] / [i915#2411]) -> [DMESG-WARN][24] ([i915#2411])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/fi-tgl-y/igt@i915_pm_rpm@basic-pci-d3-state.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/fi-tgl-y/igt@i915_pm_rpm@basic-pci-d3-state.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
  [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
  [i915#2417]: https://gitlab.freedesktop.org/drm/intel/issues/2417
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402


Participating hosts (41 -> 39)
------------------------------

  Missing    (2): fi-bsw-cyan fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_9214 -> Patchwork_18801

  CI-20190529: 20190529
  CI_DRM_9214: c485050a56cf0edaed15b8297d5540bd0f4310b9 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5827: 7fd7e3fb8b42eb4e62a4575f6edc5a048e5bec3d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_18801: bd3fd9cc28ab22e429cf6eb3374feafd810cb2b1 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

bd3fd9cc28ab drm/i915: Get rid of ibx_irq_pre_postinstall()
f2def9dff59f drm/i915: Use GEN3_IRQ_INIT() to init south interrupts in icp+
3059c7ee9196 drm/i915: Enable hpd logic only for ports that are present
26e100e104d0 drm/i915: Remove the per-plaform IIR HPD masking
567b2cbf4a84 drm/i915: Rename 'tmp_mask'
62b52af3a1fc drm/i915: Don't enable hpd detection logic from irq_postinstall()
2cecffb1a88e drm/i915: Split gen11_hpd_detection_setup() into tc vs. tbt variants
15e7a4125c07 drm/i915: Relocate intel_hpd_{enabled, hotplug}_irqs()
8b3e20e749bc drm/i915: s/tc_port/hpd_pin/ in icp+ TC hotplug bits
6d636206aba9 drm/i915: s/tc_port/hpd_pin/ in GEN11_{TC, TBT}_HOTPLUG()
60ce87b4b638 drm/i915: s/port/hpd_pin/ for icp+ ddi hpd bits
4a178195598a drm/i915: Introduce GEN8_DE_PORT_HOTPLUG()
00239142669f drm/i915: Parametrize BXT_DE_PORT_HP_DDI with hpd_pin
cb0bc14e42f1 drm/i915: Use AUX_CH_USBCn for the RKL VBT AUX CH setup
907a6f378413 drm/i915: Pimp AUX CH names
5b31fc7d2973 drm/i915: Introduce AUX_CH_USBCn
287c7226cbc0 drm/i915: Give DDI encoders even better names
fe19b59abf59 drm/i915: Add PORT_TCn aliases to enum port
ee08af3a4155 drm/i915: s/PORT_TC/TC_PORT_/

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/index.html

[-- Attachment #1.2: Type: text/html, Size: 8917 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Futher cleanup around hpd pins and port identfiers (rev5)

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 17034 bytes --]

== Series Details ==

Series: drm/i915: Futher cleanup around hpd pins and port identfiers (rev5)
URL   : https://patchwork.freedesktop.org/series/82411/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9214_full -> Patchwork_18801_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_18801_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_18801_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_18801_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_create@create-clear:
    - shard-tglb:         [PASS][1] -> [DMESG-FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-tglb3/igt@gem_create@create-clear.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/shard-tglb6/igt@gem_create@create-clear.html

  * igt@gem_exec_whisper@basic-contexts-all:
    - shard-iclb:         [PASS][3] -> [INCOMPLETE][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-iclb5/igt@gem_exec_whisper@basic-contexts-all.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/shard-iclb2/igt@gem_exec_whisper@basic-contexts-all.html

  
New tests
---------

  New tests have been introduced between CI_DRM_9214_full and Patchwork_18801_full:

### New CI tests (1) ###

  * boot:
    - Statuses : 200 pass(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in Patchwork_18801_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@drm_read@empty-block:
    - shard-glk:          [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-glk1/igt@drm_read@empty-block.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/shard-glk8/igt@drm_read@empty-block.html

  * igt@kms_cursor_crc@pipe-c-cursor-128x42-sliding:
    - shard-skl:          [PASS][7] -> [FAIL][8] ([i915#54]) +1 similar issue
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-skl8/igt@kms_cursor_crc@pipe-c-cursor-128x42-sliding.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/shard-skl8/igt@kms_cursor_crc@pipe-c-cursor-128x42-sliding.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
    - shard-skl:          [PASS][9] -> [FAIL][10] ([i915#79])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/shard-skl2/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@a-dp1:
    - shard-apl:          [PASS][11] -> [DMESG-WARN][12] ([i915#1635] / [i915#1982]) +1 similar issue
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-apl2/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-dp1.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/shard-apl3/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-dp1.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1:
    - shard-iclb:         [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) +2 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-iclb8/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/shard-iclb5/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html

  * igt@kms_flip_tiling@flip-y-tiled:
    - shard-kbl:          [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) +2 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-kbl2/igt@kms_flip_tiling@flip-y-tiled.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/shard-kbl4/igt@kms_flip_tiling@flip-y-tiled.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-skl:          [PASS][17] -> [FAIL][18] ([i915#1188]) +2 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-skl10/igt@kms_hdr@bpc-switch-dpms.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/shard-skl1/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_plane_cursor@pipe-c-primary-size-128:
    - shard-skl:          [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) +11 similar issues
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-skl7/igt@kms_plane_cursor@pipe-c-primary-size-128.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/shard-skl6/igt@kms_plane_cursor@pipe-c-primary-size-128.html

  * igt@kms_psr2_su@frontbuffer:
    - shard-iclb:         [PASS][21] -> [SKIP][22] ([fdo#109642] / [fdo#111068])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/shard-iclb7/igt@kms_psr2_su@frontbuffer.html

  * igt@kms_psr@psr2_cursor_render:
    - shard-iclb:         [PASS][23] -> [SKIP][24] ([fdo#109441]) +1 similar issue
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/shard-iclb8/igt@kms_psr@psr2_cursor_render.html

  * igt@perf@polling-parameterized:
    - shard-glk:          [PASS][25] -> [FAIL][26] ([i915#1542])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-glk3/igt@perf@polling-parameterized.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/shard-glk9/igt@perf@polling-parameterized.html

  * igt@prime_vgem@sync@rcs0:
    - shard-iclb:         [PASS][27] -> [INCOMPLETE][28] ([i915#409])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-iclb3/igt@prime_vgem@sync@rcs0.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/shard-iclb4/igt@prime_vgem@sync@rcs0.html

  * igt@prime_vgem@sync@vcs0:
    - shard-tglb:         [PASS][29] -> [INCOMPLETE][30] ([i915#409])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-tglb2/igt@prime_vgem@sync@vcs0.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/shard-tglb1/igt@prime_vgem@sync@vcs0.html

  
#### Possible fixes ####

  * igt@api_intel_bb@blit-noreloc-purge-cache:
    - shard-hsw:          [FAIL][31] -> [PASS][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-hsw4/igt@api_intel_bb@blit-noreloc-purge-cache.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/shard-hsw7/igt@api_intel_bb@blit-noreloc-purge-cache.html

  * igt@core_hotunplug@hotrebind-lateclose:
    - shard-snb:          [INCOMPLETE][33] ([i915#82]) -> [PASS][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-snb5/igt@core_hotunplug@hotrebind-lateclose.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/shard-snb2/igt@core_hotunplug@hotrebind-lateclose.html

  * igt@gem_exec_create@madvise:
    - shard-hsw:          [FAIL][35] ([i915#1888]) -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-hsw1/igt@gem_exec_create@madvise.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/shard-hsw4/igt@gem_exec_create@madvise.html

  * igt@gem_huc_copy@huc-copy:
    - shard-tglb:         [SKIP][37] ([i915#2190]) -> [PASS][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-tglb6/igt@gem_huc_copy@huc-copy.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/shard-tglb8/igt@gem_huc_copy@huc-copy.html

  * igt@gem_ppgtt@blt-vs-render-ctx0:
    - shard-snb:          [DMESG-FAIL][39] -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-snb7/igt@gem_ppgtt@blt-vs-render-ctx0.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/shard-snb6/igt@gem_ppgtt@blt-vs-render-ctx0.html

  * igt@i915_suspend@forcewake:
    - shard-skl:          [INCOMPLETE][41] ([i915#636]) -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-skl8/igt@i915_suspend@forcewake.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/shard-skl4/igt@i915_suspend@forcewake.html

  * igt@kms_cursor_crc@pipe-c-cursor-256x85-sliding:
    - shard-skl:          [FAIL][43] ([i915#54]) -> [PASS][44] +2 similar issues
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-skl2/igt@kms_cursor_crc@pipe-c-cursor-256x85-sliding.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/shard-skl1/igt@kms_cursor_crc@pipe-c-cursor-256x85-sliding.html

  * igt@kms_cursor_edge_walk@pipe-b-256x256-bottom-edge:
    - shard-glk:          [DMESG-WARN][45] ([i915#1982]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-glk8/igt@kms_cursor_edge_walk@pipe-b-256x256-bottom-edge.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/shard-glk7/igt@kms_cursor_edge_walk@pipe-b-256x256-bottom-edge.html
    - shard-hsw:          [DMESG-WARN][47] ([i915#1982]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-hsw1/igt@kms_cursor_edge_walk@pipe-b-256x256-bottom-edge.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/shard-hsw1/igt@kms_cursor_edge_walk@pipe-b-256x256-bottom-edge.html

  * igt@kms_cursor_edge_walk@pipe-c-128x128-right-edge:
    - shard-apl:          [DMESG-WARN][49] ([i915#1635] / [i915#1982]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-apl1/igt@kms_cursor_edge_walk@pipe-c-128x128-right-edge.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/shard-apl4/igt@kms_cursor_edge_walk@pipe-c-128x128-right-edge.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic:
    - shard-skl:          [FAIL][51] ([i915#2346]) -> [PASS][52] +1 similar issue
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2:
    - shard-glk:          [FAIL][53] ([i915#2122]) -> [PASS][54] +1 similar issue
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-glk1/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2.html

  * igt@kms_frontbuffer_tracking@psr-slowdraw:
    - shard-skl:          [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] +3 similar issues
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-skl3/igt@kms_frontbuffer_tracking@psr-slowdraw.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/shard-skl9/igt@kms_frontbuffer_tracking@psr-slowdraw.html

  * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
    - shard-skl:          [FAIL][57] ([fdo#108145] / [i915#265]) -> [PASS][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html

  * igt@kms_plane_lowres@pipe-a-tiling-x:
    - shard-kbl:          [DMESG-WARN][59] ([i915#165] / [i915#78]) -> [PASS][60]
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-kbl2/igt@kms_plane_lowres@pipe-a-tiling-x.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/shard-kbl6/igt@kms_plane_lowres@pipe-a-tiling-x.html

  * igt@kms_psr@psr2_primary_mmap_gtt:
    - shard-iclb:         [SKIP][61] ([fdo#109441]) -> [PASS][62]
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-iclb5/igt@kms_psr@psr2_primary_mmap_gtt.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html

  * igt@kms_universal_plane@universal-plane-gen9-features-pipe-a:
    - shard-kbl:          [DMESG-WARN][63] ([i915#1982]) -> [PASS][64] +2 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-kbl1/igt@kms_universal_plane@universal-plane-gen9-features-pipe-a.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/shard-kbl1/igt@kms_universal_plane@universal-plane-gen9-features-pipe-a.html

  * igt@perf@polling-parameterized:
    - shard-skl:          [FAIL][65] ([i915#1542]) -> [PASS][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-skl1/igt@perf@polling-parameterized.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/shard-skl10/igt@perf@polling-parameterized.html

  * igt@vgem_slow@nohang:
    - shard-hsw:          [INCOMPLETE][67] -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-hsw1/igt@vgem_slow@nohang.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/shard-hsw1/igt@vgem_slow@nohang.html

  
#### Warnings ####

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-tglb:         [DMESG-WARN][69] ([i915#1982] / [i915#2411]) -> [DMESG-WARN][70] ([i915#2411])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-tglb1/igt@kms_frontbuffer_tracking@fbc-suspend.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/shard-tglb2/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@runner@aborted:
    - shard-tglb:         [FAIL][71] ([i915#1602]) -> ([FAIL][72], [FAIL][73]) ([i915#1602] / [i915#409])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-tglb8/igt@runner@aborted.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/shard-tglb1/igt@runner@aborted.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/shard-tglb1/igt@runner@aborted.html

  * igt@sysfs_timeslice_duration@timeout@rcs0:
    - shard-skl:          [DMESG-WARN][74] ([i915#1982]) -> [DMESG-FAIL][75] ([i915#1982])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-skl1/igt@sysfs_timeslice_duration@timeout@rcs0.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/shard-skl10/igt@sysfs_timeslice_duration@timeout@rcs0.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
  [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
  [i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
  [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
  [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
  [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
  [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#409]: https://gitlab.freedesktop.org/drm/intel/issues/409
  [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
  [i915#636]: https://gitlab.freedesktop.org/drm/intel/issues/636
  [i915#78]: https://gitlab.freedesktop.org/drm/intel/issues/78
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82


Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * Linux: CI_DRM_9214 -> Patchwork_18801

  CI-20190529: 20190529
  CI_DRM_9214: c485050a56cf0edaed15b8297d5540bd0f4310b9 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5827: 7fd7e3fb8b42eb4e62a4575f6edc5a048e5bec3d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_18801: bd3fd9cc28ab22e429cf6eb3374feafd810cb2b1 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/index.html

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Re: [Intel-gfx] [PATCH v3 17/19] drm/i915: Enable hpd logic only for ports that are present

[Ville Syrjälä]

On Wed, Oct 28, 2020 at 03:16:57PM -0700, Lucas De Marchi wrote:
> On Wed, Oct 28, 2020 at 11:33:21PM +0200, Ville Syrjälä wrote:
> >From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> >Let's enable the hardware hpd logic only for the ports we
> >can actually use.
> >
> >In theory this may save some miniscule amounts of power,
> >and more importantly it eliminates a lot if platform specific
> >codepaths since the generic thing can now deal with any
> >combination of ports being present on each SKU.
> >
> >v2: Deal with DG1
> >
> >Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> 
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

While applying I noticed that I fumbled the dg1 changes slightly.
icp_ddi_hotplug_enables() was missing the HPD_PORT_D stuff.
I fixed that up and pushed the lot.

Thanks for the review.

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH v3 03/19] drm/i915: Give DDI encoders even better names

[Jani Nikula]

On Wed, 28 Oct 2020, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Let's pimp the DDI encoder->name to reflect what the spec calls them.
> Ie. on pre-tgl DDI A-F, on tgl+ DDI A-C or DDI TC1-6.
>
> Also since each encoder is really a combination of the DDI and the PHY
> we include the PHY name as well.
>
> ICL is a bit special since it already has the two different types
> of DDIs (combo or TC) but it still calls them just DDI A-F regarless
> of the type. For that let's add an extra "(TC)" note to remind
> is which type of DDI it really is.
>
> The code is darn ugly, but not sure there's much we can do about it.
>
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 27 ++++++++++++++++++++++--
>  1 file changed, 25 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 24245157dcb9..19b16517a502 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -5174,8 +5174,31 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
>  
>  	encoder = &dig_port->base;
>  
> -	drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
> -			 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
> +	if (INTEL_GEN(dev_priv) >= 12) {
> +		enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> +
> +		drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
> +				 DRM_MODE_ENCODER_TMDS,
> +				 "DDI %s%c/PHY %s%c",
> +				 port >= PORT_TC1 ? "TC" : "",
> +				 port >= PORT_TC1 ? port_name(port) : port - PORT_TC1 + '1',
> +				 tc_port != TC_PORT_NONE ? "TC" : "",
> +				 tc_port != TC_PORT_NONE ? phy_name(phy) : tc_port - TC_PORT_1 + '1');

Frankly, this is a really ugly way to define encoder names, and it's
hard to decipher what's actually going on. Even after I see logs with
obviously bogus names such as:

[ENCODER:235:DDI ./PHY 0]

I find it tedious to decipher what exactly is wrong here.

I guess the 2nd port >= PORT_TC1 check should be reversed, but it
doesn't exactly give me confidence about the rest.

BR,
Jani.


> +	} else if (INTEL_GEN(dev_priv) >= 11) {
> +		enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> +
> +		drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
> +				 DRM_MODE_ENCODER_TMDS,
> +				 "DDI %c%s/PHY %s%c",
> +				 port_name(port),
> +				 port >= PORT_C ? " (TC)" : "",
> +				 tc_port != TC_PORT_NONE ? "TC" : "",
> +				 tc_port != TC_PORT_NONE ? phy_name(phy) : tc_port - TC_PORT_1 + '1');
> +	} else {
> +		drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
> +				 DRM_MODE_ENCODER_TMDS,
> +				 "DDI %c/PHY %c", port_name(port),  phy_name(phy));
> +	}
>  
>  	mutex_init(&dig_port->hdcp_mutex);
>  	dig_port->num_hdcp_streams = 0;

-- 
Jani Nikula, Intel Open Source Graphics Center
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Re: [Intel-gfx] [PATCH v3 03/19] drm/i915: Give DDI encoders even better names

[Ville Syrjälä]

On Tue, Nov 17, 2020 at 04:33:24PM +0200, Jani Nikula wrote:
> On Wed, 28 Oct 2020, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Let's pimp the DDI encoder->name to reflect what the spec calls them.
> > Ie. on pre-tgl DDI A-F, on tgl+ DDI A-C or DDI TC1-6.
> >
> > Also since each encoder is really a combination of the DDI and the PHY
> > we include the PHY name as well.
> >
> > ICL is a bit special since it already has the two different types
> > of DDIs (combo or TC) but it still calls them just DDI A-F regarless
> > of the type. For that let's add an extra "(TC)" note to remind
> > is which type of DDI it really is.
> >
> > The code is darn ugly, but not sure there's much we can do about it.
> >
> > Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_ddi.c | 27 ++++++++++++++++++++++--
> >  1 file changed, 25 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 24245157dcb9..19b16517a502 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -5174,8 +5174,31 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
> >  
> >  	encoder = &dig_port->base;
> >  
> > -	drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
> > -			 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
> > +	if (INTEL_GEN(dev_priv) >= 12) {
> > +		enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> > +
> > +		drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
> > +				 DRM_MODE_ENCODER_TMDS,
> > +				 "DDI %s%c/PHY %s%c",
> > +				 port >= PORT_TC1 ? "TC" : "",
> > +				 port >= PORT_TC1 ? port_name(port) : port - PORT_TC1 + '1',
> > +				 tc_port != TC_PORT_NONE ? "TC" : "",
> > +				 tc_port != TC_PORT_NONE ? phy_name(phy) : tc_port - TC_PORT_1 + '1');
> 
> Frankly, this is a really ugly way to define encoder names, and it's
> hard to decipher what's actually going on. Even after I see logs with
> obviously bogus names such as:
> 
> [ENCODER:235:DDI ./PHY 0]
> 
> I find it tedious to decipher what exactly is wrong here.
> 
> I guess the 2nd port >= PORT_TC1 check should be reversed, but it
> doesn't exactly give me confidence about the rest.

Doh. Yeah, that is definitely the case. The second tc_port check
seems equally crap. Maybe I just don't know how to use ?: anymore :/

I guess a few extra macros/functions could clean it up a bit. The
other option would be just the fully declarative approach that was
discussed before. But there's an annoying amount of runtime
detection going on with port init so not sure how much we can
declare up front.

> 
> BR,
> Jani.
> 
> 
> > +	} else if (INTEL_GEN(dev_priv) >= 11) {
> > +		enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> > +
> > +		drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
> > +				 DRM_MODE_ENCODER_TMDS,
> > +				 "DDI %c%s/PHY %s%c",
> > +				 port_name(port),
> > +				 port >= PORT_C ? " (TC)" : "",
> > +				 tc_port != TC_PORT_NONE ? "TC" : "",
> > +				 tc_port != TC_PORT_NONE ? phy_name(phy) : tc_port - TC_PORT_1 + '1');
> > +	} else {
> > +		drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
> > +				 DRM_MODE_ENCODER_TMDS,
> > +				 "DDI %c/PHY %c", port_name(port),  phy_name(phy));
> > +	}
> >  
> >  	mutex_init(&dig_port->hdcp_mutex);
> >  	dig_port->num_hdcp_streams = 0;
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center

-- 
Ville Syrjälä
Intel
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