* [Intel-gfx] [PATCH] drm/i915/dg1: map/unmap pll clocks
@ 2020-11-06 21:00 Lucas De Marchi
2020-11-06 21:15 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Lucas De Marchi @ 2020-11-06 21:00 UTC (permalink / raw)
To: intel-gfx
DG1 uses 2 registers for the ddi clock mapping, with PHY A and B using
DPCLKA_CFGCR0 and PHY C and D using DPCLKA1_CFGCR0. Hide this behind a
single macro that chooses the correct register according to the phy
being accessed, use the correct bitfields for each pll/phy and implement
separate functions for DG1 since it doesn't share much with ICL/TGL
anymore.
The previous values were correct for PHY A and B since they were using
the same register as before and the bitfields were matching.
v2: Add comment and try to simplify DG1_DPCLKA* macros by reusing
previous ones
v3:
- Fix DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK() after wrong macro reuse
- Move phy -> id map to a separate macro (Aditya)
- Remove DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK where not required
(Aditya)
- Use drm_WARN_ON
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 91 +++++++++++++++++++-
drivers/gpu/drm/i915/display/intel_display.c | 24 +++++-
drivers/gpu/drm/i915/i915_reg.h | 24 ++++++
3 files changed, 135 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 19b16517a502..36a4a1f4d775 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2970,6 +2970,40 @@ static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
return 0;
}
+static void dg1_map_plls_to_ports(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+ u32 val;
+
+ /*
+ * If we fail this, something went very wrong: first 2 PLLs should be
+ * used by first 2 phys and last 2 PLLs by last phys
+ */
+ if (drm_WARN_ON(&dev_priv->drm,
+ (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) ||
+ (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C)))
+ return;
+
+ mutex_lock(&dev_priv->dpll.lock);
+
+ val = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
+ drm_WARN_ON(&dev_priv->drm,
+ (val & DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)) == 0);
+
+ val &= ~DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+ val |= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
+ intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val);
+ intel_de_posting_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
+
+ val &= ~DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
+ intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val);
+
+ mutex_unlock(&dev_priv->dpll.lock);
+}
+
static void icl_map_plls_to_ports(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
@@ -3017,6 +3051,19 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
mutex_unlock(&dev_priv->dpll.lock);
}
+static void dg1_unmap_plls_to_ports(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+
+ mutex_lock(&dev_priv->dpll.lock);
+
+ intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy), 0,
+ DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
+
+ mutex_unlock(&dev_priv->dpll.lock);
+}
+
static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -3032,6 +3079,37 @@ static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
mutex_unlock(&dev_priv->dpll.lock);
}
+static void dg1_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
+ u32 port_mask, bool ddi_clk_needed)
+{
+ enum port port;
+ u32 val;
+
+ for_each_port_masked(port, port_mask) {
+ enum phy phy = intel_port_to_phy(dev_priv, port);
+ bool ddi_clk_off;
+
+ val = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
+ ddi_clk_off = val & DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
+
+ if (ddi_clk_needed == !ddi_clk_off)
+ continue;
+
+ /*
+ * Punt on the case now where clock is gated, but it would
+ * be needed by the port. Something else is really broken then.
+ */
+ if (drm_WARN_ON(&dev_priv->drm, ddi_clk_needed))
+ continue;
+
+ drm_notice(&dev_priv->drm,
+ "PHY %c is disabled with an ungated DDI clock, gate it\n",
+ phy_name(phy));
+ val |= DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
+ intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val);
+ }
+}
+
static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
u32 port_mask, bool ddi_clk_needed)
{
@@ -3114,7 +3192,10 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
ddi_clk_needed = false;
}
- icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed);
+ if (IS_DG1(dev_priv))
+ dg1_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed);
+ else
+ icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed);
}
static void intel_ddi_clk_select(struct intel_encoder *encoder,
@@ -3666,7 +3747,9 @@ static void intel_ddi_pre_enable(struct intel_atomic_state *state,
drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder);
- if (INTEL_GEN(dev_priv) >= 11)
+ if (IS_DG1(dev_priv))
+ dg1_map_plls_to_ports(encoder, crtc_state);
+ else if (INTEL_GEN(dev_priv) >= 11)
icl_map_plls_to_ports(encoder, crtc_state);
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
@@ -3848,7 +3931,9 @@ static void intel_ddi_post_disable(struct intel_atomic_state *state,
intel_ddi_post_disable_dp(state, encoder, old_crtc_state,
old_conn_state);
- if (INTEL_GEN(dev_priv) >= 11)
+ if (IS_DG1(dev_priv))
+ dg1_unmap_plls_to_ports(encoder);
+ else if (INTEL_GEN(dev_priv) >= 11)
icl_unmap_plls_to_ports(encoder);
if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 6faca1e739c8..2729c852c668 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11003,6 +11003,26 @@ static int hsw_crtc_compute_clock(struct intel_crtc *crtc,
return 0;
}
+static void dg1_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
+ struct intel_crtc_state *pipe_config)
+{
+ enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
+ enum phy phy = intel_port_to_phy(dev_priv, port);
+ enum intel_dpll_id id;
+ u32 clk_sel;
+
+ clk_sel = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy)) & DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+ id = DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_DPLL_MAP(clk_sel, phy);
+
+ if (WARN_ON(id > DPLL_ID_DG1_DPLL3))
+ return;
+
+ pipe_config->icl_port_dplls[port_dpll_id].pll =
+ intel_get_shared_dpll_by_id(dev_priv, id);
+
+ icl_set_active_port_dpll(pipe_config, port_dpll_id);
+}
+
static void cnl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
struct intel_crtc_state *pipe_config)
{
@@ -11311,7 +11331,9 @@ static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
}
- if (INTEL_GEN(dev_priv) >= 11)
+ if (IS_DG1(dev_priv))
+ dg1_get_ddi_pll(dev_priv, port, pipe_config);
+ else if (INTEL_GEN(dev_priv) >= 11)
icl_get_ddi_pll(dev_priv, port, pipe_config);
else if (IS_CANNONLAKE(dev_priv))
cnl_get_ddi_pll(dev_priv, port, pipe_config);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bb0656875697..39664ba553ec 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -230,12 +230,14 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b)
#define _PORT(port, a, b) _PICK_EVEN(port, a, b)
#define _PLL(pll, a, b) _PICK_EVEN(pll, a, b)
+#define _PHY(phy, a, b) _PICK_EVEN(phy, a, b)
#define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
#define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b))
#define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))
#define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
#define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
+#define _MMIO_PHY(phy, a, b) _MMIO(_PHY(phy, a, b))
#define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__)
@@ -10300,6 +10302,7 @@ enum skl_power_gate {
#define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
#define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
+/* ICL Clocks */
#define ICL_DPCLKA_CFGCR0 _MMIO(0x164280)
#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24))
#define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10)
@@ -10315,6 +10318,27 @@ enum skl_power_gate {
#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \
((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
+/*
+ * DG1 Clocks
+ * First registers controls the first A and B, while the second register
+ * controls the phy C and D. The bits on these registers are the
+ * same, but refer to different phys
+ */
+#define _DG1_DPCLKA_CFGCR0 0x164280
+#define _DG1_DPCLKA1_CFGCR0 0x16C280
+#define _DG1_DPCLKA_PHY_IDX(phy) ((phy) % 2)
+#define _DG1_DPCLKA_PLL_IDX(pll) ((pll) % 2)
+#define _DG1_PHY_DPLL_MAP(phy) ((phy) >= PHY_C ? DPLL_ID_DG1_DPLL2 : DPLL_ID_DG1_DPLL0)
+#define DG1_DPCLKA_CFGCR0(phy) _MMIO_PHY((phy) / 2, \
+ _DG1_DPCLKA_CFGCR0, \
+ _DG1_DPCLKA1_CFGCR0)
+#define DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT(_DG1_DPCLKA_PHY_IDX(phy) + 10)
+#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) (_DG1_DPCLKA_PHY_IDX(phy) * 2)
+#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) (_DG1_DPCLKA_PLL_IDX(pll) << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
+#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (0x3 << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
+#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_DPLL_MAP(clk_sel, phy) \
+ (((clk_sel) >> DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) + _DG1_PHY_DPLL_MAP(phy))
+
/* CNL PLL */
#define DPLL0_ENABLE 0x46010
#define DPLL1_ENABLE 0x46014
--
2.29.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dg1: map/unmap pll clocks
2020-11-06 21:00 [Intel-gfx] [PATCH] drm/i915/dg1: map/unmap pll clocks Lucas De Marchi
@ 2020-11-06 21:15 ` Patchwork
2020-11-06 21:45 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2020-11-06 21:15 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/dg1: map/unmap pll clocks
URL : https://patchwork.freedesktop.org/series/83592/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a589e37423a2 drm/i915/dg1: map/unmap pll clocks
-:187: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#187: FILE: drivers/gpu/drm/i915/display/intel_display.c:11014:
+ clk_sel = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy)) & DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
-:254: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#254: FILE: drivers/gpu/drm/i915/i915_reg.h:10331:
+#define _DG1_PHY_DPLL_MAP(phy) ((phy) >= PHY_C ? DPLL_ID_DG1_DPLL2 : DPLL_ID_DG1_DPLL0)
-:260: WARNING:LONG_LINE: line length of 126 exceeds 100 columns
#260: FILE: drivers/gpu/drm/i915/i915_reg.h:10337:
+#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) (_DG1_DPCLKA_PLL_IDX(pll) << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
-:261: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#261: FILE: drivers/gpu/drm/i915/i915_reg.h:10338:
+#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (0x3 << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
-:262: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'phy' - possible side-effects?
#262: FILE: drivers/gpu/drm/i915/i915_reg.h:10339:
+#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_DPLL_MAP(clk_sel, phy) \
+ (((clk_sel) >> DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) + _DG1_PHY_DPLL_MAP(phy))
total: 0 errors, 4 warnings, 1 checks, 211 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dg1: map/unmap pll clocks
2020-11-06 21:00 [Intel-gfx] [PATCH] drm/i915/dg1: map/unmap pll clocks Lucas De Marchi
2020-11-06 21:15 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
@ 2020-11-06 21:45 ` Patchwork
2020-11-06 22:56 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-11-06 23:02 ` [Intel-gfx] [PATCH] " Aditya Swarup
3 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2020-11-06 21:45 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 6065 bytes --]
== Series Details ==
Series: drm/i915/dg1: map/unmap pll clocks
URL : https://patchwork.freedesktop.org/series/83592/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9284 -> Patchwork_18869
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/index.html
New tests
---------
New tests have been introduced between CI_DRM_9284 and Patchwork_18869:
### New CI tests (1) ###
* boot:
- Statuses : 40 pass(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_18869 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@read_all_entries:
- fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#1982] / [i915#402])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9284/fi-tgl-y/igt@debugfs_test@read_all_entries.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/fi-tgl-y/igt@debugfs_test@read_all_entries.html
* igt@gem_tiled_blits@basic:
- fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9284/fi-tgl-y/igt@gem_tiled_blits@basic.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/fi-tgl-y/igt@gem_tiled_blits@basic.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9284/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@i915_selftest@live@execlists:
- fi-cfl-8109u: [PASS][7] -> [INCOMPLETE][8] ([i915#2089])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9284/fi-cfl-8109u/igt@i915_selftest@live@execlists.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/fi-cfl-8109u/igt@i915_selftest@live@execlists.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-skl-6700k2: [PASS][9] -> [DMESG-WARN][10] ([i915#1982])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9284/fi-skl-6700k2/igt@kms_chamelium@hdmi-crc-fast.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/fi-skl-6700k2/igt@kms_chamelium@hdmi-crc-fast.html
* igt@kms_frontbuffer_tracking@basic:
- fi-tgl-y: [PASS][11] -> [DMESG-WARN][12] ([i915#1982])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9284/fi-tgl-y/igt@kms_frontbuffer_tracking@basic.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/fi-tgl-y/igt@kms_frontbuffer_tracking@basic.html
#### Possible fixes ####
* igt@gem_exec_create@basic:
- fi-icl-u2: [INCOMPLETE][13] -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9284/fi-icl-u2/igt@gem_exec_create@basic.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/fi-icl-u2/igt@gem_exec_create@basic.html
* igt@gem_exec_suspend@basic-s0:
- fi-apl-guc: [DMESG-WARN][15] ([i915#1635] / [i915#62]) -> [PASS][16] +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9284/fi-apl-guc/igt@gem_exec_suspend@basic-s0.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/fi-apl-guc/igt@gem_exec_suspend@basic-s0.html
* igt@gem_sync@basic-each:
- fi-tgl-y: [DMESG-WARN][17] ([i915#402]) -> [PASS][18] +1 similar issue
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9284/fi-tgl-y/igt@gem_sync@basic-each.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/fi-tgl-y/igt@gem_sync@basic-each.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-byt-j1900: [DMESG-WARN][19] ([i915#1982]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9284/fi-byt-j1900/igt@i915_pm_rpm@basic-pci-d3-state.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/fi-byt-j1900/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-apl-guc: [DMESG-WARN][21] ([i915#1635] / [i915#1982]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9284/fi-apl-guc/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/fi-apl-guc/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
#### Warnings ####
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-tgl-y: [DMESG-WARN][23] ([i915#2411]) -> [DMESG-WARN][24] ([i915#1982] / [i915#2411])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9284/fi-tgl-y/igt@i915_pm_rpm@basic-pci-d3-state.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/fi-tgl-y/igt@i915_pm_rpm@basic-pci-d3-state.html
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2089]: https://gitlab.freedesktop.org/drm/intel/issues/2089
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
Participating hosts (44 -> 40)
------------------------------
Missing (4): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u
Build changes
-------------
* Linux: CI_DRM_9284 -> Patchwork_18869
CI-20190529: 20190529
CI_DRM_9284: d0c4fd640b80d3dc107e269992a38c26f71a0990 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5836: 4c2ec0ad123b82f42f9fe2297e1a41fec73c9229 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18869: a589e37423a2a4cfae0dd2ce3de35e9e5655817b @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
a589e37423a2 drm/i915/dg1: map/unmap pll clocks
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/index.html
[-- Attachment #1.2: Type: text/html, Size: 7657 bytes --]
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dg1: map/unmap pll clocks
2020-11-06 21:00 [Intel-gfx] [PATCH] drm/i915/dg1: map/unmap pll clocks Lucas De Marchi
2020-11-06 21:15 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2020-11-06 21:45 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-11-06 22:56 ` Patchwork
2020-11-06 23:02 ` [Intel-gfx] [PATCH] " Aditya Swarup
3 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2020-11-06 22:56 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 16920 bytes --]
== Series Details ==
Series: drm/i915/dg1: map/unmap pll clocks
URL : https://patchwork.freedesktop.org/series/83592/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9284_full -> Patchwork_18869_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_18869_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18869_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_18869_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_mmap_gtt@cpuset-medium-copy-odd:
- shard-hsw: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9284/shard-hsw2/igt@gem_mmap_gtt@cpuset-medium-copy-odd.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/shard-hsw1/igt@gem_mmap_gtt@cpuset-medium-copy-odd.html
* igt@perf_pmu@most-busy-idle-check-all@bcs0:
- shard-hsw: [PASS][3] -> [FAIL][4] +2 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9284/shard-hsw7/igt@perf_pmu@most-busy-idle-check-all@bcs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/shard-hsw7/igt@perf_pmu@most-busy-idle-check-all@bcs0.html
New tests
---------
New tests have been introduced between CI_DRM_9284_full and Patchwork_18869_full:
### New CI tests (1) ###
* boot:
- Statuses : 199 pass(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_18869_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_softpin@noreloc-s3:
- shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#180])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9284/shard-kbl1/igt@gem_softpin@noreloc-s3.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/shard-kbl2/igt@gem_softpin@noreloc-s3.html
* igt@gem_userptr_blits@sync-unmap-cycles:
- shard-snb: [PASS][7] -> [INCOMPLETE][8] ([i915#2651])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9284/shard-snb6/igt@gem_userptr_blits@sync-unmap-cycles.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/shard-snb7/igt@gem_userptr_blits@sync-unmap-cycles.html
* igt@gen9_exec_parse@batch-without-end:
- shard-skl: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) +8 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9284/shard-skl9/igt@gen9_exec_parse@batch-without-end.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/shard-skl5/igt@gen9_exec_parse@batch-without-end.html
* igt@kms_cursor_crc@pipe-c-cursor-128x128-sliding:
- shard-skl: [PASS][11] -> [FAIL][12] ([i915#54])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9284/shard-skl7/igt@kms_cursor_crc@pipe-c-cursor-128x128-sliding.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/shard-skl10/igt@kms_cursor_crc@pipe-c-cursor-128x128-sliding.html
* igt@kms_cursor_legacy@short-flip-before-cursor-atomic-transitions:
- shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#1982])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9284/shard-kbl6/igt@kms_cursor_legacy@short-flip-before-cursor-atomic-transitions.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/shard-kbl3/igt@kms_cursor_legacy@short-flip-before-cursor-atomic-transitions.html
* igt@kms_flip@flip-vs-wf_vblank-interruptible@a-dp1:
- shard-apl: [PASS][15] -> [DMESG-WARN][16] ([i915#1635] / [i915#1982]) +6 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9284/shard-apl6/igt@kms_flip@flip-vs-wf_vblank-interruptible@a-dp1.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/shard-apl6/igt@kms_flip@flip-vs-wf_vblank-interruptible@a-dp1.html
* igt@kms_flip@flip-vs-wf_vblank-interruptible@a-hdmi-a1:
- shard-glk: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) +4 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9284/shard-glk4/igt@kms_flip@flip-vs-wf_vblank-interruptible@a-hdmi-a1.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/shard-glk3/igt@kms_flip@flip-vs-wf_vblank-interruptible@a-hdmi-a1.html
* igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1:
- shard-skl: [PASS][19] -> [FAIL][20] ([i915#2122])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9284/shard-skl10/igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/shard-skl3/igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
- shard-glk: [PASS][21] -> [FAIL][22] ([i915#49])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9284/shard-glk6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/shard-glk8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [PASS][23] -> [FAIL][24] ([i915#1188])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9284/shard-skl10/igt@kms_hdr@bpc-switch-dpms.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/shard-skl7/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-iclb: [PASS][25] -> [SKIP][26] ([fdo#109441])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9284/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/shard-iclb6/igt@kms_psr@psr2_sprite_mmap_gtt.html
#### Possible fixes ####
* igt@feature_discovery@psr2:
- shard-iclb: [SKIP][27] ([i915#658]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9284/shard-iclb8/igt@feature_discovery@psr2.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/shard-iclb2/igt@feature_discovery@psr2.html
* igt@gem_exec_params@batch-first:
- shard-hsw: [FAIL][29] -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9284/shard-hsw2/igt@gem_exec_params@batch-first.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/shard-hsw8/igt@gem_exec_params@batch-first.html
* igt@gem_exec_reloc@basic-many-active@rcs0:
- shard-glk: [FAIL][31] ([i915#2389]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9284/shard-glk7/igt@gem_exec_reloc@basic-many-active@rcs0.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/shard-glk3/igt@gem_exec_reloc@basic-many-active@rcs0.html
* igt@gem_mmap_gtt@medium-copy-xy:
- shard-skl: [DMESG-WARN][33] ([i915#1982]) -> [PASS][34] +1 similar issue
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9284/shard-skl9/igt@gem_mmap_gtt@medium-copy-xy.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/shard-skl5/igt@gem_mmap_gtt@medium-copy-xy.html
* {igt@kms_async_flips@async-flip-with-page-flip-events}:
- shard-apl: [FAIL][35] ([i915#1635] / [i915#2521]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9284/shard-apl4/igt@kms_async_flips@async-flip-with-page-flip-events.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/shard-apl4/igt@kms_async_flips@async-flip-with-page-flip-events.html
* igt@kms_cursor_crc@pipe-a-cursor-64x64-sliding:
- shard-skl: [FAIL][37] ([i915#54]) -> [PASS][38] +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9284/shard-skl6/igt@kms_cursor_crc@pipe-a-cursor-64x64-sliding.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/shard-skl4/igt@kms_cursor_crc@pipe-a-cursor-64x64-sliding.html
* igt@kms_cursor_edge_walk@pipe-c-256x256-right-edge:
- shard-apl: [DMESG-WARN][39] ([i915#1635] / [i915#1982]) -> [PASS][40] +3 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9284/shard-apl3/igt@kms_cursor_edge_walk@pipe-c-256x256-right-edge.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/shard-apl1/igt@kms_cursor_edge_walk@pipe-c-256x256-right-edge.html
* igt@kms_cursor_edge_walk@pipe-c-64x64-bottom-edge:
- shard-kbl: [DMESG-WARN][41] ([i915#1982]) -> [PASS][42] +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9284/shard-kbl1/igt@kms_cursor_edge_walk@pipe-c-64x64-bottom-edge.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/shard-kbl7/igt@kms_cursor_edge_walk@pipe-c-64x64-bottom-edge.html
* igt@kms_cursor_edge_walk@pipe-c-64x64-top-edge:
- shard-kbl: [FAIL][43] ([i915#70]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9284/shard-kbl1/igt@kms_cursor_edge_walk@pipe-c-64x64-top-edge.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/shard-kbl2/igt@kms_cursor_edge_walk@pipe-c-64x64-top-edge.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: [FAIL][45] ([i915#2346]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9284/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/shard-skl8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size:
- shard-tglb: [DMESG-WARN][47] ([i915#1982]) -> [PASS][48] +2 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9284/shard-tglb5/igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/shard-tglb7/igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html
* igt@kms_flip@2x-flip-vs-absolute-wf_vblank@ab-hdmi-a1-hdmi-a2:
- shard-glk: [DMESG-WARN][49] ([i915#1982]) -> [PASS][50] +4 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9284/shard-glk7/igt@kms_flip@2x-flip-vs-absolute-wf_vblank@ab-hdmi-a1-hdmi-a2.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/shard-glk4/igt@kms_flip@2x-flip-vs-absolute-wf_vblank@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-skl: [FAIL][51] ([i915#79]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9284/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/shard-skl10/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-tglb: [FAIL][53] ([i915#2598]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9284/shard-tglb8/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/shard-tglb1/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [DMESG-WARN][55] ([i915#180]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9284/shard-kbl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [FAIL][57] ([fdo#108145] / [i915#265]) -> [PASS][58] +1 similar issue
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9284/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_cursor_plane_move:
- shard-iclb: [SKIP][59] ([fdo#109441]) -> [PASS][60] +2 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9284/shard-iclb8/igt@kms_psr@psr2_cursor_plane_move.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html
* igt@perf@blocking:
- shard-skl: [FAIL][61] ([i915#1542]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9284/shard-skl7/igt@perf@blocking.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/shard-skl10/igt@perf@blocking.html
* igt@syncobj_basic@illegal-fd-to-handle:
- shard-snb: [INCOMPLETE][63] ([i915#2377] / [i915#82]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9284/shard-snb4/igt@syncobj_basic@illegal-fd-to-handle.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/shard-snb2/igt@syncobj_basic@illegal-fd-to-handle.html
#### Warnings ####
* igt@gem_exec_endless@dispatch:
- shard-hsw: [SKIP][65] ([fdo#109271]) -> [INCOMPLETE][66] ([i915#2377])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9284/shard-hsw6/igt@gem_exec_endless@dispatch.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/shard-hsw4/igt@gem_exec_endless@dispatch.html
* igt@i915_pm_dc@dc6-dpms:
- shard-skl: [FAIL][67] ([i915#454]) -> [INCOMPLETE][68] ([i915#198])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9284/shard-skl1/igt@i915_pm_dc@dc6-dpms.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/shard-skl10/igt@i915_pm_dc@dc6-dpms.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
- shard-apl: [FAIL][69] ([fdo#108145] / [i915#1635] / [i915#265]) -> [DMESG-FAIL][70] ([fdo#108145] / [i915#1635] / [i915#1982])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9284/shard-apl6/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/shard-apl6/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2377]: https://gitlab.freedesktop.org/drm/intel/issues/2377
[i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2598]: https://gitlab.freedesktop.org/drm/intel/issues/2598
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2651]: https://gitlab.freedesktop.org/drm/intel/issues/2651
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#70]: https://gitlab.freedesktop.org/drm/intel/issues/70
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_9284 -> Patchwork_18869
CI-20190529: 20190529
CI_DRM_9284: d0c4fd640b80d3dc107e269992a38c26f71a0990 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5836: 4c2ec0ad123b82f42f9fe2297e1a41fec73c9229 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18869: a589e37423a2a4cfae0dd2ce3de35e9e5655817b @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18869/index.html
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_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/dg1: map/unmap pll clocks
2020-11-06 21:00 [Intel-gfx] [PATCH] drm/i915/dg1: map/unmap pll clocks Lucas De Marchi
` (2 preceding siblings ...)
2020-11-06 22:56 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2020-11-06 23:02 ` Aditya Swarup
3 siblings, 0 replies; 5+ messages in thread
From: Aditya Swarup @ 2020-11-06 23:02 UTC (permalink / raw)
To: Lucas De Marchi, intel-gfx
On 11/6/20 1:00 PM, Lucas De Marchi wrote:
> DG1 uses 2 registers for the ddi clock mapping, with PHY A and B using
> DPCLKA_CFGCR0 and PHY C and D using DPCLKA1_CFGCR0. Hide this behind a
> single macro that chooses the correct register according to the phy
> being accessed, use the correct bitfields for each pll/phy and implement
> separate functions for DG1 since it doesn't share much with ICL/TGL
> anymore.
>
> The previous values were correct for PHY A and B since they were using
> the same register as before and the bitfields were matching.
>
> v2: Add comment and try to simplify DG1_DPCLKA* macros by reusing
> previous ones
> v3:
> - Fix DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK() after wrong macro reuse
> - Move phy -> id map to a separate macro (Aditya)
> - Remove DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK where not required
> (Aditya)
> - Use drm_WARN_ON
>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Aditya Swarup <aditya.swarup@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
LGTM!
Reviewed-by: Aditya Swarup <aditya.swarup@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 91 +++++++++++++++++++-
> drivers/gpu/drm/i915/display/intel_display.c | 24 +++++-
> drivers/gpu/drm/i915/i915_reg.h | 24 ++++++
> 3 files changed, 135 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 19b16517a502..36a4a1f4d775 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2970,6 +2970,40 @@ static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
> return 0;
> }
>
> +static void dg1_map_plls_to_ports(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> + enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> + u32 val;
> +
> + /*
> + * If we fail this, something went very wrong: first 2 PLLs should be
> + * used by first 2 phys and last 2 PLLs by last phys
> + */
> + if (drm_WARN_ON(&dev_priv->drm,
> + (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) ||
> + (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C)))
> + return;
> +
> + mutex_lock(&dev_priv->dpll.lock);
> +
> + val = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
> + drm_WARN_ON(&dev_priv->drm,
> + (val & DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)) == 0);
> +
> + val &= ~DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> + val |= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
> + intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val);
> + intel_de_posting_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
> +
> + val &= ~DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
> + intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val);
> +
> + mutex_unlock(&dev_priv->dpll.lock);
> +}
> +
> static void icl_map_plls_to_ports(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> @@ -3017,6 +3051,19 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
> mutex_unlock(&dev_priv->dpll.lock);
> }
>
> +static void dg1_unmap_plls_to_ports(struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> +
> + mutex_lock(&dev_priv->dpll.lock);
> +
> + intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy), 0,
> + DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
> +
> + mutex_unlock(&dev_priv->dpll.lock);
> +}
> +
> static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> @@ -3032,6 +3079,37 @@ static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
> mutex_unlock(&dev_priv->dpll.lock);
> }
>
> +static void dg1_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
> + u32 port_mask, bool ddi_clk_needed)
> +{
> + enum port port;
> + u32 val;
> +
> + for_each_port_masked(port, port_mask) {
> + enum phy phy = intel_port_to_phy(dev_priv, port);
> + bool ddi_clk_off;
> +
> + val = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
> + ddi_clk_off = val & DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
> +
> + if (ddi_clk_needed == !ddi_clk_off)
> + continue;
> +
> + /*
> + * Punt on the case now where clock is gated, but it would
> + * be needed by the port. Something else is really broken then.
> + */
> + if (drm_WARN_ON(&dev_priv->drm, ddi_clk_needed))
> + continue;
> +
> + drm_notice(&dev_priv->drm,
> + "PHY %c is disabled with an ungated DDI clock, gate it\n",
> + phy_name(phy));
> + val |= DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
> + intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val);
> + }
> +}
> +
> static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
> u32 port_mask, bool ddi_clk_needed)
> {
> @@ -3114,7 +3192,10 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
> ddi_clk_needed = false;
> }
>
> - icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed);
> + if (IS_DG1(dev_priv))
> + dg1_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed);
> + else
> + icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed);
> }
>
> static void intel_ddi_clk_select(struct intel_encoder *encoder,
> @@ -3666,7 +3747,9 @@ static void intel_ddi_pre_enable(struct intel_atomic_state *state,
>
> drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder);
>
> - if (INTEL_GEN(dev_priv) >= 11)
> + if (IS_DG1(dev_priv))
> + dg1_map_plls_to_ports(encoder, crtc_state);
> + else if (INTEL_GEN(dev_priv) >= 11)
> icl_map_plls_to_ports(encoder, crtc_state);
>
> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
> @@ -3848,7 +3931,9 @@ static void intel_ddi_post_disable(struct intel_atomic_state *state,
> intel_ddi_post_disable_dp(state, encoder, old_crtc_state,
> old_conn_state);
>
> - if (INTEL_GEN(dev_priv) >= 11)
> + if (IS_DG1(dev_priv))
> + dg1_unmap_plls_to_ports(encoder);
> + else if (INTEL_GEN(dev_priv) >= 11)
> icl_unmap_plls_to_ports(encoder);
>
> if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port)
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 6faca1e739c8..2729c852c668 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -11003,6 +11003,26 @@ static int hsw_crtc_compute_clock(struct intel_crtc *crtc,
> return 0;
> }
>
> +static void dg1_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
> + struct intel_crtc_state *pipe_config)
> +{
> + enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
> + enum phy phy = intel_port_to_phy(dev_priv, port);
> + enum intel_dpll_id id;
> + u32 clk_sel;
> +
> + clk_sel = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy)) & DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> + id = DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_DPLL_MAP(clk_sel, phy);
> +
> + if (WARN_ON(id > DPLL_ID_DG1_DPLL3))
> + return;
> +
> + pipe_config->icl_port_dplls[port_dpll_id].pll =
> + intel_get_shared_dpll_by_id(dev_priv, id);
> +
> + icl_set_active_port_dpll(pipe_config, port_dpll_id);
> +}
> +
> static void cnl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
> struct intel_crtc_state *pipe_config)
> {
> @@ -11311,7 +11331,9 @@ static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
> port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
> }
>
> - if (INTEL_GEN(dev_priv) >= 11)
> + if (IS_DG1(dev_priv))
> + dg1_get_ddi_pll(dev_priv, port, pipe_config);
> + else if (INTEL_GEN(dev_priv) >= 11)
> icl_get_ddi_pll(dev_priv, port, pipe_config);
> else if (IS_CANNONLAKE(dev_priv))
> cnl_get_ddi_pll(dev_priv, port, pipe_config);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index bb0656875697..39664ba553ec 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -230,12 +230,14 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b)
> #define _PORT(port, a, b) _PICK_EVEN(port, a, b)
> #define _PLL(pll, a, b) _PICK_EVEN(pll, a, b)
> +#define _PHY(phy, a, b) _PICK_EVEN(phy, a, b)
>
> #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
> #define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b))
> #define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))
> #define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
> #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
> +#define _MMIO_PHY(phy, a, b) _MMIO(_PHY(phy, a, b))
>
> #define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__)
>
> @@ -10300,6 +10302,7 @@ enum skl_power_gate {
> #define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
> #define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
>
> +/* ICL Clocks */
> #define ICL_DPCLKA_CFGCR0 _MMIO(0x164280)
> #define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24))
> #define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10)
> @@ -10315,6 +10318,27 @@ enum skl_power_gate {
> #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \
> ((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
>
> +/*
> + * DG1 Clocks
> + * First registers controls the first A and B, while the second register
> + * controls the phy C and D. The bits on these registers are the
> + * same, but refer to different phys
> + */
> +#define _DG1_DPCLKA_CFGCR0 0x164280
> +#define _DG1_DPCLKA1_CFGCR0 0x16C280
> +#define _DG1_DPCLKA_PHY_IDX(phy) ((phy) % 2)
> +#define _DG1_DPCLKA_PLL_IDX(pll) ((pll) % 2)
> +#define _DG1_PHY_DPLL_MAP(phy) ((phy) >= PHY_C ? DPLL_ID_DG1_DPLL2 : DPLL_ID_DG1_DPLL0)
> +#define DG1_DPCLKA_CFGCR0(phy) _MMIO_PHY((phy) / 2, \
> + _DG1_DPCLKA_CFGCR0, \
> + _DG1_DPCLKA1_CFGCR0)
> +#define DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT(_DG1_DPCLKA_PHY_IDX(phy) + 10)
> +#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) (_DG1_DPCLKA_PHY_IDX(phy) * 2)
> +#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) (_DG1_DPCLKA_PLL_IDX(pll) << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
> +#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (0x3 << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
> +#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_DPLL_MAP(clk_sel, phy) \
> + (((clk_sel) >> DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) + _DG1_PHY_DPLL_MAP(phy))
> +
> /* CNL PLL */
> #define DPLL0_ENABLE 0x46010
> #define DPLL1_ENABLE 0x46014
>
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^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2020-11-06 23:02 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-11-06 21:00 [Intel-gfx] [PATCH] drm/i915/dg1: map/unmap pll clocks Lucas De Marchi
2020-11-06 21:15 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2020-11-06 21:45 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-11-06 22:56 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-11-06 23:02 ` [Intel-gfx] [PATCH] " Aditya Swarup
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