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* [PATCH v2] clk: exynos7: Keep aclk_fsys1_200 enabled
@ 2020-11-07 12:14 ` Paweł Chmiel
  0 siblings, 0 replies; 10+ messages in thread
From: Paweł Chmiel @ 2020-11-07 12:14 UTC (permalink / raw)
  To: kgene, krzk, mturquette, sboyd
  Cc: s.nawrocki, tomasz.figa, cw00.choi, linux-samsung-soc, linux-clk,
	linux-arm-kernel, linux-kernel, Paweł Chmiel

This clock must be always enabled to allow access to any registers in
fsys1 CMU. Until proper solution based on runtime PM is applied
(similar to what was done for Exynos5433), fix this by calling
clk_prepare_enable() directly from clock provider driver.

It was observed on Samsung Galaxy S6 device (based on Exynos7420), where
UFS module is probed before pmic used to power that device.
In this case defer probe was happening and that clock was disabled by
UFS driver, causing whole boot to hang on next CMU access.

Signed-off-by: Paweł Chmiel <pawel.mikolaj.chmiel@gmail.com>
---
Changes from v1:
  - Instead of marking clock as critical, enable it manually in driver.
---
 drivers/clk/samsung/clk-exynos7.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
index c1ff715e960c..e05b673e277f 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -6,6 +6,7 @@
 
 #include <linux/clk-provider.h>
 #include <linux/of.h>
+#include <linux/clk.h>
 
 #include "clk.h"
 #include <dt-bindings/clock/exynos7-clk.h>
@@ -571,6 +572,10 @@ static const struct samsung_cmu_info top1_cmu_info __initconst = {
 static void __init exynos7_clk_top1_init(struct device_node *np)
 {
 	samsung_cmu_register_one(np, &top1_cmu_info);
+	/*
+	 * Keep top FSYS1 aclk enabled permanently. It's required for CMU register access.
+	 */
+	clk_prepare_enable(__clk_lookup("aclk_fsys1_200"));
 }
 
 CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",
-- 
2.27.0


^ permalink raw reply related	[flat|nested] 10+ messages in thread
* [PATCH v2] clk: exynos7: Keep aclk_fsys1_200 enabled
@ 2020-11-07 12:14 ` Paweł Chmiel
  0 siblings, 0 replies; 10+ messages in thread
From: Paweł Chmiel @ 2020-11-07 12:14 UTC (permalink / raw)
  To: kgene, krzk, mturquette, sboyd
  Cc: linux-samsung-soc, tomasz.figa, linux-kernel, cw00.choi,
	s.nawrocki, linux-clk, linux-arm-kernel, Paweł Chmiel

This clock must be always enabled to allow access to any registers in
fsys1 CMU. Until proper solution based on runtime PM is applied
(similar to what was done for Exynos5433), fix this by calling
clk_prepare_enable() directly from clock provider driver.

It was observed on Samsung Galaxy S6 device (based on Exynos7420), where
UFS module is probed before pmic used to power that device.
In this case defer probe was happening and that clock was disabled by
UFS driver, causing whole boot to hang on next CMU access.

Signed-off-by: Paweł Chmiel <pawel.mikolaj.chmiel@gmail.com>
---
Changes from v1:
  - Instead of marking clock as critical, enable it manually in driver.
---
 drivers/clk/samsung/clk-exynos7.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
index c1ff715e960c..e05b673e277f 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -6,6 +6,7 @@
 
 #include <linux/clk-provider.h>
 #include <linux/of.h>
+#include <linux/clk.h>
 
 #include "clk.h"
 #include <dt-bindings/clock/exynos7-clk.h>
@@ -571,6 +572,10 @@ static const struct samsung_cmu_info top1_cmu_info __initconst = {
 static void __init exynos7_clk_top1_init(struct device_node *np)
 {
 	samsung_cmu_register_one(np, &top1_cmu_info);
+	/*
+	 * Keep top FSYS1 aclk enabled permanently. It's required for CMU register access.
+	 */
+	clk_prepare_enable(__clk_lookup("aclk_fsys1_200"));
 }
 
 CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",
-- 
2.27.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 10+ messages in thread
* Re: [PATCH v2] clk: exynos7: Keep aclk_fsys1_200 enabled
  2020-11-07 12:14 ` Paweł Chmiel
@ 2020-11-08 18:41   ` Krzysztof Kozlowski
  -1 siblings, 0 replies; 10+ messages in thread
From: Krzysztof Kozlowski @ 2020-11-08 18:41 UTC (permalink / raw)
  To: Paweł Chmiel
  Cc: kgene, mturquette, sboyd, s.nawrocki, tomasz.figa, cw00.choi,
	linux-samsung-soc, linux-clk, linux-arm-kernel, linux-kernel

On Sat, Nov 07, 2020 at 01:14:56PM +0100, Paweł Chmiel wrote:
> This clock must be always enabled to allow access to any registers in
> fsys1 CMU. Until proper solution based on runtime PM is applied
> (similar to what was done for Exynos5433), fix this by calling
> clk_prepare_enable() directly from clock provider driver.
> 
> It was observed on Samsung Galaxy S6 device (based on Exynos7420), where
> UFS module is probed before pmic used to power that device.
> In this case defer probe was happening and that clock was disabled by
> UFS driver, causing whole boot to hang on next CMU access.
> 
> Signed-off-by: Paweł Chmiel <pawel.mikolaj.chmiel@gmail.com>
> ---
> Changes from v1:
>   - Instead of marking clock as critical, enable it manually in driver.
> ---
>  drivers/clk/samsung/clk-exynos7.c | 5 +++++
>  1 file changed, 5 insertions(+)

Acked-by: Krzysztof Kozlowski <krzk@kernel.org>

Best regards,
Krzysztof

^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [PATCH v2] clk: exynos7: Keep aclk_fsys1_200 enabled
@ 2020-11-08 18:41   ` Krzysztof Kozlowski
  0 siblings, 0 replies; 10+ messages in thread
From: Krzysztof Kozlowski @ 2020-11-08 18:41 UTC (permalink / raw)
  To: Paweł Chmiel
  Cc: linux-samsung-soc, sboyd, mturquette, tomasz.figa, linux-kernel,
	cw00.choi, kgene, s.nawrocki, linux-clk, linux-arm-kernel

On Sat, Nov 07, 2020 at 01:14:56PM +0100, Paweł Chmiel wrote:
> This clock must be always enabled to allow access to any registers in
> fsys1 CMU. Until proper solution based on runtime PM is applied
> (similar to what was done for Exynos5433), fix this by calling
> clk_prepare_enable() directly from clock provider driver.
> 
> It was observed on Samsung Galaxy S6 device (based on Exynos7420), where
> UFS module is probed before pmic used to power that device.
> In this case defer probe was happening and that clock was disabled by
> UFS driver, causing whole boot to hang on next CMU access.
> 
> Signed-off-by: Paweł Chmiel <pawel.mikolaj.chmiel@gmail.com>
> ---
> Changes from v1:
>   - Instead of marking clock as critical, enable it manually in driver.
> ---
>  drivers/clk/samsung/clk-exynos7.c | 5 +++++
>  1 file changed, 5 insertions(+)

Acked-by: Krzysztof Kozlowski <krzk@kernel.org>

Best regards,
Krzysztof

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [PATCH v2] clk: exynos7: Keep aclk_fsys1_200 enabled
  2020-11-07 12:14 ` Paweł Chmiel
@ 2020-11-09 12:32   ` Sylwester Nawrocki
  -1 siblings, 0 replies; 10+ messages in thread
From: Sylwester Nawrocki @ 2020-11-09 12:32 UTC (permalink / raw)
  To: Paweł Chmiel
  Cc: kgene, krzk, mturquette, sboyd, s.nawrocki, tomasz.figa,
	cw00.choi, linux-samsung-soc, linux-clk, linux-arm-kernel,
	linux-kernel

Hi Paweł,

On 11/7/20 13:14, Paweł Chmiel wrote:
> This clock must be always enabled to allow access to any registers in
> fsys1 CMU. Until proper solution based on runtime PM is applied
> (similar to what was done for Exynos5433), fix this by calling
> clk_prepare_enable() directly from clock provider driver.
> 
> It was observed on Samsung Galaxy S6 device (based on Exynos7420), where
> UFS module is probed before pmic used to power that device.
> In this case defer probe was happening and that clock was disabled by
> UFS driver, causing whole boot to hang on next CMU access.
> 
> Signed-off-by: Paweł Chmiel <pawel.mikolaj.chmiel@gmail.com>

> --- a/drivers/clk/samsung/clk-exynos7.c
> +++ b/drivers/clk/samsung/clk-exynos7.c

> @@ -571,6 +572,10 @@ static const struct samsung_cmu_info top1_cmu_info __initconst = {
>   static void __init exynos7_clk_top1_init(struct device_node *np)
>   {
>   	samsung_cmu_register_one(np, &top1_cmu_info);
> +	/*
> +	 * Keep top FSYS1 aclk enabled permanently. It's required for CMU register access.
> +	 */
> +	clk_prepare_enable(__clk_lookup("aclk_fsys1_200"));

Thanks for the patch. Could you rework it to avoid the __clk_lookup() call?
I.e. could you change it to something along the lines of:

-------------8<----------------
diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
index 87ee1ba..9ecf498 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -570,7 +570,15 @@ static const struct samsung_cmu_info top1_cmu_info __initconst = {
 
 static void __init exynos7_clk_top1_init(struct device_node *np)
 {
-       samsung_cmu_register_one(np, &top1_cmu_info);
+       struct samsung_clk_provider *ctx;
+       struct clk_hw **hws;
+
+       ctx = samsung_cmu_register_one(np, &top1_cmu_info);
+       if (!ctx)
+               return;
+       hws = ctx->clk_data.hws;
+
+       clk_prepare_enable(hws[CLK_ACLK_FSYS1_200]);
 }
 
 CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",
-------------8<----------------
?

--
Regards,
Sylwester



^ permalink raw reply related	[flat|nested] 10+ messages in thread
* Re: [PATCH v2] clk: exynos7: Keep aclk_fsys1_200 enabled
@ 2020-11-09 12:32   ` Sylwester Nawrocki
  0 siblings, 0 replies; 10+ messages in thread
From: Sylwester Nawrocki @ 2020-11-09 12:32 UTC (permalink / raw)
  To: Paweł Chmiel
  Cc: linux-samsung-soc, sboyd, mturquette, tomasz.figa, krzk,
	linux-kernel, cw00.choi, kgene, s.nawrocki, linux-clk,
	linux-arm-kernel

Hi Paweł,

On 11/7/20 13:14, Paweł Chmiel wrote:
> This clock must be always enabled to allow access to any registers in
> fsys1 CMU. Until proper solution based on runtime PM is applied
> (similar to what was done for Exynos5433), fix this by calling
> clk_prepare_enable() directly from clock provider driver.
> 
> It was observed on Samsung Galaxy S6 device (based on Exynos7420), where
> UFS module is probed before pmic used to power that device.
> In this case defer probe was happening and that clock was disabled by
> UFS driver, causing whole boot to hang on next CMU access.
> 
> Signed-off-by: Paweł Chmiel <pawel.mikolaj.chmiel@gmail.com>

> --- a/drivers/clk/samsung/clk-exynos7.c
> +++ b/drivers/clk/samsung/clk-exynos7.c

> @@ -571,6 +572,10 @@ static const struct samsung_cmu_info top1_cmu_info __initconst = {
>   static void __init exynos7_clk_top1_init(struct device_node *np)
>   {
>   	samsung_cmu_register_one(np, &top1_cmu_info);
> +	/*
> +	 * Keep top FSYS1 aclk enabled permanently. It's required for CMU register access.
> +	 */
> +	clk_prepare_enable(__clk_lookup("aclk_fsys1_200"));

Thanks for the patch. Could you rework it to avoid the __clk_lookup() call?
I.e. could you change it to something along the lines of:

-------------8<----------------
diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
index 87ee1ba..9ecf498 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -570,7 +570,15 @@ static const struct samsung_cmu_info top1_cmu_info __initconst = {
 
 static void __init exynos7_clk_top1_init(struct device_node *np)
 {
-       samsung_cmu_register_one(np, &top1_cmu_info);
+       struct samsung_clk_provider *ctx;
+       struct clk_hw **hws;
+
+       ctx = samsung_cmu_register_one(np, &top1_cmu_info);
+       if (!ctx)
+               return;
+       hws = ctx->clk_data.hws;
+
+       clk_prepare_enable(hws[CLK_ACLK_FSYS1_200]);
 }
 
 CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",
-------------8<----------------
?

--
Regards,
Sylwester



_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 10+ messages in thread
* Re: [PATCH v2] clk: exynos7: Keep aclk_fsys1_200 enabled
  2020-11-09 12:32   ` Sylwester Nawrocki
@ 2020-11-09 12:43     ` Sylwester Nawrocki
  -1 siblings, 0 replies; 10+ messages in thread
From: Sylwester Nawrocki @ 2020-11-09 12:43 UTC (permalink / raw)
  To: Paweł Chmiel
  Cc: kgene, krzk, mturquette, sboyd, s.nawrocki, tomasz.figa,
	cw00.choi, linux-samsung-soc, linux-clk, linux-arm-kernel,
	linux-kernel

On 11/9/20 13:32, Sylwester Nawrocki wrote:
> -------------8<----------------
> diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
> index 87ee1ba..9ecf498 100644
> --- a/drivers/clk/samsung/clk-exynos7.c
> +++ b/drivers/clk/samsung/clk-exynos7.c
> @@ -570,7 +570,15 @@ static const struct samsung_cmu_info top1_cmu_info __initconst = {
>   
>   static void __init exynos7_clk_top1_init(struct device_node *np)
>   {
> -       samsung_cmu_register_one(np, &top1_cmu_info);
> +       struct samsung_clk_provider *ctx;
> +       struct clk_hw **hws;
> +
> +       ctx = samsung_cmu_register_one(np, &top1_cmu_info);
> +       if (!ctx)
> +               return;
> +       hws = ctx->clk_data.hws;
> +
> +       clk_prepare_enable(hws[CLK_ACLK_FSYS1_200]);

Of course it was supposed to be:

  clk_prepare_enable(hws[CLK_ACLK_FSYS1_200]->clk);

>   }
>   
>   CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",
> -------------8<----------------

^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [PATCH v2] clk: exynos7: Keep aclk_fsys1_200 enabled
@ 2020-11-09 12:43     ` Sylwester Nawrocki
  0 siblings, 0 replies; 10+ messages in thread
From: Sylwester Nawrocki @ 2020-11-09 12:43 UTC (permalink / raw)
  To: Paweł Chmiel
  Cc: linux-samsung-soc, sboyd, mturquette, tomasz.figa, krzk,
	linux-kernel, cw00.choi, kgene, s.nawrocki, linux-clk,
	linux-arm-kernel

On 11/9/20 13:32, Sylwester Nawrocki wrote:
> -------------8<----------------
> diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
> index 87ee1ba..9ecf498 100644
> --- a/drivers/clk/samsung/clk-exynos7.c
> +++ b/drivers/clk/samsung/clk-exynos7.c
> @@ -570,7 +570,15 @@ static const struct samsung_cmu_info top1_cmu_info __initconst = {
>   
>   static void __init exynos7_clk_top1_init(struct device_node *np)
>   {
> -       samsung_cmu_register_one(np, &top1_cmu_info);
> +       struct samsung_clk_provider *ctx;
> +       struct clk_hw **hws;
> +
> +       ctx = samsung_cmu_register_one(np, &top1_cmu_info);
> +       if (!ctx)
> +               return;
> +       hws = ctx->clk_data.hws;
> +
> +       clk_prepare_enable(hws[CLK_ACLK_FSYS1_200]);

Of course it was supposed to be:

  clk_prepare_enable(hws[CLK_ACLK_FSYS1_200]->clk);

>   }
>   
>   CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",
> -------------8<----------------

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [PATCH v2] clk: exynos7: Keep aclk_fsys1_200 enabled
  2020-11-09 12:32   ` Sylwester Nawrocki
@ 2020-11-09 16:35     ` Paweł Chmiel
  -1 siblings, 0 replies; 10+ messages in thread
From: Paweł Chmiel @ 2020-11-09 16:35 UTC (permalink / raw)
  To: Sylwester Nawrocki
  Cc: kgene, krzk, mturquette, sboyd, s.nawrocki, tomasz.figa,
	cw00.choi, linux-samsung-soc, linux-clk, linux-arm-kernel,
	linux-kernel



On 09.11.2020 13:32, Sylwester Nawrocki wrote:
> Hi Paweł,
> 
> On 11/7/20 13:14, Paweł Chmiel wrote:
>> This clock must be always enabled to allow access to any registers in
>> fsys1 CMU. Until proper solution based on runtime PM is applied
>> (similar to what was done for Exynos5433), fix this by calling
>> clk_prepare_enable() directly from clock provider driver.
>>
>> It was observed on Samsung Galaxy S6 device (based on Exynos7420), where
>> UFS module is probed before pmic used to power that device.
>> In this case defer probe was happening and that clock was disabled by
>> UFS driver, causing whole boot to hang on next CMU access.
>>
>> Signed-off-by: Paweł Chmiel <pawel.mikolaj.chmiel@gmail.com>
> 
>> --- a/drivers/clk/samsung/clk-exynos7.c
>> +++ b/drivers/clk/samsung/clk-exynos7.c
> 
>> @@ -571,6 +572,10 @@ static const struct samsung_cmu_info top1_cmu_info __initconst = {
>>   static void __init exynos7_clk_top1_init(struct device_node *np)
>>   {
>>   	samsung_cmu_register_one(np, &top1_cmu_info);
>> +	/*
>> +	 * Keep top FSYS1 aclk enabled permanently. It's required for CMU register access.
>> +	 */
>> +	clk_prepare_enable(__clk_lookup("aclk_fsys1_200"));
> 
> Thanks for the patch. Could you rework it to avoid the __clk_lookup() call?
> I.e. could you change it to something along the lines of:
Hi.
I'll send v3 version with this fixed.

Thanks for review and comments
> 
> -------------8<----------------
> diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
> index 87ee1ba..9ecf498 100644
> --- a/drivers/clk/samsung/clk-exynos7.c
> +++ b/drivers/clk/samsung/clk-exynos7.c
> @@ -570,7 +570,15 @@ static const struct samsung_cmu_info top1_cmu_info __initconst = {
>  
>  static void __init exynos7_clk_top1_init(struct device_node *np)
>  {
> -       samsung_cmu_register_one(np, &top1_cmu_info);
> +       struct samsung_clk_provider *ctx;
> +       struct clk_hw **hws;
> +
> +       ctx = samsung_cmu_register_one(np, &top1_cmu_info);
> +       if (!ctx)
> +               return;
> +       hws = ctx->clk_data.hws;
> +
> +       clk_prepare_enable(hws[CLK_ACLK_FSYS1_200]);
>  }
>  
>  CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",
> -------------8<----------------
> ?
> 
> --
> Regards,
> Sylwester
> 
> 

^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [PATCH v2] clk: exynos7: Keep aclk_fsys1_200 enabled
@ 2020-11-09 16:35     ` Paweł Chmiel
  0 siblings, 0 replies; 10+ messages in thread
From: Paweł Chmiel @ 2020-11-09 16:35 UTC (permalink / raw)
  To: Sylwester Nawrocki
  Cc: linux-samsung-soc, sboyd, mturquette, tomasz.figa, krzk,
	linux-kernel, cw00.choi, kgene, s.nawrocki, linux-clk,
	linux-arm-kernel



On 09.11.2020 13:32, Sylwester Nawrocki wrote:
> Hi Paweł,
> 
> On 11/7/20 13:14, Paweł Chmiel wrote:
>> This clock must be always enabled to allow access to any registers in
>> fsys1 CMU. Until proper solution based on runtime PM is applied
>> (similar to what was done for Exynos5433), fix this by calling
>> clk_prepare_enable() directly from clock provider driver.
>>
>> It was observed on Samsung Galaxy S6 device (based on Exynos7420), where
>> UFS module is probed before pmic used to power that device.
>> In this case defer probe was happening and that clock was disabled by
>> UFS driver, causing whole boot to hang on next CMU access.
>>
>> Signed-off-by: Paweł Chmiel <pawel.mikolaj.chmiel@gmail.com>
> 
>> --- a/drivers/clk/samsung/clk-exynos7.c
>> +++ b/drivers/clk/samsung/clk-exynos7.c
> 
>> @@ -571,6 +572,10 @@ static const struct samsung_cmu_info top1_cmu_info __initconst = {
>>   static void __init exynos7_clk_top1_init(struct device_node *np)
>>   {
>>   	samsung_cmu_register_one(np, &top1_cmu_info);
>> +	/*
>> +	 * Keep top FSYS1 aclk enabled permanently. It's required for CMU register access.
>> +	 */
>> +	clk_prepare_enable(__clk_lookup("aclk_fsys1_200"));
> 
> Thanks for the patch. Could you rework it to avoid the __clk_lookup() call?
> I.e. could you change it to something along the lines of:
Hi.
I'll send v3 version with this fixed.

Thanks for review and comments
> 
> -------------8<----------------
> diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
> index 87ee1ba..9ecf498 100644
> --- a/drivers/clk/samsung/clk-exynos7.c
> +++ b/drivers/clk/samsung/clk-exynos7.c
> @@ -570,7 +570,15 @@ static const struct samsung_cmu_info top1_cmu_info __initconst = {
>  
>  static void __init exynos7_clk_top1_init(struct device_node *np)
>  {
> -       samsung_cmu_register_one(np, &top1_cmu_info);
> +       struct samsung_clk_provider *ctx;
> +       struct clk_hw **hws;
> +
> +       ctx = samsung_cmu_register_one(np, &top1_cmu_info);
> +       if (!ctx)
> +               return;
> +       hws = ctx->clk_data.hws;
> +
> +       clk_prepare_enable(hws[CLK_ACLK_FSYS1_200]);
>  }
>  
>  CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",
> -------------8<----------------
> ?
> 
> --
> Regards,
> Sylwester
> 
> 

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^ permalink raw reply	[flat|nested] 10+ messages in thread
end of thread, other threads:[~2020-11-09 16:36 UTC | newest]

Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-11-07 12:14 [PATCH v2] clk: exynos7: Keep aclk_fsys1_200 enabled Paweł Chmiel
2020-11-07 12:14 ` Paweł Chmiel
2020-11-08 18:41 ` Krzysztof Kozlowski
2020-11-08 18:41   ` Krzysztof Kozlowski
2020-11-09 12:32 ` Sylwester Nawrocki
2020-11-09 12:32   ` Sylwester Nawrocki
2020-11-09 12:43   ` Sylwester Nawrocki
2020-11-09 12:43     ` Sylwester Nawrocki
2020-11-09 16:35   ` Paweł Chmiel
2020-11-09 16:35     ` Paweł Chmiel

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