[Intel-gfx] [PATCH 1/4] drm/i915: Introduce intel_dpll_get_hw_state()

[Intel-gfx] [PATCH 1/4] drm/i915: Introduce intel_dpll_get_hw_state()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add a wrapper for the pll .get_hw_state() vfunc. Makes life
a bit less miserable when you don't have to worry where the
function pointer is stored.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  | 14 +++++++------
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 20 ++++++++++++++++---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h |  3 +++
 3 files changed, 28 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 2729c852c668..a7c4cd7a8a31 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10927,6 +10927,7 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc,
 	if (intel_de_read(dev_priv, PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
 		struct intel_shared_dpll *pll;
 		enum intel_dpll_id pll_id;
+		bool pll_active;
 
 		pipe_config->has_pch_encoder = true;
 
@@ -10954,8 +10955,9 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc,
 			intel_get_shared_dpll_by_id(dev_priv, pll_id);
 		pll = pipe_config->shared_dpll;
 
-		drm_WARN_ON(dev, !pll->info->funcs->get_hw_state(dev_priv, pll,
-						 &pipe_config->dpll_hw_state));
+		pll_active = intel_dpll_get_hw_state(dev_priv, pll,
+						     &pipe_config->dpll_hw_state);
+		drm_WARN_ON(dev, !pll_active);
 
 		tmp = pipe_config->dpll_hw_state.dpll;
 		pipe_config->pixel_multiplier =
@@ -11346,9 +11348,9 @@ static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
 
 	pll = pipe_config->shared_dpll;
 	if (pll) {
-		drm_WARN_ON(&dev_priv->drm,
-			    !pll->info->funcs->get_hw_state(dev_priv, pll,
-						&pipe_config->dpll_hw_state));
+		bool pll_active = intel_dpll_get_hw_state(dev_priv, pll,
+							  &pipe_config->dpll_hw_state);
+		drm_WARN_ON(&dev_priv->drm, !pll_active);
 	}
 
 	/*
@@ -14587,7 +14589,7 @@ verify_single_dpll_state(struct drm_i915_private *dev_priv,
 
 	drm_dbg_kms(&dev_priv->drm, "%s\n", pll->info->name);
 
-	active = pll->info->funcs->get_hw_state(dev_priv, pll, &dpll_hw_state);
+	active = intel_dpll_get_hw_state(dev_priv, pll, &dpll_hw_state);
 
 	if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
 		I915_STATE_WARN(!pll->on && pll->active_mask,
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index a95e6a2ac698..1604c20bac33 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -141,7 +141,7 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
 		     "asserting DPLL %s with no DPLL\n", onoff(state)))
 		return;
 
-	cur_state = pll->info->funcs->get_hw_state(dev_priv, pll, &hw_state);
+	cur_state = intel_dpll_get_hw_state(dev_priv, pll, &hw_state);
 	I915_STATE_WARN(cur_state != state,
 	     "%s assertion failure (expected %s, current %s)\n",
 			pll->info->name, onoff(state), onoff(cur_state));
@@ -4527,13 +4527,27 @@ int intel_dpll_get_freq(struct drm_i915_private *i915,
 	return pll->info->funcs->get_freq(i915, pll);
 }
 
+/**
+ * intel_dpll_get_hw_state - readout the DPLL's hardware state
+ * @i915: i915 device
+ * @pll: DPLL for which to calculate the output frequency
+ * @hw_state: DPLL's hardware state
+ *
+ * Read out @pll's hardware state into @hw_state.
+ */
+bool intel_dpll_get_hw_state(struct drm_i915_private *i915,
+			     struct intel_shared_dpll *pll,
+			     struct intel_dpll_hw_state *hw_state)
+{
+	return pll->info->funcs->get_hw_state(i915, pll, hw_state);
+}
+
 static void readout_dpll_hw_state(struct drm_i915_private *i915,
 				  struct intel_shared_dpll *pll)
 {
 	struct intel_crtc *crtc;
 
-	pll->on = pll->info->funcs->get_hw_state(i915, pll,
-						 &pll->state.hw_state);
+	pll->on = intel_dpll_get_hw_state(i915, pll, &pll->state.hw_state);
 
 	if (IS_JSL_EHL(i915) && pll->on &&
 	    pll->info->id == DPLL_ID_EHL_DPLL4) {
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 205542fb8dc7..4357f92eafd6 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -400,6 +400,9 @@ void intel_update_active_dpll(struct intel_atomic_state *state,
 			      struct intel_encoder *encoder);
 int intel_dpll_get_freq(struct drm_i915_private *i915,
 			const struct intel_shared_dpll *pll);
+bool intel_dpll_get_hw_state(struct drm_i915_private *i915,
+			     struct intel_shared_dpll *pll,
+			     struct intel_dpll_hw_state *hw_state);
 void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state);
 void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
 void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
-- 
2.26.2

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[Intel-gfx] [PATCH 2/4] drm/i915: Move intel_dpll_get_hw_state() into the hsw+ platform specific functions

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

On icl+ we want to populate both crtc_state.{shared_dpll,dpll_hw_state}
and crtc_state.port_dplls[] during readout, whereas on pre-icl we
want to leave the latter stuff untouched. Rather than adding more ifs
into hsw_get_ddi_port_state() to copy the DPLL hw state around let's
just move the whole dpll readout into hsw_get_ddi_dpll() & co.
Slightly repetitive, but meh.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 68 +++++++++++++++-----
 1 file changed, 52 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a7c4cd7a8a31..8ab622c0186e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11010,7 +11010,10 @@ static void dg1_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
 {
 	enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
 	enum phy phy = intel_port_to_phy(dev_priv, port);
+	struct icl_port_dpll *port_dpll;
+	struct intel_shared_dpll *pll;
 	enum intel_dpll_id id;
+	bool pll_active;
 	u32 clk_sel;
 
 	clk_sel = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy)) & DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
@@ -11019,8 +11022,13 @@ static void dg1_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
 	if (WARN_ON(id > DPLL_ID_DG1_DPLL3))
 		return;
 
-	pipe_config->icl_port_dplls[port_dpll_id].pll =
-		intel_get_shared_dpll_by_id(dev_priv, id);
+	pll = intel_get_shared_dpll_by_id(dev_priv, id);
+	port_dpll = &pipe_config->icl_port_dplls[port_dpll_id];
+
+	port_dpll->pll = pll;
+	pll_active = intel_dpll_get_hw_state(dev_priv, pll,
+					     &port_dpll->hw_state);
+	drm_WARN_ON(&dev_priv->drm, !pll_active);
 
 	icl_set_active_port_dpll(pipe_config, port_dpll_id);
 }
@@ -11028,7 +11036,9 @@ static void dg1_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
 static void cnl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
 			    struct intel_crtc_state *pipe_config)
 {
+	struct intel_shared_dpll *pll;
 	enum intel_dpll_id id;
+	bool pll_active;
 	u32 temp;
 
 	temp = intel_de_read(dev_priv, DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
@@ -11037,7 +11047,12 @@ static void cnl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
 	if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL2))
 		return;
 
-	pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
+	pll = intel_get_shared_dpll_by_id(dev_priv, id);
+
+	pipe_config->shared_dpll = pll;
+	pll_active = intel_dpll_get_hw_state(dev_priv, pll,
+					     &pipe_config->dpll_hw_state);
+	drm_WARN_ON(&dev_priv->drm, !pll_active);
 }
 
 static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
@@ -11045,7 +11060,10 @@ static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
 {
 	enum phy phy = intel_port_to_phy(dev_priv, port);
 	enum icl_port_dpll_id port_dpll_id;
+	struct icl_port_dpll *port_dpll;
+	struct intel_shared_dpll *pll;
 	enum intel_dpll_id id;
+	bool pll_active;
 	u32 temp;
 
 	if (intel_phy_is_combo(dev_priv, phy)) {
@@ -11080,8 +11098,13 @@ static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
 		return;
 	}
 
-	pipe_config->icl_port_dplls[port_dpll_id].pll =
-		intel_get_shared_dpll_by_id(dev_priv, id);
+	pll = intel_get_shared_dpll_by_id(dev_priv, id);
+	port_dpll = &pipe_config->icl_port_dplls[port_dpll_id];
+
+	port_dpll->pll = pll;
+	pll_active = intel_dpll_get_hw_state(dev_priv, pll,
+					     &port_dpll->hw_state);
+	drm_WARN_ON(&dev_priv->drm, !pll_active);
 
 	icl_set_active_port_dpll(pipe_config, port_dpll_id);
 }
@@ -11090,7 +11113,9 @@ static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
 				enum port port,
 				struct intel_crtc_state *pipe_config)
 {
+	struct intel_shared_dpll *pll;
 	enum intel_dpll_id id;
+	bool pll_active;
 
 	switch (port) {
 	case PORT_A:
@@ -11107,13 +11132,20 @@ static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
 		return;
 	}
 
-	pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
+	pll = intel_get_shared_dpll_by_id(dev_priv, id);
+
+	pipe_config->shared_dpll = pll;
+	pll_active = intel_dpll_get_hw_state(dev_priv, pll,
+					     &pipe_config->dpll_hw_state);
+	drm_WARN_ON(&dev_priv->drm, !pll_active);
 }
 
 static void skl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
 			    struct intel_crtc_state *pipe_config)
 {
+	struct intel_shared_dpll *pll;
 	enum intel_dpll_id id;
+	bool pll_active;
 	u32 temp;
 
 	temp = intel_de_read(dev_priv, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
@@ -11122,14 +11154,21 @@ static void skl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
 	if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL3))
 		return;
 
-	pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
+	pll = intel_get_shared_dpll_by_id(dev_priv, id);
+
+	pipe_config->shared_dpll = pll;
+	pll_active = intel_dpll_get_hw_state(dev_priv, pll,
+					     &pipe_config->dpll_hw_state);
+	drm_WARN_ON(&dev_priv->drm, !pll_active);
 }
 
 static void hsw_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
 			    struct intel_crtc_state *pipe_config)
 {
+	struct intel_shared_dpll *pll;
 	enum intel_dpll_id id;
 	u32 ddi_pll_sel = intel_de_read(dev_priv, PORT_CLK_SEL(port));
+	bool pll_active;
 
 	switch (ddi_pll_sel) {
 	case PORT_CLK_SEL_WRPLL1:
@@ -11157,7 +11196,12 @@ static void hsw_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
 		return;
 	}
 
-	pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
+	pll = intel_get_shared_dpll_by_id(dev_priv, id);
+
+	pipe_config->shared_dpll = pll;
+	pll_active = intel_dpll_get_hw_state(dev_priv, pll,
+					     &pipe_config->dpll_hw_state);
+	drm_WARN_ON(&dev_priv->drm, !pll_active);
 }
 
 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
@@ -11317,7 +11361,6 @@ static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
-	struct intel_shared_dpll *pll;
 	enum port port;
 	u32 tmp;
 
@@ -11346,13 +11389,6 @@ static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
 	else
 		hsw_get_ddi_pll(dev_priv, port, pipe_config);
 
-	pll = pipe_config->shared_dpll;
-	if (pll) {
-		bool pll_active = intel_dpll_get_hw_state(dev_priv, pll,
-							  &pipe_config->dpll_hw_state);
-		drm_WARN_ON(&dev_priv->drm, !pll_active);
-	}
-
 	/*
 	 * Haswell has only FDI/PCH transcoder A. It is which is connected to
 	 * DDI E. So just check whether this pipe is wired to DDI E and whether
-- 
2.26.2

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[Intel-gfx] [PATCH 3/4] drm/i915: Use actual readout results for .get_freq()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Currently the DPLL .get_freq() uses pll->state.hw_state which
is not the thing we actually read out (except during driver
load/resume). Outside of that pll->state.hw_state is just the
thing we committed last time around. During state check we
just read the thing into crtc_state->dpll_hw_state, so that
is what we should use for calculating the DPLL output frequency.

I think we used to do this so that the results of the readout
were actually used, but somehow it got changed when the
.get_freq() refactoring happened.

Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c        |  3 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      |  3 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 78 +++++++++++--------
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h |  8 +-
 4 files changed, 54 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 096652921453..769bb1b0d543 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1496,7 +1496,8 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
 
 	/* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
 	pipe_config->port_clock = intel_dpll_get_freq(i915,
-						      pipe_config->shared_dpll);
+						      pipe_config->shared_dpll,
+						      &pipe_config->dpll_hw_state);
 
 	pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk;
 	if (intel_dsi->dual_link)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index d4b1b73c7aab..9d80e47e9558 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1755,7 +1755,8 @@ static void intel_ddi_clock_get(struct intel_encoder *encoder,
 								encoder->port);
 	else
 		pipe_config->port_clock =
-			intel_dpll_get_freq(dev_priv, pipe_config->shared_dpll);
+			intel_dpll_get_freq(dev_priv, pipe_config->shared_dpll,
+					    &pipe_config->dpll_hw_state);
 
 	ddi_dotclock_get(pipe_config);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 1604c20bac33..0f14c4dee02c 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -891,11 +891,12 @@ hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state,
 }
 
 static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
-				  const struct intel_shared_dpll *pll)
+				  const struct intel_shared_dpll *pll,
+				  const struct intel_dpll_hw_state *pll_state)
 {
 	int refclk;
 	int n, p, r;
-	u32 wrpll = pll->state.hw_state.wrpll;
+	u32 wrpll = pll_state->wrpll;
 
 	switch (wrpll & WRPLL_REF_MASK) {
 	case WRPLL_REF_SPECIAL_HSW:
@@ -962,7 +963,8 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
 }
 
 static int hsw_ddi_lcpll_get_freq(struct drm_i915_private *i915,
-				  const struct intel_shared_dpll *pll)
+				  const struct intel_shared_dpll *pll,
+				  const struct intel_dpll_hw_state *pll_state)
 {
 	int link_clock = 0;
 
@@ -1002,11 +1004,12 @@ hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
 }
 
 static int hsw_ddi_spll_get_freq(struct drm_i915_private *i915,
-				 const struct intel_shared_dpll *pll)
+				 const struct intel_shared_dpll *pll,
+				 const struct intel_dpll_hw_state *pll_state)
 {
 	int link_clock = 0;
 
-	switch (pll->state.hw_state.spll & SPLL_FREQ_MASK) {
+	switch (pll_state->spll & SPLL_FREQ_MASK) {
 	case SPLL_FREQ_810MHz:
 		link_clock = 81000;
 		break;
@@ -1577,9 +1580,9 @@ static bool skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
 }
 
 static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
-				  const struct intel_shared_dpll *pll)
+				  const struct intel_shared_dpll *pll,
+				  const struct intel_dpll_hw_state *pll_state)
 {
-	const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state;
 	int ref_clock = i915->dpll.ref_clks.nssc;
 	u32 p0, p1, p2, dco_freq;
 
@@ -1688,12 +1691,12 @@ skl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
 }
 
 static int skl_ddi_lcpll_get_freq(struct drm_i915_private *i915,
-				  const struct intel_shared_dpll *pll)
+				  const struct intel_shared_dpll *pll,
+				  const struct intel_dpll_hw_state *pll_state)
 {
 	int link_clock = 0;
 
-	switch ((pll->state.hw_state.ctrl1 &
-		 DPLL_CTRL1_LINK_RATE_MASK(0)) >>
+	switch ((pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0)) >>
 		DPLL_CTRL1_LINK_RATE_SHIFT(0)) {
 	case DPLL_CTRL1_LINK_RATE_810:
 		link_clock = 81000;
@@ -1771,16 +1774,17 @@ static bool skl_get_dpll(struct intel_atomic_state *state,
 }
 
 static int skl_ddi_pll_get_freq(struct drm_i915_private *i915,
-				const struct intel_shared_dpll *pll)
+				const struct intel_shared_dpll *pll,
+				const struct intel_dpll_hw_state *pll_state)
 {
 	/*
 	 * ctrl1 register is already shifted for each pll, just use 0 to get
 	 * the internal shift for each field
 	 */
-	if (pll->state.hw_state.ctrl1 & DPLL_CTRL1_HDMI_MODE(0))
-		return skl_ddi_wrpll_get_freq(i915, pll);
+	if (pll_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0))
+		return skl_ddi_wrpll_get_freq(i915, pll, pll_state);
 	else
-		return skl_ddi_lcpll_get_freq(i915, pll);
+		return skl_ddi_lcpll_get_freq(i915, pll, pll_state);
 }
 
 static void skl_update_dpll_ref_clks(struct drm_i915_private *i915)
@@ -2218,9 +2222,9 @@ bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
 }
 
 static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915,
-				const struct intel_shared_dpll *pll)
+				const struct intel_shared_dpll *pll,
+				const struct intel_dpll_hw_state *pll_state)
 {
-	const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state;
 	struct dpll clock;
 
 	clock.m1 = 2;
@@ -2650,9 +2654,9 @@ ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
 
 static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
 				    const struct intel_shared_dpll *pll,
+				    const struct intel_dpll_hw_state *pll_state,
 				    int ref_clock)
 {
-	const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state;
 	u32 dco_fraction;
 	u32 p0, p1, p2, dco_freq;
 
@@ -2711,9 +2715,11 @@ static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
 }
 
 static int cnl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
-				  const struct intel_shared_dpll *pll)
+				  const struct intel_shared_dpll *pll,
+				  const struct intel_dpll_hw_state *pll_state)
 {
-	return __cnl_ddi_wrpll_get_freq(i915, pll, i915->dpll.ref_clks.nssc);
+	return __cnl_ddi_wrpll_get_freq(i915, pll, pll_state,
+					i915->dpll.ref_clks.nssc);
 }
 
 static bool
@@ -2762,11 +2768,12 @@ cnl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
 }
 
 static int cnl_ddi_lcpll_get_freq(struct drm_i915_private *i915,
-				  const struct intel_shared_dpll *pll)
+				  const struct intel_shared_dpll *pll,
+				  const struct intel_dpll_hw_state *pll_state)
 {
 	int link_clock = 0;
 
-	switch (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK) {
+	switch (pll_state->cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK) {
 	case DPLL_CFGCR0_LINK_RATE_810:
 		link_clock = 81000;
 		break;
@@ -2849,12 +2856,13 @@ static bool cnl_get_dpll(struct intel_atomic_state *state,
 }
 
 static int cnl_ddi_pll_get_freq(struct drm_i915_private *i915,
-				const struct intel_shared_dpll *pll)
+				const struct intel_shared_dpll *pll,
+				const struct intel_dpll_hw_state *pll_state)
 {
-	if (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_HDMI_MODE)
-		return cnl_ddi_wrpll_get_freq(i915, pll);
+	if (pll_state->cfgcr0 & DPLL_CFGCR0_HDMI_MODE)
+		return cnl_ddi_wrpll_get_freq(i915, pll, pll_state);
 	else
-		return cnl_ddi_lcpll_get_freq(i915, pll);
+		return cnl_ddi_lcpll_get_freq(i915, pll, pll_state);
 }
 
 static void cnl_update_dpll_ref_clks(struct drm_i915_private *i915)
@@ -3039,7 +3047,8 @@ static bool icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
 }
 
 static int icl_ddi_tbt_pll_get_freq(struct drm_i915_private *i915,
-				    const struct intel_shared_dpll *pll)
+				    const struct intel_shared_dpll *pll,
+				    const struct intel_dpll_hw_state *pll_state)
 {
 	/*
 	 * The PLL outputs multiple frequencies at the same time, selection is
@@ -3075,9 +3084,10 @@ icl_calc_wrpll(struct intel_crtc_state *crtc_state,
 }
 
 static int icl_ddi_combo_pll_get_freq(struct drm_i915_private *i915,
-				      const struct intel_shared_dpll *pll)
+				      const struct intel_shared_dpll *pll,
+				      const struct intel_dpll_hw_state *pll_state)
 {
-	return __cnl_ddi_wrpll_get_freq(i915, pll,
+	return __cnl_ddi_wrpll_get_freq(i915, pll, pll_state,
 					icl_wrpll_ref_clock(i915));
 }
 
@@ -3402,9 +3412,9 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
 }
 
 static int icl_ddi_mg_pll_get_freq(struct drm_i915_private *dev_priv,
-				   const struct intel_shared_dpll *pll)
+				   const struct intel_shared_dpll *pll,
+				   const struct intel_dpll_hw_state *pll_state)
 {
-	const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state;
 	u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
 	u64 tmp;
 
@@ -4515,16 +4525,18 @@ void intel_update_active_dpll(struct intel_atomic_state *state,
  * intel_dpll_get_freq - calculate the DPLL's output frequency
  * @i915: i915 device
  * @pll: DPLL for which to calculate the output frequency
+ * @pll_state: DPLL state from which to calculate the output frequency
  *
- * Return the output frequency corresponding to @pll's current state.
+ * Return the output frequency corresponding to @pll's passed in @pll_state.
  */
 int intel_dpll_get_freq(struct drm_i915_private *i915,
-			const struct intel_shared_dpll *pll)
+			const struct intel_shared_dpll *pll,
+			const struct intel_dpll_hw_state *pll_state)
 {
 	if (drm_WARN_ON(&i915->drm, !pll->info->funcs->get_freq))
 		return 0;
 
-	return pll->info->funcs->get_freq(i915, pll);
+	return pll->info->funcs->get_freq(i915, pll, pll_state);
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 4357f92eafd6..2eb7618ef957 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -300,10 +300,11 @@ struct intel_shared_dpll_funcs {
 	 * @get_freq:
 	 *
 	 * Hook for calculating the pll's output frequency based on its
-	 * current state.
+	 * passed in state.
 	 */
 	int (*get_freq)(struct drm_i915_private *i915,
-			const struct intel_shared_dpll *pll);
+			const struct intel_shared_dpll *pll,
+			const struct intel_dpll_hw_state *pll_state);
 };
 
 /**
@@ -399,7 +400,8 @@ void intel_update_active_dpll(struct intel_atomic_state *state,
 			      struct intel_crtc *crtc,
 			      struct intel_encoder *encoder);
 int intel_dpll_get_freq(struct drm_i915_private *i915,
-			const struct intel_shared_dpll *pll);
+			const struct intel_shared_dpll *pll,
+			const struct intel_dpll_hw_state *pll_state);
 bool intel_dpll_get_hw_state(struct drm_i915_private *i915,
 			     struct intel_shared_dpll *pll,
 			     struct intel_dpll_hw_state *hw_state);
-- 
2.26.2

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[Intel-gfx] [PATCH 4/4] drm/i915: Relocate cnl_get_ddi_pll()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Move cnl_get_ddi_pll() into a better spot from between
icl_get_ddi_pll() and dg1_get_ddi_pll(). Also reorder
the calls to the skl and bxt functions because ocd.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 48 ++++++++++----------
 1 file changed, 24 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 8ab622c0186e..322db0f3bbc6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11033,28 +11033,6 @@ static void dg1_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
 	icl_set_active_port_dpll(pipe_config, port_dpll_id);
 }
 
-static void cnl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
-			    struct intel_crtc_state *pipe_config)
-{
-	struct intel_shared_dpll *pll;
-	enum intel_dpll_id id;
-	bool pll_active;
-	u32 temp;
-
-	temp = intel_de_read(dev_priv, DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
-	id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
-
-	if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL2))
-		return;
-
-	pll = intel_get_shared_dpll_by_id(dev_priv, id);
-
-	pipe_config->shared_dpll = pll;
-	pll_active = intel_dpll_get_hw_state(dev_priv, pll,
-					     &pipe_config->dpll_hw_state);
-	drm_WARN_ON(&dev_priv->drm, !pll_active);
-}
-
 static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
 			    struct intel_crtc_state *pipe_config)
 {
@@ -11109,6 +11087,28 @@ static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
 	icl_set_active_port_dpll(pipe_config, port_dpll_id);
 }
 
+static void cnl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
+			    struct intel_crtc_state *pipe_config)
+{
+	struct intel_shared_dpll *pll;
+	enum intel_dpll_id id;
+	bool pll_active;
+	u32 temp;
+
+	temp = intel_de_read(dev_priv, DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
+	id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
+
+	if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL2))
+		return;
+
+	pll = intel_get_shared_dpll_by_id(dev_priv, id);
+
+	pipe_config->shared_dpll = pll;
+	pll_active = intel_dpll_get_hw_state(dev_priv, pll,
+					     &pipe_config->dpll_hw_state);
+	drm_WARN_ON(&dev_priv->drm, !pll_active);
+}
+
 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
 				enum port port,
 				struct intel_crtc_state *pipe_config)
@@ -11382,10 +11382,10 @@ static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
 		icl_get_ddi_pll(dev_priv, port, pipe_config);
 	else if (IS_CANNONLAKE(dev_priv))
 		cnl_get_ddi_pll(dev_priv, port, pipe_config);
-	else if (IS_GEN9_BC(dev_priv))
-		skl_get_ddi_pll(dev_priv, port, pipe_config);
 	else if (IS_GEN9_LP(dev_priv))
 		bxt_get_ddi_pll(dev_priv, port, pipe_config);
+	else if (IS_GEN9_BC(dev_priv))
+		skl_get_ddi_pll(dev_priv, port, pipe_config);
 	else
 		hsw_get_ddi_pll(dev_priv, port, pipe_config);
 
-- 
2.26.2

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Re: [Intel-gfx] [PATCH 1/4] drm/i915: Introduce intel_dpll_get_hw_state()

[Imre Deak]

On Tue, Nov 10, 2020 at 01:12:36AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Add a wrapper for the pll .get_hw_state() vfunc. Makes life
> a bit less miserable when you don't have to worry where the
> function pointer is stored.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

There's also assert_shared_dpll().

> ---
>  drivers/gpu/drm/i915/display/intel_display.c  | 14 +++++++------
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 20 ++++++++++++++++---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.h |  3 +++
>  3 files changed, 28 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 2729c852c668..a7c4cd7a8a31 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -10927,6 +10927,7 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc,
>  	if (intel_de_read(dev_priv, PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
>  		struct intel_shared_dpll *pll;
>  		enum intel_dpll_id pll_id;
> +		bool pll_active;
>  
>  		pipe_config->has_pch_encoder = true;
>  
> @@ -10954,8 +10955,9 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc,
>  			intel_get_shared_dpll_by_id(dev_priv, pll_id);
>  		pll = pipe_config->shared_dpll;
>  
> -		drm_WARN_ON(dev, !pll->info->funcs->get_hw_state(dev_priv, pll,
> -						 &pipe_config->dpll_hw_state));
> +		pll_active = intel_dpll_get_hw_state(dev_priv, pll,
> +						     &pipe_config->dpll_hw_state);
> +		drm_WARN_ON(dev, !pll_active);
>  
>  		tmp = pipe_config->dpll_hw_state.dpll;
>  		pipe_config->pixel_multiplier =
> @@ -11346,9 +11348,9 @@ static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
>  
>  	pll = pipe_config->shared_dpll;
>  	if (pll) {
> -		drm_WARN_ON(&dev_priv->drm,
> -			    !pll->info->funcs->get_hw_state(dev_priv, pll,
> -						&pipe_config->dpll_hw_state));
> +		bool pll_active = intel_dpll_get_hw_state(dev_priv, pll,
> +							  &pipe_config->dpll_hw_state);
> +		drm_WARN_ON(&dev_priv->drm, !pll_active);
>  	}
>  
>  	/*
> @@ -14587,7 +14589,7 @@ verify_single_dpll_state(struct drm_i915_private *dev_priv,
>  
>  	drm_dbg_kms(&dev_priv->drm, "%s\n", pll->info->name);
>  
> -	active = pll->info->funcs->get_hw_state(dev_priv, pll, &dpll_hw_state);
> +	active = intel_dpll_get_hw_state(dev_priv, pll, &dpll_hw_state);
>  
>  	if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
>  		I915_STATE_WARN(!pll->on && pll->active_mask,
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index a95e6a2ac698..1604c20bac33 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -141,7 +141,7 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
>  		     "asserting DPLL %s with no DPLL\n", onoff(state)))
>  		return;
>  
> -	cur_state = pll->info->funcs->get_hw_state(dev_priv, pll, &hw_state);
> +	cur_state = intel_dpll_get_hw_state(dev_priv, pll, &hw_state);
>  	I915_STATE_WARN(cur_state != state,
>  	     "%s assertion failure (expected %s, current %s)\n",
>  			pll->info->name, onoff(state), onoff(cur_state));
> @@ -4527,13 +4527,27 @@ int intel_dpll_get_freq(struct drm_i915_private *i915,
>  	return pll->info->funcs->get_freq(i915, pll);
>  }
>  
> +/**
> + * intel_dpll_get_hw_state - readout the DPLL's hardware state
> + * @i915: i915 device
> + * @pll: DPLL for which to calculate the output frequency
> + * @hw_state: DPLL's hardware state
> + *
> + * Read out @pll's hardware state into @hw_state.
> + */
> +bool intel_dpll_get_hw_state(struct drm_i915_private *i915,
> +			     struct intel_shared_dpll *pll,
> +			     struct intel_dpll_hw_state *hw_state)
> +{
> +	return pll->info->funcs->get_hw_state(i915, pll, hw_state);
> +}
> +
>  static void readout_dpll_hw_state(struct drm_i915_private *i915,
>  				  struct intel_shared_dpll *pll)
>  {
>  	struct intel_crtc *crtc;
>  
> -	pll->on = pll->info->funcs->get_hw_state(i915, pll,
> -						 &pll->state.hw_state);
> +	pll->on = intel_dpll_get_hw_state(i915, pll, &pll->state.hw_state);
>  
>  	if (IS_JSL_EHL(i915) && pll->on &&
>  	    pll->info->id == DPLL_ID_EHL_DPLL4) {
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index 205542fb8dc7..4357f92eafd6 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -400,6 +400,9 @@ void intel_update_active_dpll(struct intel_atomic_state *state,
>  			      struct intel_encoder *encoder);
>  int intel_dpll_get_freq(struct drm_i915_private *i915,
>  			const struct intel_shared_dpll *pll);
> +bool intel_dpll_get_hw_state(struct drm_i915_private *i915,
> +			     struct intel_shared_dpll *pll,
> +			     struct intel_dpll_hw_state *hw_state);
>  void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state);
>  void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
>  void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
> -- 
> 2.26.2
> 
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Re: [Intel-gfx] [PATCH 1/4] drm/i915: Introduce intel_dpll_get_hw_state()

[Imre Deak]

On Tue, Nov 10, 2020 at 01:25:45PM +0200, Imre Deak wrote:
> On Tue, Nov 10, 2020 at 01:12:36AM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Add a wrapper for the pll .get_hw_state() vfunc. Makes life
> > a bit less miserable when you don't have to worry where the
> > function pointer is stored.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Reviewed-by: Imre Deak <imre.deak@intel.com>
> 
> There's also assert_shared_dpll().

Ah nvm, it's also converted.

> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c  | 14 +++++++------
> >  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 20 ++++++++++++++++---
> >  drivers/gpu/drm/i915/display/intel_dpll_mgr.h |  3 +++
> >  3 files changed, 28 insertions(+), 9 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index 2729c852c668..a7c4cd7a8a31 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -10927,6 +10927,7 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc,
> >  	if (intel_de_read(dev_priv, PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
> >  		struct intel_shared_dpll *pll;
> >  		enum intel_dpll_id pll_id;
> > +		bool pll_active;
> >  
> >  		pipe_config->has_pch_encoder = true;
> >  
> > @@ -10954,8 +10955,9 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc,
> >  			intel_get_shared_dpll_by_id(dev_priv, pll_id);
> >  		pll = pipe_config->shared_dpll;
> >  
> > -		drm_WARN_ON(dev, !pll->info->funcs->get_hw_state(dev_priv, pll,
> > -						 &pipe_config->dpll_hw_state));
> > +		pll_active = intel_dpll_get_hw_state(dev_priv, pll,
> > +						     &pipe_config->dpll_hw_state);
> > +		drm_WARN_ON(dev, !pll_active);
> >  
> >  		tmp = pipe_config->dpll_hw_state.dpll;
> >  		pipe_config->pixel_multiplier =
> > @@ -11346,9 +11348,9 @@ static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
> >  
> >  	pll = pipe_config->shared_dpll;
> >  	if (pll) {
> > -		drm_WARN_ON(&dev_priv->drm,
> > -			    !pll->info->funcs->get_hw_state(dev_priv, pll,
> > -						&pipe_config->dpll_hw_state));
> > +		bool pll_active = intel_dpll_get_hw_state(dev_priv, pll,
> > +							  &pipe_config->dpll_hw_state);
> > +		drm_WARN_ON(&dev_priv->drm, !pll_active);
> >  	}
> >  
> >  	/*
> > @@ -14587,7 +14589,7 @@ verify_single_dpll_state(struct drm_i915_private *dev_priv,
> >  
> >  	drm_dbg_kms(&dev_priv->drm, "%s\n", pll->info->name);
> >  
> > -	active = pll->info->funcs->get_hw_state(dev_priv, pll, &dpll_hw_state);
> > +	active = intel_dpll_get_hw_state(dev_priv, pll, &dpll_hw_state);
> >  
> >  	if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
> >  		I915_STATE_WARN(!pll->on && pll->active_mask,
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > index a95e6a2ac698..1604c20bac33 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > @@ -141,7 +141,7 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
> >  		     "asserting DPLL %s with no DPLL\n", onoff(state)))
> >  		return;
> >  
> > -	cur_state = pll->info->funcs->get_hw_state(dev_priv, pll, &hw_state);
> > +	cur_state = intel_dpll_get_hw_state(dev_priv, pll, &hw_state);
> >  	I915_STATE_WARN(cur_state != state,
> >  	     "%s assertion failure (expected %s, current %s)\n",
> >  			pll->info->name, onoff(state), onoff(cur_state));
> > @@ -4527,13 +4527,27 @@ int intel_dpll_get_freq(struct drm_i915_private *i915,
> >  	return pll->info->funcs->get_freq(i915, pll);
> >  }
> >  
> > +/**
> > + * intel_dpll_get_hw_state - readout the DPLL's hardware state
> > + * @i915: i915 device
> > + * @pll: DPLL for which to calculate the output frequency
> > + * @hw_state: DPLL's hardware state
> > + *
> > + * Read out @pll's hardware state into @hw_state.
> > + */
> > +bool intel_dpll_get_hw_state(struct drm_i915_private *i915,
> > +			     struct intel_shared_dpll *pll,
> > +			     struct intel_dpll_hw_state *hw_state)
> > +{
> > +	return pll->info->funcs->get_hw_state(i915, pll, hw_state);
> > +}
> > +
> >  static void readout_dpll_hw_state(struct drm_i915_private *i915,
> >  				  struct intel_shared_dpll *pll)
> >  {
> >  	struct intel_crtc *crtc;
> >  
> > -	pll->on = pll->info->funcs->get_hw_state(i915, pll,
> > -						 &pll->state.hw_state);
> > +	pll->on = intel_dpll_get_hw_state(i915, pll, &pll->state.hw_state);
> >  
> >  	if (IS_JSL_EHL(i915) && pll->on &&
> >  	    pll->info->id == DPLL_ID_EHL_DPLL4) {
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > index 205542fb8dc7..4357f92eafd6 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > @@ -400,6 +400,9 @@ void intel_update_active_dpll(struct intel_atomic_state *state,
> >  			      struct intel_encoder *encoder);
> >  int intel_dpll_get_freq(struct drm_i915_private *i915,
> >  			const struct intel_shared_dpll *pll);
> > +bool intel_dpll_get_hw_state(struct drm_i915_private *i915,
> > +			     struct intel_shared_dpll *pll,
> > +			     struct intel_dpll_hw_state *hw_state);
> >  void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state);
> >  void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
> >  void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
> > -- 
> > 2.26.2
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH 2/4] drm/i915: Move intel_dpll_get_hw_state() into the hsw+ platform specific functions

[Imre Deak]

On Tue, Nov 10, 2020 at 01:12:37AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> On icl+ we want to populate both crtc_state.{shared_dpll,dpll_hw_state}
> and crtc_state.port_dplls[] during readout, whereas on pre-icl we
> want to leave the latter stuff untouched. Rather than adding more ifs
> into hsw_get_ddi_port_state() to copy the DPLL hw state around let's
> just move the whole dpll readout into hsw_get_ddi_dpll() & co.

making the port_dpll->hw_state -> crtc_state->dpll_hw_state copy
in icl_set_active_port_dpll() having more sense.

> Slightly repetitive, but meh.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 68 +++++++++++++++-----
>  1 file changed, 52 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index a7c4cd7a8a31..8ab622c0186e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -11010,7 +11010,10 @@ static void dg1_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
>  {
>  	enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
>  	enum phy phy = intel_port_to_phy(dev_priv, port);
> +	struct icl_port_dpll *port_dpll;
> +	struct intel_shared_dpll *pll;
>  	enum intel_dpll_id id;
> +	bool pll_active;
>  	u32 clk_sel;
>  
>  	clk_sel = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy)) & DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> @@ -11019,8 +11022,13 @@ static void dg1_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
>  	if (WARN_ON(id > DPLL_ID_DG1_DPLL3))
>  		return;
>  
> -	pipe_config->icl_port_dplls[port_dpll_id].pll =
> -		intel_get_shared_dpll_by_id(dev_priv, id);
> +	pll = intel_get_shared_dpll_by_id(dev_priv, id);
> +	port_dpll = &pipe_config->icl_port_dplls[port_dpll_id];
> +
> +	port_dpll->pll = pll;
> +	pll_active = intel_dpll_get_hw_state(dev_priv, pll,
> +					     &port_dpll->hw_state);
> +	drm_WARN_ON(&dev_priv->drm, !pll_active);
>  
>  	icl_set_active_port_dpll(pipe_config, port_dpll_id);
>  }
> @@ -11028,7 +11036,9 @@ static void dg1_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
>  static void cnl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
>  			    struct intel_crtc_state *pipe_config)
>  {
> +	struct intel_shared_dpll *pll;
>  	enum intel_dpll_id id;
> +	bool pll_active;
>  	u32 temp;
>  
>  	temp = intel_de_read(dev_priv, DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
> @@ -11037,7 +11047,12 @@ static void cnl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
>  	if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL2))
>  		return;
>  
> -	pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
> +	pll = intel_get_shared_dpll_by_id(dev_priv, id);
> +
> +	pipe_config->shared_dpll = pll;
> +	pll_active = intel_dpll_get_hw_state(dev_priv, pll,
> +					     &pipe_config->dpll_hw_state);
> +	drm_WARN_ON(&dev_priv->drm, !pll_active);
>  }
>  
>  static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
> @@ -11045,7 +11060,10 @@ static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
>  {
>  	enum phy phy = intel_port_to_phy(dev_priv, port);
>  	enum icl_port_dpll_id port_dpll_id;
> +	struct icl_port_dpll *port_dpll;
> +	struct intel_shared_dpll *pll;
>  	enum intel_dpll_id id;
> +	bool pll_active;
>  	u32 temp;
>  
>  	if (intel_phy_is_combo(dev_priv, phy)) {
> @@ -11080,8 +11098,13 @@ static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
>  		return;
>  	}
>  
> -	pipe_config->icl_port_dplls[port_dpll_id].pll =
> -		intel_get_shared_dpll_by_id(dev_priv, id);
> +	pll = intel_get_shared_dpll_by_id(dev_priv, id);
> +	port_dpll = &pipe_config->icl_port_dplls[port_dpll_id];
> +
> +	port_dpll->pll = pll;
> +	pll_active = intel_dpll_get_hw_state(dev_priv, pll,
> +					     &port_dpll->hw_state);
> +	drm_WARN_ON(&dev_priv->drm, !pll_active);
>  
>  	icl_set_active_port_dpll(pipe_config, port_dpll_id);
>  }
> @@ -11090,7 +11113,9 @@ static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
>  				enum port port,
>  				struct intel_crtc_state *pipe_config)
>  {
> +	struct intel_shared_dpll *pll;
>  	enum intel_dpll_id id;
> +	bool pll_active;
>  
>  	switch (port) {
>  	case PORT_A:
> @@ -11107,13 +11132,20 @@ static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
>  		return;
>  	}
>  
> -	pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
> +	pll = intel_get_shared_dpll_by_id(dev_priv, id);
> +
> +	pipe_config->shared_dpll = pll;
> +	pll_active = intel_dpll_get_hw_state(dev_priv, pll,
> +					     &pipe_config->dpll_hw_state);
> +	drm_WARN_ON(&dev_priv->drm, !pll_active);
>  }
>  
>  static void skl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
>  			    struct intel_crtc_state *pipe_config)
>  {
> +	struct intel_shared_dpll *pll;
>  	enum intel_dpll_id id;
> +	bool pll_active;
>  	u32 temp;
>  
>  	temp = intel_de_read(dev_priv, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
> @@ -11122,14 +11154,21 @@ static void skl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
>  	if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL3))
>  		return;
>  
> -	pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
> +	pll = intel_get_shared_dpll_by_id(dev_priv, id);
> +
> +	pipe_config->shared_dpll = pll;
> +	pll_active = intel_dpll_get_hw_state(dev_priv, pll,
> +					     &pipe_config->dpll_hw_state);
> +	drm_WARN_ON(&dev_priv->drm, !pll_active);
>  }
>  
>  static void hsw_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
>  			    struct intel_crtc_state *pipe_config)
>  {
> +	struct intel_shared_dpll *pll;
>  	enum intel_dpll_id id;
>  	u32 ddi_pll_sel = intel_de_read(dev_priv, PORT_CLK_SEL(port));
> +	bool pll_active;
>  
>  	switch (ddi_pll_sel) {
>  	case PORT_CLK_SEL_WRPLL1:
> @@ -11157,7 +11196,12 @@ static void hsw_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
>  		return;
>  	}
>  
> -	pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
> +	pll = intel_get_shared_dpll_by_id(dev_priv, id);
> +
> +	pipe_config->shared_dpll = pll;
> +	pll_active = intel_dpll_get_hw_state(dev_priv, pll,
> +					     &pipe_config->dpll_hw_state);
> +	drm_WARN_ON(&dev_priv->drm, !pll_active);
>  }
>  
>  static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
> @@ -11317,7 +11361,6 @@ static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
> -	struct intel_shared_dpll *pll;
>  	enum port port;
>  	u32 tmp;
>  
> @@ -11346,13 +11389,6 @@ static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
>  	else
>  		hsw_get_ddi_pll(dev_priv, port, pipe_config);
>  
> -	pll = pipe_config->shared_dpll;
> -	if (pll) {
> -		bool pll_active = intel_dpll_get_hw_state(dev_priv, pll,
> -							  &pipe_config->dpll_hw_state);
> -		drm_WARN_ON(&dev_priv->drm, !pll_active);
> -	}
> -
>  	/*
>  	 * Haswell has only FDI/PCH transcoder A. It is which is connected to
>  	 * DDI E. So just check whether this pipe is wired to DDI E and whether
> -- 
> 2.26.2
> 
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Re: [Intel-gfx] [PATCH 3/4] drm/i915: Use actual readout results for .get_freq()

[Imre Deak]

On Tue, Nov 10, 2020 at 01:12:38AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Currently the DPLL .get_freq() uses pll->state.hw_state which
> is not the thing we actually read out (except during driver
> load/resume). Outside of that pll->state.hw_state is just the
> thing we committed last time around. During state check we
> just read the thing into crtc_state->dpll_hw_state, so that
> is what we should use for calculating the DPLL output frequency.
> 
> I think we used to do this so that the results of the readout
> were actually used, but somehow it got changed when the
> .get_freq() refactoring happened.
> 
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Makes sense:
Reviewed-by: Imre Deak <imre.deak@intel.com>

We do actually check if pll->state.hw_state matches the actual HW state
in verify_single_dpll_state().

> ---
>  drivers/gpu/drm/i915/display/icl_dsi.c        |  3 +-
>  drivers/gpu/drm/i915/display/intel_ddi.c      |  3 +-
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 78 +++++++++++--------
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.h |  8 +-
>  4 files changed, 54 insertions(+), 38 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 096652921453..769bb1b0d543 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -1496,7 +1496,8 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
>  
>  	/* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
>  	pipe_config->port_clock = intel_dpll_get_freq(i915,
> -						      pipe_config->shared_dpll);
> +						      pipe_config->shared_dpll,
> +						      &pipe_config->dpll_hw_state);
>  
>  	pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk;
>  	if (intel_dsi->dual_link)
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index d4b1b73c7aab..9d80e47e9558 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1755,7 +1755,8 @@ static void intel_ddi_clock_get(struct intel_encoder *encoder,
>  								encoder->port);
>  	else
>  		pipe_config->port_clock =
> -			intel_dpll_get_freq(dev_priv, pipe_config->shared_dpll);
> +			intel_dpll_get_freq(dev_priv, pipe_config->shared_dpll,
> +					    &pipe_config->dpll_hw_state);
>  
>  	ddi_dotclock_get(pipe_config);
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 1604c20bac33..0f14c4dee02c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -891,11 +891,12 @@ hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state,
>  }
>  
>  static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
> -				  const struct intel_shared_dpll *pll)
> +				  const struct intel_shared_dpll *pll,
> +				  const struct intel_dpll_hw_state *pll_state)
>  {
>  	int refclk;
>  	int n, p, r;
> -	u32 wrpll = pll->state.hw_state.wrpll;
> +	u32 wrpll = pll_state->wrpll;
>  
>  	switch (wrpll & WRPLL_REF_MASK) {
>  	case WRPLL_REF_SPECIAL_HSW:
> @@ -962,7 +963,8 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
>  }
>  
>  static int hsw_ddi_lcpll_get_freq(struct drm_i915_private *i915,
> -				  const struct intel_shared_dpll *pll)
> +				  const struct intel_shared_dpll *pll,
> +				  const struct intel_dpll_hw_state *pll_state)
>  {
>  	int link_clock = 0;
>  
> @@ -1002,11 +1004,12 @@ hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
>  }
>  
>  static int hsw_ddi_spll_get_freq(struct drm_i915_private *i915,
> -				 const struct intel_shared_dpll *pll)
> +				 const struct intel_shared_dpll *pll,
> +				 const struct intel_dpll_hw_state *pll_state)
>  {
>  	int link_clock = 0;
>  
> -	switch (pll->state.hw_state.spll & SPLL_FREQ_MASK) {
> +	switch (pll_state->spll & SPLL_FREQ_MASK) {
>  	case SPLL_FREQ_810MHz:
>  		link_clock = 81000;
>  		break;
> @@ -1577,9 +1580,9 @@ static bool skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
>  }
>  
>  static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
> -				  const struct intel_shared_dpll *pll)
> +				  const struct intel_shared_dpll *pll,
> +				  const struct intel_dpll_hw_state *pll_state)
>  {
> -	const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state;
>  	int ref_clock = i915->dpll.ref_clks.nssc;
>  	u32 p0, p1, p2, dco_freq;
>  
> @@ -1688,12 +1691,12 @@ skl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
>  }
>  
>  static int skl_ddi_lcpll_get_freq(struct drm_i915_private *i915,
> -				  const struct intel_shared_dpll *pll)
> +				  const struct intel_shared_dpll *pll,
> +				  const struct intel_dpll_hw_state *pll_state)
>  {
>  	int link_clock = 0;
>  
> -	switch ((pll->state.hw_state.ctrl1 &
> -		 DPLL_CTRL1_LINK_RATE_MASK(0)) >>
> +	switch ((pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0)) >>
>  		DPLL_CTRL1_LINK_RATE_SHIFT(0)) {
>  	case DPLL_CTRL1_LINK_RATE_810:
>  		link_clock = 81000;
> @@ -1771,16 +1774,17 @@ static bool skl_get_dpll(struct intel_atomic_state *state,
>  }
>  
>  static int skl_ddi_pll_get_freq(struct drm_i915_private *i915,
> -				const struct intel_shared_dpll *pll)
> +				const struct intel_shared_dpll *pll,
> +				const struct intel_dpll_hw_state *pll_state)
>  {
>  	/*
>  	 * ctrl1 register is already shifted for each pll, just use 0 to get
>  	 * the internal shift for each field
>  	 */
> -	if (pll->state.hw_state.ctrl1 & DPLL_CTRL1_HDMI_MODE(0))
> -		return skl_ddi_wrpll_get_freq(i915, pll);
> +	if (pll_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0))
> +		return skl_ddi_wrpll_get_freq(i915, pll, pll_state);
>  	else
> -		return skl_ddi_lcpll_get_freq(i915, pll);
> +		return skl_ddi_lcpll_get_freq(i915, pll, pll_state);
>  }
>  
>  static void skl_update_dpll_ref_clks(struct drm_i915_private *i915)
> @@ -2218,9 +2222,9 @@ bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
>  }
>  
>  static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915,
> -				const struct intel_shared_dpll *pll)
> +				const struct intel_shared_dpll *pll,
> +				const struct intel_dpll_hw_state *pll_state)
>  {
> -	const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state;
>  	struct dpll clock;
>  
>  	clock.m1 = 2;
> @@ -2650,9 +2654,9 @@ ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
>  
>  static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
>  				    const struct intel_shared_dpll *pll,
> +				    const struct intel_dpll_hw_state *pll_state,
>  				    int ref_clock)
>  {
> -	const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state;
>  	u32 dco_fraction;
>  	u32 p0, p1, p2, dco_freq;
>  
> @@ -2711,9 +2715,11 @@ static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
>  }
>  
>  static int cnl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
> -				  const struct intel_shared_dpll *pll)
> +				  const struct intel_shared_dpll *pll,
> +				  const struct intel_dpll_hw_state *pll_state)
>  {
> -	return __cnl_ddi_wrpll_get_freq(i915, pll, i915->dpll.ref_clks.nssc);
> +	return __cnl_ddi_wrpll_get_freq(i915, pll, pll_state,
> +					i915->dpll.ref_clks.nssc);
>  }
>  
>  static bool
> @@ -2762,11 +2768,12 @@ cnl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
>  }
>  
>  static int cnl_ddi_lcpll_get_freq(struct drm_i915_private *i915,
> -				  const struct intel_shared_dpll *pll)
> +				  const struct intel_shared_dpll *pll,
> +				  const struct intel_dpll_hw_state *pll_state)
>  {
>  	int link_clock = 0;
>  
> -	switch (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK) {
> +	switch (pll_state->cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK) {
>  	case DPLL_CFGCR0_LINK_RATE_810:
>  		link_clock = 81000;
>  		break;
> @@ -2849,12 +2856,13 @@ static bool cnl_get_dpll(struct intel_atomic_state *state,
>  }
>  
>  static int cnl_ddi_pll_get_freq(struct drm_i915_private *i915,
> -				const struct intel_shared_dpll *pll)
> +				const struct intel_shared_dpll *pll,
> +				const struct intel_dpll_hw_state *pll_state)
>  {
> -	if (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_HDMI_MODE)
> -		return cnl_ddi_wrpll_get_freq(i915, pll);
> +	if (pll_state->cfgcr0 & DPLL_CFGCR0_HDMI_MODE)
> +		return cnl_ddi_wrpll_get_freq(i915, pll, pll_state);
>  	else
> -		return cnl_ddi_lcpll_get_freq(i915, pll);
> +		return cnl_ddi_lcpll_get_freq(i915, pll, pll_state);
>  }
>  
>  static void cnl_update_dpll_ref_clks(struct drm_i915_private *i915)
> @@ -3039,7 +3047,8 @@ static bool icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
>  }
>  
>  static int icl_ddi_tbt_pll_get_freq(struct drm_i915_private *i915,
> -				    const struct intel_shared_dpll *pll)
> +				    const struct intel_shared_dpll *pll,
> +				    const struct intel_dpll_hw_state *pll_state)
>  {
>  	/*
>  	 * The PLL outputs multiple frequencies at the same time, selection is
> @@ -3075,9 +3084,10 @@ icl_calc_wrpll(struct intel_crtc_state *crtc_state,
>  }
>  
>  static int icl_ddi_combo_pll_get_freq(struct drm_i915_private *i915,
> -				      const struct intel_shared_dpll *pll)
> +				      const struct intel_shared_dpll *pll,
> +				      const struct intel_dpll_hw_state *pll_state)
>  {
> -	return __cnl_ddi_wrpll_get_freq(i915, pll,
> +	return __cnl_ddi_wrpll_get_freq(i915, pll, pll_state,
>  					icl_wrpll_ref_clock(i915));
>  }
>  
> @@ -3402,9 +3412,9 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
>  }
>  
>  static int icl_ddi_mg_pll_get_freq(struct drm_i915_private *dev_priv,
> -				   const struct intel_shared_dpll *pll)
> +				   const struct intel_shared_dpll *pll,
> +				   const struct intel_dpll_hw_state *pll_state)
>  {
> -	const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state;
>  	u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
>  	u64 tmp;
>  
> @@ -4515,16 +4525,18 @@ void intel_update_active_dpll(struct intel_atomic_state *state,
>   * intel_dpll_get_freq - calculate the DPLL's output frequency
>   * @i915: i915 device
>   * @pll: DPLL for which to calculate the output frequency
> + * @pll_state: DPLL state from which to calculate the output frequency
>   *
> - * Return the output frequency corresponding to @pll's current state.
> + * Return the output frequency corresponding to @pll's passed in @pll_state.
>   */
>  int intel_dpll_get_freq(struct drm_i915_private *i915,
> -			const struct intel_shared_dpll *pll)
> +			const struct intel_shared_dpll *pll,
> +			const struct intel_dpll_hw_state *pll_state)
>  {
>  	if (drm_WARN_ON(&i915->drm, !pll->info->funcs->get_freq))
>  		return 0;
>  
> -	return pll->info->funcs->get_freq(i915, pll);
> +	return pll->info->funcs->get_freq(i915, pll, pll_state);
>  }
>  
>  /**
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index 4357f92eafd6..2eb7618ef957 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -300,10 +300,11 @@ struct intel_shared_dpll_funcs {
>  	 * @get_freq:
>  	 *
>  	 * Hook for calculating the pll's output frequency based on its
> -	 * current state.
> +	 * passed in state.
>  	 */
>  	int (*get_freq)(struct drm_i915_private *i915,
> -			const struct intel_shared_dpll *pll);
> +			const struct intel_shared_dpll *pll,
> +			const struct intel_dpll_hw_state *pll_state);
>  };
>  
>  /**
> @@ -399,7 +400,8 @@ void intel_update_active_dpll(struct intel_atomic_state *state,
>  			      struct intel_crtc *crtc,
>  			      struct intel_encoder *encoder);
>  int intel_dpll_get_freq(struct drm_i915_private *i915,
> -			const struct intel_shared_dpll *pll);
> +			const struct intel_shared_dpll *pll,
> +			const struct intel_dpll_hw_state *pll_state);
>  bool intel_dpll_get_hw_state(struct drm_i915_private *i915,
>  			     struct intel_shared_dpll *pll,
>  			     struct intel_dpll_hw_state *hw_state);
> -- 
> 2.26.2
> 
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Re: [Intel-gfx] [PATCH 4/4] drm/i915: Relocate cnl_get_ddi_pll()

[Imre Deak]

On Tue, Nov 10, 2020 at 01:12:39AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Move cnl_get_ddi_pll() into a better spot from between
> icl_get_ddi_pll() and dg1_get_ddi_pll(). Also reorder
> the calls to the skl and bxt functions because ocd.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 48 ++++++++++----------
>  1 file changed, 24 insertions(+), 24 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 8ab622c0186e..322db0f3bbc6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -11033,28 +11033,6 @@ static void dg1_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
>  	icl_set_active_port_dpll(pipe_config, port_dpll_id);
>  }
>  
> -static void cnl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
> -			    struct intel_crtc_state *pipe_config)
> -{
> -	struct intel_shared_dpll *pll;
> -	enum intel_dpll_id id;
> -	bool pll_active;
> -	u32 temp;
> -
> -	temp = intel_de_read(dev_priv, DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
> -	id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
> -
> -	if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL2))
> -		return;
> -
> -	pll = intel_get_shared_dpll_by_id(dev_priv, id);
> -
> -	pipe_config->shared_dpll = pll;
> -	pll_active = intel_dpll_get_hw_state(dev_priv, pll,
> -					     &pipe_config->dpll_hw_state);
> -	drm_WARN_ON(&dev_priv->drm, !pll_active);
> -}
> -
>  static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
>  			    struct intel_crtc_state *pipe_config)
>  {
> @@ -11109,6 +11087,28 @@ static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
>  	icl_set_active_port_dpll(pipe_config, port_dpll_id);
>  }
>  
> +static void cnl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
> +			    struct intel_crtc_state *pipe_config)
> +{
> +	struct intel_shared_dpll *pll;
> +	enum intel_dpll_id id;
> +	bool pll_active;
> +	u32 temp;
> +
> +	temp = intel_de_read(dev_priv, DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
> +	id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
> +
> +	if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL2))
> +		return;
> +
> +	pll = intel_get_shared_dpll_by_id(dev_priv, id);
> +
> +	pipe_config->shared_dpll = pll;
> +	pll_active = intel_dpll_get_hw_state(dev_priv, pll,
> +					     &pipe_config->dpll_hw_state);
> +	drm_WARN_ON(&dev_priv->drm, !pll_active);
> +}
> +
>  static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
>  				enum port port,
>  				struct intel_crtc_state *pipe_config)
> @@ -11382,10 +11382,10 @@ static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
>  		icl_get_ddi_pll(dev_priv, port, pipe_config);
>  	else if (IS_CANNONLAKE(dev_priv))
>  		cnl_get_ddi_pll(dev_priv, port, pipe_config);
> -	else if (IS_GEN9_BC(dev_priv))
> -		skl_get_ddi_pll(dev_priv, port, pipe_config);
>  	else if (IS_GEN9_LP(dev_priv))
>  		bxt_get_ddi_pll(dev_priv, port, pipe_config);
> +	else if (IS_GEN9_BC(dev_priv))
> +		skl_get_ddi_pll(dev_priv, port, pipe_config);
>  	else
>  		hsw_get_ddi_pll(dev_priv, port, pipe_config);
>  
> -- 
> 2.26.2
> 
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/4] drm/i915: Introduce intel_dpll_get_hw_state()

[Patchwork]

== Series Details ==

Series: series starting with [1/4] drm/i915: Introduce intel_dpll_get_hw_state()
URL   : https://patchwork.freedesktop.org/series/83664/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_reset.c:1312:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:    expected void *in
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:    got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:    expected void const *src
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:    got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: warning: incorrect type in argument 2 (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:    expected void *in
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:    got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:    expected void const *src
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:    got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: warning: incorrect type in argument 2 (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:    expected unsigned int [usertype] *s
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:    got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: warning: incorrect type in argument 1 (different address spaces)
+drivers/gpu/drm/i915/gvt/mmio.c:290:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1440:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1494:15: warning: memset with byte count of 16777216
+./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31
+./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31
+./include/linux/seqlock.h:864:16: warning: trying to copy expression type 31
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block


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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: Introduce intel_dpll_get_hw_state()

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 5136 bytes --]

== Series Details ==

Series: series starting with [1/4] drm/i915: Introduce intel_dpll_get_hw_state()
URL   : https://patchwork.freedesktop.org/series/83664/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9305 -> Patchwork_18877
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18877/index.html

New tests
---------

  New tests have been introduced between CI_DRM_9305 and Patchwork_18877:

### New CI tests (1) ###

  * boot:
    - Statuses : 41 pass(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in Patchwork_18877 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_hotunplug@unbind-rebind:
    - fi-skl-lmem:        [PASS][1] -> [DMESG-WARN][2] ([i915#2605])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9305/fi-skl-lmem/igt@core_hotunplug@unbind-rebind.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18877/fi-skl-lmem/igt@core_hotunplug@unbind-rebind.html
    - fi-icl-y:           [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9305/fi-icl-y/igt@core_hotunplug@unbind-rebind.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18877/fi-icl-y/igt@core_hotunplug@unbind-rebind.html

  * igt@i915_module_load@reload:
    - fi-icl-u2:          [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) +1 similar issue
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9305/fi-icl-u2/igt@i915_module_load@reload.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18877/fi-icl-u2/igt@i915_module_load@reload.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - fi-byt-j1900:       [PASS][7] -> [DMESG-WARN][8] ([i915#1982])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9305/fi-byt-j1900/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18877/fi-byt-j1900/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
    - fi-cfl-8109u:       [PASS][9] -> [DMESG-WARN][10] ([i915#165]) +15 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9305/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18877/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html

  
#### Possible fixes ####

  * igt@i915_pm_rpm@module-reload:
    - fi-byt-j1900:       [DMESG-WARN][11] ([i915#1982]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9305/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18877/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html

  * igt@kms_busy@basic@flip:
    - {fi-kbl-7560u}:     [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] +1 similar issue
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9305/fi-kbl-7560u/igt@kms_busy@basic@flip.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18877/fi-kbl-7560u/igt@kms_busy@basic@flip.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - fi-bsw-kefka:       [DMESG-WARN][15] ([i915#1982]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9305/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18877/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
  [i915#2601]: https://gitlab.freedesktop.org/drm/intel/issues/2601
  [i915#2605]: https://gitlab.freedesktop.org/drm/intel/issues/2605


Participating hosts (47 -> 41)
------------------------------

  Missing    (6): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-tgl-y fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_9305 -> Patchwork_18877

  CI-20190529: 20190529
  CI_DRM_9305: de2429aefa185f06afb2b69d9bef24d3479d310b @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5846: 2d522ecdf26c346af22e0406e0243b2932197b34 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_18877: 163eaa5f262d4b3485b087cecabf5f8f8829188d @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

163eaa5f262d drm/i915: Relocate cnl_get_ddi_pll()
a50c06e0ec42 drm/i915: Use actual readout results for .get_freq()
015cdcfafb22 drm/i915: Move intel_dpll_get_hw_state() into the hsw+ platform specific functions
bb9dc4a8fda4 drm/i915: Introduce intel_dpll_get_hw_state()

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18877/index.html

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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/4] drm/i915: Introduce intel_dpll_get_hw_state()

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 17687 bytes --]

== Series Details ==

Series: series starting with [1/4] drm/i915: Introduce intel_dpll_get_hw_state()
URL   : https://patchwork.freedesktop.org/series/83664/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9305_full -> Patchwork_18877_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_18877_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_18877_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_18877_full:

### IGT changes ###

#### Possible regressions ####

  * igt@core_hotunplug@hotrebind-lateclose:
    - shard-snb:          [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9305/shard-snb7/igt@core_hotunplug@hotrebind-lateclose.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18877/shard-snb6/igt@core_hotunplug@hotrebind-lateclose.html

  
New tests
---------

  New tests have been introduced between CI_DRM_9305_full and Patchwork_18877_full:

### New CI tests (1) ###

  * boot:
    - Statuses : 200 pass(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in Patchwork_18877_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_hotunplug@unbind-rebind:
    - shard-iclb:         [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9305/shard-iclb1/igt@core_hotunplug@unbind-rebind.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18877/shard-iclb7/igt@core_hotunplug@unbind-rebind.html

  * igt@kms_atomic@crtc-invalid-params-fence:
    - shard-tglb:         [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9305/shard-tglb5/igt@kms_atomic@crtc-invalid-params-fence.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18877/shard-tglb2/igt@kms_atomic@crtc-invalid-params-fence.html

  * igt@kms_cursor_crc@pipe-b-cursor-256x256-random:
    - shard-skl:          [PASS][7] -> [FAIL][8] ([i915#54]) +1 similar issue
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9305/shard-skl9/igt@kms_cursor_crc@pipe-b-cursor-256x256-random.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18877/shard-skl4/igt@kms_cursor_crc@pipe-b-cursor-256x256-random.html

  * igt@kms_cursor_edge_walk@pipe-a-256x256-top-edge:
    - shard-glk:          [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) +2 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9305/shard-glk2/igt@kms_cursor_edge_walk@pipe-a-256x256-top-edge.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18877/shard-glk4/igt@kms_cursor_edge_walk@pipe-a-256x256-top-edge.html

  * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
    - shard-hsw:          [PASS][11] -> [FAIL][12] ([i915#96])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9305/shard-hsw5/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18877/shard-hsw8/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank@a-edp1:
    - shard-skl:          [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) +8 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9305/shard-skl7/igt@kms_flip@flip-vs-absolute-wf_vblank@a-edp1.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18877/shard-skl7/igt@kms_flip@flip-vs-absolute-wf_vblank@a-edp1.html

  * igt@kms_flip@flip-vs-expired-vblank@b-edp1:
    - shard-skl:          [PASS][15] -> [FAIL][16] ([i915#79])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9305/shard-skl10/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18877/shard-skl3/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html

  * igt@kms_flip@plain-flip-ts-check@c-edp1:
    - shard-skl:          [PASS][17] -> [FAIL][18] ([i915#2122])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9305/shard-skl9/igt@kms_flip@plain-flip-ts-check@c-edp1.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18877/shard-skl4/igt@kms_flip@plain-flip-ts-check@c-edp1.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-cpu:
    - shard-kbl:          [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) +1 similar issue
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9305/shard-kbl3/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-cpu.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18877/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-cpu.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
    - shard-skl:          [PASS][21] -> [INCOMPLETE][22] ([i915#198])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9305/shard-skl10/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18877/shard-skl2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html

  * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
    - shard-skl:          [PASS][23] -> [FAIL][24] ([fdo#108145] / [i915#265])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9305/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18877/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html

  * igt@kms_plane_scaling@pipe-b-scaler-with-pixel-format:
    - shard-apl:          [PASS][25] -> [DMESG-WARN][26] ([i915#1635] / [i915#1982]) +3 similar issues
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9305/shard-apl4/igt@kms_plane_scaling@pipe-b-scaler-with-pixel-format.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18877/shard-apl8/igt@kms_plane_scaling@pipe-b-scaler-with-pixel-format.html

  * igt@kms_psr@psr2_cursor_plane_move:
    - shard-iclb:         [PASS][27] -> [SKIP][28] ([fdo#109441]) +1 similar issue
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9305/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18877/shard-iclb4/igt@kms_psr@psr2_cursor_plane_move.html

  * igt@kms_setmode@basic:
    - shard-hsw:          [PASS][29] -> [FAIL][30] ([i915#31])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9305/shard-hsw1/igt@kms_setmode@basic.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18877/shard-hsw6/igt@kms_setmode@basic.html

  * igt@kms_vblank@pipe-c-wait-forked-busy:
    - shard-hsw:          [PASS][31] -> [DMESG-WARN][32] ([i915#1982])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9305/shard-hsw1/igt@kms_vblank@pipe-c-wait-forked-busy.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18877/shard-hsw4/igt@kms_vblank@pipe-c-wait-forked-busy.html

  
#### Possible fixes ####

  * igt@gem_exec_flush@basic-wb-rw-before-default:
    - shard-snb:          [FAIL][33] -> [PASS][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9305/shard-snb2/igt@gem_exec_flush@basic-wb-rw-before-default.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18877/shard-snb5/igt@gem_exec_flush@basic-wb-rw-before-default.html

  * igt@gem_exec_schedule@preempt-other@bcs0:
    - shard-skl:          [FAIL][35] -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9305/shard-skl6/igt@gem_exec_schedule@preempt-other@bcs0.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18877/shard-skl3/igt@gem_exec_schedule@preempt-other@bcs0.html

  * {igt@kms_async_flips@alternate-sync-async-flip}:
    - shard-tglb:         [FAIL][37] ([i915#2521]) -> [PASS][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9305/shard-tglb3/igt@kms_async_flips@alternate-sync-async-flip.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18877/shard-tglb2/igt@kms_async_flips@alternate-sync-async-flip.html

  * igt@kms_atomic@crtc-invalid-params-fence:
    - shard-snb:          [SKIP][39] ([fdo#109271]) -> [PASS][40] +3 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9305/shard-snb2/igt@kms_atomic@crtc-invalid-params-fence.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18877/shard-snb7/igt@kms_atomic@crtc-invalid-params-fence.html

  * igt@kms_cursor_crc@pipe-b-cursor-128x128-random:
    - shard-skl:          [FAIL][41] ([i915#54]) -> [PASS][42] +5 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9305/shard-skl8/igt@kms_cursor_crc@pipe-b-cursor-128x128-random.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18877/shard-skl8/igt@kms_cursor_crc@pipe-b-cursor-128x128-random.html

  * igt@kms_cursor_crc@pipe-b-cursor-alpha-transparent:
    - shard-hsw:          [INCOMPLETE][43] -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9305/shard-hsw6/igt@kms_cursor_crc@pipe-b-cursor-alpha-transparent.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18877/shard-hsw6/igt@kms_cursor_crc@pipe-b-cursor-alpha-transparent.html

  * igt@kms_cursor_edge_walk@pipe-b-64x64-right-edge:
    - shard-glk:          [DMESG-WARN][45] ([i915#1982]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9305/shard-glk2/igt@kms_cursor_edge_walk@pipe-b-64x64-right-edge.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18877/shard-glk4/igt@kms_cursor_edge_walk@pipe-b-64x64-right-edge.html

  * igt@kms_flip@flip-vs-dpms-off-vs-modeset@b-vga1:
    - shard-hsw:          [DMESG-WARN][47] ([i915#44]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9305/shard-hsw5/igt@kms_flip@flip-vs-dpms-off-vs-modeset@b-vga1.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18877/shard-hsw8/igt@kms_flip@flip-vs-dpms-off-vs-modeset@b-vga1.html

  * igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a2:
    - shard-glk:          [FAIL][49] ([i915#79]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9305/shard-glk3/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a2.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18877/shard-glk1/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a2.html

  * igt@kms_flip@flip-vs-fences@a-dp1:
    - shard-apl:          [DMESG-WARN][51] ([i915#1635] / [i915#1982]) -> [PASS][52] +3 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9305/shard-apl4/igt@kms_flip@flip-vs-fences@a-dp1.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18877/shard-apl8/igt@kms_flip@flip-vs-fences@a-dp1.html

  * igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack:
    - shard-kbl:          [DMESG-WARN][53] ([i915#1982]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9305/shard-kbl1/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18877/shard-kbl2/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-iclb:         [INCOMPLETE][55] ([i915#1185]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9305/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-suspend.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18877/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-skl:          [FAIL][57] ([i915#1188]) -> [PASS][58] +1 similar issue
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9305/shard-skl8/igt@kms_hdr@bpc-switch-suspend.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18877/shard-skl8/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_plane_lowres@pipe-a-tiling-yf:
    - shard-skl:          [DMESG-WARN][59] ([i915#1982]) -> [PASS][60] +2 similar issues
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9305/shard-skl9/igt@kms_plane_lowres@pipe-a-tiling-yf.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18877/shard-skl5/igt@kms_plane_lowres@pipe-a-tiling-yf.html

  * igt@kms_psr@psr2_sprite_mmap_gtt:
    - shard-iclb:         [SKIP][61] ([fdo#109441]) -> [PASS][62] +2 similar issues
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9305/shard-iclb7/igt@kms_psr@psr2_sprite_mmap_gtt.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18877/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html

  * igt@sysfs_heartbeat_interval@mixed@rcs0:
    - shard-kbl:          [INCOMPLETE][63] ([i915#1731]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9305/shard-kbl6/igt@sysfs_heartbeat_interval@mixed@rcs0.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18877/shard-kbl7/igt@sysfs_heartbeat_interval@mixed@rcs0.html

  * igt@sysfs_timeslice_duration@timeout@rcs0:
    - shard-skl:          [FAIL][65] ([i915#1732]) -> [PASS][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9305/shard-skl2/igt@sysfs_timeslice_duration@timeout@rcs0.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18877/shard-skl4/igt@sysfs_timeslice_duration@timeout@rcs0.html

  
#### Warnings ####

  * igt@core_hotunplug@hotrebind-lateclose:
    - shard-hsw:          [FAIL][67] ([i915#2644]) -> [WARN][68] ([i915#2283])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9305/shard-hsw8/igt@core_hotunplug@hotrebind-lateclose.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18877/shard-hsw4/igt@core_hotunplug@hotrebind-lateclose.html

  * igt@kms_dp_dsc@basic-dsc-enable-edp:
    - shard-iclb:         [SKIP][69] ([fdo#109349]) -> [DMESG-WARN][70] ([i915#1226])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9305/shard-iclb8/igt@kms_dp_dsc@basic-dsc-enable-edp.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18877/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html

  * igt@runner@aborted:
    - shard-kbl:          [FAIL][71] ([i915#1611] / [i915#2439]) -> [FAIL][72] ([i915#1611] / [i915#2439] / [i915#483])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9305/shard-kbl7/igt@runner@aborted.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18877/shard-kbl3/igt@runner@aborted.html
    - shard-glk:          ([FAIL][73], [FAIL][74]) ([i915#1611] / [i915#1814] / [i915#2439] / [k.org#202321]) -> [FAIL][75] ([i915#1611] / [i915#2439] / [k.org#202321])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9305/shard-glk5/igt@runner@aborted.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9305/shard-glk8/igt@runner@aborted.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18877/shard-glk6/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [i915#1185]: https://gitlab.freedesktop.org/drm/intel/issues/1185
  [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
  [i915#1226]: https://gitlab.freedesktop.org/drm/intel/issues/1226
  [i915#1611]: https://gitlab.freedesktop.org/drm/intel/issues/1611
  [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
  [i915#1731]: https://gitlab.freedesktop.org/drm/intel/issues/1731
  [i915#1732]: https://gitlab.freedesktop.org/drm/intel/issues/1732
  [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
  [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
  [i915#2283]: https://gitlab.freedesktop.org/drm/intel/issues/2283
  [i915#2439]: https://gitlab.freedesktop.org/drm/intel/issues/2439
  [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
  [i915#2644]: https://gitlab.freedesktop.org/drm/intel/issues/2644
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
  [i915#44]: https://gitlab.freedesktop.org/drm/intel/issues/44
  [i915#483]: https://gitlab.freedesktop.org/drm/intel/issues/483
  [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#96]: https://gitlab.freedesktop.org/drm/intel/issues/96
  [k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321


Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * Linux: CI_DRM_9305 -> Patchwork_18877

  CI-20190529: 20190529
  CI_DRM_9305: de2429aefa185f06afb2b69d9bef24d3479d310b @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5846: 2d522ecdf26c346af22e0406e0243b2932197b34 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_18877: 163eaa5f262d4b3485b087cecabf5f8f8829188d @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18877/index.html

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