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From: Will Deacon <will@kernel.org>
To: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Cc: Robin Murphy <robin.murphy@arm.com>,
	Joerg Roedel <joro@8bytes.org>,
	Jordan Crouse <jcrouse@codeaurora.org>,
	Rob Clark <robdclark@gmail.com>,
	iommu@lists.linux-foundation.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
	Akhil P Oommen <akhilpo@codeaurora.org>,
	freedreno@lists.freedesktop.org,
	"Kristian H . Kristensen" <hoegsberg@google.com>,
	dri-devel@lists.freedesktop.org
Subject: Re: [PATCHv7 1/7] iommu/io-pgtable-arm: Add support to use system cache
Date: Tue, 10 Nov 2020 12:18:56 +0000	[thread overview]
Message-ID: <20201110121855.GD16239@willie-the-truck> (raw)
In-Reply-To: <1d4979c0dcf649c5717605c598067b4b225ab9de.1604048969.git.saiprakash.ranjan@codeaurora.org>

On Fri, Oct 30, 2020 at 02:53:08PM +0530, Sai Prakash Ranjan wrote:
> Add a quirk IO_PGTABLE_QUIRK_SYS_CACHE to override the
> attributes set in TCR for the page table walker when
> using system cache.
> 
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> ---
>  drivers/iommu/io-pgtable-arm.c | 7 ++++++-
>  include/linux/io-pgtable.h     | 4 ++++
>  2 files changed, 10 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
> index a7a9bc08dcd1..a356caf1683a 100644
> --- a/drivers/iommu/io-pgtable-arm.c
> +++ b/drivers/iommu/io-pgtable-arm.c
> @@ -761,7 +761,8 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie)
>  
>  	if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS |
>  			    IO_PGTABLE_QUIRK_NON_STRICT |
> -			    IO_PGTABLE_QUIRK_ARM_TTBR1))
> +			    IO_PGTABLE_QUIRK_ARM_TTBR1 |
> +			    IO_PGTABLE_QUIRK_SYS_CACHE))
>  		return NULL;
>  
>  	data = arm_lpae_alloc_pgtable(cfg);
> @@ -773,6 +774,10 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie)
>  		tcr->sh = ARM_LPAE_TCR_SH_IS;
>  		tcr->irgn = ARM_LPAE_TCR_RGN_WBWA;
>  		tcr->orgn = ARM_LPAE_TCR_RGN_WBWA;
> +	} else if (cfg->quirks & IO_PGTABLE_QUIRK_SYS_CACHE) {
> +		tcr->sh = ARM_LPAE_TCR_SH_OS;
> +		tcr->irgn = ARM_LPAE_TCR_RGN_NC;
> +		tcr->orgn = ARM_LPAE_TCR_RGN_WBWA;

Given that this only applies in the case where then page-table walker is
non-coherent, I think we'd be better off renaming the quirk to something
like IO_PGTABLE_QUIRK_ARM_OUTER_WBWA and then rejecting it in the
non-coherent case.

>  	} else {
>  		tcr->sh = ARM_LPAE_TCR_SH_OS;
>  		tcr->irgn = ARM_LPAE_TCR_RGN_NC;
> diff --git a/include/linux/io-pgtable.h b/include/linux/io-pgtable.h
> index 4cde111e425b..86631f711e05 100644
> --- a/include/linux/io-pgtable.h
> +++ b/include/linux/io-pgtable.h
> @@ -86,6 +86,9 @@ struct io_pgtable_cfg {
>  	 *
>  	 * IO_PGTABLE_QUIRK_ARM_TTBR1: (ARM LPAE format) Configure the table
>  	 *	for use in the upper half of a split address space.
> +	 *
> +	 * IO_PGTABLE_QUIRK_SYS_CACHE: Override the attributes set in TCR for
> +	 *	the page table walker when using system cache.

and then update this accordingly.

Will

WARNING: multiple messages have this Message-ID (diff)
From: Will Deacon <will@kernel.org>
To: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Cc: freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org,
	iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org,
	Akhil P Oommen <akhilpo@codeaurora.org>,
	dri-devel@lists.freedesktop.org,
	"Kristian H . Kristensen" <hoegsberg@google.com>,
	Robin Murphy <robin.murphy@arm.com>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCHv7 1/7] iommu/io-pgtable-arm: Add support to use system cache
Date: Tue, 10 Nov 2020 12:18:56 +0000	[thread overview]
Message-ID: <20201110121855.GD16239@willie-the-truck> (raw)
In-Reply-To: <1d4979c0dcf649c5717605c598067b4b225ab9de.1604048969.git.saiprakash.ranjan@codeaurora.org>

On Fri, Oct 30, 2020 at 02:53:08PM +0530, Sai Prakash Ranjan wrote:
> Add a quirk IO_PGTABLE_QUIRK_SYS_CACHE to override the
> attributes set in TCR for the page table walker when
> using system cache.
> 
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> ---
>  drivers/iommu/io-pgtable-arm.c | 7 ++++++-
>  include/linux/io-pgtable.h     | 4 ++++
>  2 files changed, 10 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
> index a7a9bc08dcd1..a356caf1683a 100644
> --- a/drivers/iommu/io-pgtable-arm.c
> +++ b/drivers/iommu/io-pgtable-arm.c
> @@ -761,7 +761,8 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie)
>  
>  	if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS |
>  			    IO_PGTABLE_QUIRK_NON_STRICT |
> -			    IO_PGTABLE_QUIRK_ARM_TTBR1))
> +			    IO_PGTABLE_QUIRK_ARM_TTBR1 |
> +			    IO_PGTABLE_QUIRK_SYS_CACHE))
>  		return NULL;
>  
>  	data = arm_lpae_alloc_pgtable(cfg);
> @@ -773,6 +774,10 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie)
>  		tcr->sh = ARM_LPAE_TCR_SH_IS;
>  		tcr->irgn = ARM_LPAE_TCR_RGN_WBWA;
>  		tcr->orgn = ARM_LPAE_TCR_RGN_WBWA;
> +	} else if (cfg->quirks & IO_PGTABLE_QUIRK_SYS_CACHE) {
> +		tcr->sh = ARM_LPAE_TCR_SH_OS;
> +		tcr->irgn = ARM_LPAE_TCR_RGN_NC;
> +		tcr->orgn = ARM_LPAE_TCR_RGN_WBWA;

Given that this only applies in the case where then page-table walker is
non-coherent, I think we'd be better off renaming the quirk to something
like IO_PGTABLE_QUIRK_ARM_OUTER_WBWA and then rejecting it in the
non-coherent case.

>  	} else {
>  		tcr->sh = ARM_LPAE_TCR_SH_OS;
>  		tcr->irgn = ARM_LPAE_TCR_RGN_NC;
> diff --git a/include/linux/io-pgtable.h b/include/linux/io-pgtable.h
> index 4cde111e425b..86631f711e05 100644
> --- a/include/linux/io-pgtable.h
> +++ b/include/linux/io-pgtable.h
> @@ -86,6 +86,9 @@ struct io_pgtable_cfg {
>  	 *
>  	 * IO_PGTABLE_QUIRK_ARM_TTBR1: (ARM LPAE format) Configure the table
>  	 *	for use in the upper half of a split address space.
> +	 *
> +	 * IO_PGTABLE_QUIRK_SYS_CACHE: Override the attributes set in TCR for
> +	 *	the page table walker when using system cache.

and then update this accordingly.

Will
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu

WARNING: multiple messages have this Message-ID (diff)
From: Will Deacon <will@kernel.org>
To: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Cc: freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org,
	Joerg Roedel <joro@8bytes.org>,
	Jordan Crouse <jcrouse@codeaurora.org>,
	iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org,
	Rob Clark <robdclark@gmail.com>,
	Akhil P Oommen <akhilpo@codeaurora.org>,
	dri-devel@lists.freedesktop.org,
	"Kristian H . Kristensen" <hoegsberg@google.com>,
	Robin Murphy <robin.murphy@arm.com>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCHv7 1/7] iommu/io-pgtable-arm: Add support to use system cache
Date: Tue, 10 Nov 2020 12:18:56 +0000	[thread overview]
Message-ID: <20201110121855.GD16239@willie-the-truck> (raw)
In-Reply-To: <1d4979c0dcf649c5717605c598067b4b225ab9de.1604048969.git.saiprakash.ranjan@codeaurora.org>

On Fri, Oct 30, 2020 at 02:53:08PM +0530, Sai Prakash Ranjan wrote:
> Add a quirk IO_PGTABLE_QUIRK_SYS_CACHE to override the
> attributes set in TCR for the page table walker when
> using system cache.
> 
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> ---
>  drivers/iommu/io-pgtable-arm.c | 7 ++++++-
>  include/linux/io-pgtable.h     | 4 ++++
>  2 files changed, 10 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
> index a7a9bc08dcd1..a356caf1683a 100644
> --- a/drivers/iommu/io-pgtable-arm.c
> +++ b/drivers/iommu/io-pgtable-arm.c
> @@ -761,7 +761,8 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie)
>  
>  	if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS |
>  			    IO_PGTABLE_QUIRK_NON_STRICT |
> -			    IO_PGTABLE_QUIRK_ARM_TTBR1))
> +			    IO_PGTABLE_QUIRK_ARM_TTBR1 |
> +			    IO_PGTABLE_QUIRK_SYS_CACHE))
>  		return NULL;
>  
>  	data = arm_lpae_alloc_pgtable(cfg);
> @@ -773,6 +774,10 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie)
>  		tcr->sh = ARM_LPAE_TCR_SH_IS;
>  		tcr->irgn = ARM_LPAE_TCR_RGN_WBWA;
>  		tcr->orgn = ARM_LPAE_TCR_RGN_WBWA;
> +	} else if (cfg->quirks & IO_PGTABLE_QUIRK_SYS_CACHE) {
> +		tcr->sh = ARM_LPAE_TCR_SH_OS;
> +		tcr->irgn = ARM_LPAE_TCR_RGN_NC;
> +		tcr->orgn = ARM_LPAE_TCR_RGN_WBWA;

Given that this only applies in the case where then page-table walker is
non-coherent, I think we'd be better off renaming the quirk to something
like IO_PGTABLE_QUIRK_ARM_OUTER_WBWA and then rejecting it in the
non-coherent case.

>  	} else {
>  		tcr->sh = ARM_LPAE_TCR_SH_OS;
>  		tcr->irgn = ARM_LPAE_TCR_RGN_NC;
> diff --git a/include/linux/io-pgtable.h b/include/linux/io-pgtable.h
> index 4cde111e425b..86631f711e05 100644
> --- a/include/linux/io-pgtable.h
> +++ b/include/linux/io-pgtable.h
> @@ -86,6 +86,9 @@ struct io_pgtable_cfg {
>  	 *
>  	 * IO_PGTABLE_QUIRK_ARM_TTBR1: (ARM LPAE format) Configure the table
>  	 *	for use in the upper half of a split address space.
> +	 *
> +	 * IO_PGTABLE_QUIRK_SYS_CACHE: Override the attributes set in TCR for
> +	 *	the page table walker when using system cache.

and then update this accordingly.

Will

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

WARNING: multiple messages have this Message-ID (diff)
From: Will Deacon <will@kernel.org>
To: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Cc: freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org,
	Joerg Roedel <joro@8bytes.org>,
	iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org,
	Akhil P Oommen <akhilpo@codeaurora.org>,
	dri-devel@lists.freedesktop.org,
	"Kristian H . Kristensen" <hoegsberg@google.com>,
	Robin Murphy <robin.murphy@arm.com>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCHv7 1/7] iommu/io-pgtable-arm: Add support to use system cache
Date: Tue, 10 Nov 2020 12:18:56 +0000	[thread overview]
Message-ID: <20201110121855.GD16239@willie-the-truck> (raw)
In-Reply-To: <1d4979c0dcf649c5717605c598067b4b225ab9de.1604048969.git.saiprakash.ranjan@codeaurora.org>

On Fri, Oct 30, 2020 at 02:53:08PM +0530, Sai Prakash Ranjan wrote:
> Add a quirk IO_PGTABLE_QUIRK_SYS_CACHE to override the
> attributes set in TCR for the page table walker when
> using system cache.
> 
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> ---
>  drivers/iommu/io-pgtable-arm.c | 7 ++++++-
>  include/linux/io-pgtable.h     | 4 ++++
>  2 files changed, 10 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
> index a7a9bc08dcd1..a356caf1683a 100644
> --- a/drivers/iommu/io-pgtable-arm.c
> +++ b/drivers/iommu/io-pgtable-arm.c
> @@ -761,7 +761,8 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie)
>  
>  	if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS |
>  			    IO_PGTABLE_QUIRK_NON_STRICT |
> -			    IO_PGTABLE_QUIRK_ARM_TTBR1))
> +			    IO_PGTABLE_QUIRK_ARM_TTBR1 |
> +			    IO_PGTABLE_QUIRK_SYS_CACHE))
>  		return NULL;
>  
>  	data = arm_lpae_alloc_pgtable(cfg);
> @@ -773,6 +774,10 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie)
>  		tcr->sh = ARM_LPAE_TCR_SH_IS;
>  		tcr->irgn = ARM_LPAE_TCR_RGN_WBWA;
>  		tcr->orgn = ARM_LPAE_TCR_RGN_WBWA;
> +	} else if (cfg->quirks & IO_PGTABLE_QUIRK_SYS_CACHE) {
> +		tcr->sh = ARM_LPAE_TCR_SH_OS;
> +		tcr->irgn = ARM_LPAE_TCR_RGN_NC;
> +		tcr->orgn = ARM_LPAE_TCR_RGN_WBWA;

Given that this only applies in the case where then page-table walker is
non-coherent, I think we'd be better off renaming the quirk to something
like IO_PGTABLE_QUIRK_ARM_OUTER_WBWA and then rejecting it in the
non-coherent case.

>  	} else {
>  		tcr->sh = ARM_LPAE_TCR_SH_OS;
>  		tcr->irgn = ARM_LPAE_TCR_RGN_NC;
> diff --git a/include/linux/io-pgtable.h b/include/linux/io-pgtable.h
> index 4cde111e425b..86631f711e05 100644
> --- a/include/linux/io-pgtable.h
> +++ b/include/linux/io-pgtable.h
> @@ -86,6 +86,9 @@ struct io_pgtable_cfg {
>  	 *
>  	 * IO_PGTABLE_QUIRK_ARM_TTBR1: (ARM LPAE format) Configure the table
>  	 *	for use in the upper half of a split address space.
> +	 *
> +	 * IO_PGTABLE_QUIRK_SYS_CACHE: Override the attributes set in TCR for
> +	 *	the page table walker when using system cache.

and then update this accordingly.

Will
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

  reply	other threads:[~2020-11-10 12:19 UTC|newest]

Thread overview: 71+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-30  9:23 [PATCHv7 0/7] System Cache support for GPU and required SMMU support Sai Prakash Ranjan
2020-10-30  9:23 ` Sai Prakash Ranjan
2020-10-30  9:23 ` Sai Prakash Ranjan
2020-10-30  9:23 ` Sai Prakash Ranjan
2020-10-30  9:23 ` [PATCHv7 1/7] iommu/io-pgtable-arm: Add support to use system cache Sai Prakash Ranjan
2020-10-30  9:23   ` Sai Prakash Ranjan
2020-10-30  9:23   ` Sai Prakash Ranjan
2020-10-30  9:23   ` Sai Prakash Ranjan
2020-11-10 12:18   ` Will Deacon [this message]
2020-11-10 12:18     ` Will Deacon
2020-11-10 12:18     ` Will Deacon
2020-11-10 12:18     ` Will Deacon
2020-11-11  6:02     ` Sai Prakash Ranjan
2020-11-11  6:02       ` Sai Prakash Ranjan
2020-11-11  6:02       ` Sai Prakash Ranjan
2020-11-11  6:02       ` Sai Prakash Ranjan
2020-11-12  9:43       ` Will Deacon
2020-11-12  9:43         ` Will Deacon
2020-11-12  9:43         ` Will Deacon
2020-11-12  9:43         ` Will Deacon
2020-10-30  9:23 ` [PATCHv7 2/7] iommu/arm-smmu: Add domain attribute for " Sai Prakash Ranjan
2020-10-30  9:23   ` Sai Prakash Ranjan
2020-10-30  9:23   ` Sai Prakash Ranjan
2020-10-30  9:23   ` Sai Prakash Ranjan
2020-11-10 12:18   ` Will Deacon
2020-11-10 12:18     ` Will Deacon
2020-11-10 12:18     ` Will Deacon
2020-11-10 12:18     ` Will Deacon
2020-11-11  6:40     ` Sai Prakash Ranjan
2020-11-11  6:40       ` Sai Prakash Ranjan
2020-11-11  6:40       ` Sai Prakash Ranjan
2020-11-11  6:40       ` Sai Prakash Ranjan
2020-11-12  9:35       ` Will Deacon
2020-11-12  9:35         ` Will Deacon
2020-11-12  9:35         ` Will Deacon
2020-11-12  9:35         ` Will Deacon
2020-11-14 11:47         ` Sai Prakash Ranjan
2020-11-14 11:47           ` Sai Prakash Ranjan
2020-11-14 11:47           ` Sai Prakash Ranjan
2020-10-30  9:23 ` [PATCHv7 3/7] drm/msm: rearrange the gpu_rmw() function Sai Prakash Ranjan
2020-10-30  9:23   ` Sai Prakash Ranjan
2020-10-30  9:23   ` Sai Prakash Ranjan
2020-10-30  9:23   ` Sai Prakash Ranjan
2020-10-30  9:23 ` [PATCHv7 4/7] drm/msm/a6xx: Add support for using system cache(LLC) Sai Prakash Ranjan
2020-10-30  9:23   ` Sai Prakash Ranjan
2020-10-30  9:23   ` Sai Prakash Ranjan
2020-10-30  9:23   ` Sai Prakash Ranjan
2020-10-30  9:23 ` [PATCHv7 5/7] drm/msm/a6xx: Add support for using system cache on MMU500 based targets Sai Prakash Ranjan
2020-10-30  9:23   ` Sai Prakash Ranjan
2020-10-30  9:23   ` Sai Prakash Ranjan
2020-10-30  9:23   ` Sai Prakash Ranjan
2020-10-30  9:23 ` [PATCHv7 6/7] iommu: arm-smmu-impl: Use table to list QCOM implementations Sai Prakash Ranjan
2020-10-30  9:23   ` Sai Prakash Ranjan
2020-10-30  9:23   ` Sai Prakash Ranjan
2020-10-30  9:23   ` Sai Prakash Ranjan
2020-11-10 12:11   ` Will Deacon
2020-11-10 12:11     ` Will Deacon
2020-11-10 12:11     ` Will Deacon
2020-11-10 12:11     ` Will Deacon
2020-10-30  9:23 ` [PATCHv7 7/7] iommu: arm-smmu-impl: Add a space before open parenthesis Sai Prakash Ranjan
2020-10-30  9:23   ` Sai Prakash Ranjan
2020-10-30  9:23   ` Sai Prakash Ranjan
2020-10-30  9:23   ` Sai Prakash Ranjan
2020-11-10 12:12   ` Will Deacon
2020-11-10 12:12     ` Will Deacon
2020-11-10 12:12     ` Will Deacon
2020-11-10 12:12     ` Will Deacon
2020-11-09  5:15 ` [PATCHv7 0/7] System Cache support for GPU and required SMMU support Sai Prakash Ranjan
2020-11-09  5:15   ` Sai Prakash Ranjan
2020-11-09  5:15   ` Sai Prakash Ranjan
2020-11-09  5:15   ` Sai Prakash Ranjan

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